Merge tag 'drm-intel-fixes-2013-12-11' of git://people.freedesktop.org/~danvet/drm...

Just a bunch of regression fixes plus a few patches for long-standing
issues in gem corner-cases that we've hunted down in the past weeks. Since
apparently people hit those in the wild (and we also have nice igts for
them) I've opted for -fixes and cc: stable.

There's 1-2 things oustanding on top of this where I'm still waiting on
confirmation from testing, but nothing really scary.

* tag 'drm-intel-fixes-2013-12-11' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: don't update the dri1 breadcrumb with modesetting
  drm/i915: Repeat eviction search after idling the GPU
  drm/i915: Fix use-after-free in do_switch
  drm/i915: fix pm init ordering
  drm/i915: Hold mutex across i915_gem_release
  drm/i915: Skip clock checks on BDW
  drm/i915: Do not clobber config status after a forced restore of hw state
  drm/i915: Take modeset locks around intel_modeset_setup_hw_state()

diff --combined drivers/gpu/drm/i915/i915_drv.h
index 79ae94a436a00b2aa04610c4a7db07e1612cb37c,6f04fa4b31fdccabad7c03e167c3fd75fe58a9bd..90fcccba17b00da4a91ea2556b53a81e877356f0
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -1755,13 -1755,8 +1755,13 @@@ struct drm_i915_file_private 
  #define IS_MOBILE(dev)                (INTEL_INFO(dev)->is_mobile)
  #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
                                 ((dev)->pdev->device & 0xFF00) == 0x0C00)
 -#define IS_ULT(dev)           (IS_HASWELL(dev) && \
 +#define IS_BDW_ULT(dev)               (IS_BROADWELL(dev) && \
 +                               (((dev)->pdev->device & 0xf) == 0x2  || \
 +                               ((dev)->pdev->device & 0xf) == 0x6 || \
 +                               ((dev)->pdev->device & 0xf) == 0xe))
 +#define IS_HSW_ULT(dev)               (IS_HASWELL(dev) && \
                                 ((dev)->pdev->device & 0xFF00) == 0x0A00)
 +#define IS_ULT(dev)           (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
  #define IS_HSW_GT3(dev)               (IS_HASWELL(dev) && \
                                 ((dev)->pdev->device & 0x00F0) == 0x0020)
  #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
@@@ -1906,9 -1901,7 +1906,7 @@@ void i915_queue_hangcheck(struct drm_de
  void i915_handle_error(struct drm_device *dev, bool wedged);
  
  extern void intel_irq_init(struct drm_device *dev);
- extern void intel_pm_init(struct drm_device *dev);
  extern void intel_hpd_init(struct drm_device *dev);
- extern void intel_pm_init(struct drm_device *dev);
  
  extern void intel_uncore_sanitize(struct drm_device *dev);
  extern void intel_uncore_early_sanitize(struct drm_device *dev);

diff --combined drivers/gpu/drm/i915/intel_pm.c
index aa5f99c906ef7086a00835d0b793924a7e5a6051,e0dec95c764ec2826c9b43f85d33f6da85fc278f..3657ab43c8fd1e20fc9deb10856166b4c35ec0d4
--- 1/drivers/gpu/drm/i915/intel_pm.c
--- 2/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@@ -5685,7 -5685,6 +5685,7 @@@ static void __intel_set_power_well(stru
  {
        struct drm_i915_private *dev_priv = dev->dev_private;
        bool is_enabled, enable_requested;
 +      unsigned long irqflags;
        uint32_t tmp;
  
        tmp = I915_READ(HSW_PWR_WELL_DRIVER);
@@@ -5703,24 -5702,9 +5703,24 @@@
                                      HSW_PWR_WELL_STATE_ENABLED), 20))
                                DRM_ERROR("Timeout enabling power well\n");
                }
 +
 +              if (IS_BROADWELL(dev)) {
 +                      spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 +                      I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
 +                                 dev_priv->de_irq_mask[PIPE_B]);
 +                      I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
 +                                 ~dev_priv->de_irq_mask[PIPE_B] |
 +                                 GEN8_PIPE_VBLANK);
 +                      I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
 +                                 dev_priv->de_irq_mask[PIPE_C]);
 +                      I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
 +                                 ~dev_priv->de_irq_mask[PIPE_C] |
 +                                 GEN8_PIPE_VBLANK);
 +                      POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
 +                      spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 +              }
        } else {
                if (enable_requested) {
 -                      unsigned long irqflags;
                        enum pipe p;
  
                        I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
@@@ -6146,10 -6130,19 +6146,19 @@@ int vlv_freq_opcode(int ddr_freq, int v
        return val;
  }
  
- void intel_pm_init(struct drm_device *dev)
+ void intel_pm_setup(struct drm_device *dev)
  {
        struct drm_i915_private *dev_priv = dev->dev_private;
  
+       mutex_init(&dev_priv->rps.hw_lock);
+ 
+       mutex_init(&dev_priv->pc8.lock);
+       dev_priv->pc8.requirements_met = false;
+       dev_priv->pc8.gpu_idle = false;
+       dev_priv->pc8.irqs_disabled = false;
+       dev_priv->pc8.enabled = false;
+       dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
+       INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
        INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
                          intel_gen6_powersave_work);
  }