arm: dts: imx6: add sleep state pinctrl settings for ethernet pins to reduce sleep...

diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index f5542353b4bdb813f6294e7b6b31af4409596053..2b6194d2bfcf4b34324e2472378f7b7a8e95494d 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -273,8 +273,10 @@
 };
 
 &fec {
 };
 
 &fec {

-       pinctrl-names = "default";
+       pinctrl-names = "default", "sleep";

        pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
        pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;

+       pinctrl-1 = <&pinctrl_enet_sleep &pinctrl_enet_mdio_sleep
+                    &pinctrl_etnphy_rst_sleep>;

        clocks = <&clks IMX6QDL_CLK_ENET>,
                 <&clks IMX6QDL_CLK_ENET>,
                 <&clks IMX6QDL_CLK_ENET_REF>,
        clocks = <&clks IMX6QDL_CLK_ENET>,
                 <&clks IMX6QDL_CLK_ENET>,
                 <&clks IMX6QDL_CLK_ENET_REF>,


@@ -487,6 +489,19 @@
                >;
        };
 
                >;
        };
 

+       pinctrl_enet_sleep: enet-sleepgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_16__GPIO7_IO11          0x038b0
+                       MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x038b0
+                       MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x038b0
+                       MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x038b0
+                       MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x038b0
+                       MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x038b0
+                       MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x038b0
+                       MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x038b0
+               >;
+       };
+

        pinctrl_enet_mdio: enet-mdiogrp {
                fsl,pins = <
                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
        pinctrl_enet_mdio: enet-mdiogrp {
                fsl,pins = <
                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0


@@ -494,6 +509,13 @@
                >;
        };
 
                >;
        };
 

+       pinctrl_enet_mdio_sleep: enet-mdio-sleepgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_ENET_MDC__GPIO1_IO31         0x038b0
+                       MX6QDL_PAD_ENET_MDIO__GPIO1_IO22        0x038b0
+               >;
+       };
+

        pinctrl_etnphy_int: etnphy-intgrp {
                fsl,pins = <
                        MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
        pinctrl_etnphy_int: etnphy-intgrp {
                fsl,pins = <
                        MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */


@@ -512,6 +534,12 @@
                >;
        };
 
                >;
        };
 

+       pinctrl_etnphy_rst_sleep: etnphy-rst-sleepgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x038b0
+               >;
+       };
+

        pinctrl_flexcan1: flexcan1grp {
                fsl,pins = <
                        MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
        pinctrl_flexcan1: flexcan1grp {
                fsl,pins = <
                        MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0

diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index 7371661d3a3aa8953bece874bf72ad70a4289726..377f353115f3ee8579dc5515a2ae06eccb25a505 100644 (file)
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -307,8 +307,10 @@
 };
 
 &fec1 {
 };
 
 &fec1 {

-       pinctrl-names = "default";
+       pinctrl-names = "default", "sleep";

        pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
        pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;

+       pinctrl-1 = <&pinctrl_enet1_sleep &pinctrl_enet1_mdio_sleep
+                    &pinctrl_etnphy0_rst_sleep>;

        phy-mode = "rmii";
        phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
        phy-reset-post-delay = <10>;
        phy-mode = "rmii";
        phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
        phy-reset-post-delay = <10>;


@@ -343,8 +345,9 @@
 };
 
 &fec2 {
 };
 
 &fec2 {

-       pinctrl-names = "default";
+       pinctrl-names = "default", "sleep";

        pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
        pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;

+       pinctrl-1 = <&pinctrl_enet2_sleep &pinctrl_etnphy1_rst_sleep>;

        phy-mode = "rmii";
        phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
        phy-supply = <&reg_3v3_etn>;
        phy-mode = "rmii";
        phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
        phy-supply = <&reg_3v3_etn>;


@@ -722,6 +725,33 @@
                >;
        };
 
                >;
        };
 

+       pinctrl_enet1_mdio: enet1-mdiogrp {
+               fsl,pins = <
+                       MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
+                       MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
+               >;
+       };
+
+       pinctrl_enet1_mdio_sleep: enet1-mdio-sleepgrp {
+               fsl,pins = <
+                       MX6UL_PAD_GPIO1_IO07__GPIO1_IO07        0x038b0
+                       MX6UL_PAD_GPIO1_IO06__GPIO1_IO06        0x038b0
+               >;
+       };
+
+       pinctrl_enet1_sleep: enet1-sleepgrp {
+               fsl,pins = <
+                       MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0x038b0
+                       MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01    0x038b0
+                       MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02       0x038b0
+                       MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07       0x038b0
+                       MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05       0x038b0
+                       MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03    0x038b0
+                       MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04    0x038b0
+                       MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06      0x038b0
+               >;
+       };
+

        pinctrl_enet2: enet2grp {
                fsl,pins = <
                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
        pinctrl_enet2: enet2grp {
                fsl,pins = <
                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0


@@ -735,10 +765,16 @@
                >;
        };
 
                >;
        };
 

-       pinctrl_enet1_mdio: enet1-mdiogrp {
+       pinctrl_enet2_sleep: enet2grp {

                fsl,pins = <
                fsl,pins = <

-                       MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
-                       MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
+                       MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
+                       MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
+                       MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x000b0
+                       MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x000b0
+                       MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x000b0
+                       MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
+                       MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
+                       MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000018

                >;
        };
 
                >;
        };
 


@@ -760,6 +796,12 @@
                >;
        };
 
                >;
        };
 

+       pinctrl_etnphy0_rst_sleep: etnphy-rst-sleepgrp-0 {
+               fsl,pins = <
+                       MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x038b0
+               >;
+       };
+

        pinctrl_etnphy1_int: etnphy-intgrp-1 {
                fsl,pins = <
                        MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x0b0b0 /* ETN PHY INT */
        pinctrl_etnphy1_int: etnphy-intgrp-1 {
                fsl,pins = <
                        MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x0b0b0 /* ETN PHY INT */


@@ -772,6 +814,12 @@
                >;
        };
 
                >;
        };
 

+       pinctrl_etnphy1_rst_sleep: etnphy-rst-sleepgrp-1 {
+               fsl,pins = <
+                       MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x038b0
+               >;
+       };
+

        pinctrl_flexcan1: flexcan1grp {
                fsl,pins = <
                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
        pinctrl_flexcan1: flexcan1grp {
                fsl,pins = <
                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0

diff --git a/arch/arm/boot/dts/imx6ul-txul-mainboard.dtsi b/arch/arm/boot/dts/imx6ul-txul-mainboard.dtsi
index b02f3afea43f874b534b19b69f9230a1e5a2b947..19f9ce2a2dbb4e2353305e147909590e838def19 100644 (file)
--- a/arch/arm/boot/dts/imx6ul-txul-mainboard.dtsi
+++ b/arch/arm/boot/dts/imx6ul-txul-mainboard.dtsi
@@ -63,12 +63,15 @@
 
 &fec1 {
        pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>;
 
 &fec1 {
        pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>;

+       pinctrl-1 = <&pinctrl_enet1_sleep &pinctrl_etnphy0_rst_sleep>;

        /delete-node/ mdio;
 };
 
 &fec2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
        /delete-node/ mdio;
 };
 
 &fec2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;

+       pinctrl-1 = <&pinctrl_enet2_sleep &pinctrl_enet2_mdio_sleep
+                    &pinctrl_etnphy1_rst_sleep>;

        phy-mode = "rmii";
        phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
        phy-supply = <&reg_3v3_etn>;
        phy-mode = "rmii";
        phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
        phy-supply = <&reg_3v3_etn>;


@@ -224,6 +227,13 @@
                >;
        };
 
                >;
        };
 

+       pinctrl_enet2_mdio_sleep: enet2-mdio-sleepgrp {
+               fsl,pins = <
+                       MX6UL_PAD_GPIO1_IO07__GPIO1_IO07        0x038b0
+                       MX6UL_PAD_GPIO1_IO06__GPIO1_IO06        0x038b0
+               >;
+       };
+

        pinctrl_uart3: uart3grp {
                fsl,pins = <
                        MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x0b0b0
        pinctrl_uart3: uart3grp {
                fsl,pins = <
                        MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x0b0b0