ENGR00273425 ARM: imx: enable suspend code for imx6q/dl

Enable DSM code for imx6, the code porting form kernel 3.5.7.So with the patch,
we can suspend imx6q, imx6dl from iram to decrease power number of DDR IO:
save ~15mA@1.5V on imx6qsabresd, but need more ~30us in suspend and resume back.

Signed-off-by: Robin Gong <b38343@freescale.com>

diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index abf43bb47eca16d05253cb757fc823e1cdfc5645..ffb154848e0960ff6c8e0d1d4146a1bc7054b032 100644 (file)
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -107,6 +107,7 @@
 
 #include "mx51.h"
 #include "mx53.h"
+#include "mx6.h"
 #include "mx3x.h"
 #include "mx31.h"
 #include "mx35.h"

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 8f98173457584fb6b259f6d6f81c41d47e9603c9..85ec12ca55c6a4cd40a2a5059d0a17b4872aca5b 100644 (file)
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -406,6 +406,7 @@ static void __init imx6q_map_io(void)
 {
        debug_ll_io_init();
        imx_scu_map_io();
+       imx6_pm_map_io();
 }
 
 static void __init imx6q_init_irq(void)

diff --git a/arch/arm/mach-imx/mx6.h b/arch/arm/mach-imx/mx6.h
new file mode 100644 (file)
index 0000000..16f7eea
--- /dev/null
+++ b/arch/arm/mach-imx/mx6.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_IOMAP_H__
+#define __ASM_ARCH_MXC_IOMAP_H__
+
+#define MX6Q_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX6Q_IO_ADDRESS(x)              IOMEM(MX6Q_IO_P2V(x))
+
+#define MX6Q_L2_BASE_ADDR               0x00a02000
+#define MX6Q_L2_SIZE                   0x1000
+#define MX6Q_IOMUXC_BASE_ADDR          0x020e0000
+#define MX6Q_IOMUXC_SIZE               0x4000
+#define MX6Q_SRC_BASE_ADDR             0x020d8000
+#define MX6Q_SRC_SIZE                  0x4000
+#define MX6Q_CCM_BASE_ADDR             0x020c4000
+#define MX6Q_CCM_SIZE                  0x4000
+#define MX6Q_ANATOP_BASE_ADDR          0x020c8000
+#define MX6Q_ANATOP_SIZE               0x1000
+#define MX6Q_GPC_BASE_ADDR             0x020dc000
+#define MX6Q_GPC_SIZE                  0x4000
+#define MX6Q_MMDC_P0_BASE_ADDR         0x021b0000
+#define MX6Q_MMDC_P0_SIZE              0x4000
+#define MX6Q_MMDC_P1_BASE_ADDR         0x021b4000
+#define MX6Q_MMDC_P1_SIZE              0x4000
+
+#define MX6_SUSPEND_IRAM_SIZE          0x1000
+#endif