drm/i915: Handle untiled planes when computing their offsets

commit bc752862170c135d6c09fb22d79eeb451023568e upstream.

We trim the fb to fit the CRTC by computing the offset of that CRTC to
its nearest tile_row origin. This allows us to use framebuffers that are
larger than the CRTC limits without additional work.

However, we failed to compute the offset for a linear framebuffer
correctly as we treated its x-advance in whole tiles (instead of the
linear increment expected), leaving the CRTC misaligned with its
contents.

Fixes regression from commit c2c75131244507c93f812862fdbd4f3a37139401
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu Jul 5 12:17:30 2012 +0200

    drm/i915: adjust framebuffer base address on gen4+

v2: Adjust relative x-coordinate after linear alignment (vsyrjala)
v3: Repaint with pokadots (vsyrjala)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61152
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3eaa3067695677c583f8af8d910aa5f6ae59010b..80aa1fc12f4390ccf68d0bf42ff56fc25056e2d8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2017,18 +2017,29 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
 
 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  * is assumed to be a power-of-two. */
-unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
-                                              unsigned int bpp,
-                                              unsigned int pitch)
+unsigned long intel_gen4_compute_page_offset(int *x, int *y,
+                                            unsigned int tiling_mode,
+                                            unsigned int cpp,
+                                            unsigned int pitch)
 {
-       int tile_rows, tiles;
+       if (tiling_mode != I915_TILING_NONE) {
+               unsigned int tile_rows, tiles;
 
-       tile_rows = *y / 8;
-       *y %= 8;
-       tiles = *x / (512/bpp);
-       *x %= 512/bpp;
+               tile_rows = *y / 8;
+               *y %= 8;
 
-       return tile_rows * pitch * 8 + tiles * 4096;
+               tiles = *x / (512/cpp);
+               *x %= 512/cpp;
+
+               return tile_rows * pitch * 8 + tiles * 4096;
+       } else {
+               unsigned int offset;
+
+               offset = *y * pitch + *x * cpp;
+               *y = 0;
+               *x = (offset & 4095) / cpp;
+               return offset & -4096;
+       }
 }
 
 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
@@ -2105,9 +2116,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 
        if (INTEL_INFO(dev)->gen >= 4) {
                intel_crtc->dspaddr_offset =
-                       intel_gen4_compute_offset_xtiled(&x, &y,
-                                                        fb->bits_per_pixel / 8,
-                                                        fb->pitches[0]);
+                       intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+                                                      fb->bits_per_pixel / 8,
+                                                      fb->pitches[0]);
                linear_offset -= intel_crtc->dspaddr_offset;
        } else {
                intel_crtc->dspaddr_offset = linear_offset;
@@ -2198,9 +2209,9 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
 
        linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
        intel_crtc->dspaddr_offset =
-               intel_gen4_compute_offset_xtiled(&x, &y,
-                                                fb->bits_per_pixel / 8,
-                                                fb->pitches[0]);
+               intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+                                              fb->bits_per_pixel / 8,
+                                              fb->pitches[0]);
        linear_offset -= intel_crtc->dspaddr_offset;
 
        DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 42dd62e22fbbf47a7135d7bd3f8f504dd65ea092..1c1840f18d6663fe11f5fbbe62c500bfe8a128b7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -627,9 +627,10 @@ extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
                         struct drm_display_mode *mode);
 
-extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
-                                                     unsigned int bpp,
-                                                     unsigned int pitch);
+extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
+                                                   unsigned int tiling_mode,
+                                                   unsigned int bpp,
+                                                   unsigned int pitch);
 
 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
                                     struct drm_file *file_priv);

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index d7b060e0a23199b064c21d30366dd5ff78566e13..9a8d6676a587a2fc36b605fcb063e9bbbaa63fd8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -122,8 +122,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 
        linear_offset = y * fb->pitches[0] + x * pixel_size;
        sprsurf_offset =
-               intel_gen4_compute_offset_xtiled(&x, &y,
-                                                pixel_size, fb->pitches[0]);
+               intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+                                              pixel_size, fb->pitches[0]);
        linear_offset -= sprsurf_offset;
 
        /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
@@ -287,8 +287,8 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 
        linear_offset = y * fb->pitches[0] + x * pixel_size;
        dvssurf_offset =
-               intel_gen4_compute_offset_xtiled(&x, &y,
-                                                pixel_size, fb->pitches[0]);
+               intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+                                              pixel_size, fb->pitches[0]);
        linear_offset -= dvssurf_offset;
 
        if (obj->tiling_mode != I915_TILING_NONE)