reg = <0x021d8000 0x4000>;
status = "disabled";
};
+
+ gpu@02200000 {
+ compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
+ reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
+ <0x80000000 0x0>;
+ reg-names = "iobase_2d", "iobase_vg",
+ "phys_baseaddr";
+ interrupts = <0 10 0x04>, <0 11 0x04>;
+ interrupt-names = "irq_2d", "irq_vg";
+ clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
+ <&clks IMX6SL_CLK_MMDC_ROOT>,
+ <&clks IMX6SL_CLK_GPU2D_OVG>;
+ clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
+ "gpu2d_clk";
+ resets = <&src 3>, <&src 3>;
+ reset-names = "gpu2d", "gpuvg";
+ };
+
};
};
};