arm64: dts: juno: enable some SMMUs

The IOMMU-backed DMA API support has now been in place for a while and
proven stable, so there's no real need to keep most of Juno's SMMUs
disabled. The USB, HDLCDs, and CoreSight ETR all just need to map RAM
buffers for DMA - enabling their SMMUs obviates CPU bounce buffering for
USB's streaming DMA to the upper memory bank, and lets the other two
allocate their relatively large coherent buffers without pressuring CMA.

Some more software work is still needed for the DMA-330 and PCIe before
those can accommodate SMMU translation correctly in all cases, so we
leave those alone for now.

Tested-by: Liviu Dudau <Liviu.Dudau@arm.com> [only HDLCD]
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 48bc5abb37a20e48c006a14a5659b567fea12889..e8b7413ec890b8fc88f1fb62d691d7ffcdae8570 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -53,7 +53,6 @@
                #global-interrupts = <1>;
                dma-coherent;
                power-domains = <&scpi_devpd 0>;
-               status = "disabled";
        };
 
        gic: interrupt-controller@2c010000 {
@@ -600,7 +599,6 @@
                             <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
                #iommu-cells = <1>;
                #global-interrupts = <1>;
-               status = "disabled";
        };
 
        smmu_hdlcd0: iommu@7fb20000 {
@@ -610,7 +608,6 @@
                             <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                #iommu-cells = <1>;
                #global-interrupts = <1>;
-               status = "disabled";
        };
 
        smmu_usb: iommu@7fb30000 {
@@ -621,7 +618,6 @@
                #iommu-cells = <1>;
                #global-interrupts = <1>;
                dma-coherent;
-               status = "disabled";
        };
 
        dma@7ff00000 {