powerpc: Only do ERAT invalidate on radix context switch on P9 DD1

From: Michael Neuling <mikey@neuling.org>

On P9 (Nimbus) DD2 and later, in radix mode, the move to the PID
register will implicitly invalidate the user space ERAT entries
and leave the kernel ones alone. Thus the only thing needed is
an isync() to synchronize this with subsequent uaccess's

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/mm/mmu_context_book3s64.c b/arch/powerpc/mm/mmu_context_book3s64.c
index c6dca2ae78ef9f1225dd6a13e0997034132315a4..3ef0a89503bfb3b19dd9f31677541632e7e659d6 100644 (file)
--- a/arch/powerpc/mm/mmu_context_book3s64.c
+++ b/arch/powerpc/mm/mmu_context_book3s64.c
@@ -235,10 +235,15 @@ void destroy_context(struct mm_struct *mm)
 #ifdef CONFIG_PPC_RADIX_MMU
 void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
 {
-       asm volatile("isync": : :"memory");
-       mtspr(SPRN_PID, next->context.id);
-       asm volatile("isync \n"
-                    PPC_SLBIA(0x7)
-                    : : :"memory");
+
+       if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
+               isync();
+               mtspr(SPRN_PID, next->context.id);
+               isync();
+               asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
+       } else {
+               mtspr(SPRN_PID, next->context.id);
+               isync();
+       }
 }
 #endif