]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
MLK-10161-2: ARM: imx6sl: Add SPDIF_GCLK clock in clock tree
authorShengjiu Wang <shengjiu.wang@freescale.com>
Tue, 27 Jan 2015 08:43:17 +0000 (16:43 +0800)
committerShengjiu Wang <shengjiu.wang@freescale.com>
Wed, 28 Jan 2015 07:44:35 +0000 (15:44 +0800)
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_prepare in init function, so SPDIF clock is prepared in probe, then its
root clock (pll clock) is prepared also, which cause the arm can't enter
low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
Its root clock is ipg clock, and register it to regmap, then the issue can be
fixed.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
arch/arm/boot/dts/imx6sl.dtsi
arch/arm/mach-imx/clk-imx6sl.c
include/dt-bindings/clock/imx6sl-clock.h

index d06c5228a32430be4d669dc61180d37f7c23102d..85a64be05c6a346ba7b885f260fba94772aa48c9 100644 (file)
                                        dmas = <&sdma 14 18 0>,
                                               <&sdma 15 18 0>;
                                        dma-names = "rx", "tx";
-                                       clocks = <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_OSC>,
+                                       clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
                                                 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
                                                 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
                                                 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
index 8de4ac5c8a4b19221f0d0eeddeb73c693c13a1ff..78961c50c197473250c361ed4d22f44adf35c15b 100644 (file)
@@ -104,6 +104,7 @@ static struct clk_div_table video_div_table[] = {
 static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
+static unsigned int share_count_spdif;
 
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -425,7 +426,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
        clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
        clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
-       clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
+       clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif0_podf",   base + 0x7c, 14, &share_count_spdif);
+       clks[IMX6SL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",  "ipg",         base + 0x7c, 14, &share_count_spdif);
        clks[IMX6SL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",     "ipg",        base + 0x7c, 18, &share_count_ssi1);
        clks[IMX6SL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",     "ipg",        base + 0x7c, 20, &share_count_ssi2);
        clks[IMX6SL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",     "ipg",        base + 0x7c, 22, &share_count_ssi3);
index 9af14ae859db4f88489a68d6a1fab8a33e1de883..4a2c4c61f766ebe441fc7faaef3ccb9e46ca283b 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
 #define IMX6SL_CLK_SSI2_IPG            161
 #define IMX6SL_CLK_SSI3_IPG            162
 #define IMX6SL_CLK_UART_OSC_4M         163
-#define IMX6SL_CLK_END                 164
+#define IMX6SL_CLK_SPDIF_GCLK          164
+#define IMX6SL_CLK_END                 165
 
  
 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */