]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
authorGregory CLEMENT <gregory.clement@free-electrons.com>
Mon, 7 Jan 2013 10:27:14 +0000 (11:27 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 7 Jan 2013 15:04:17 +0000 (15:04 +0000)
This patch fixes a bug for Aurora L2 cache controller when the
write-through mode is enable. For the clean operation even if we don't
have to flush the lines we still need to invalidate them.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/cache-l2x0.c

index 05d577613b132c86c036569049e39ae673ff7027..55ca637a4930a8794fb62ae620f8801e7226293d 100644 (file)
@@ -506,15 +506,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end)
 
 static void aurora_flush_range(unsigned long start, unsigned long end)
 {
-       if (!l2_wt_override) {
-               start &= ~(CACHE_LINE_SIZE - 1);
-               end = ALIGN(end, CACHE_LINE_SIZE);
-               while (start != end) {
-                       unsigned long range_end = calc_range_end(start, end);
+       start &= ~(CACHE_LINE_SIZE - 1);
+       end = ALIGN(end, CACHE_LINE_SIZE);
+       while (start != end) {
+               unsigned long range_end = calc_range_end(start, end);
+               /*
+                * If L2 is forced to WT, the L2 will always be clean and we
+                * just need to invalidate.
+                */
+               if (l2_wt_override)
                        aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
-                                       AURORA_FLUSH_RANGE_REG);
-                       start = range_end;
-               }
+                                                       AURORA_INVAL_RANGE_REG);
+               else
+                       aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+                                                       AURORA_FLUSH_RANGE_REG);
+               start = range_end;
        }
 }