MGS-504 imx: i.MX6DL gpu3d_core_clk should be 528M instead of 396M

This patch is refined from the previous commit 20d89c9c909:

-Update the parent of gpu2d_core for mx6dl.
-Update the parent of gpu3d_shader and gpu3d_core for mx6dl.
-Update the clock of gpu3d_shader and gpu3d_core for mx6dl.
The code change is cherry-picked from patch 00e75bcba16d.

Signed-off-by: Loren Huang <b02279@freescale.com>
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit e63222bdba7c2de063c6367017ccd6a1d1d3cc22)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 47997904a7a472a40e7e985ea57398c1d53c2323..213485756283a6928539b94a1ede867a06caaca3 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -518,11 +518,29 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        imx_clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
 
        /* gpu clock initilazation */
+       /*
+       * On mx6dl, 2d core clock sources(sel, podf) is from 3d
+       * shader core clock, but 3d shader clock multiplexer of
+       * mx6dl is different. For instance the equivalent of
+       * pll2_pfd_594M on mx6q is pll2_pfd_528M on mx6dl.
+       * Make a note here.
+       */
        imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
-       imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 594000000);
-       imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
-       imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
-       imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
+       if (cpu_is_imx6dl()) {
+               imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 528000000);
+               /* for mx6dl, change gpu3d_core parent to 594_PFD*/
+               imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
+               imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
+               /* for mx6dl, change gpu2d_core parent to 594_PFD*/
+               imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
+               imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 528000000);
+       } else if (cpu_is_imx6q()) {
+               imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 594000000);
+               imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
+               imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
+               imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
+               imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 480000000);
+       }
 
        /*
         * Let's initially set up CLKO with OSC24M, since this configuration