]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux...
authorLothar Waßmann <LW@KARO-electronics.de>
Wed, 2 Jul 2014 12:13:45 +0000 (14:13 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Wed, 2 Jul 2014 12:13:45 +0000 (14:13 +0200)
1  2 
arch/arm/Kconfig
arch/arm/boot/dts/Makefile
arch/arm/configs/imx_v6_v7_defconfig
arch/arm/mach-imx/clk-imx6sl.c
include/linux/regulator/consumer.h

diff --combined arch/arm/Kconfig
index eaf5961aa85b4de36f9e65bafaa783d14439547a,245058b3b0ef7d5d27b7c113d6199127d8cd5a8c..e907971f44acf97083331ae1a1f18b91116de122
@@@ -175,13 -175,6 +175,6 @@@ config ARCH_HAS_ILOG2_U3
  config ARCH_HAS_ILOG2_U64
        bool
  
- config ARCH_HAS_CPUFREQ
-       bool
-       help
-         Internal node to signify that the ARCH has CPUFREQ support
-         and that the relevant menu configurations are displayed for
-         it.
  config ARCH_HAS_BANDGAP
        bool
  
@@@ -318,7 -311,6 +311,6 @@@ config ARCH_MULTIPLATFOR
  
  config ARCH_INTEGRATOR
        bool "ARM Ltd. Integrator family"
-       select ARCH_HAS_CPUFREQ
        select ARM_AMBA
        select ARM_PATCH_PHYS_VIRT
        select AUTO_ZRELADDR
@@@ -538,7 -530,6 +530,6 @@@ config ARCH_DOV
  
  config ARCH_KIRKWOOD
        bool "Marvell Kirkwood"
-       select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select CPU_FEROCEON
        select GENERIC_CLOCKEVENTS
@@@ -637,7 -628,6 +628,6 @@@ config ARCH_LPC32X
  config ARCH_PXA
        bool "PXA2xx/PXA3xx-based"
        depends on MMU
-       select ARCH_HAS_CPUFREQ
        select ARCH_MTD_XIP
        select ARCH_REQUIRE_GPIOLIB
        select ARM_CPU_SUSPEND if PM
@@@ -707,7 -697,6 +697,6 @@@ config ARCH_RP
  
  config ARCH_SA1100
        bool "SA1100-based"
-       select ARCH_HAS_CPUFREQ
        select ARCH_MTD_XIP
        select ARCH_REQUIRE_GPIOLIB
        select ARCH_SPARSEMEM_ENABLE
  
  config ARCH_S3C24XX
        bool "Samsung S3C24XX SoCs"
-       select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select ATAGS
        select CLKDEV_LOOKUP
  
  config ARCH_S3C64XX
        bool "Samsung S3C64XX"
-       select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
        select ARM_VIC
@@@ -809,7 -796,6 +796,6 @@@ config ARCH_S5PC10
  
  config ARCH_S5PV210
        bool "Samsung S5PV210/S5PC110"
-       select ARCH_HAS_CPUFREQ
        select ARCH_HAS_HOLES_MEMORYMODEL
        select ARCH_SPARSEMEM_ENABLE
        select ATAGS
@@@ -845,7 -831,6 +831,6 @@@ config ARCH_DAVINC
  config ARCH_OMAP1
        bool "TI OMAP1"
        depends on MMU
-       select ARCH_HAS_CPUFREQ
        select ARCH_HAS_HOLES_MEMORYMODEL
        select ARCH_OMAP
        select ARCH_REQUIRE_GPIOLIB
@@@ -1009,8 -994,6 +994,6 @@@ source "arch/arm/mach-rockchip/Kconfig
  
  source "arch/arm/mach-sa1100/Kconfig"
  
- source "arch/arm/plat-samsung/Kconfig"
  source "arch/arm/mach-socfpga/Kconfig"
  
  source "arch/arm/mach-spear/Kconfig"
@@@ -1028,6 -1011,7 +1011,7 @@@ source "arch/arm/mach-s5pc100/Kconfig
  source "arch/arm/mach-s5pv210/Kconfig"
  
  source "arch/arm/mach-exynos/Kconfig"
+ source "arch/arm/plat-samsung/Kconfig"
  
  source "arch/arm/mach-shmobile/Kconfig"
  
@@@ -1774,7 -1758,6 +1758,7 @@@ config FORCE_MAX_ZONEORDE
        range 11 64 if ARCH_SHMOBILE_LEGACY
        default "12" if SOC_AM33XX
        default "9" if SA1111 || ARCH_EFM32
 +      default "14" if ARCH_MXC
        default "11"
        help
          The kernel memory allocator divides physically contiguous memory
@@@ -2110,9 -2093,7 +2094,7 @@@ endmen
  
  menu "CPU Power Management"
  
- if ARCH_HAS_CPUFREQ
  source "drivers/cpufreq/Kconfig"
- endif
  
  source "drivers/cpuidle/Kconfig"
  
index ce1cb18cc15fd05b1cbaf2f89530f74fe33cd16c,adb5ed9e269e196a55c380002d266062fd06c3b7..37a4c8cb88fbef2be55768a981392c3337c769e7
@@@ -195,9 -195,6 +195,9 @@@ dtb-$(CONFIG_ARCH_MXC) += 
        imx6dl-sabreauto.dtb \
        imx6dl-sabrelite.dtb \
        imx6dl-sabresd.dtb \
 +      imx6dl-tx6dl-comtft.dtb \
 +      imx6dl-tx6u-801x.dtb \
 +      imx6dl-tx6u-811x.dtb \
        imx6dl-wandboard.dtb \
        imx6q-arm2.dtb \
        imx6q-cm-fx6.dtb \
        imx6q-sabrelite.dtb \
        imx6q-sabresd.dtb \
        imx6q-sbc6x.dtb \
 +      imx6q-tx6q-1010.dtb \
 +      imx6q-tx6q-1010-comtft.dtb \
 +      imx6q-tx6q-1020.dtb \
 +      imx6q-tx6q-1020-comtft.dtb \
 +      imx6q-tx6q-1110.dtb \
        imx6q-udoo.dtb \
        imx6q-wandboard.dtb \
        imx6sl-evk.dtb \
@@@ -365,7 -357,7 +365,7 @@@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.
        stih415-b2020.dtb \
        stih416-b2000.dtb \
        stih416-b2020.dtb \
-       stih416-b2020-revE.dtb
+       stih416-b2020e.dtb
  dtb-$(CONFIG_MACH_SUN4I) += \
        sun4i-a10-a1000.dtb \
        sun4i-a10-cubieboard.dtb \
index be3d5f4bf6db413a4cd8835881f89dd1290236e3,59b7e45142d80931c5e46882188c524530d4b22a..0273619414cb3add2aa8c11e45be64bb73bf20cc
@@@ -49,7 -49,6 +49,7 @@@ CONFIG_CMDLINE="noinitrd console=ttymxc
  CONFIG_CPU_FREQ=y
  CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
  CONFIG_ARM_IMX6Q_CPUFREQ=y
 +CONFIG_CPU_IDLE=y
  CONFIG_VFP=y
  CONFIG_NEON=y
  CONFIG_BINFMT_MISC=m
@@@ -161,7 -160,6 +161,7 @@@ CONFIG_SPI=
  CONFIG_SPI_IMX=y
  CONFIG_GPIO_SYSFS=y
  CONFIG_GPIO_MC9S08DZ60=y
 +CONFIG_GPIO_PCA953X=y
  # CONFIG_HWMON is not set
  CONFIG_WATCHDOG=y
  CONFIG_IMX2_WDT=y
@@@ -183,13 -181,12 +183,14 @@@ CONFIG_MEDIA_RC_SUPPORT=
  CONFIG_RC_DEVICES=y
  CONFIG_IR_GPIO_CIR=y
  CONFIG_V4L_PLATFORM_DRIVERS=y
 +CONFIG_VIDEO_MXC_OUTPUT=y
 +CONFIG_VIDEO_MXC_IPU_OUTPUT=y
  CONFIG_SOC_CAMERA=y
  CONFIG_VIDEO_MX3=y
  CONFIG_V4L_MEM2MEM_DRIVERS=y
  CONFIG_VIDEO_CODA=y
  CONFIG_SOC_CAMERA_OV2640=y
+ CONFIG_IMX_IPUV3_CORE=y
  CONFIG_DRM=y
  CONFIG_DRM_PANEL_SIMPLE=y
  CONFIG_BACKLIGHT_LCD_SUPPORT=y
@@@ -224,7 -221,6 +225,7 @@@ CONFIG_USB_GADGET=
  CONFIG_USB_ETH=m
  CONFIG_USB_MASS_STORAGE=m
  CONFIG_MMC=y
 +CONFIG_MMC_UNSAFE_RESUME=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_PLTFM=y
  CONFIG_MMC_SDHCI_ESDHC_IMX=y
@@@ -244,7 -240,6 +245,7 @@@ CONFIG_RTC_DRV_MC13XXX=
  CONFIG_RTC_DRV_MXC=y
  CONFIG_RTC_DRV_SNVS=y
  CONFIG_DMADEVICES=y
 +CONFIG_MXC_PXP_V2=y
  CONFIG_IMX_SDMA=y
  CONFIG_MXS_DMA=y
  CONFIG_STAGING=y
index 627ca39f0cec6d8f3a431ee6aafe2af2fcda1f3e,5408ca70c8d62ca01cc9d7dbf0fb331b51edec32..6163c50b08d3217f0dc0319a1fd646afc828b405
@@@ -182,13 -182,13 +182,13 @@@ static void __init imx6sl_clocks_init(s
        anatop_base = base;
  
        /*                                             type               name            parent  base         div_mask */
 -      clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f);
 -      clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc", base + 0x30, 0x1);
 -      clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc", base + 0x10, 0x3);
 -      clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc", base + 0x70, 0x7f);
 -      clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc", base + 0xa0, 0x7f);
 -      clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc", base + 0xe0, 0x3);
 -      clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc", base + 0x20, 0x3);
 +      clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f, true);
 +      clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc", base + 0x30, 0x1, true);
 +      clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc", base + 0x10, 0x3, false);
 +      clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc", base + 0x70, 0x7f, false);
 +      clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc", base + 0xa0, 0x7f, false);
 +      clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc", base + 0xe0, 0x3, false);
 +      clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc", base + 0x20, 0x3, false);
  
        /*
         * usbphy1 and usbphy2 are implemented as dummy gates using reserve
        clks[IMX6SL_CLK_EPDC_AXI_SEL]     = imx_clk_mux("epdc_axi_sel",     base + 0x34, 15, 3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
        clks[IMX6SL_CLK_GPU2D_OVG_SEL]    = imx_clk_mux("gpu2d_ovg_sel",    base + 0x18, 4,  2, gpu2d_ovg_sels,    ARRAY_SIZE(gpu2d_ovg_sels));
        clks[IMX6SL_CLK_GPU2D_SEL]        = imx_clk_mux("gpu2d_sel",        base + 0x18, 8,  2, gpu2d_sels,        ARRAY_SIZE(gpu2d_sels));
 -      clks[IMX6SL_CLK_LCDIF_PIX_SEL]    = imx_clk_mux("lcdif_pix_sel",    base + 0x38, 6,  3, lcdif_pix_sels,    ARRAY_SIZE(lcdif_pix_sels));
 -      clks[IMX6SL_CLK_EPDC_PIX_SEL]     = imx_clk_mux("epdc_pix_sel",     base + 0x38, 15, 3, epdc_pix_sels,     ARRAY_SIZE(epdc_pix_sels));
 +      clks[IMX6SL_CLK_LCDIF_PIX_SEL]    = imx_clk_mux_flags("lcdif_pix_sel",    base + 0x38, 6,  3, lcdif_pix_sels,    ARRAY_SIZE(lcdif_pix_sels), CLK_SET_RATE_PARENT);
 +      clks[IMX6SL_CLK_EPDC_PIX_SEL]     = imx_clk_mux_flags("epdc_pix_sel",     base + 0x38, 15, 3, epdc_pix_sels,     ARRAY_SIZE(epdc_pix_sels), CLK_SET_RATE_PARENT);
        clks[IMX6SL_CLK_SPDIF0_SEL]       = imx_clk_mux("spdif0_sel",       base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
        clks[IMX6SL_CLK_SPDIF1_SEL]       = imx_clk_mux("spdif1_sel",       base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
        clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
        clks[IMX6SL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",       "ecspi_root",        base + 0x6c, 2);
        clks[IMX6SL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",       "ecspi_root",        base + 0x6c, 4);
        clks[IMX6SL_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",       "ecspi_root",        base + 0x6c, 6);
+       clks[IMX6SL_CLK_ENET]         = imx_clk_gate2("enet",         "ipg",               base + 0x6c, 10);
        clks[IMX6SL_CLK_EPIT1]        = imx_clk_gate2("epit1",        "perclk",            base + 0x6c, 12);
        clks[IMX6SL_CLK_EPIT2]        = imx_clk_gate2("epit2",        "perclk",            base + 0x6c, 14);
        clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                clk_prepare_enable(clks[clks_init_on[i]]);
  
 +      /*
 +       * Make sure the MMDC clk is enabled to maintain the correct usecount
 +       * and enabling/disabling of parent PLLs.
 +       */
 +      ret = clk_prepare_enable(clks[IMX6SL_CLK_MMDC_ROOT]);
 +      if (ret)
 +              pr_warn("%s: failed to enable MMDC clock %d\n",
 +                      __func__, ret);
 +
        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
  
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
        mxc_timer_init_dt(np);
 +
 +      /* Initialize Video PLLs to valid frequency (650MHz). */
 +      clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO_DIV], 650000000);
 +      /* set PLL5 video as lcdif pix parent clock */
 +      clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
 +                      clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
  }
  CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
index a0de9ccbde347f28f937c3bcb9e3da0b6b4e5570,14ec18d5e18b80e5adc47f0842b625e57c6918f7..48ab02c773729e628ac3dda88aa29bac5b3a5c0d
@@@ -2,7 -2,6 +2,7 @@@
   * consumer.h -- SoC Regulator consumer support.
   *
   * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
 + * Copyright (C) 2013 Freescale Semiconductor, Inc.
   *
   * Author: Liam Girdwood <lrg@slimlogic.co.uk>
   *
@@@ -106,8 -105,6 +106,8 @@@ struct notifier_block
  #define REGULATOR_EVENT_FORCE_DISABLE         0x20
  #define REGULATOR_EVENT_VOLTAGE_CHANGE                0x40
  #define REGULATOR_EVENT_DISABLE               0x80
 +#define REGULATOR_EVENT_PRE_DISABLE           0x100
 +#define REGULATOR_EVENT_ENABLE                        0x200
  
  struct regulator;
  
@@@ -398,6 -395,11 +398,11 @@@ static inline void regulator_bulk_free(
  {
  }
  
+ static inline int regulator_can_change_voltage(struct regulator *regulator)
+ {
+       return 0;
+ }
  static inline int regulator_set_voltage(struct regulator *regulator,
                                        int min_uV, int max_uV)
  {