ARM: dts: imx6ul: add support for Ka-Ro TXUL modules
authorLothar Waßmann <LW@KARO-electronics.de>
Tue, 3 Nov 2015 11:12:04 +0000 (12:12 +0100)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 5 Nov 2015 13:47:35 +0000 (14:47 +0100)
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/imx6ul-14x14-evk.dts
arch/arm/boot/dts/imx6ul-tx6ul-0010.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6ul-tx6ul-0011.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6ul-tx6ul.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx6ul.dtsi
drivers/clk/imx/clk-imx6ul.c
include/dt-bindings/clock/imx6ul-clock.h

index e4172af..8ff67f9 100644 (file)
@@ -354,7 +354,9 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
        imx6sx-sdb-reva.dtb \
        imx6sx-sdb.dtb
 dtb-$(CONFIG_SOC_IMX6UL) += \
-       imx6ul-14x14-evk.dtb
+       imx6ul-14x14-evk.dtb \
+       imx6ul-tx6ul-0010.dtb \
+       imx6ul-tx6ul-0011.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
        imx7d-sdb.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
index 6aaa5ec..a6f459a 100644 (file)
@@ -8,7 +8,6 @@
 
 /dts-v1/;
 
-#include <dt-bindings/input/input.h>
 #include "imx6ul.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts b/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts
new file mode 100644 (file)
index 0000000..40d1b4c
--- /dev/null
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+/dts-v1/;
+#include "imx6ul.dtsi"
+#include "imx6ul-tx6ul.dtsi"
+
+/ {
+       model = "Ka-Ro electronics TXUL-0010 Module";
+       compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
+
+       aliases {
+               mmc0 = &usdhc1;
+               /delete-property/ mmc1;
+       };
+};
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts b/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts
new file mode 100644 (file)
index 0000000..80f9171
--- /dev/null
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+/dts-v1/;
+#include "imx6ul.dtsi"
+#include "imx6ul-tx6ul.dtsi"
+
+/ {
+       model = "Ka-Ro electronics TXUL-0011 Module";
+       compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
+
+       aliases {
+               mmc0 = &usdhc2;
+               mmc1 = &usdhc1;
+       };
+};
+
+&gpmi {
+       status = "disabled";
+};
+
+&iomuxc {
+       imx6qdl-tx6 {
+               pinctrl_usdhc2: usdhc2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
+                               /* eMMC RESET */
+                               MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
+                       >;
+               };
+       };
+};
+
+&usdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       bus-width = <4>;
+       no-1-8-v;
+       non-removable;
+       fsl,wp-controller;
+       status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
new file mode 100644 (file)
index 0000000..f2050d8
--- /dev/null
@@ -0,0 +1,879 @@
+/*
+ * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+       aliases {
+               can0 = &can2;
+               can1 = &can1;
+               display = &display;
+               i2c0 = &i2c_gpio;
+               i2c1 = &i2c2;
+               lcdif_23bit_pins_a = &pinctrl_disp0_1;
+               lcdif_24bit_pins_a = &pinctrl_disp0_2;
+               pwm0 = &pwm5;
+               reg_can_xcvr = &reg_can_xcvr;
+               serial2 = &uart5;
+//             spi0 = &ecspi2;
+               spi0 = &spi_gpio;
+               stk5led = &user_led;
+               usbh1 = &usbotg2;
+               usbotg = &usbotg1;
+       };
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       memory {
+               reg = <0 0>; /* will be filled by U-Boot */
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               mclk: clock@0 {
+                       compatible = "fixed-clock";
+                       reg = <0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <27000000>;
+               };
+       };
+
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
+               power-supply = <&reg_3v3>;
+               /*
+                * a poor man's way to create a 1:1 relationship between
+                * the PWM value and the actual duty cycle
+                */
+               brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+                                    10 11 12 13 14 15 16 17 18 19
+                                    20 21 22 23 24 25 26 27 28 29
+                                    30 31 32 33 34 35 36 37 38 39
+                                    40 41 42 43 44 45 46 47 48 49
+                                    50 51 52 53 54 55 56 57 58 59
+                                    60 61 62 63 64 65 66 67 68 69
+                                    70 71 72 73 74 75 76 77 78 79
+                                    80 81 82 83 84 85 86 87 88 89
+                                    90 91 92 93 94 95 96 97 98 99
+                                   100>;
+               default-brightness-level = <50>;
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+       };
+
+       i2c_gpio: i2c-gpio {
+               compatible = "i2c-gpio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_i2c_gpio>;
+               gpios = <
+                       &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
+                       &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
+               >;
+               clock-frequency = <400000>;
+               status = "okay";
+
+               ds1339: rtc@68 {
+                       compatible = "dallas,ds1339";
+                       reg = <0x68>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               user_led: user {
+                       label = "Heartbeat";
+                       gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               reg_3v3_etn: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "3V3_ETN";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_etnphy_power>;
+                       gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+               reg_2v5: regulator@1 {
+                       compatible = "regulator-fixed";
+                       reg = <1>;
+                       regulator-name = "2V5";
+                       regulator-min-microvolt = <2500000>;
+                       regulator-max-microvolt = <2500000>;
+                       regulator-always-on;
+               };
+
+               reg_3v3: regulator@2 {
+                       compatible = "regulator-fixed";
+                       reg = <2>;
+                       regulator-name = "3V3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+               };
+
+               reg_can_xcvr: regulator@3 {
+                       compatible = "regulator-fixed";
+                       reg = <3>;
+                       regulator-name = "CAN XCVR";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_flexcan_xcvr>;
+                       gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+                       enable-active-low;
+               };
+
+               reg_lcd_pwr: regulator@5 {
+                       compatible = "regulator-fixed";
+                       reg = <5>;
+                       regulator-name = "LCD POWER";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_lcd1_pwr>;
+                       gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               reg_usbh1_vbus: regulator@6 {
+                       compatible = "regulator-fixed";
+                       reg = <6>;
+                       regulator-name = "usbh1_vbus";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
+                       gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+               reg_usbotg_vbus: regulator@7 {
+                       compatible = "regulator-fixed";
+                       reg = <7>;
+                       regulator-name = "usbotg_vbus";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
+                       gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+       };
+
+       spi_gpio: spi-gpio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "spi-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_spi_gpio>;
+               gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+               gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+               gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+               num-chipselects = <2>;
+               cs-gpios = <
+                       &gpio1 29 GPIO_ACTIVE_HIGH
+                       &gpio1 10 GPIO_ACTIVE_HIGH
+               >;
+               status = "okay";
+
+               spidev0: spi@0 {
+                       compatible = "spidev";
+                       reg = <0>;
+                       spi-max-frequency = <54000000>;
+               };
+
+               spidev1: spi@1 {
+                       compatible = "spidev";
+                       reg = <1>;
+                       spi-max-frequency = <54000000>;
+               };
+       };
+};
+
+&can1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       xceiver-supply = <&reg_can_xcvr>;
+       status = "okay";
+};
+
+&can2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       xceiver-supply = <&reg_can_xcvr>;
+       status = "okay";
+};
+
+#if 0
+&ecspi2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       fsl,spi-num-chipselects = <2>;
+       cs-gpios = <
+               &gpio1 29 GPIO_ACTIVE_HIGH
+               &gpio1 10 GPIO_ACTIVE_HIGH
+       >;
+       status = "okay";
+
+       spidev0: spi@0 {
+               compatible = "spidev";
+               reg = <0>;
+               spi-max-frequency = <54000000>;
+       };
+
+       spidev1: spi@1 {
+               compatible = "spidev";
+               reg = <1>;
+               spi-max-frequency = <54000000>;
+       };
+};
+#endif
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet_mdio>;
+       phy-mode = "rmii";
+       phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
+       phy-supply = <&reg_3v3_etn>;
+       phy-handle = <&etnphy0>;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               etnphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+                       interrupt-parent = <&gpio5>;
+                       interrupts = <5>;
+                       status = "okay";
+               };
+
+               etnphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+                       status = "okay";
+               };
+       };
+};
+
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet2>;
+       phy-mode = "rmii";
+       phy-supply = <&reg_3v3_etn>;
+       phy-handle = <&etnphy1>;
+       status = "okay";
+};
+
+&gpmi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpmi_nand>;
+       nand-on-flash-bbt;
+       fsl,no-blockmark-swap;
+       status = "okay";
+};
+
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       clock-frequency = <400000>;
+       status = "okay";
+
+       sgtl5000: sgtl5000@0a {
+               compatible = "fsl,sgtl5000";
+               reg = <0x0a>;
+               VDDA-supply = <&reg_2v5>;
+               VDDIO-supply = <&reg_3v3>;
+               clocks = <&mclk>;
+       };
+
+       polytouch: edt-ft5x06@38 {
+               compatible = "edt,edt-ft5x06";
+               reg = <0x38>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_edt_ft5x06>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+               reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+               wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
+               linux,wakeup;
+       };
+
+       touchscreen: tsc2007@48 {
+               compatible = "ti,tsc2007";
+               reg = <0x48>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tsc2007>;
+               interrupt-parent = <&gpio3>;
+               interrupts = <26 0>;
+               gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+               ti,x-plate-ohms = <660>;
+               linux,wakeup;
+       };
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog>;
+
+       imx6qdl-tx6 {
+               pinctrl_hog: hoggrp {
+                       fsl,pins = <
+                               MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x0b0b0 /* LED */
+                               MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0 /* ETN PHY RESET */
+                               MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0 /* ETN PHY INT */
+                       >;
+               };
+
+               pinctrl_disp0_1: disp0grp-1 {
+                       fsl,pins = <
+                               MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
+                               MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
+                               MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC                0x10 /* HSYNC */
+                               MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC                0x10 /* VSYNC */
+                               /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
+                               MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
+                               MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
+                               MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
+                               MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
+                               MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
+                               MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
+                               MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
+                               MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
+                               MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
+                               MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
+                               MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
+                               MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
+                               MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
+                               MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
+                               MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
+                               MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
+                               MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
+                               MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
+                               MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
+                               MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
+                               MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
+                               MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
+                               MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
+                       >;
+               };
+
+               pinctrl_disp0_2: disp0grp-2 {
+                       fsl,pins = <
+                               MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
+                               MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
+                               MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
+                               MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
+                               MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x10
+                               MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x10
+                               MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
+                               MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
+                               MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
+                               MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
+                               MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
+                               MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
+                               MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x10
+                               MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x10
+                               MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
+                               MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
+                               MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
+                               MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
+                               MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
+                               MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
+                               MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x10
+                               MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x10
+                               MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
+                               MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
+                               MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
+                               MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
+                               MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
+                               MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
+                       >;
+               };
+
+               pinctrl_ecspi2: ecspi2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
+                               MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
+                               MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI    0x0b0b0 /* CSPI_MOSI */
+                               MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO    0x0b0b0 /* CSPI_MISO */
+                               MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK    0x0b0b0 /* CSPI_SCLK */
+                       >;
+               };
+
+               pinctrl_edt_ft5x06: edt-ft5x06grp {
+                       fsl,pins = <
+                               MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* Interrupt */
+                               MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* Reset */
+                               MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x1b0b0 /* Wake */
+                       >;
+               };
+
+               pinctrl_enet1: enet1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x0b0b0
+                               MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x0b0b0
+                               MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x0b0b0
+                               MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x0b0b0
+                               MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x0b0b0
+                               MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x0b0b0
+                               MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x0b0b0
+                               MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40000031
+                       >;
+               };
+
+               pinctrl_enet2: enet2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x0b0b0
+                               MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x0b0b0
+                               MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x0b0b0
+                               MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x0b0b0
+                               MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x0b0b0
+                               MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x0b0b0
+                               MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x0b0b0
+                               MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40000031
+                       >;
+               };
+
+               pinctrl_enet_mdio: enet-mdiogrp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x0b0b0
+                               MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
+                       >;
+               };
+
+               pinctrl_etnphy_power: etnphy-pwrgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0 /* ETN PHY POWER */
+                       >;
+               };
+
+               pinctrl_flexcan1: flexcan1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b0b0
+                               MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b0b0
+                       >;
+               };
+
+               pinctrl_flexcan2: flexcan2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b0b0
+                               MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b0b0
+                       >;
+               };
+
+               pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x0b0b0 /* Flexcan XCVR enable */
+                       >;
+               };
+
+               pinctrl_gpmi_nand: gpminandgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
+                               MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
+                               MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
+                               MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
+                               MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
+                               MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
+                               MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
+                               MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
+                               MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
+                               MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
+                               MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
+                               MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
+                               MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
+                               MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
+                               MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
+                       >;
+               };
+
+               pinctrl_i2c_gpio: i2c-gpiogrp {
+                       fsl,pins = <
+                               MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x4001b8b1 /* I2C SCL */
+                               MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x4001b8b1 /* I2C SDA */
+                       >;
+               };
+
+               pinctrl_i2c2: i2c2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO00__I2C2_SCL          0x4001b8b1
+                               MX6UL_PAD_GPIO1_IO01__I2C2_SDA          0x4001b8b1
+                       >;
+               };
+
+               pinctrl_kpp: kppgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04     0x1b0b0
+                               MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05     0x1b0b0
+                               MX6UL_PAD_ENET2_TX_EN__KPP_COL06        0x1b0b0
+                               MX6UL_PAD_ENET2_RX_ER__KPP_COL07        0x1b0b0
+                               MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04     0x1b0b0
+                               MX6UL_PAD_ENET2_RX_EN__KPP_ROW05        0x1b0b0
+                               MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06     0x1b0b0
+                               MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07       0x1b0b0
+                       >;
+               };
+
+               pinctrl_lcd1_pwr: lcd1-pwrgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0 /* LCD Power Enable */
+                       >;
+               };
+
+               pinctrl_pwm5: pwm5grp {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_DQS__PWM5_OUT            0x0b0b0
+                       >;
+               };
+
+               pinctrl_sai2: sai2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x0b0b0 /* SSI1_RXD */
+                               MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x0b0b0 /* SSI1_TXD */
+                               MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x0b0b0 /* SSI1_CLK */
+                               MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x0b0b0 /* SSI1_FS */
+                       >;
+               };
+
+               pinctrl_spi_gpio: spi-gpiogrp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29     0x0b0b0 /* CSPI_SS */
+                               MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x0b0b0 /* CSPI_SS */
+                               MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x0b0b0 /* CSPI_MOSI */
+                               MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x0b0b0 /* CSPI_MISO */
+                               MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x0b0b0 /* CSPI_SCLK */
+                       >;
+               };
+
+               pinctrl_tsc2007: tsc2007grp {
+                       fsl,pins = <
+                               MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x1b0b0 /* Interrupt */
+                       >;
+               };
+
+               pinctrl_uart1: uart1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x0b0b0
+                               MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x0b0b0
+                       >;
+               };
+
+               pinctrl_uart1_rtscts: uart1_rtsctsgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x0b0b0
+                               MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x0b0b0
+                       >;
+               };
+
+               pinctrl_uart2: uart2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x0b0b0
+                               MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x0b0b0
+                       >;
+               };
+
+               pinctrl_uart2_rtscts: uart2_rtsctsgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x0b0b0
+                               MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x0b0b0
+                       >;
+               };
+
+               pinctrl_uart5: uart5grp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x0b0b0
+                               MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x0b0b0
+                       >;
+               };
+
+               pinctrl_uart5_rtscts: uart5_rtsctsgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x0b0b0
+                               MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x0b0b0
+                       >;
+               };
+
+               pinctrl_usbh1_oc: usbh1-ocgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x17059 /* USBH1_OC */
+                       >;
+               };
+
+               pinctrl_usbh1_vbus: usbh1-vbusgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x0b0b0 /* USBH1_VBUSEN */
+                       >;
+               };
+
+               pinctrl_usbotg_oc: usbotg-ocgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x17059 /* USBOTG_OC */
+                       >;
+               };
+
+               pinctrl_usbotg_vbus: usbotg-vbusgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x1b0b0 /* USBOTG_VBUSEN */
+                       >;
+               };
+
+               pinctrl_usdhc1: usdhc1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x070b1
+                               MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x07099
+                               MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x070b1
+                               MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x070b1
+                               MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x070b1
+                               MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x070b1
+                               /* SD1 CD */
+                               MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x170b0 /* SD1 CD */
+                       >;
+               };
+               pinctrl_usdhc2: usdhc2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x070b1
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x070b1
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x070b1
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x070b1
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x070b1
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x070b1
+                               /* eMMC RESET */
+                               MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170b0
+                       >;
+               };
+       };
+};
+
+&kpp {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_kpp>;
+       /* sample keymap */
+       /* row/col 0,1 are mapped to KPP row/col 6,7 */
+       linux,keymap = <
+               MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
+               MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
+               MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
+               MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
+               MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
+               MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
+               MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
+               MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
+               MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
+               MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
+               MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
+       >;
+       status = "okay";
+};
+
+&lcdif {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_disp0_1>;
+       lcd-supply = <&reg_lcd_pwr>;
+       display = <&display>;
+       status = "okay";
+
+       display: display@di0 {
+               bits-per-pixel = <32>;
+               bus-width = <24>;
+               status = "okay";
+
+               display-timings {
+                       VGA {
+                               clock-frequency = <25200000>;
+                               hactive = <640>;
+                               vactive = <480>;
+                               hback-porch = <48>;
+                               hsync-len = <96>;
+                               hfront-porch = <16>;
+                               vback-porch = <31>;
+                               vsync-len = <2>;
+                               vfront-porch = <12>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;
+                       };
+
+                       ETV570 {
+                               clock-frequency = <25200000>;
+                               hactive = <640>;
+                               vactive = <480>;
+                               hback-porch = <114>;
+                               hsync-len = <30>;
+                               hfront-porch = <16>;
+                               vback-porch = <32>;
+                               vsync-len = <3>;
+                               vfront-porch = <10>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;
+                       };
+
+                       ET0350 {
+                               clock-frequency = <6413760>;
+                               hactive = <320>;
+                               vactive = <240>;
+                               hback-porch = <34>;
+                               hsync-len = <34>;
+                               hfront-porch = <20>;
+                               vback-porch = <15>;
+                               vsync-len = <3>;
+                               vfront-porch = <4>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;
+                       };
+
+                       ET0430 {
+                               clock-frequency = <9009000>;
+                               hactive = <480>;
+                               vactive = <272>;
+                               hback-porch = <2>;
+                               hsync-len = <41>;
+                               hfront-porch = <2>;
+                               vback-porch = <2>;
+                               vsync-len = <10>;
+                               vfront-porch = <2>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <1>;
+                       };
+
+                       ET0500 {
+                               clock-frequency = <33264000>;
+                               hactive = <800>;
+                               vactive = <480>;
+                               hback-porch = <88>;
+                               hsync-len = <128>;
+                               hfront-porch = <40>;
+                               vback-porch = <33>;
+                               vsync-len = <2>;
+                               vfront-porch = <10>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;
+                       };
+
+                       ET0700 { /* same as ET0500 */
+                               clock-frequency = <33264000>;
+                               hactive = <800>;
+                               vactive = <480>;
+                               hback-porch = <88>;
+                               hsync-len = <128>;
+                               hfront-porch = <40>;
+                               vback-porch = <33>;
+                               vsync-len = <2>;
+                               vfront-porch = <10>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;
+                       };
+
+                       ETQ570 {
+                               clock-frequency = <6596040>;
+                               hactive = <320>;
+                               vactive = <240>;
+                               hback-porch = <38>;
+                               hsync-len = <30>;
+                               hfront-porch = <30>;
+                               vback-porch = <16>;
+                               vsync-len = <3>;
+                               vfront-porch = <4>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               de-active = <1>;
+                               pixelclk-active = <0>;
+                       };
+               };
+       };
+};
+
+&pwm5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm5>;
+       #pwm-cells = <3>;
+       status = "okay";
+};
+
+&sai2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai2>;
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
+       status = "okay";
+};
+
+&uart5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
+       status = "okay";
+};
+
+&usbotg2 {
+       vbus-supply = <&reg_usbh1_vbus>;
+       dr_mode = "host";
+       disable-over-current;
+       status = "okay";
+};
+
+&usbotg1 {
+       vbus-supply = <&reg_usbotg_vbus>;
+       dr_mode = "peripheral";
+       disable-over-current;
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       bus-width = <4>;
+       no-1-8-v;
+       cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
+       fsl,wp-controller;
+       status = "okay";
+};
index b676389..993d1cb 100644 (file)
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/clock/imx6ul-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "imx6ul-pinfunc.h"
 #include "skeleton.dtsi"
                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
+
+                               sai1: sai@02028000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx6q-ssi",
+                                                       "fsl,imx51-ssi";
+                                       reg = <0x02028000 0x4000>;
+                                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
+                                                <&clks IMX6UL_CLK_SAI1>;
+                                       clock-names = "ipg", "baud";
+                                       dmas = <&sdma 35 1 0>,
+                                              <&sdma 36 1 0>;
+                                       dma-names = "rx", "tx";
+                                       fsl,fifo-depth = <15>;
+                                       status = "disabled";
+                               };
+
+                               sai2: sai@0202c000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx6q-ssi",
+                                                       "fsl,imx51-ssi";
+                                       reg = <0x0202c000 0x4000>;
+                                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
+                                                <&clks IMX6UL_CLK_SAI2>;
+                                       clock-names = "ipg", "baud";
+                                       dmas = <&sdma 37 1 0>,
+                                              <&sdma 38 1 0>;
+                                       dma-names = "rx", "tx";
+                                       fsl,fifo-depth = <15>;
+                                       status = "disabled";
+                               };
+
+                               sai3: sai@02030000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx6q-ssi",
+                                                       "fsl,imx51-ssi";
+                                       reg = <0x02030000 0x4000>;
+                                       interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
+                                                <&clks IMX6UL_CLK_SAI3>;
+                                       clock-names = "ipg", "baud";
+                                       dmas = <&sdma 39 1 0>,
+                                              <&sdma 40 1 0>;
+                                       dma-names = "rx", "tx";
+                                       fsl,fifo-depth = <15>;
+                                       status = "disabled";
+                               };
+                       };
+
+                       tsc: tsc@02040000 {
+                               compatible = "fsl,imx6ul-tsc";
+                               reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
+                               interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_IPG>,
+                                        <&clks IMX6UL_CLK_ADC2>;
+                               clock-names = "tsc", "adc";
+                               status = "disabled";
+                       };
+
+                       can1: flexcan@02090000 {
+                               compatible = "fsl,imx6q-flexcan";
+                               reg = <0x02090000 0x4000>;
+                               interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
+                                        <&clks IMX6UL_CLK_CAN1_SERIAL>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
+                       };
+
+                       can2: flexcan@02094000 {
+                               compatible = "fsl,imx6q-flexcan";
+                               reg = <0x02094000 0x4000>;
+                               interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
+                                        <&clks IMX6UL_CLK_CAN2_SERIAL>;
+                               clock-names = "ipg", "per";
+                               status = "disabled";
                        };
 
                        gpt1: gpt@02098000 {
                                status = "disabled";
                        };
 
+                       kpp: kpp@020b8000 {
+                               compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
+                               reg = <0x020b8000 0x4000>;
+                               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_KPP>;
+                               status = "disabled";
+                       };
+
                        wdog1: wdog@020bc000 {
                                compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
                                reg = <0x020bc000 0x4000>;
                                compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
                                reg = <0x020e8000 0x4000>;
                                interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_DUMMY>,
-                                        <&clks IMX6UL_CLK_DUMMY>;
+                               clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
+                                        <&clks IMX6UL_CLK_GPT2_SERIAL>;
                                clock-names = "ipg", "per";
                        };
 
+                       sdma: sdma@020ec000 {
+                               compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+                               reg = <0x020ec000 0x4000>;
+                               interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_SDMA>,
+                                        <&clks IMX6UL_CLK_SDMA>;
+                               clock-names = "ipg", "ahb";
+                               #dma-cells = <3>;
+                               fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+                       };
+
                        pwm5: pwm@020f0000 {
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x020f0000 0x4000>;
                                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_DUMMY>,
-                                        <&clks IMX6UL_CLK_DUMMY>;
+                               clocks = <&clks IMX6UL_CLK_PWM5>,
+                                        <&clks IMX6UL_CLK_PWM5>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
                        };
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x020f4000 0x4000>;
                                interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_DUMMY>,
-                                        <&clks IMX6UL_CLK_DUMMY>;
+                               clocks = <&clks IMX6UL_CLK_PWM6>,
+                                        <&clks IMX6UL_CLK_PWM6>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
                        };
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x020f8000 0x4000>;
                                interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_DUMMY>,
-                                        <&clks IMX6UL_CLK_DUMMY>;
+                               clocks = <&clks IMX6UL_CLK_PWM7>,
+                                        <&clks IMX6UL_CLK_PWM7>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
                        };
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x020fc000 0x4000>;
                                interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_DUMMY>,
-                                        <&clks IMX6UL_CLK_DUMMY>;
+                               clocks = <&clks IMX6UL_CLK_PWM8>,
+                                        <&clks IMX6UL_CLK_PWM8>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
                        };
                                status = "disabled";
                        };
 
-                       tsc: tsc@02040000 {
-                               compatible = "fsl,imx6ul-tsc";
-                               reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
-                               interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-                                            <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_IPG>,
-                                        <&clks IMX6UL_CLK_ADC2>;
-                               clock-names = "tsc", "adc";
-                               status = "disabled";
-                       };
-
                        usdhc1: usdhc@02190000 {
                                compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
                                reg = <0x02190000 0x4000>;
index 01718d0..8c75cf8 100644 (file)
@@ -157,9 +157,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        clk_set_parent(clks[IMX6UL_PLL7_BYPASS], clks[IMX6UL_CLK_PLL7]);
 
        clks[IMX6UL_CLK_PLL1_SYS]       = imx_clk_fixed_factor("pll1_sys",      "pll1_bypass", 1, 1);
-       clks[IMX6UL_CLK_PLL2_BUS]       = imx_clk_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
-       clks[IMX6UL_CLK_PLL3_USB_OTG]   = imx_clk_gate("pll3_usb_otg",  "pll3_bypass", base + 0x10, 13);
-       clks[IMX6UL_CLK_PLL4_AUDIO]     = imx_clk_gate("pll4_audio",    "pll4_bypass", base + 0x70, 13);
+       clks[IMX6UL_CLK_PLL2_BUS]       = imx_clk_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
+       clks[IMX6UL_CLK_PLL3_USB_OTG]   = imx_clk_gate("pll3_usb_otg",  "pll3_bypass", base + 0x10, 13);
+       clks[IMX6UL_CLK_PLL4_AUDIO]     = imx_clk_gate("pll4_audio",    "pll4_bypass", base + 0x70, 13);
        clks[IMX6UL_CLK_PLL5_VIDEO]     = imx_clk_gate("pll5_video",    "pll5_bypass", base + 0xa0, 13);
        clks[IMX6UL_CLK_PLL6_ENET]      = imx_clk_gate("pll6_enet",     "pll6_bypass", base + 0xe0, 13);
        clks[IMX6UL_CLK_PLL7_USB_HOST]  = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
@@ -196,8 +196,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
                        base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
 
        clks[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20);
-       clks[IMX6UL_CLK_ENET_PTP_REF]   = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
-       clks[IMX6UL_CLK_ENET_PTP]       = imx_clk_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21);
+       clks[IMX6UL_CLK_ENET_PTP_REF]   = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
+       clks[IMX6UL_CLK_ENET_PTP]       = imx_clk_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21);
 
        clks[IMX6UL_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
                 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
@@ -210,8 +210,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 
        /*                                                 name         parent_name      mult  div */
        clks[IMX6UL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1,     2);
-       clks[IMX6UL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1,     6);
-       clks[IMX6UL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1,     8);
+       clks[IMX6UL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1,     6);
+       clks[IMX6UL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1,     8);
        clks[IMX6UL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",     "osc",           1,     8);
 
        np = ccm_node;
@@ -219,34 +219,34 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        WARN_ON(!base);
 
        clks[IMX6UL_CA7_SECONDARY_SEL]    = imx_clk_mux("ca7_secondary_sel", base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels));
-       clks[IMX6UL_CLK_STEP]             = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels));
-       clks[IMX6UL_CLK_PLL1_SW]          = imx_clk_mux_flags("pll1_sw",   base + 0x0c, 2,  1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0);
+       clks[IMX6UL_CLK_STEP]             = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels));
+       clks[IMX6UL_CLK_PLL1_SW]          = imx_clk_mux_flags("pll1_sw",   base + 0x0c, 2,  1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0);
        clks[IMX6UL_CLK_AXI_ALT_SEL]      = imx_clk_mux("axi_alt_sel",          base + 0x14, 7,  1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
-       clks[IMX6UL_CLK_AXI_SEL]          = imx_clk_mux_flags("axi_sel",        base + 0x14, 6,  1, axi_sels, ARRAY_SIZE(axi_sels), 0);
-       clks[IMX6UL_CLK_PERIPH_PRE]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
-       clks[IMX6UL_CLK_PERIPH2_PRE]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
+       clks[IMX6UL_CLK_AXI_SEL]          = imx_clk_mux_flags("axi_sel",        base + 0x14, 6,  1, axi_sels, ARRAY_SIZE(axi_sels), 0);
+       clks[IMX6UL_CLK_PERIPH_PRE]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
+       clks[IMX6UL_CLK_PERIPH2_PRE]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
        clks[IMX6UL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
        clks[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
-       clks[IMX6UL_CLK_EIM_SLOW_SEL]     = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
+       clks[IMX6UL_CLK_EIM_SLOW_SEL]     = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
        clks[IMX6UL_CLK_GPMI_SEL]         = imx_clk_mux("gpmi_sel",     base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels));
-       clks[IMX6UL_CLK_BCH_SEL]          = imx_clk_mux("bch_sel",      base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels));
+       clks[IMX6UL_CLK_BCH_SEL]          = imx_clk_mux("bch_sel",      base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels));
        clks[IMX6UL_CLK_USDHC2_SEL]       = imx_clk_mux("usdhc2_sel",   base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
        clks[IMX6UL_CLK_USDHC1_SEL]       = imx_clk_mux("usdhc1_sel",   base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
-       clks[IMX6UL_CLK_SAI3_SEL]         = imx_clk_mux("sai3_sel",     base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels));
+       clks[IMX6UL_CLK_SAI3_SEL]         = imx_clk_mux("sai3_sel",     base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels));
        clks[IMX6UL_CLK_SAI2_SEL]         = imx_clk_mux("sai2_sel",     base + 0x1c, 12, 2, sai_sels, ARRAY_SIZE(sai_sels));
-       clks[IMX6UL_CLK_SAI1_SEL]         = imx_clk_mux("sai1_sel",     base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels));
-       clks[IMX6UL_CLK_QSPI1_SEL]        = imx_clk_mux("qspi1_sel",    base + 0x1c, 7,  3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
-       clks[IMX6UL_CLK_PERCLK_SEL]       = imx_clk_mux("perclk_sel",   base + 0x1c, 6,  1, perclk_sels, ARRAY_SIZE(perclk_sels));
-       clks[IMX6UL_CLK_CAN_SEL]          = imx_clk_mux("can_sel",      base + 0x20, 8,  2, can_sels, ARRAY_SIZE(can_sels));
+       clks[IMX6UL_CLK_SAI1_SEL]         = imx_clk_mux("sai1_sel",     base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels));
+       clks[IMX6UL_CLK_QSPI1_SEL]        = imx_clk_mux("qspi1_sel",    base + 0x1c, 7,  3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
+       clks[IMX6UL_CLK_PERCLK_SEL]       = imx_clk_mux("perclk_sel",   base + 0x1c, 6,  1, perclk_sels, ARRAY_SIZE(perclk_sels));
+       clks[IMX6UL_CLK_CAN_SEL]          = imx_clk_mux("can_sel",      base + 0x20, 8,  2, can_sels, ARRAY_SIZE(can_sels));
        clks[IMX6UL_CLK_UART_SEL]         = imx_clk_mux("uart_sel",     base + 0x24, 6,  1, uart_sels, ARRAY_SIZE(uart_sels));
        clks[IMX6UL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",     base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels));
        clks[IMX6UL_CLK_LDB_DI0_SEL]      = imx_clk_mux("ldb_di0_sel",  base + 0x2c, 9,  3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
        clks[IMX6UL_CLK_SPDIF_SEL]        = imx_clk_mux("spdif_sel",    base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
-       clks[IMX6UL_CLK_SIM_PRE_SEL]      = imx_clk_mux("sim_pre_sel",  base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
-       clks[IMX6UL_CLK_SIM_SEL]          = imx_clk_mux("sim_sel",      base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
+       clks[IMX6UL_CLK_SIM_PRE_SEL]      = imx_clk_mux("sim_pre_sel",  base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
+       clks[IMX6UL_CLK_SIM_SEL]          = imx_clk_mux("sim_sel",      base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
        clks[IMX6UL_CLK_ECSPI_SEL]        = imx_clk_mux("ecspi_sel",    base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
        clks[IMX6UL_CLK_LCDIF_PRE_SEL]    = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
-       clks[IMX6UL_CLK_LCDIF_SEL]        = imx_clk_mux("lcdif_sel",    base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
+       clks[IMX6UL_CLK_LCDIF_SEL]        = imx_clk_mux("lcdif_sel",    base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
 
        clks[IMX6UL_CLK_LDB_DI0_DIV_SEL]  = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
        clks[IMX6UL_CLK_LDB_DI1_DIV_SEL]  = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
@@ -259,11 +259,11 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        clks[IMX6UL_CLK_PERIPH]  = imx_clk_busy_mux("periph",  base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
        clks[IMX6UL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
 
-       clks[IMX6UL_CLK_PERIPH_CLK2]    = imx_clk_divider("periph_clk2",   "periph_clk2_sel",   base + 0x14, 27, 3);
-       clks[IMX6UL_CLK_PERIPH2_CLK2]   = imx_clk_divider("periph2_clk2",  "periph2_clk2_sel",  base + 0x14, 0,  3);
+       clks[IMX6UL_CLK_PERIPH_CLK2]    = imx_clk_divider("periph_clk2",   "periph_clk2_sel",   base + 0x14, 27, 3);
+       clks[IMX6UL_CLK_PERIPH2_CLK2]   = imx_clk_divider("periph2_clk2",  "periph2_clk2_sel",  base + 0x14, 0,  3);
        clks[IMX6UL_CLK_IPG]            = imx_clk_divider("ipg",           "ahb",               base + 0x14, 8,  2);
        clks[IMX6UL_CLK_LCDIF_PODF]     = imx_clk_divider("lcdif_podf",    "lcdif_pred",        base + 0x18, 23, 3);
-       clks[IMX6UL_CLK_QSPI1_PDOF]     = imx_clk_divider("qspi1_podf",    "qspi1_sel",         base + 0x1c, 26, 3);
+       clks[IMX6UL_CLK_QSPI1_PDOF]     = imx_clk_divider("qspi1_podf",    "qspi1_sel",         base + 0x1c, 26, 3);
        clks[IMX6UL_CLK_EIM_SLOW_PODF]  = imx_clk_divider("eim_slow_podf", "eim_slow_sel",      base + 0x1c, 23, 3);
        clks[IMX6UL_CLK_PERCLK]         = imx_clk_divider("perclk",        "perclk_sel",        base + 0x1c, 0,  6);
        clks[IMX6UL_CLK_CAN_PODF]       = imx_clk_divider("can_podf",      "can_sel",           base + 0x20, 2,  6);
@@ -287,14 +287,14 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        clks[IMX6UL_CLK_LCDIF_PRED]     = imx_clk_divider("lcdif_pred",    "lcdif_pre_sel",     base + 0x38, 12, 3);
        clks[IMX6UL_CLK_CSI_PODF]       = imx_clk_divider("csi_podf",      "csi_sel",           base + 0x3c, 11, 3);
 
-       clks[IMX6UL_CLK_ARM]            = imx_clk_busy_divider("arm",       "pll1_sw",  base +  0x10, 0,  3,  base + 0x48, 16);
+       clks[IMX6UL_CLK_ARM]            = imx_clk_busy_divider("arm",       "pll1_sw",  base +  0x10, 0,  3,  base + 0x48, 16);
        clks[IMX6UL_CLK_MMDC_PODF]      = imx_clk_busy_divider("mmdc_podf", "periph2",  base +  0x14, 3,  3,  base + 0x48, 2);
        clks[IMX6UL_CLK_AXI_PODF]       = imx_clk_busy_divider("axi_podf",  "axi_sel",  base +  0x14, 16, 3,  base + 0x48, 0);
        clks[IMX6UL_CLK_AHB]            = imx_clk_busy_divider("ahb",       "periph",   base +  0x14, 10, 3,  base + 0x48, 1);
 
        /* CCGR0 */
-       clks[IMX6UL_CLK_AIPSTZ1]        = imx_clk_gate2("aips_tz1",     "ahb",          base + 0x68,    0);
-       clks[IMX6UL_CLK_AIPSTZ2]        = imx_clk_gate2("aips_tz2",     "ahb",          base + 0x68,    2);
+       clks[IMX6UL_CLK_AIPSTZ1]        = imx_clk_gate2("aips_tz1",     "ahb",          base + 0x68,    0);
+       clks[IMX6UL_CLK_AIPSTZ2]        = imx_clk_gate2("aips_tz2",     "ahb",          base + 0x68,    2);
        clks[IMX6UL_CLK_APBHDMA]        = imx_clk_gate2("apbh_dma",     "bch_podf",     base + 0x68,    4);
        clks[IMX6UL_CLK_ASRC_IPG]       = imx_clk_gate2_shared("asrc_ipg",      "ahb",  base + 0x68,    6, &share_count_asrc);
        clks[IMX6UL_CLK_ASRC_MEM]       = imx_clk_gate2_shared("asrc_mem",      "ahb",  base + 0x68,    6, &share_count_asrc);
@@ -302,7 +302,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        clks[IMX6UL_CLK_CAAM_ACLK]      = imx_clk_gate2("caam_aclk",    "ahb",          base + 0x68,    10);
        clks[IMX6UL_CLK_CAAM_IPG]       = imx_clk_gate2("caam_ipg",     "ipg",          base + 0x68,    12);
        clks[IMX6UL_CLK_CAN1_IPG]       = imx_clk_gate2("can1_ipg",     "ipg",          base + 0x68,    14);
-       clks[IMX6UL_CLK_CAN1_SERIAL]    = imx_clk_gate2("can1_serial",  "can_podf",     base + 0x68,    16);
+       clks[IMX6UL_CLK_CAN1_SERIAL]    = imx_clk_gate2("can1_serial",  "can_podf",     base + 0x68,    16);
        clks[IMX6UL_CLK_CAN2_IPG]       = imx_clk_gate2("can2_ipg",     "ipg",          base + 0x68,    18);
        clks[IMX6UL_CLK_CAN2_SERIAL]    = imx_clk_gate2("can2_serial",  "can_podf",     base + 0x68,    20);
        clks[IMX6UL_CLK_GPT2_BUS]       = imx_clk_gate2("gpt_bus",      "perclk",       base + 0x68,    24);
@@ -331,7 +331,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        clks[IMX6UL_CLK_CSI]            = imx_clk_gate2("csi",          "csi_podf",             base + 0x70,    2);
        clks[IMX6UL_CLK_I2C1]           = imx_clk_gate2("i2c1",         "perclk",       base + 0x70,    6);
        clks[IMX6UL_CLK_I2C2]           = imx_clk_gate2("i2c2",         "perclk",       base + 0x70,    8);
-       clks[IMX6UL_CLK_I2C3]           = imx_clk_gate2("i2c3",         "perclk",       base + 0x70,    10);
+       clks[IMX6UL_CLK_I2C3]           = imx_clk_gate2("i2c3",         "perclk",       base + 0x70,    10);
        clks[IMX6UL_CLK_OCOTP]          = imx_clk_gate2("ocotp",        "ipg",          base + 0x70,    12);
        clks[IMX6UL_CLK_IOMUXC]         = imx_clk_gate2("iomuxc",       "lcdif_podf",   base + 0x70,    14);
        clks[IMX6UL_CLK_LCDIF_APB]      = imx_clk_gate2("lcdif_apb",    "axi",          base + 0x70,    28);
@@ -365,6 +365,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        /* CCGR5 */
        clks[IMX6UL_CLK_ROM]            = imx_clk_gate2("rom",          "ahb",          base + 0x7c,    0);
        clks[IMX6UL_CLK_SDMA]           = imx_clk_gate2("sdma",         "ahb",          base + 0x7c,    6);
+       clks[IMX6UL_CLK_KPP]            = imx_clk_gate2("kpp",          "ipg",          base + 0x7c,    8);
        clks[IMX6UL_CLK_WDOG2]          = imx_clk_gate2("wdog2",        "ipg",          base + 0x7c,    10);
        clks[IMX6UL_CLK_SPBA]           = imx_clk_gate2("spba",         "ipg",          base + 0x7c,    12);
        clks[IMX6UL_CLK_SPDIF]          = imx_clk_gate2_shared("spdif",         "spdif_podf",   base + 0x7c,    14, &share_count_audio);
@@ -391,7 +392,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        clks[IMX6UL_CLK_UART8_IPG]      = imx_clk_gate2("uart8_ipg",    "ipg",           base + 0x80,   14);
        clks[IMX6UL_CLK_UART8_SERIAL]   = imx_clk_gate2("uart8_serial", "uart_podf",     base + 0x80,   14);
        clks[IMX6UL_CLK_WDOG3]          = imx_clk_gate2("wdog3",        "ipg",           base + 0x80,   20);
-       clks[IMX6UL_CLK_I2C4]           = imx_clk_gate2("i2c4",         "perclk",        base + 0x80,   24);
+       clks[IMX6UL_CLK_I2C4]           = imx_clk_gate2("i2c4",         "perclk",        base + 0x80,   24);
        clks[IMX6UL_CLK_PWM5]           = imx_clk_gate2("pwm5",         "perclk",        base + 0x80,   26);
        clks[IMX6UL_CLK_PWM6]           = imx_clk_gate2("pwm6",         "perclk",        base + 0x80,   28);
        clks[IMX6UL_CLK_PWM7]           = imx_clk_gate2("Pwm7",         "perclk",        base + 0x80,   30);
index c343894..fd8aee8 100644 (file)
 #define IMX6UL_PLL5_BYPASS_SRC         8
 #define IMX6UL_PLL6_BYPASS_SRC         9
 #define IMX6UL_PLL7_BYPASS_SRC         10
-#define IMX6UL_CLK_PLL1                11
-#define IMX6UL_CLK_PLL2                12
-#define IMX6UL_CLK_PLL3                13
-#define IMX6UL_CLK_PLL4                14
-#define IMX6UL_CLK_PLL5                15
-#define IMX6UL_CLK_PLL6                16
-#define IMX6UL_CLK_PLL7                17
+#define IMX6UL_CLK_PLL1                        11
+#define IMX6UL_CLK_PLL2                        12
+#define IMX6UL_CLK_PLL3                        13
+#define IMX6UL_CLK_PLL4                        14
+#define IMX6UL_CLK_PLL5                        15
+#define IMX6UL_CLK_PLL6                        16
+#define IMX6UL_CLK_PLL7                        17
 #define IMX6UL_PLL1_BYPASS             18
 #define IMX6UL_PLL2_BYPASS             19
 #define IMX6UL_PLL3_BYPASS             20
@@ -37,7 +37,7 @@
 #define IMX6UL_PLL7_BYPASS             24
 #define IMX6UL_CLK_PLL1_SYS            25
 #define IMX6UL_CLK_PLL2_BUS            26
-#define IMX6UL_CLK_PLL3_USB_OTG        27
+#define IMX6UL_CLK_PLL3_USB_OTG                27
 #define IMX6UL_CLK_PLL4_AUDIO          28
 #define IMX6UL_CLK_PLL5_VIDEO          29
 #define IMX6UL_CLK_PLL6_ENET           30
@@ -66,7 +66,7 @@
 #define IMX6UL_CLK_PLL2_198M           53
 #define IMX6UL_CLK_PLL3_80M            54
 #define IMX6UL_CLK_PLL3_60M            55
-#define IMX6UL_CLK_STEP                56
+#define IMX6UL_CLK_STEP                        56
 #define IMX6UL_CLK_PLL1_SW             57
 #define IMX6UL_CLK_AXI_ALT_SEL         58
 #define IMX6UL_CLK_AXI_SEL             59
@@ -78,7 +78,7 @@
 #define IMX6UL_CLK_USDHC2_SEL          65
 #define IMX6UL_CLK_BCH_SEL             66
 #define IMX6UL_CLK_GPMI_SEL            67
-#define IMX6UL_CLK_EIM_SLOW_SEL        68
+#define IMX6UL_CLK_EIM_SLOW_SEL                68
 #define IMX6UL_CLK_SPDIF_SEL           69
 #define IMX6UL_CLK_SAI1_SEL            70
 #define IMX6UL_CLK_SAI2_SEL            71
 #define IMX6UL_CLK_LDB_DI1_DIV_SEL     92
 #define IMX6UL_CLK_ARM                 93
 #define IMX6UL_CLK_PERIPH_CLK2         94
-#define IMX6UL_CLK_PERIPH2_CLK2        95
+#define IMX6UL_CLK_PERIPH2_CLK2                95
 #define IMX6UL_CLK_AHB                 96
-#define IMX6UL_CLK_MMDC_PODF           97
+#define IMX6UL_CLK_MMDC_PODF           97
 #define IMX6UL_CLK_AXI_PODF            98
 #define IMX6UL_CLK_PERCLK              99
 #define IMX6UL_CLK_IPG                 100
 #define IMX6UL_CLK_CAN_PODF            120
 #define IMX6UL_CLK_ECSPI_PODF          121
 #define IMX6UL_CLK_UART_PODF           122
-#define IMX6UL_CLK_ADC1                123
-#define IMX6UL_CLK_ADC2                124
+#define IMX6UL_CLK_ADC1                        123
+#define IMX6UL_CLK_ADC2                        124
 #define IMX6UL_CLK_AIPSTZ1             125
 #define IMX6UL_CLK_AIPSTZ2             126
 #define IMX6UL_CLK_AIPSTZ3             127
 #define IMX6UL_CLK_APBHDMA             128
 #define IMX6UL_CLK_ASRC_IPG            129
 #define IMX6UL_CLK_ASRC_MEM            130
-#define IMX6UL_CLK_GPMI_BCH_APB        131
-#define IMX6UL_CLK_GPMI_BCH            132
+#define IMX6UL_CLK_GPMI_BCH_APB                131
+#define IMX6UL_CLK_GPMI_BCH            132
 #define IMX6UL_CLK_GPMI_IO             133
 #define IMX6UL_CLK_GPMI_APB            134
 #define IMX6UL_CLK_CAAM_MEM            135
 #define IMX6UL_CLK_ECSPI3              141
 #define IMX6UL_CLK_ECSPI4              142
 #define IMX6UL_CLK_EIM                 143
-#define IMX6UL_CLK_ENET                144
+#define IMX6UL_CLK_ENET                        144
 #define IMX6UL_CLK_ENET_AHB            145
 #define IMX6UL_CLK_EPIT1               146
 #define IMX6UL_CLK_EPIT2               147
 #define IMX6UL_CLK_GPT1_SERIAL         153
 #define IMX6UL_CLK_GPT2_BUS            154
 #define IMX6UL_CLK_GPT2_SERIAL         155
-#define IMX6UL_CLK_I2C1                156
-#define IMX6UL_CLK_I2C2                157
-#define IMX6UL_CLK_I2C3                158
-#define IMX6UL_CLK_I2C4                159
-#define IMX6UL_CLK_IOMUXC              160
-#define IMX6UL_CLK_LCDIF_APB           161
-#define IMX6UL_CLK_LCDIF_PIX           162
-#define IMX6UL_CLK_MMDC_P0_FAST        163
-#define IMX6UL_CLK_MMDC_P0_IPG         164
-#define IMX6UL_CLK_OCOTP               165
-#define IMX6UL_CLK_OCRAM               166
-#define IMX6UL_CLK_PWM1                167
-#define IMX6UL_CLK_PWM2                168
-#define IMX6UL_CLK_PWM3                169
-#define IMX6UL_CLK_PWM4                170
-#define IMX6UL_CLK_PWM5                171
-#define IMX6UL_CLK_PWM6                172
-#define IMX6UL_CLK_PWM7                173
-#define IMX6UL_CLK_PWM8                174
-#define IMX6UL_CLK_PXP                 175
-#define IMX6UL_CLK_QSPI                176
-#define IMX6UL_CLK_ROM                 177
-#define IMX6UL_CLK_SAI1                178
-#define IMX6UL_CLK_SAI1_IPG            179
-#define IMX6UL_CLK_SAI2                180
-#define IMX6UL_CLK_SAI2_IPG            181
-#define IMX6UL_CLK_SAI3                182
-#define IMX6UL_CLK_SAI3_IPG            183
-#define IMX6UL_CLK_SDMA                184
-#define IMX6UL_CLK_SIM                 185
-#define IMX6UL_CLK_SIM_S               186
-#define IMX6UL_CLK_SPBA                187
-#define IMX6UL_CLK_SPDIF               188
-#define IMX6UL_CLK_UART1_IPG           189
-#define IMX6UL_CLK_UART1_SERIAL        190
-#define IMX6UL_CLK_UART2_IPG           191
-#define IMX6UL_CLK_UART2_SERIAL        192
-#define IMX6UL_CLK_UART3_IPG           193
-#define IMX6UL_CLK_UART3_SERIAL        194
-#define IMX6UL_CLK_UART4_IPG           195
-#define IMX6UL_CLK_UART4_SERIAL        196
-#define IMX6UL_CLK_UART5_IPG           197
-#define IMX6UL_CLK_UART5_SERIAL        198
-#define IMX6UL_CLK_UART6_IPG           199
-#define IMX6UL_CLK_UART6_SERIAL        200
-#define IMX6UL_CLK_UART7_IPG           201
-#define IMX6UL_CLK_UART7_SERIAL        202
-#define IMX6UL_CLK_UART8_IPG           203
-#define IMX6UL_CLK_UART8_SERIAL        204
-#define IMX6UL_CLK_USBOH3              205
-#define IMX6UL_CLK_USDHC1              206
-#define IMX6UL_CLK_USDHC2              207
-#define IMX6UL_CLK_WDOG1               208
-#define IMX6UL_CLK_WDOG2               209
-#define IMX6UL_CLK_WDOG3               210
+#define IMX6UL_CLK_I2C1                        156
+#define IMX6UL_CLK_I2C2                        157
+#define IMX6UL_CLK_I2C3                        158
+#define IMX6UL_CLK_I2C4                        159
+#define IMX6UL_CLK_IOMUXC              160
+#define IMX6UL_CLK_LCDIF_APB           161
+#define IMX6UL_CLK_LCDIF_PIX           162
+#define IMX6UL_CLK_MMDC_P0_FAST                163
+#define IMX6UL_CLK_MMDC_P0_IPG         164
+#define IMX6UL_CLK_OCOTP               165
+#define IMX6UL_CLK_OCRAM               166
+#define IMX6UL_CLK_PWM1                        167
+#define IMX6UL_CLK_PWM2                        168
+#define IMX6UL_CLK_PWM3                        169
+#define IMX6UL_CLK_PWM4                        170
+#define IMX6UL_CLK_PWM5                        171
+#define IMX6UL_CLK_PWM6                        172
+#define IMX6UL_CLK_PWM7                        173
+#define IMX6UL_CLK_PWM8                        174
+#define IMX6UL_CLK_PXP                 175
+#define IMX6UL_CLK_QSPI                        176
+#define IMX6UL_CLK_ROM                 177
+#define IMX6UL_CLK_SAI1                        178
+#define IMX6UL_CLK_SAI1_IPG            179
+#define IMX6UL_CLK_SAI2                        180
+#define IMX6UL_CLK_SAI2_IPG            181
+#define IMX6UL_CLK_SAI3                        182
+#define IMX6UL_CLK_SAI3_IPG            183
+#define IMX6UL_CLK_SDMA                        184
+#define IMX6UL_CLK_SIM                 185
+#define IMX6UL_CLK_SIM_S               186
+#define IMX6UL_CLK_SPBA                        187
+#define IMX6UL_CLK_SPDIF               188
+#define IMX6UL_CLK_UART1_IPG           189
+#define IMX6UL_CLK_UART1_SERIAL                190
+#define IMX6UL_CLK_UART2_IPG           191
+#define IMX6UL_CLK_UART2_SERIAL                192
+#define IMX6UL_CLK_UART3_IPG           193
+#define IMX6UL_CLK_UART3_SERIAL                194
+#define IMX6UL_CLK_UART4_IPG           195
+#define IMX6UL_CLK_UART4_SERIAL                196
+#define IMX6UL_CLK_UART5_IPG           197
+#define IMX6UL_CLK_UART5_SERIAL                198
+#define IMX6UL_CLK_UART6_IPG           199
+#define IMX6UL_CLK_UART6_SERIAL                200
+#define IMX6UL_CLK_UART7_IPG           201
+#define IMX6UL_CLK_UART7_SERIAL                202
+#define IMX6UL_CLK_UART8_IPG           203
+#define IMX6UL_CLK_UART8_SERIAL                204
+#define IMX6UL_CLK_USBOH3              205
+#define IMX6UL_CLK_USDHC1              206
+#define IMX6UL_CLK_USDHC2              207
+#define IMX6UL_CLK_WDOG1               208
+#define IMX6UL_CLK_WDOG2               209
+#define IMX6UL_CLK_WDOG3               210
 #define IMX6UL_CLK_LDB_DI0             211
-#define IMX6UL_CLK_AXI                 212
+#define IMX6UL_CLK_AXI                 212
 #define IMX6UL_CLK_SPDIF_GCLK          213
 #define IMX6UL_CLK_GPT_3M              214
 #define IMX6UL_CLK_SIM2                        215
 #define IMX6UL_CLK_CSI_SEL             221
 #define IMX6UL_CLK_CSI_PODF            222
 #define IMX6UL_CLK_PLL3_120M           223
+#define IMX6UL_CLK_KPP                 224
 
-#define IMX6UL_CLK_END                 224
+#define IMX6UL_CLK_END                 225
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */