clk: qcom: ipq4019: correct sdcc frequency and parent name

1. The parent for sdcc clock is sdccpll.
2. The frequency value was wrong so modified the same.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index f4780c0aaeee043d78c76b572fe5123cfeafcf7c..62a36e05dcde6721d95660fcd905d4fee59309af 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -124,7 +124,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = {
 
 static const char * const gcc_xo_sdcc1_500[] = {
        "xo",
-       "ddrpll",
+       "ddrpllsdcc",
        "fepll500",
 };
 
@@ -549,7 +549,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
        F(25000000,  P_FEPLL500,                1,  1, 20),
        F(50000000,  P_FEPLL500,                1,  1, 10),
        F(100000000, P_FEPLL500,                1,  1, 5),
-       F(193000000, P_DDRPLL,          1,  0, 0),
+       F(192000000, P_DDRPLL,                  1,  0, 0),
        { }
 };