MLK-9961-2 Revert "MLK-10007-02 arm: imx: enable pll1 when changing arm_podf value"

This reverts commit 09bcfcabc08a57bce3000677052d5a2fcc2b1b68.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>

diff --git a/arch/arm/mach-imx/busfreq-imx6.c b/arch/arm/mach-imx/busfreq-imx6.c
index 0d74b9671d4747f2f6b9876266fe7f1092242c2e..5f7649bc5a1a31d19348922579ca6e9545c98474 100644 (file)
--- a/arch/arm/mach-imx/busfreq-imx6.c
+++ b/arch/arm/mach-imx/busfreq-imx6.c
@@ -288,13 +288,9 @@ static void enter_lpm_imx6sl(void)
                        imx_clk_set_parent(pll1_sw_clk, step_clk);
                        /*
                         * Ensure that the clock will be
-                        * at original speed. the arm_podf can only be
-                        * changed when the pll1 output is enabled. So
-                        * enable pll1 output before change cpu_clk.
+                        * at original speed.
                         */
-                       imx6sl_enable_pll_arm(true);
                        imx_clk_set_rate(cpu_clk, org_arm_rate);
-                       imx6sl_enable_pll_arm(false);
                }
                low_bus_freq_mode = 0;
                ultra_low_bus_freq_mode = 0;
@@ -406,14 +402,7 @@ static void exit_lpm_imx6sl(void)
                /* Move ARM from PLL1_SW_CLK to PLL2_400. */
                imx_clk_set_parent(step_clk, pll2_400);
                imx_clk_set_parent(pll1_sw_clk, step_clk);
-               /*
-                * arm_podf can only be changed when pll1 output
-                * is enabled. Enable pll1 output before changing
-                * cpu_clk rate.
-                */
-               imx6sl_enable_pll_arm(true);
                imx_clk_set_rate(cpu_clk, org_arm_rate);
-               imx6sl_enable_pll_arm(false);
                ultra_low_bus_freq_mode = 0;
        }
 }

diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 78961c50c197473250c361ed4d22f44adf35c15b..17ebe1b748b5cbaba780894d8ad89610d1bcb9c8 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -35,7 +35,6 @@
 #define BM_PLL_ARM_DIV_SELECT  (0x7f << 0)
 #define BM_PLL_ARM_POWERDOWN   (1 << 12)
 #define BM_PLL_ARM_ENABLE      (1 << 13)
-#define BM_PLL_ARM_BYPASS      (1 << 16)
 #define BM_PLL_ARM_LOCK                (1 << 31)
 #define PLL_ARM_DIV_792M       66
 
@@ -151,7 +150,7 @@ static int imx6sl_get_arm_divider_for_wait(void)
        }
 }
 
-void imx6sl_enable_pll_arm(bool enable)
+static void imx6sl_enable_pll_arm(bool enable)
 {
        static u32 saved_pll_arm;
        u32 val;
@@ -159,8 +158,10 @@ void imx6sl_enable_pll_arm(bool enable)
        if (enable) {
                saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
                val |= BM_PLL_ARM_ENABLE;
-               val |= BM_PLL_ARM_BYPASS;
+               val &= ~BM_PLL_ARM_POWERDOWN;
                writel_relaxed(val, anatop_base + PLL_ARM);
+               while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
+                       ;
        } else {
                 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
        }

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 54201afeb7555c4aa92b6f88a2cab6a6e6541fd5..1d2cd61e5084fa536e4fd916aac076e33d46f91e 100644 (file)
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -154,7 +154,6 @@ void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
 void imx6q_set_int_mem_clk_lpm(bool enable);
-void imx6sl_enable_pll_arm(bool enable);
 void imx6sl_set_wait_clk(bool enter);
 void imx6_enet_mac_init(const char *compatible);
 int imx_mmdc_get_ddr_type(void);