ARM: dts: add SDC2 and SDC4 to the MSM8660 family

To make the picture complete, add DTS entries also for the
second and fourth MMC/SD blocks on the MSM8660. SDC2 is
an 8-bit interface and SDC4 is a 4-bit interface.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 91c9a62ae7250184147c9750e417d39f54915827..747669a62aa82ff9520b9f3d0bb1f9210b7714c5 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -392,6 +392,21 @@
                                cap-mmc-highspeed;
                        };
 
+                       sdcc2: sdcc@12140000 {
+                               status          = "disabled";
+                               compatible      = "arm,pl18x", "arm,primecell";
+                               arm,primecell-periphid = <0x00051180>;
+                               reg             = <0x12140000 0x8000>;
+                               interrupts      = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "cmd_irq";
+                               clocks          = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
+                               clock-names     = "mclk", "apb_pclk";
+                               bus-width       = <8>;
+                               max-frequency   = <48000000>;
+                               cap-sd-highspeed;
+                               cap-mmc-highspeed;
+                       };
+
                        sdcc3: sdcc@12180000 {
                                compatible      = "arm,pl18x", "arm,primecell";
                                arm,primecell-periphid = <0x00051180>;
@@ -408,6 +423,21 @@
                                no-1-8-v;
                        };
 
+                       sdcc4: sdcc@121c0000 {
+                               compatible      = "arm,pl18x", "arm,primecell";
+                               arm,primecell-periphid = <0x00051180>;
+                               status          = "disabled";
+                               reg             = <0x121c0000 0x8000>;
+                               interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "cmd_irq";
+                               clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
+                               clock-names     = "mclk", "apb_pclk";
+                               bus-width       = <4>;
+                               max-frequency   = <48000000>;
+                               cap-sd-highspeed;
+                               cap-mmc-highspeed;
+                       };
+
                        sdcc5: sdcc@12200000 {
                                compatible      = "arm,pl18x", "arm,primecell";
                                arm,primecell-periphid = <0x00051180>;