ENGR00286961-3 ARM: dtsi: imx6qdl: Use non-default value for audmux pinctrl

It's better to specify pinctrl value so that we can clearly know what the
exact configuration they are. Also, when we need to set pinctrl state from
another state to default one, it must be given the exact values of pinctrl.

And this patch also sets TXD iomux to PUE keep. This would force TXD pin not
to pull down its signal during an unused state so that it won't distort its
output signal during that state.

Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <b42378@freescale.com>

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index a6f7df397a300db95a83a24dd3c2fd1b77884134..afaa70615a66785605591e63b1563367ba2a1289 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1124,27 +1124,27 @@
        audmux {
                pinctrl_audmux_1: audmux-1 {
                        fsl,pins = <
-                               MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
-                               MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
-                               MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
-                               MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
+                               MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x130b0
+                               MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x130b0
+                               MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x110b0
+                               MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
                        >;
                };
 
                pinctrl_audmux_2: audmux-2 {
                        fsl,pins = <
-                               MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
-                               MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
-                               MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
-                               MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+                               MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x130b0
+                               MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x130b0
+                               MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x110b0
+                               MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
                        >;
                };
 
                pinctrl_audmux_3: audmux-3 {
                        fsl,pins = <
-                               MX6QDL_PAD_DISP0_DAT16__AUD5_TXC  0x80000000
-                               MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
-                               MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
+                               MX6QDL_PAD_DISP0_DAT16__AUD5_TXC  0x130b0
+                               MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
+                               MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x130b0
                        >;
                };
        };