--- /dev/null
+Ingenic jz47xx GPIO controller
+
+That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl
+driver node.
+
+Required properties:
+--------------------
+
+ - compatible: Must contain one of:
+ - "ingenic,jz4740-gpio"
+ - "ingenic,jz4770-gpio"
+ - "ingenic,jz4780-gpio"
+ - reg: The GPIO bank number.
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - interrupts: Interrupt specifier for the controllers interrupt.
+ - #interrupt-cells: Should be 2. Refer to
+ ../interrupt-controller/interrupts.txt for more details.
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+ cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
+ GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
+ - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
+ 'gpio.txt' in this directory for more details.
+
+Example:
+--------
+
+&pinctrl {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpa: gpio@0 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ };
+};
--- /dev/null
+Ingenic jz47xx pin controller
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may
+be used as GPIOs, multiplexed device functions are configured within the
+GPIO port configuration registers and it is typical to refer to pins using the
+naming scheme "PxN" where x is a character identifying the GPIO port with
+which the pin is associated and N is an integer from 0 to 31 identifying the
+pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
+PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
+PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a
+total of 192 pins.
+
+
+Required properties:
+--------------------
+
+ - compatible: One of:
+ - "ingenic,jz4740-pinctrl"
+ - "ingenic,jz4770-pinctrl"
+ - "ingenic,jz4780-pinctrl"
+ - reg: Address range of the pinctrl registers.
+
+
+GPIO sub-nodes
+--------------
+
+The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver;
+please refer to ../gpio/ingenic,gpio.txt.
+
+
+Example:
+--------
+
+pinctrl: pin-controller@10010000 {
+ compatible = "ingenic,jz4740-pinctrl";
+ reg = <0x10010000 0x400>;
+};
--- /dev/null
+* ZTE ZX Pin Controller
+
+The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of
+a main controller and an auxiliary one. For example, on ZX296718 SoC, the
+main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both
+controllers work together to control pin multiplexing and configuration in
+the way illustrated as below.
+
+
+ GMII_RXD3 ---+
+ |
+ DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
+ |
+ BGPIO16 ---+ ^
+ | pinconf
+ ^ |
+ | pinmux |
+ | |
+
+ TOP_PMM (main) AON_IOCFG (aux)
+
+ | | |
+ | pinmux | |
+ | pinmux v |
+ v | pinconf
+ KEY_ROW2 ---+ v
+ PORT1_LCD_TE ---+ |
+ | AGPIO10 ---+------ KEY_ROW2 (AON pin)
+ I2S0_DOUT3 ---+ |
+ |-----------------------+
+ PWM_OUT3 ---+
+ |
+ VGA_VS1 ---+
+
+
+For most of pins like GMII_RXD3 in the figure, the pinmux function is
+controlled by TOP_PMM block only, and this type of pins are meant by term
+'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both
+TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for
+the pin spread in both controllers. This type of pins are called 'AON pins'.
+Though pinmux implementation is quite different, pinconf is same for both
+types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG
+on ZX296718.
+
+Required properties:
+- compatible: should be "zte,zx296718-pmm".
+- reg: the register physical address and length.
+- zte,auxiliary-controller: phandle to the auxiliary pin controller which
+ implements pinmux for AON pins and pinconf for all pins.
+
+The following pin configuration are supported. Please refer to
+pinctrl-bindings.txt in this directory for more details of the common
+pinctrl bindings used by client devices.
+
+- bias-pull-up
+- bias-pull-down
+- drive-strength
+- input-enable
+- slew-rate
+
+Examples:
+
+iocfg: pin-controller@119000 {
+ compatible = "zte,zx296718-iocfg";
+ reg = <0x119000 0x1000>;
+};
+
+pmm: pin-controller@1462000 {
+ compatible = "zte,zx296718-pmm";
+ reg = <0x1462000 0x1000>;
+ zte,auxiliary-controller = <&iocfg>;
+};
+
+&pmm {
+ vga_pins: vga {
+ pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2";
+ function = "VGA";
+ };
+};
+
+&vga {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vga_pins>;
+ status = "okay";
+};
select SYS_SUPPORTS_ZBOOT_UART16550
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
+ select PINCTRL
select GPIOLIB
select COMMON_CLK
select GENERIC_IRQ_CHIP
&uart0 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart0>;
};
&uart1 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart1>;
};
&uart3 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart2>;
};
&uart4 {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart4>;
};
&nemc {
ingenic,nemc-tAW = <15>;
ingenic,nemc-tSTRV = <100>;
+ /*
+ * Only CLE/ALE are needed for the devices that are connected, rather
+ * than the full address line set.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc>;
+
nand@1 {
reg = <1>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs1>;
+
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
&bch {
status = "okay";
};
+
+&pinctrl {
+ pins_uart0: uart0 {
+ function = "uart0";
+ groups = "uart0-data";
+ bias-disable;
+ };
+
+ pins_uart1: uart1 {
+ function = "uart1";
+ groups = "uart1-data";
+ bias-disable;
+ };
+
+ pins_uart2: uart2 {
+ function = "uart2";
+ groups = "uart2-data", "uart2-hwflow";
+ bias-disable;
+ };
+
+ pins_uart4: uart4 {
+ function = "uart4";
+ groups = "uart4-data";
+ bias-disable;
+ };
+
+ pins_nemc: nemc {
+ function = "nemc";
+ groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";
+ bias-disable;
+ };
+
+ pins_nemc_cs1: nemc-cs1 {
+ function = "nemc-cs1";
+ groups = "nemc-cs1";
+ bias-disable;
+ };
+};
clock-names = "rtc";
};
+ pinctrl: pin-controller@10010000 {
+ compatible = "ingenic,jz4740-pinctrl";
+ reg = <0x10010000 0x400>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpa: gpio@0 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ };
+
+ gpb: gpio@1 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <1>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27>;
+ };
+
+ gpc: gpio@2 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <2>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <26>;
+ };
+
+ gpd: gpio@3 {
+ compatible = "ingenic,jz4740-gpio";
+ reg = <3>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <25>;
+ };
+ };
+
uart0: serial@10030000 {
compatible = "ingenic,jz4740-uart";
reg = <0x10030000 0x100>;
#clock-cells = <1>;
};
+ pinctrl: pin-controller@10010000 {
+ compatible = "ingenic,jz4780-pinctrl";
+ reg = <0x10010000 0x600>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpa: gpio@0 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+ };
+
+ gpb: gpio@1 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <1>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <16>;
+ };
+
+ gpc: gpio@2 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <2>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <15>;
+ };
+
+ gpd: gpio@3 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <3>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <14>;
+ };
+
+ gpe: gpio@4 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <4>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <13>;
+ };
+
+ gpf: gpio@5 {
+ compatible = "ingenic,jz4780-gpio";
+ reg = <5>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 160 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+ };
+ };
+
uart0: serial@10030000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10030000 0x100>;
&rtc_dev {
system-power-controller;
};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart0>;
+};
+
+&pinctrl {
+ pins_uart0: uart0 {
+ function = "uart0";
+ groups = "uart0-data";
+ bias-disable;
+ };
+};
#ifndef _JZ_GPIO_H
#define _JZ_GPIO_H
-#include <linux/types.h>
-
-enum jz_gpio_function {
- JZ_GPIO_FUNC_NONE,
- JZ_GPIO_FUNC1,
- JZ_GPIO_FUNC2,
- JZ_GPIO_FUNC3,
-};
-
-/*
- Usually a driver for a SoC component has to request several gpio pins and
- configure them as function pins.
- jz_gpio_bulk_request can be used to ease this process.
- Usually one would do something like:
-
- static const struct jz_gpio_bulk_request i2c_pins[] = {
- JZ_GPIO_BULK_PIN(I2C_SDA),
- JZ_GPIO_BULK_PIN(I2C_SCK),
- };
-
- inside the probe function:
-
- ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
- if (ret) {
- ...
-
- inside the remove function:
-
- jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
-
-*/
-
-struct jz_gpio_bulk_request {
- int gpio;
- const char *name;
- enum jz_gpio_function function;
-};
-
-#define JZ_GPIO_BULK_PIN(pin) { \
- .gpio = JZ_GPIO_ ## pin, \
- .name = #pin, \
- .function = JZ_GPIO_FUNC_ ## pin \
-}
-
-int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
-void jz_gpio_enable_pullup(unsigned gpio);
-void jz_gpio_disable_pullup(unsigned gpio);
-int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
-
-int jz_gpio_port_direction_input(int port, uint32_t mask);
-int jz_gpio_port_direction_output(int port, uint32_t mask);
-void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
-uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
-
#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
-/* Port A function pins */
-#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
-#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
-#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
-#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
-#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
-#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
-#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
-#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
-#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
-#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
-#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
-#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
-#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
-#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
-#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
-#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
-#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
-#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
-#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
-#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
-#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
-#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
-#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
-#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
-#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
-#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
-#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
-#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
-#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
-#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
-#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
-#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
-
-#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
-
-/* Port B function pins */
-#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
-#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
-#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
-#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
-#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
-#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
-#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
-#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
-#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
-#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
-#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
-#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
-#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
-#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
-#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
-#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
-#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
-#define JZ_GPIO_LCD_CLS JZ_GPIO_PORTB(17)
-#define JZ_GPIO_LCD_SPL JZ_GPIO_PORTB(18)
-#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
-#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
-#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
-#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
-#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
-#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
-#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
-#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
-#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
-#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
-#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
-#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
-#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
-
-#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_SPL JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
-
-
-#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
-#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
-
-#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
-
-/* Port C function pins */
-#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
-#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
-#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
-#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
-#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
-#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
-#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
-#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
-#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
-#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
-#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
-#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
-#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
-#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
-#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
-#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
-#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
-#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
-#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
-#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
-#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
-#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
-#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
-#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
-#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
-#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
-#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
-#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
-#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
-#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
-
-#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
-
-
-#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
-#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
-
-#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
-
-/* Port D function pins */
-#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
-#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
-#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
-#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
-#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
-#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
-#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
-#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
-#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
-#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
-#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
-#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
-#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
-#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
-#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
-#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
-#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
-#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
-#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
-#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
-#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
-#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
-#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
-#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
-#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
-#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
-#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
-#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
-#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
-#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
-#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
-
-#define JZ_GPIO_FUNC_CIM_DATA JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC_CIM_DATA
-#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_DATA JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC_MSC_DATA
-#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC_MSC_DATA
-#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC_MSC_DATA
-#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC_MSC_DATA
-#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
-
-#define JZ_GPIO_FUNC_PWM JZ_GPIO_FUNC1
-#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC_PWM
-#define JZ_GPIO_FUNC_PWM7 JZ_GPIO_FUNC_PWM
-
-#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
-#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
-#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
-#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
-#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
-#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
-#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
-#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
-#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
-#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
-#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
-#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
-#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
-
-#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
-#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
-
-#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
-#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
-
-#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
-#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
-
#endif
obj-y += prom.o time.o reset.o setup.o \
platform.o timer.o
-obj-$(CONFIG_MACH_JZ4740) += gpio.o
-
CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
# board specific support
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/power_supply.h>
#include <linux/power/jz4740-battery.h>
#include <linux/power/gpio-charger.h>
static struct gpiod_lookup_table qi_lb60_nand_gpio_table = {
.dev_id = "jz4740-nand.0",
.table = {
- GPIO_LOOKUP("Bank C", 30, "busy", 0),
+ GPIO_LOOKUP("GPIOC", 30, "busy", 0),
{ },
},
};
static struct gpiod_lookup_table qi_lb60_audio_gpio_table = {
.dev_id = "qi-lb60-audio",
.table = {
- GPIO_LOOKUP("Bank B", 29, "snd", 0),
- GPIO_LOOKUP("Bank D", 4, "amp", 0),
+ GPIO_LOOKUP("GPIOB", 29, "snd", 0),
+ GPIO_LOOKUP("GPIOD", 4, "amp", 0),
{ },
},
};
&qi_lb60_audio_device,
};
-static void __init board_gpio_setup(void)
-{
- /* We only need to enable/disable pullup here for pins used in generic
- * drivers. Everything else is done by the drivers themselves. */
- jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N);
- jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD);
-}
+static unsigned long pin_cfg_bias_disable[] = {
+ PIN_CONFIG_BIAS_DISABLE,
+};
+
+static struct pinctrl_map pin_map[] __initdata = {
+ /* NAND pin configuration */
+ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand",
+ "10010000.jz4740-pinctrl", "nand", "nand-cs1"),
+
+ /* fbdev pin configuration */
+ PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT,
+ "10010000.jz4740-pinctrl", "lcd", "lcd-8bit"),
+ PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP,
+ "10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"),
+
+ /* MMC pin configuration */
+ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
+ "10010000.jz4740-pinctrl", "mmc", "mmc-1bit"),
+ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
+ "10010000.jz4740-pinctrl", "mmc", "mmc-4bit"),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
+ "10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
+ "10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable),
+
+ /* PWM pin configuration */
+ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm",
+ "10010000.jz4740-pinctrl", "pwm4", "pwm4"),
+};
+
static int __init qi_lb60_init_platform_devices(void)
{
ARRAY_SIZE(qi_lb60_spi_board_info));
pwm_add_table(qi_lb60_pwm_lookup, ARRAY_SIZE(qi_lb60_pwm_lookup));
+ pinctrl_register_mappings(pin_map, ARRAY_SIZE(pin_map));
return platform_add_devices(jz_platform_devices,
ARRAY_SIZE(jz_platform_devices));
{
printk(KERN_INFO "Qi Hardware JZ4740 QI LB60 setup\n");
- board_gpio_setup();
-
if (qi_lb60_init_platform_devices())
panic("Failed to initialize platform devices");
+++ /dev/null
-/*
- * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform GPIO support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/init.h>
-
-#include <linux/io.h>
-#include <linux/gpio/driver.h>
-/* FIXME: needed for gpio_request(), try to remove consumer API from driver */
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/irqchip/ingenic.h>
-#include <linux/bitops.h>
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-#include <asm/mach-jz4740/base.h>
-#include <asm/mach-jz4740/gpio.h>
-
-#define JZ4740_GPIO_BASE_A (32*0)
-#define JZ4740_GPIO_BASE_B (32*1)
-#define JZ4740_GPIO_BASE_C (32*2)
-#define JZ4740_GPIO_BASE_D (32*3)
-
-#define JZ4740_GPIO_NUM_A 32
-#define JZ4740_GPIO_NUM_B 32
-#define JZ4740_GPIO_NUM_C 31
-#define JZ4740_GPIO_NUM_D 32
-
-#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
-#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
-#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
-#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
-
-#define JZ_REG_GPIO_PIN 0x00
-#define JZ_REG_GPIO_DATA 0x10
-#define JZ_REG_GPIO_DATA_SET 0x14
-#define JZ_REG_GPIO_DATA_CLEAR 0x18
-#define JZ_REG_GPIO_MASK 0x20
-#define JZ_REG_GPIO_MASK_SET 0x24
-#define JZ_REG_GPIO_MASK_CLEAR 0x28
-#define JZ_REG_GPIO_PULL 0x30
-#define JZ_REG_GPIO_PULL_SET 0x34
-#define JZ_REG_GPIO_PULL_CLEAR 0x38
-#define JZ_REG_GPIO_FUNC 0x40
-#define JZ_REG_GPIO_FUNC_SET 0x44
-#define JZ_REG_GPIO_FUNC_CLEAR 0x48
-#define JZ_REG_GPIO_SELECT 0x50
-#define JZ_REG_GPIO_SELECT_SET 0x54
-#define JZ_REG_GPIO_SELECT_CLEAR 0x58
-#define JZ_REG_GPIO_DIRECTION 0x60
-#define JZ_REG_GPIO_DIRECTION_SET 0x64
-#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
-#define JZ_REG_GPIO_TRIGGER 0x70
-#define JZ_REG_GPIO_TRIGGER_SET 0x74
-#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
-#define JZ_REG_GPIO_FLAG 0x80
-#define JZ_REG_GPIO_FLAG_CLEAR 0x14
-
-#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
-#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
-#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
-
-struct jz_gpio_chip {
- unsigned int irq;
- unsigned int irq_base;
- uint32_t edge_trigger_both;
-
- void __iomem *base;
-
- struct gpio_chip gpio_chip;
-};
-
-static struct jz_gpio_chip jz4740_gpio_chips[];
-
-static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
-{
- return &jz4740_gpio_chips[gpio >> 5];
-}
-
-static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gc)
-{
- return gpiochip_get_data(gc);
-}
-
-static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
-{
- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- return gc->private;
-}
-
-static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
-{
- writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
-}
-
-int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
-{
- if (function == JZ_GPIO_FUNC_NONE) {
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
- } else {
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
- switch (function) {
- case JZ_GPIO_FUNC1:
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
- break;
- case JZ_GPIO_FUNC3:
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
- case JZ_GPIO_FUNC2: /* Falltrough */
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
- break;
- default:
- BUG();
- break;
- }
- }
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(jz_gpio_set_function);
-
-int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
- int ret;
-
- for (i = 0; i < num; ++i, ++request) {
- ret = gpio_request(request->gpio, request->name);
- if (ret)
- goto err;
- jz_gpio_set_function(request->gpio, request->function);
- }
-
- return 0;
-
-err:
- for (--request; i > 0; --i, --request) {
- gpio_free(request->gpio);
- jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
- }
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
-
-void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
-
- for (i = 0; i < num; ++i, ++request) {
- gpio_free(request->gpio);
- jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
- }
-
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
-
-void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
-
- for (i = 0; i < num; ++i, ++request) {
- jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
- jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
- }
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
-
-void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
-{
- size_t i;
-
- for (i = 0; i < num; ++i, ++request)
- jz_gpio_set_function(request->gpio, request->function);
-}
-EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
-
-void jz_gpio_enable_pullup(unsigned gpio)
-{
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
-}
-EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
-
-void jz_gpio_disable_pullup(unsigned gpio)
-{
- jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
-}
-EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
-
-static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
-}
-
-static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
- reg += !value;
- writel(BIT(gpio), reg);
-}
-
-static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
- int value)
-{
- writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
- jz_gpio_set_value(chip, gpio, value);
-
- return 0;
-}
-
-static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
-
- return 0;
-}
-
-static int jz_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-{
- struct jz_gpio_chip *jz_gpio = gpiochip_get_data(chip);
-
- return jz_gpio->irq_base + gpio;
-}
-
-int jz_gpio_port_direction_input(int port, uint32_t mask)
-{
- writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
-
- return 0;
-}
-EXPORT_SYMBOL(jz_gpio_port_direction_input);
-
-int jz_gpio_port_direction_output(int port, uint32_t mask)
-{
- writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
-
- return 0;
-}
-EXPORT_SYMBOL(jz_gpio_port_direction_output);
-
-void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
-{
- writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
- writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
-}
-EXPORT_SYMBOL(jz_gpio_port_set_value);
-
-uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
-{
- uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
-
- return value & mask;
-}
-EXPORT_SYMBOL(jz_gpio_port_get_value);
-
-#define IRQ_TO_BIT(irq) BIT((irq - JZ4740_IRQ_GPIO(0)) & 0x1f)
-
-static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
-{
- uint32_t value;
- void __iomem *reg;
- uint32_t mask = IRQ_TO_BIT(irq);
-
- if (!(chip->edge_trigger_both & mask))
- return;
-
- reg = chip->base;
-
- value = readl(chip->base + JZ_REG_GPIO_PIN);
- if (value & mask)
- reg += JZ_REG_GPIO_DIRECTION_CLEAR;
- else
- reg += JZ_REG_GPIO_DIRECTION_SET;
-
- writel(mask, reg);
-}
-
-static void jz_gpio_irq_demux_handler(struct irq_desc *desc)
-{
- uint32_t flag;
- unsigned int gpio_irq;
- struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
-
- flag = readl(chip->base + JZ_REG_GPIO_FLAG);
- if (!flag)
- return;
-
- gpio_irq = chip->irq_base + __fls(flag);
-
- jz_gpio_check_trigger_both(chip, gpio_irq);
-
- generic_handle_irq(gpio_irq);
-};
-
-static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
-{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
- writel(IRQ_TO_BIT(data->irq), chip->base + reg);
-}
-
-static void jz_gpio_irq_unmask(struct irq_data *data)
-{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
-
- jz_gpio_check_trigger_both(chip, data->irq);
- irq_gc_unmask_enable_reg(data);
-};
-
-/* TODO: Check if function is gpio */
-static unsigned int jz_gpio_irq_startup(struct irq_data *data)
-{
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
- jz_gpio_irq_unmask(data);
- return 0;
-}
-
-static void jz_gpio_irq_shutdown(struct irq_data *data)
-{
- irq_gc_mask_disable_reg(data);
-
- /* Set direction to input */
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
-}
-
-static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
-{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
- unsigned int irq = data->irq;
-
- if (flow_type == IRQ_TYPE_EDGE_BOTH) {
- uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
- if (value & IRQ_TO_BIT(irq))
- flow_type = IRQ_TYPE_EDGE_FALLING;
- else
- flow_type = IRQ_TYPE_EDGE_RISING;
- chip->edge_trigger_both |= IRQ_TO_BIT(irq);
- } else {
- chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
- }
-
- switch (flow_type) {
- case IRQ_TYPE_EDGE_RISING:
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
- break;
- case IRQ_TYPE_EDGE_FALLING:
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
- break;
- case IRQ_TYPE_LEVEL_HIGH:
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
- break;
- case IRQ_TYPE_LEVEL_LOW:
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
- jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
-{
- struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
-
- irq_gc_set_wake(data, on);
- irq_set_irq_wake(chip->irq, on);
-
- return 0;
-}
-
-#define JZ4740_GPIO_CHIP(_bank) { \
- .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
- .gpio_chip = { \
- .label = "Bank " # _bank, \
- .owner = THIS_MODULE, \
- .set = jz_gpio_set_value, \
- .get = jz_gpio_get_value, \
- .direction_output = jz_gpio_direction_output, \
- .direction_input = jz_gpio_direction_input, \
- .to_irq = jz_gpio_to_irq, \
- .base = JZ4740_GPIO_BASE_ ## _bank, \
- .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
- }, \
-}
-
-static struct jz_gpio_chip jz4740_gpio_chips[] = {
- JZ4740_GPIO_CHIP(A),
- JZ4740_GPIO_CHIP(B),
- JZ4740_GPIO_CHIP(C),
- JZ4740_GPIO_CHIP(D),
-};
-
-static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
-{
- struct irq_chip_generic *gc;
- struct irq_chip_type *ct;
-
- chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
-
- chip->irq = JZ4740_IRQ_INTC_GPIO(id);
- irq_set_chained_handler_and_data(chip->irq,
- jz_gpio_irq_demux_handler, chip);
-
- gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,
- chip->base, handle_level_irq);
-
- gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio);
- gc->private = chip;
-
- ct = gc->chip_types;
- ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR;
- ct->regs.disable = JZ_REG_GPIO_MASK_SET;
- ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR;
-
- ct->chip.name = "GPIO";
- ct->chip.irq_mask = irq_gc_mask_disable_reg;
- ct->chip.irq_unmask = jz_gpio_irq_unmask;
- ct->chip.irq_ack = irq_gc_ack_set_bit;
- ct->chip.irq_suspend = ingenic_intc_irq_suspend;
- ct->chip.irq_resume = ingenic_intc_irq_resume;
- ct->chip.irq_startup = jz_gpio_irq_startup;
- ct->chip.irq_shutdown = jz_gpio_irq_shutdown;
- ct->chip.irq_set_type = jz_gpio_irq_set_type;
- ct->chip.irq_set_wake = jz_gpio_irq_set_wake;
- ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
-
- irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio),
- IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL);
-
- gpiochip_add_data(&chip->gpio_chip, chip);
-}
-
-static int __init jz4740_gpio_init(void)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
- jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
-
- printk(KERN_INFO "JZ4740 GPIO initialized\n");
-
- return 0;
-}
-arch_initcall(jz4740_gpio_init);
-
-#ifdef CONFIG_DEBUG_FS
-
-static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
- const char *name, unsigned int reg)
-{
- seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
-}
-
-static int gpio_regs_show(struct seq_file *s, void *unused)
-{
- struct jz_gpio_chip *chip = jz4740_gpio_chips;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
- seq_printf(s, "==GPIO %d==\n", i);
- gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
- gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
- gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
- gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
- gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
- gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
- gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
- gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
- gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
- }
-
- return 0;
-}
-
-static int gpio_regs_open(struct inode *inode, struct file *file)
-{
- return single_open(file, gpio_regs_show, NULL);
-}
-
-static const struct file_operations gpio_regs_operations = {
- .open = gpio_regs_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init gpio_debugfs_init(void)
-{
- (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
- NULL, NULL, &gpio_regs_operations);
- return 0;
-}
-subsys_initcall(gpio_debugfs_init);
-
-#endif
If unsure, say N.
+config GPIO_INGENIC
+ tristate "Ingenic JZ47xx SoCs GPIO support"
+ depends on MACH_INGENIC || COMPILE_TEST
+ select GPIOLIB_IRQCHIP
+ help
+ Say yes here to support the GPIO functionality present on the
+ JZ4740 and JZ4780 SoCs from Ingenic.
+
+ If unsure, say N.
+
config GPIO_IOP
tristate "Intel IOP GPIO"
depends on ARCH_IOP32X || ARCH_IOP33X || COMPILE_TEST
obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o
obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o
obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
+obj-$(CONFIG_GPIO_INGENIC) += gpio-ingenic.o
obj-$(CONFIG_GPIO_IOP) += gpio-iop.o
obj-$(CONFIG_GPIO_IT87) += gpio-it87.o
obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
--- /dev/null
+/*
+ * Ingenic JZ47xx GPIO driver
+ *
+ * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/regmap.h>
+
+#define GPIO_PIN 0x00
+#define GPIO_MSK 0x20
+
+#define JZ4740_GPIO_DATA 0x10
+#define JZ4740_GPIO_SELECT 0x50
+#define JZ4740_GPIO_DIR 0x60
+#define JZ4740_GPIO_TRIG 0x70
+#define JZ4740_GPIO_FLAG 0x80
+
+#define JZ4770_GPIO_INT 0x10
+#define JZ4770_GPIO_PAT1 0x30
+#define JZ4770_GPIO_PAT0 0x40
+#define JZ4770_GPIO_FLAG 0x50
+
+#define REG_SET(x) ((x) + 0x4)
+#define REG_CLEAR(x) ((x) + 0x8)
+
+enum jz_version {
+ ID_JZ4740,
+ ID_JZ4770,
+ ID_JZ4780,
+};
+
+struct ingenic_gpio_chip {
+ struct regmap *map;
+ struct gpio_chip gc;
+ struct irq_chip irq_chip;
+ unsigned int irq, reg_base;
+ enum jz_version version;
+};
+
+static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
+{
+ unsigned int val;
+
+ regmap_read(jzgc->map, jzgc->reg_base + reg, &val);
+
+ return (u32) val;
+}
+
+static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
+ u8 reg, u8 offset, bool set)
+{
+ if (set)
+ reg = REG_SET(reg);
+ else
+ reg = REG_CLEAR(reg);
+
+ regmap_write(jzgc->map, jzgc->reg_base + reg, BIT(offset));
+}
+
+static inline bool gpio_get_value(struct ingenic_gpio_chip *jzgc, u8 offset)
+{
+ unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
+
+ return !!(val & BIT(offset));
+}
+
+static void gpio_set_value(struct ingenic_gpio_chip *jzgc, u8 offset, int value)
+{
+ if (jzgc->version >= ID_JZ4770)
+ gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
+ else
+ gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
+}
+
+static void irq_set_type(struct ingenic_gpio_chip *jzgc,
+ u8 offset, unsigned int type)
+{
+ u8 reg1, reg2;
+
+ if (jzgc->version >= ID_JZ4770) {
+ reg1 = JZ4770_GPIO_PAT1;
+ reg2 = JZ4770_GPIO_PAT0;
+ } else {
+ reg1 = JZ4740_GPIO_TRIG;
+ reg2 = JZ4740_GPIO_DIR;
+ }
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ gpio_ingenic_set_bit(jzgc, reg2, offset, true);
+ gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ gpio_ingenic_set_bit(jzgc, reg2, offset, false);
+ gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ gpio_ingenic_set_bit(jzgc, reg2, offset, true);
+ gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ default:
+ gpio_ingenic_set_bit(jzgc, reg2, offset, false);
+ gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+ break;
+ }
+}
+
+static void ingenic_gpio_irq_mask(struct irq_data *irqd)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+
+ gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
+}
+
+static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+
+ gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
+}
+
+static void ingenic_gpio_irq_enable(struct irq_data *irqd)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+ int irq = irqd->hwirq;
+
+ if (jzgc->version >= ID_JZ4770)
+ gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
+ else
+ gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
+
+ ingenic_gpio_irq_unmask(irqd);
+}
+
+static void ingenic_gpio_irq_disable(struct irq_data *irqd)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+ int irq = irqd->hwirq;
+
+ ingenic_gpio_irq_mask(irqd);
+
+ if (jzgc->version >= ID_JZ4770)
+ gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
+ else
+ gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
+}
+
+static void ingenic_gpio_irq_ack(struct irq_data *irqd)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+ int irq = irqd->hwirq;
+ bool high;
+
+ if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
+ /*
+ * Switch to an interrupt for the opposite edge to the one that
+ * triggered the interrupt being ACKed.
+ */
+ high = gpio_get_value(jzgc, irq);
+ if (high)
+ irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING);
+ else
+ irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
+ }
+
+ if (jzgc->version >= ID_JZ4770)
+ gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
+ else
+ gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
+}
+
+static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_BOTH:
+ case IRQ_TYPE_EDGE_RISING:
+ case IRQ_TYPE_EDGE_FALLING:
+ irq_set_handler_locked(irqd, handle_edge_irq);
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ case IRQ_TYPE_LEVEL_LOW:
+ irq_set_handler_locked(irqd, handle_level_irq);
+ break;
+ default:
+ irq_set_handler_locked(irqd, handle_bad_irq);
+ }
+
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ /*
+ * The hardware does not support interrupts on both edges. The
+ * best we can do is to set up a single-edge interrupt and then
+ * switch to the opposing edge when ACKing the interrupt.
+ */
+ bool high = gpio_get_value(jzgc, irqd->hwirq);
+
+ type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
+ }
+
+ irq_set_type(jzgc, irqd->hwirq, type);
+ return 0;
+}
+
+static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+
+ return irq_set_irq_wake(jzgc->irq, on);
+}
+
+static void ingenic_gpio_irq_handler(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+ struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
+ unsigned long flag, i;
+
+ chained_irq_enter(irq_chip, desc);
+
+ if (jzgc->version >= ID_JZ4770)
+ flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG);
+ else
+ flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
+
+ for_each_set_bit(i, &flag, 32)
+ generic_handle_irq(irq_linear_revmap(gc->irqdomain, i));
+ chained_irq_exit(irq_chip, desc);
+}
+
+static void ingenic_gpio_set(struct gpio_chip *gc,
+ unsigned int offset, int value)
+{
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+
+ gpio_set_value(jzgc, offset, value);
+}
+
+static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
+
+ return (int) gpio_get_value(jzgc, offset);
+}
+
+static int ingenic_gpio_direction_input(struct gpio_chip *gc,
+ unsigned int offset)
+{
+ return pinctrl_gpio_direction_input(gc->base + offset);
+}
+
+static int ingenic_gpio_direction_output(struct gpio_chip *gc,
+ unsigned int offset, int value)
+{
+ ingenic_gpio_set(gc, offset, value);
+ return pinctrl_gpio_direction_output(gc->base + offset);
+}
+
+static const struct of_device_id ingenic_gpio_of_match[] = {
+ { .compatible = "ingenic,jz4740-gpio", .data = (void *)ID_JZ4740 },
+ { .compatible = "ingenic,jz4770-gpio", .data = (void *)ID_JZ4770 },
+ { .compatible = "ingenic,jz4780-gpio", .data = (void *)ID_JZ4780 },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ingenic_gpio_of_match);
+
+static int ingenic_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *of_id = of_match_device(
+ ingenic_gpio_of_match, dev);
+ struct ingenic_gpio_chip *jzgc;
+ u32 bank;
+ int err;
+
+ jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
+ if (!jzgc)
+ return -ENOMEM;
+
+ jzgc->map = dev_get_drvdata(dev->parent);
+ if (!jzgc->map) {
+ dev_err(dev, "Cannot get parent regmap\n");
+ return -ENXIO;
+ }
+
+ err = of_property_read_u32(dev->of_node, "reg", &bank);
+ if (err) {
+ dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
+ return err;
+ }
+
+ jzgc->reg_base = bank * 0x100;
+
+ jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
+ if (!jzgc->gc.label)
+ return -ENOMEM;
+
+ /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
+ * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
+ * <linux/gpio/consumer.h> INSTEAD.
+ */
+ jzgc->gc.base = bank * 32;
+
+ jzgc->gc.ngpio = 32;
+ jzgc->gc.parent = dev;
+ jzgc->gc.of_node = dev->of_node;
+ jzgc->gc.owner = THIS_MODULE;
+ jzgc->version = (enum jz_version)of_id->data;
+
+ jzgc->gc.set = ingenic_gpio_set;
+ jzgc->gc.get = ingenic_gpio_get;
+ jzgc->gc.direction_input = ingenic_gpio_direction_input;
+ jzgc->gc.direction_output = ingenic_gpio_direction_output;
+
+ if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
+ jzgc->gc.request = gpiochip_generic_request;
+ jzgc->gc.free = gpiochip_generic_free;
+ }
+
+ err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
+ if (err)
+ return err;
+
+ jzgc->irq = irq_of_parse_and_map(dev->of_node, 0);
+ if (!jzgc->irq)
+ return -EINVAL;
+
+ jzgc->irq_chip.name = jzgc->gc.label;
+ jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
+ jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
+ jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
+ jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
+ jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
+ jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
+ jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
+ jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
+
+ err = gpiochip_irqchip_add(&jzgc->gc, &jzgc->irq_chip, 0,
+ handle_level_irq, IRQ_TYPE_NONE);
+ if (err)
+ return err;
+
+ gpiochip_set_chained_irqchip(&jzgc->gc, &jzgc->irq_chip,
+ jzgc->irq, ingenic_gpio_irq_handler);
+ return 0;
+}
+
+static int ingenic_gpio_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver ingenic_gpio_driver = {
+ .driver = {
+ .name = "gpio-ingenic",
+ .of_match_table = of_match_ptr(ingenic_gpio_of_match),
+ },
+ .probe = ingenic_gpio_probe,
+ .remove = ingenic_gpio_remove,
+};
+
+static int __init ingenic_gpio_drv_register(void)
+{
+ return platform_driver_register(&ingenic_gpio_driver);
+}
+subsys_initcall(ingenic_gpio_drv_register);
+
+static void __exit ingenic_gpio_drv_unregister(void)
+{
+ platform_driver_unregister(&ingenic_gpio_driver);
+}
+module_exit(ingenic_gpio_drv_unregister);
+
+MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
+MODULE_DESCRIPTION("Ingenic JZ47xx GPIO driver");
+MODULE_LICENSE("GPL");
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/module.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/scatterlist.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
-#include <asm/mach-jz4740/gpio.h>
#include <asm/cacheflush.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
.enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
};
-static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
- JZ_GPIO_BULK_PIN(MSC_CMD),
- JZ_GPIO_BULK_PIN(MSC_CLK),
- JZ_GPIO_BULK_PIN(MSC_DATA0),
- JZ_GPIO_BULK_PIN(MSC_DATA1),
- JZ_GPIO_BULK_PIN(MSC_DATA2),
- JZ_GPIO_BULK_PIN(MSC_DATA3),
-};
-
static int jz4740_mmc_request_gpio(struct device *dev, int gpio,
const char *name, bool output, int value)
{
gpio_free(pdata->gpio_power);
}
-static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
-{
- size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
- if (host->pdata && host->pdata->data_1bit)
- num_pins -= 3;
-
- return num_pins;
-}
-
static int jz4740_mmc_probe(struct platform_device* pdev)
{
int ret;
goto err_free_host;
}
- ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
- if (ret) {
- dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
- goto err_free_host;
- }
-
ret = jz4740_mmc_request_gpios(mmc, pdev);
if (ret)
- goto err_gpio_bulk_free;
+ goto err_release_dma;
mmc->ops = &jz4740_mmc_ops;
mmc->f_min = JZ_MMC_CLK_RATE / 128;
free_irq(host->irq, host);
err_free_gpios:
jz4740_mmc_free_gpios(pdev);
-err_gpio_bulk_free:
+err_release_dma:
if (host->use_dma)
jz4740_mmc_release_dma_channels(host);
- jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
err_free_host:
mmc_free_host(mmc);
free_irq(host->irq, host);
jz4740_mmc_free_gpios(pdev);
- jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
if (host->use_dma)
jz4740_mmc_release_dma_channels(host);
static int jz4740_mmc_suspend(struct device *dev)
{
- struct jz4740_mmc_host *host = dev_get_drvdata(dev);
-
- jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
-
- return 0;
+ return pinctrl_pm_select_sleep_state(dev);
}
static int jz4740_mmc_resume(struct device *dev)
{
- struct jz4740_mmc_host *host = dev_get_drvdata(dev);
-
- jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
-
- return 0;
+ return pinctrl_pm_select_default_state(dev);
}
static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
#include <linux/gpio.h>
-#include <asm/mach-jz4740/gpio.h>
#include <asm/mach-jz4740/jz4740_nand.h>
#define JZ_REG_NAND_CTRL 0x50
uint8_t *nand_dev_id)
{
int ret;
- int gpio;
- char gpio_name[9];
char res_name[6];
uint32_t ctrl;
struct nand_chip *chip = &nand->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
- /* Request GPIO port. */
- gpio = JZ_GPIO_MEM_CS0 + bank - 1;
- sprintf(gpio_name, "NAND CS%d", bank);
- ret = gpio_request(gpio, gpio_name);
- if (ret) {
- dev_warn(&pdev->dev,
- "Failed to request %s gpio %d: %d\n",
- gpio_name, gpio, ret);
- goto notfound_gpio;
- }
-
/* Request I/O resource. */
sprintf(res_name, "bank%d", bank);
ret = jz_nand_ioremap_resource(pdev, res_name,
&nand->bank_mem[bank - 1],
&nand->bank_base[bank - 1]);
if (ret)
- goto notfound_resource;
+ return ret;
/* Enable chip in bank. */
- jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
- jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]);
-notfound_resource:
- gpio_free(gpio);
-notfound_gpio:
return ret;
}
err_unclaim_banks:
while (chipnr--) {
unsigned char bank = nand->banks[chipnr];
- gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]);
}
if (bank != 0) {
jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]);
- gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
}
}
help
This selects the pinctrl driver for Xilinx Zynq.
+config PINCTRL_INGENIC
+ bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
+ default y
+ depends on MACH_INGENIC || COMPILE_TEST
+ select GENERIC_PINCONF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select REGMAP_MMIO
+
source "drivers/pinctrl/aspeed/Kconfig"
source "drivers/pinctrl/bcm/Kconfig"
source "drivers/pinctrl/berlin/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/vt8500/Kconfig"
source "drivers/pinctrl/mediatek/Kconfig"
+source "drivers/pinctrl/zte/Kconfig"
config PINCTRL_XWAY
bool
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
+obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-y += bcm/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_VT8500) += vt8500/
obj-$(CONFIG_PINCTRL_MTK) += mediatek/
+obj-$(CONFIG_PINCTRL_ZX) += zte/
const struct pin_desc *desc;
desc = pin_desc_get(pctldev, pin);
- if (desc == NULL) {
+ if (!desc) {
dev_err(pctldev->dev, "failed to get pin(%d) name\n",
pin);
return NULL;
pindesc = radix_tree_lookup(&pctldev->pin_desc_tree,
pins[i].number);
- if (pindesc != NULL) {
+ if (pindesc) {
radix_tree_delete(&pctldev->pin_desc_tree,
pins[i].number);
if (pindesc->dynamic_name)
struct pin_desc *pindesc;
pindesc = pin_desc_get(pctldev, pin->number);
- if (pindesc != NULL) {
+ if (pindesc) {
dev_err(pctldev->dev, "pin %d already registered\n",
pin->number);
return -EINVAL;
pindesc->name = pin->name;
} else {
pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", pin->number);
- if (pindesc->name == NULL) {
+ if (!pindesc->name) {
kfree(pindesc);
return -ENOMEM;
}
struct pinctrl_gpio_range *range;
range = pinctrl_match_gpio_range(pctldev, gpio);
- if (range != NULL) {
+ if (range) {
*outdev = pctldev;
*outrange = range;
mutex_unlock(&pinctrldev_list_mutex);
else
setting->pctldev =
get_pinctrl_dev_from_devname(map->ctrl_dev_name);
- if (setting->pctldev == NULL) {
+ if (!setting->pctldev) {
kfree(setting);
/* Do not defer probing of hogs (circular loop) */
if (!strcmp(map->ctrl_dev_name, map->dev_name))
/* Map must be for this device */
if (strcmp(map->dev_name, devname))
continue;
+ /*
+ * If pctldev is not null, we are claiming hog for it,
+ * that means, setting that is served by pctldev by itself.
+ *
+ * Thus we must skip map that is for this device but is served
+ * by other device.
+ */
+ if (pctldev &&
+ strcmp(dev_name(pctldev->dev), map->ctrl_dev_name))
+ continue;
ret = add_setting(p, pctldev, map);
/*
* return another pointer to it.
*/
p = find_pinctrl(dev);
- if (p != NULL) {
+ if (p) {
dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n");
kref_get(&p->users);
return p;
pin = pctldev->desc->pins[i].number;
desc = pin_desc_get(pctldev, pin);
/* Pin space may be sparse */
- if (desc == NULL)
+ if (!desc)
continue;
seq_printf(s, "pin %d (%s) ", pin, desc->name);
break;
}
- seq_printf(s, "\n");
+ seq_putc(s, '\n');
}
mutex_unlock(&pinctrl_maps_mutex);
{
struct pinctrl_gpio_range *range, *n;
- if (pctldev == NULL)
+ if (!pctldev)
return;
mutex_lock(&pctldev->mutex);
bool
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
- select PINCONF
+ select GENERIC_PINCONF
select REGMAP
config PINCTRL_IMX1_CORE
#include <linux/regmap.h>
#include "../core.h"
+#include "../pinconf.h"
#include "../pinmux.h"
#include "pinctrl-imx.h"
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->mux_reg);
- reg &= ~(0x7 << 20);
- reg |= (pin->mux_mode << 20);
+ reg &= ~info->mux_mask;
+ reg |= (pin->mux_mode << info->mux_shift);
writel(reg, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, reg);
} else {
writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, pin->mux_mode);
}
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, pin->mux_mode);
/*
* If the select input value begins with 0xff, it's a quirky
mux_pin:
reg = readl(ipctl->base + pin_reg->mux_reg);
- reg &= ~(0x7 << 20);
+ reg &= ~info->mux_mask;
reg |= imx_pin->config;
writel(reg, ipctl->base + pin_reg->mux_reg);
.gpio_set_direction = imx_pmx_gpio_set_direction,
};
+/* decode generic config into raw register values */
+static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_cfg_params_decode *decode;
+ enum pin_config_param param;
+ u32 raw_config = 0;
+ u32 param_val;
+ int i, j;
+
+ WARN_ON(num_configs > info->num_decodes);
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ param_val = pinconf_to_config_argument(configs[i]);
+ decode = info->decodes;
+ for (j = 0; j < info->num_decodes; j++) {
+ if (param == decode->param) {
+ if (decode->invert)
+ param_val = !param_val;
+ raw_config |= (param_val << decode->shift)
+ & decode->mask;
+ break;
+ }
+ decode++;
+ }
+ }
+
+ if (info->fixup)
+ info->fixup(configs, num_configs, &raw_config);
+
+ return raw_config;
+}
+
+static u32 imx_pinconf_parse_generic_config(struct device_node *np,
+ struct imx_pinctrl *ipctl)
+{
+ struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct pinctrl_dev *pctl = ipctl->pctl;
+ unsigned int num_configs;
+ unsigned long *configs;
+ int ret;
+
+ if (!info->generic_pinconf)
+ return 0;
+
+ ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
+ &num_configs);
+ if (ret)
+ return 0;
+
+ return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
+}
+
static int imx_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
*config = readl(ipctl->base + pin_reg->conf_reg);
if (info->flags & SHARE_MUX_CONF_REG)
- *config &= 0xffff;
+ *config &= ~info->mux_mask;
return 0;
}
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->conf_reg);
- reg &= ~0xffff;
+ reg &= info->mux_mask;
reg |= configs[i];
writel(reg, ipctl->base + pin_reg->conf_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->conf_reg, reg);
} else {
writel(configs[i], ipctl->base + pin_reg->conf_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
+ pin_reg->conf_reg, configs[i]);
}
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
- pin_reg->conf_reg, configs[i]);
} /* for each config */
return 0;
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
- struct imx_pinctrl_soc_info *info,
+ struct imx_pinctrl *ipctl,
u32 index)
{
+ struct imx_pinctrl_soc_info *info = ipctl->info;
int size, pin_size;
const __be32 *list;
int i;
pin_size = SHARE_FSL_PIN_SIZE;
else
pin_size = FSL_PIN_SIZE;
+
+ if (info->generic_pinconf)
+ pin_size -= 4;
+
/* Initialise group */
grp->name = np->name;
/*
* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
* do sanity check and calculate pins number
+ *
+ * First try legacy 'fsl,pins' property, then fall back to the
+ * generic 'pins'.
+ *
+ * Note: for generic 'pins' case, there's no CONFIG part in
+ * the binding format.
*/
list = of_get_property(np, "fsl,pins", &size);
if (!list) {
- dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
- return -EINVAL;
+ list = of_get_property(np, "pins", &size);
+ if (!list) {
+ dev_err(info->dev,
+ "no fsl,pins and pins property in node %s\n",
+ np->full_name);
+ return -EINVAL;
+ }
}
/* we do not check return since it's safe node passed down */
if (!size || size % pin_size) {
- dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
+ dev_err(info->dev, "Invalid fsl,pins or pins property in node %s\n",
+ np->full_name);
return -EINVAL;
}
+ /* first try to parse the generic pin config */
+ config = imx_pinconf_parse_generic_config(np, ipctl);
+
grp->num_pins = size / pin_size;
grp->data = devm_kzalloc(info->dev, grp->num_pins *
sizeof(struct imx_pin), GFP_KERNEL);
pin->mux_mode = be32_to_cpu(*list++);
pin->input_val = be32_to_cpu(*list++);
- /* SION bit is in mux register */
- config = be32_to_cpu(*list++);
- if (config & IMX_PAD_SION)
- pin->mux_mode |= IOMUXC_CONFIG_SION;
- pin->config = config & ~IMX_PAD_SION;
+ if (info->generic_pinconf) {
+ /* generic pin config decoded */
+ pin->config = config;
+ } else {
+ /* legacy pin config read from devicetree */
+ config = be32_to_cpu(*list++);
+
+ /* SION bit is in mux register */
+ if (config & IMX_PAD_SION)
+ pin->mux_mode |= IOMUXC_CONFIG_SION;
+ pin->config = config & ~IMX_PAD_SION;
+ }
dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
pin->mux_mode, pin->config);
dev_err(info->dev, "no groups defined in %s\n", np->full_name);
return -EINVAL;
}
- func->group_names = devm_kzalloc(info->dev,
- func->num_group_names *
+ func->group_names = devm_kcalloc(info->dev, func->num_group_names,
sizeof(char *), GFP_KERNEL);
+ if (!func->group_names)
+ return -ENOMEM;
for_each_child_of_node(np, child) {
func->group_names[i] = child->name;
info->group_index++, grp);
mutex_unlock(&info->mutex);
- imx_pinctrl_parse_groups(child, grp, info, i++);
+ imx_pinctrl_parse_groups(child, grp, ipctl, i++);
}
return 0;
imx_pinctrl_desc->confops = &imx_pinconf_ops;
imx_pinctrl_desc->owner = THIS_MODULE;
+ /* for generic pinconf */
+ imx_pinctrl_desc->custom_params = info->custom_params;
+ imx_pinctrl_desc->num_custom_params = info->num_custom_params;
+
mutex_init(&info->mutex);
ipctl->info = info;
#ifndef __DRIVERS_PINCTRL_IMX_H
#define __DRIVERS_PINCTRL_IMX_H
+#include <linux/pinctrl/pinconf-generic.h>
+
struct platform_device;
/**
s16 conf_reg;
};
+/* decode a generic config into raw register value */
+struct imx_cfg_params_decode {
+ enum pin_config_param param;
+ u32 mask;
+ u8 shift;
+ bool invert;
+};
+
struct imx_pinctrl_soc_info {
struct device *dev;
const struct pinctrl_pin_desc *pins;
unsigned int flags;
const char *gpr_compatible;
struct mutex mutex;
+
+ /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
+ unsigned int mux_mask;
+ u8 mux_shift;
+
+ /* generic pinconf */
+ bool generic_pinconf;
+ const struct pinconf_generic_params *custom_params;
+ unsigned int num_custom_params;
+ struct imx_cfg_params_decode *decodes;
+ unsigned int num_decodes;
+ void (*fixup)(unsigned long *configs, unsigned int num_configs,
+ u32 *raw_config);
};
+#define IMX_CFG_PARAMS_DECODE(p, m, o) \
+ { .param = p, .mask = m, .shift = o, .invert = false, }
+
+#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
+ { .param = p, .mask = m, .shift = o, .invert = true, }
+
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
.pins = vf610_pinctrl_pads,
.npins = ARRAY_SIZE(vf610_pinctrl_pads),
.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+ .mux_mask = 0x700000,
+ .mux_shift = 20,
};
static const struct of_device_id vf610_pinctrl_of_match[] = {
# For ARMv7 SoCs
config PINCTRL_MT2701
bool "Mediatek MT2701 pin control"
- depends on MACH_MT2701 || COMPILE_TEST
+ depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST
depends on OF
default MACH_MT2701
select PINCTRL_MTK
-config PINCTRL_MT7623
- bool "Mediatek MT7623 pin control"
- depends on MACH_MT7623 || COMPILE_TEST
- depends on OF
- default MACH_MT7623
- select PINCTRL_MTK_COMMON
-
config PINCTRL_MT8135
bool "Mediatek MT8135 pin control"
depends on MACH_MT8135 || COMPILE_TEST
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
-obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
static const struct of_device_id mt2701_pctrl_match[] = {
{ .compatible = "mediatek,mt2701-pinctrl", },
+ { .compatible = "mediatek,mt7623-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
+++ /dev/null
-/*
- * Copyright (c) 2016 John Crispin <john@phrozen.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/regmap.h>
-
-#include "pinctrl-mtk-common.h"
-#include "pinctrl-mtk-mt7623.h"
-
-static const struct mtk_drv_group_desc mt7623_drv_grp[] = {
- /* 0E4E8SR 4/8/12/16 */
- MTK_DRV_GRP(4, 16, 1, 2, 4),
- /* 0E2E4SR 2/4/6/8 */
- MTK_DRV_GRP(2, 8, 1, 2, 2),
- /* E8E4E2 2/4/6/8/10/12/14/16 */
- MTK_DRV_GRP(2, 16, 0, 2, 2)
-};
-
-#define DRV_SEL0 0xf50
-#define DRV_SEL1 0xf60
-#define DRV_SEL2 0xf70
-#define DRV_SEL3 0xf80
-#define DRV_SEL4 0xf90
-#define DRV_SEL5 0xfa0
-#define DRV_SEL6 0xfb0
-#define DRV_SEL7 0xfe0
-#define DRV_SEL8 0xfd0
-#define DRV_SEL9 0xff0
-#define DRV_SEL10 0xf00
-
-#define MSDC0_CTRL0 0xcc0
-#define MSDC0_CTRL1 0xcd0
-#define MSDC0_CTRL2 0xce0
-#define MSDC0_CTRL3 0xcf0
-#define MSDC0_CTRL4 0xd00
-#define MSDC0_CTRL5 0xd10
-#define MSDC0_CTRL6 0xd20
-#define MSDC1_CTRL0 0xd30
-#define MSDC1_CTRL1 0xd40
-#define MSDC1_CTRL2 0xd50
-#define MSDC1_CTRL3 0xd60
-#define MSDC1_CTRL4 0xd70
-#define MSDC1_CTRL5 0xd80
-#define MSDC1_CTRL6 0xd90
-
-#define IES_EN0 0xb20
-#define IES_EN1 0xb30
-#define IES_EN2 0xb40
-
-#define SMT_EN0 0xb50
-#define SMT_EN1 0xb60
-#define SMT_EN2 0xb70
-
-static const struct mtk_pin_drv_grp mt7623_pin_drv[] = {
- MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0),
- MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0),
- MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0),
- MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0),
- MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0),
- MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0),
- MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0),
- MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0),
- MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0),
- MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0),
- MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1),
- MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1),
- MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1),
- MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1),
- MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1),
- MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1),
- MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1),
- MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1),
- MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1),
- MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1),
- MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0),
- MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0),
- MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0),
- MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0),
- MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0),
- MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0),
- MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1),
-};
-
-static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = {
- MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2),
- MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6),
- MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14),
- MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14),
- MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6),
- MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2),
- MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2),
- MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14),
- MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6),
- MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2),
-};
-
-static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin,
- unsigned char align, bool isup, unsigned int r1r0)
-{
- return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd,
- ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0);
-}
-
-static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0),
- MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2),
- MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3),
- MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5),
- MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6),
- MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7),
- MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8),
- MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9),
- MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10),
- MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11),
- MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14),
- MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0),
- MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1),
- MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3),
- MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4),
- MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7),
- MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2),
- MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3),
- MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6),
- MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7),
- MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4),
- MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13),
-};
-
-static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0),
- MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2),
- MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3),
- MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5),
- MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6),
- MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7),
- MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8),
- MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9),
- MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10),
- MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11),
- MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14),
- MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0),
- MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1),
- MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3),
- MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11),
- MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3),
- MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7),
- MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11),
- MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15),
- MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11),
- MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7),
- MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3),
- MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11),
- MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15),
- MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11),
- MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7),
- MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3),
- MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7),
- MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2),
- MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3),
- MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6),
- MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7),
- MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3),
- MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13),
-};
-
-static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin,
- unsigned char align, int value, enum pin_config_param arg)
-{
- if (arg == PIN_CONFIG_INPUT_ENABLE)
- return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set,
- ARRAY_SIZE(mt7623_ies_set), pin, align, value);
- else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
- return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set,
- ARRAY_SIZE(mt7623_smt_set), pin, align, value);
- return -EINVAL;
-}
-
-static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = {
- .pins = mtk_pins_mt7623,
- .npins = ARRAY_SIZE(mtk_pins_mt7623),
- .grp_desc = mt7623_drv_grp,
- .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp),
- .pin_drv_grp = mt7623_pin_drv,
- .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv),
- .spec_pull_set = mt7623_spec_pull_set,
- .spec_ies_smt_set = mt7623_ies_smt_set,
- .dir_offset = 0x0000,
- .pullen_offset = 0x0150,
- .pullsel_offset = 0x0280,
- .dout_offset = 0x0500,
- .din_offset = 0x0630,
- .pinmux_offset = 0x0760,
- .type1_start = 280,
- .type1_end = 280,
- .port_shf = 4,
- .port_mask = 0x1f,
- .port_align = 4,
- .eint_offsets = {
- .name = "mt7623_eint",
- .stat = 0x000,
- .ack = 0x040,
- .mask = 0x080,
- .mask_set = 0x0c0,
- .mask_clr = 0x100,
- .sens = 0x140,
- .sens_set = 0x180,
- .sens_clr = 0x1c0,
- .soft = 0x200,
- .soft_set = 0x240,
- .soft_clr = 0x280,
- .pol = 0x300,
- .pol_set = 0x340,
- .pol_clr = 0x380,
- .dom_en = 0x400,
- .dbnc_ctrl = 0x500,
- .dbnc_set = 0x600,
- .dbnc_clr = 0x700,
- .port_mask = 6,
- .ports = 6,
- },
- .ap_num = 169,
- .db_cnt = 16,
-};
-
-static int mt7623_pinctrl_probe(struct platform_device *pdev)
-{
- return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL);
-}
-
-static const struct of_device_id mt7623_pctrl_match[] = {
- { .compatible = "mediatek,mt7623-pinctrl", },
- {}
-};
-MODULE_DEVICE_TABLE(of, mt7623_pctrl_match);
-
-static struct platform_driver mtk_pinctrl_driver = {
- .probe = mt7623_pinctrl_probe,
- .driver = {
- .name = "mediatek-mt7623-pinctrl",
- .of_match_table = mt7623_pctrl_match,
- },
-};
-
-static int __init mtk_pinctrl_init(void)
-{
- return platform_driver_register(&mtk_pinctrl_driver);
-}
-
-arch_initcall(mtk_pinctrl_init);
+++ /dev/null
-/*
- * Copyright (c) 2016 John Crispin <john@phrozen.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __PINCTRL_MTK_MT7623_H
-#define __PINCTRL_MTK_MT7623_H
-
-#include <linux/pinctrl/pinctrl.h>
-#include "pinctrl-mtk-common.h"
-
-static const struct mtk_desc_pin mtk_pins_mt7623[] = {
- MTK_PIN(
- PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
- "J20", "mt7623",
- MTK_EINT_FUNCTION(0, 148),
- MTK_FUNCTION(0, "GPIO0"),
- MTK_FUNCTION(1, "PWRAP_SPIDO"),
- MTK_FUNCTION(2, "PWRAP_SPIDI")
- ),
- MTK_PIN(
- PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
- "D10", "mt7623",
- MTK_EINT_FUNCTION(0, 149),
- MTK_FUNCTION(0, "GPIO1"),
- MTK_FUNCTION(1, "PWRAP_SPIDI"),
- MTK_FUNCTION(2, "PWRAP_SPIDO")
- ),
- MTK_PIN(
- PINCTRL_PIN(2, "PWRAP_INT"),
- "E11", "mt7623",
- MTK_EINT_FUNCTION(0, 150),
- MTK_FUNCTION(0, "GPIO2"),
- MTK_FUNCTION(1, "PWRAP_INT")
- ),
- MTK_PIN(
- PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
- "H12", "mt7623",
- MTK_EINT_FUNCTION(0, 151),
- MTK_FUNCTION(0, "GPIO3"),
- MTK_FUNCTION(1, "PWRAP_SPICK_I")
- ),
- MTK_PIN(
- PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
- "E12", "mt7623",
- MTK_EINT_FUNCTION(0, 152),
- MTK_FUNCTION(0, "GPIO4"),
- MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
- ),
- MTK_PIN(
- PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
- "H11", "mt7623",
- MTK_EINT_FUNCTION(0, 155),
- MTK_FUNCTION(0, "GPIO5"),
- MTK_FUNCTION(1, "PWRAP_SPICK2_I")
- ),
- MTK_PIN(
- PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
- "G11", "mt7623",
- MTK_EINT_FUNCTION(0, 156),
- MTK_FUNCTION(0, "GPIO6"),
- MTK_FUNCTION(1, "PWRAP_SPICS2_B_I")
- ),
- MTK_PIN(
- PINCTRL_PIN(7, "SPI1_CSN"),
- "G19", "mt7623",
- MTK_EINT_FUNCTION(0, 153),
- MTK_FUNCTION(0, "GPIO7"),
- MTK_FUNCTION(1, "SPI1_CS")
- ),
- MTK_PIN(
- PINCTRL_PIN(8, "SPI1_MI"),
- "F19", "mt7623",
- MTK_EINT_FUNCTION(0, 154),
- MTK_FUNCTION(0, "GPIO8"),
- MTK_FUNCTION(1, "SPI1_MI"),
- MTK_FUNCTION(2, "SPI1_MO")
- ),
- MTK_PIN(
- PINCTRL_PIN(9, "SPI1_MO"),
- "G20", "mt7623",
- MTK_EINT_FUNCTION(0, 157),
- MTK_FUNCTION(0, "GPIO9"),
- MTK_FUNCTION(1, "SPI1_MO"),
- MTK_FUNCTION(2, "SPI1_MI")
- ),
- MTK_PIN(
- PINCTRL_PIN(10, "RTC32K_CK"),
- "A13", "mt7623",
- MTK_EINT_FUNCTION(0, 158),
- MTK_FUNCTION(0, "GPIO10"),
- MTK_FUNCTION(1, "RTC32K_CK")
- ),
- MTK_PIN(
- PINCTRL_PIN(11, "WATCHDOG"),
- "D14", "mt7623",
- MTK_EINT_FUNCTION(0, 159),
- MTK_FUNCTION(0, "GPIO11"),
- MTK_FUNCTION(1, "WATCHDOG")
- ),
- MTK_PIN(
- PINCTRL_PIN(12, "SRCLKENA"),
- "C13", "mt7623",
- MTK_EINT_FUNCTION(0, 169),
- MTK_FUNCTION(0, "GPIO12"),
- MTK_FUNCTION(1, "SRCLKENA")
- ),
- MTK_PIN(
- PINCTRL_PIN(13, "SRCLKENAI"),
- "B13", "mt7623",
- MTK_EINT_FUNCTION(0, 161),
- MTK_FUNCTION(0, "GPIO13"),
- MTK_FUNCTION(1, "SRCLKENAI")
- ),
- MTK_PIN(
- PINCTRL_PIN(14, "GPIO14"),
- "E18", "mt7623",
- MTK_EINT_FUNCTION(0, 162),
- MTK_FUNCTION(0, "GPIO14"),
- MTK_FUNCTION(1, "URXD2"),
- MTK_FUNCTION(2, "UTXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(15, "GPIO15"),
- "E17", "mt7623",
- MTK_EINT_FUNCTION(0, 163),
- MTK_FUNCTION(0, "GPIO15"),
- MTK_FUNCTION(1, "UTXD2"),
- MTK_FUNCTION(2, "URXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(16, "GPIO16"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO16")
- ),
- MTK_PIN(
- PINCTRL_PIN(17, "GPIO17"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO17")
- ),
- MTK_PIN(
- PINCTRL_PIN(18, "PCM_CLK"),
- "C19", "mt7623",
- MTK_EINT_FUNCTION(0, 166),
- MTK_FUNCTION(0, "GPIO18"),
- MTK_FUNCTION(1, "PCM_CLK0"),
- MTK_FUNCTION(6, "AP_PCM_CLKO")
- ),
- MTK_PIN(
- PINCTRL_PIN(19, "PCM_SYNC"),
- "D19", "mt7623",
- MTK_EINT_FUNCTION(0, 167),
- MTK_FUNCTION(0, "GPIO19"),
- MTK_FUNCTION(1, "PCM_SYNC"),
- MTK_FUNCTION(6, "AP_PCM_SYNC")
- ),
- MTK_PIN(
- PINCTRL_PIN(20, "PCM_RX"),
- "D18", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO20"),
- MTK_FUNCTION(1, "PCM_RX"),
- MTK_FUNCTION(4, "PCM_TX"),
- MTK_FUNCTION(6, "AP_PCM_RX")
- ),
- MTK_PIN(
- PINCTRL_PIN(21, "PCM_TX"),
- "C18", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO21"),
- MTK_FUNCTION(1, "PCM_TX"),
- MTK_FUNCTION(4, "PCM_RX"),
- MTK_FUNCTION(6, "AP_PCM_TX")
- ),
- MTK_PIN(
- PINCTRL_PIN(22, "EINT0"),
- "H15", "mt7623",
- MTK_EINT_FUNCTION(0, 0),
- MTK_FUNCTION(0, "GPIO22"),
- MTK_FUNCTION(1, "UCTS0"),
- MTK_FUNCTION(2, "PCIE0_PERST_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(23, "EINT1"),
- "J16", "mt7623",
- MTK_EINT_FUNCTION(0, 1),
- MTK_FUNCTION(0, "GPIO23"),
- MTK_FUNCTION(1, "URTS0"),
- MTK_FUNCTION(2, "PCIE1_PERST_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(24, "EINT2"),
- "H16", "mt7623",
- MTK_EINT_FUNCTION(0, 2),
- MTK_FUNCTION(0, "GPIO24"),
- MTK_FUNCTION(1, "UCTS1"),
- MTK_FUNCTION(2, "PCIE2_PERST_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(25, "EINT3"),
- "K15", "mt7623",
- MTK_EINT_FUNCTION(0, 3),
- MTK_FUNCTION(0, "GPIO25"),
- MTK_FUNCTION(1, "URTS1")
- ),
- MTK_PIN(
- PINCTRL_PIN(26, "EINT4"),
- "G15", "mt7623",
- MTK_EINT_FUNCTION(0, 4),
- MTK_FUNCTION(0, "GPIO26"),
- MTK_FUNCTION(1, "UCTS3"),
- MTK_FUNCTION(6, "PCIE2_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(27, "EINT5"),
- "F15", "mt7623",
- MTK_EINT_FUNCTION(0, 5),
- MTK_FUNCTION(0, "GPIO27"),
- MTK_FUNCTION(1, "URTS3"),
- MTK_FUNCTION(6, "PCIE1_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(28, "EINT6"),
- "J15", "mt7623",
- MTK_EINT_FUNCTION(0, 6),
- MTK_FUNCTION(0, "GPIO28"),
- MTK_FUNCTION(1, "DRV_VBUS"),
- MTK_FUNCTION(6, "PCIE0_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(29, "EINT7"),
- "E15", "mt7623",
- MTK_EINT_FUNCTION(0, 7),
- MTK_FUNCTION(0, "GPIO29"),
- MTK_FUNCTION(1, "IDDIG"),
- MTK_FUNCTION(2, "MSDC1_WP"),
- MTK_FUNCTION(6, "PCIE2_PERST_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(30, "GPIO30"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO30")
- ),
- MTK_PIN(
- PINCTRL_PIN(31, "GPIO31"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO31")
- ),
- MTK_PIN(
- PINCTRL_PIN(32, "GPIO32"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO32")
- ),
- MTK_PIN(
- PINCTRL_PIN(33, "I2S1_DATA"),
- "Y18", "mt7623",
- MTK_EINT_FUNCTION(0, 15),
- MTK_FUNCTION(0, "GPIO33"),
- MTK_FUNCTION(1, "I2S1_DATA"),
- MTK_FUNCTION(3, "PCM_TX"),
- MTK_FUNCTION(6, "AP_PCM_TX")
- ),
- MTK_PIN(
- PINCTRL_PIN(34, "I2S1_DATA_IN"),
- "Y17", "mt7623",
- MTK_EINT_FUNCTION(0, 16),
- MTK_FUNCTION(0, "GPIO34"),
- MTK_FUNCTION(1, "I2S1_DATA_IN"),
- MTK_FUNCTION(3, "PCM_RX"),
- MTK_FUNCTION(6, "AP_PCM_RX")
- ),
- MTK_PIN(
- PINCTRL_PIN(35, "I2S1_BCK"),
- "V17", "mt7623",
- MTK_EINT_FUNCTION(0, 17),
- MTK_FUNCTION(0, "GPIO35"),
- MTK_FUNCTION(1, "I2S1_BCK"),
- MTK_FUNCTION(3, "PCM_CLK0"),
- MTK_FUNCTION(6, "AP_PCM_CLKO")
- ),
- MTK_PIN(
- PINCTRL_PIN(36, "I2S1_LRCK"),
- "W17", "mt7623",
- MTK_EINT_FUNCTION(0, 18),
- MTK_FUNCTION(0, "GPIO36"),
- MTK_FUNCTION(1, "I2S1_LRCK"),
- MTK_FUNCTION(3, "PCM_SYNC"),
- MTK_FUNCTION(6, "AP_PCM_SYNC")
- ),
- MTK_PIN(
- PINCTRL_PIN(37, "I2S1_MCLK"),
- "AA18", "mt7623",
- MTK_EINT_FUNCTION(0, 19),
- MTK_FUNCTION(0, "GPIO37"),
- MTK_FUNCTION(1, "I2S1_MCLK")
- ),
- MTK_PIN(
- PINCTRL_PIN(38, "GPIO38"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO38")
- ),
- MTK_PIN(
- PINCTRL_PIN(39, "JTMS"),
- "G21", "mt7623",
- MTK_EINT_FUNCTION(0, 21),
- MTK_FUNCTION(0, "GPIO39"),
- MTK_FUNCTION(1, "JTMS")
- ),
- MTK_PIN(
- PINCTRL_PIN(40, "GPIO40"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO40")
- ),
- MTK_PIN(
- PINCTRL_PIN(41, "JTDI"),
- "H22", "mt7623",
- MTK_EINT_FUNCTION(0, 23),
- MTK_FUNCTION(0, "GPIO41"),
- MTK_FUNCTION(1, "JTDI")
- ),
- MTK_PIN(
- PINCTRL_PIN(42, "JTDO"),
- "H21", "mt7623",
- MTK_EINT_FUNCTION(0, 24),
- MTK_FUNCTION(0, "GPIO42"),
- MTK_FUNCTION(1, "JTDO")
- ),
- MTK_PIN(
- PINCTRL_PIN(43, "NCLE"),
- "C7", "mt7623",
- MTK_EINT_FUNCTION(0, 25),
- MTK_FUNCTION(0, "GPIO43"),
- MTK_FUNCTION(1, "NCLE"),
- MTK_FUNCTION(2, "EXT_XCS2")
- ),
- MTK_PIN(
- PINCTRL_PIN(44, "NCEB1"),
- "C6", "mt7623",
- MTK_EINT_FUNCTION(0, 26),
- MTK_FUNCTION(0, "GPIO44"),
- MTK_FUNCTION(1, "NCEB1"),
- MTK_FUNCTION(2, "IDDIG")
- ),
- MTK_PIN(
- PINCTRL_PIN(45, "NCEB0"),
- "D7", "mt7623",
- MTK_EINT_FUNCTION(0, 27),
- MTK_FUNCTION(0, "GPIO45"),
- MTK_FUNCTION(1, "NCEB0"),
- MTK_FUNCTION(2, "DRV_VBUS")
- ),
- MTK_PIN(
- PINCTRL_PIN(46, "IR"),
- "D15", "mt7623",
- MTK_EINT_FUNCTION(0, 28),
- MTK_FUNCTION(0, "GPIO46"),
- MTK_FUNCTION(1, "IR")
- ),
- MTK_PIN(
- PINCTRL_PIN(47, "NREB"),
- "A6", "mt7623",
- MTK_EINT_FUNCTION(0, 29),
- MTK_FUNCTION(0, "GPIO47"),
- MTK_FUNCTION(1, "NREB")
- ),
- MTK_PIN(
- PINCTRL_PIN(48, "NRNB"),
- "B6", "mt7623",
- MTK_EINT_FUNCTION(0, 30),
- MTK_FUNCTION(0, "GPIO48"),
- MTK_FUNCTION(1, "NRNB")
- ),
- MTK_PIN(
- PINCTRL_PIN(49, "I2S0_DATA"),
- "AB18", "mt7623",
- MTK_EINT_FUNCTION(0, 31),
- MTK_FUNCTION(0, "GPIO49"),
- MTK_FUNCTION(1, "I2S0_DATA"),
- MTK_FUNCTION(3, "PCM_TX"),
- MTK_FUNCTION(6, "AP_I2S_DO")
- ),
- MTK_PIN(
- PINCTRL_PIN(50, "GPIO50"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO50")
- ),
- MTK_PIN(
- PINCTRL_PIN(51, "GPIO51"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO51")
- ),
- MTK_PIN(
- PINCTRL_PIN(52, "GPIO52"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO52")
- ),
- MTK_PIN(
- PINCTRL_PIN(53, "SPI0_CSN"),
- "E7", "mt7623",
- MTK_EINT_FUNCTION(0, 35),
- MTK_FUNCTION(0, "GPIO53"),
- MTK_FUNCTION(1, "SPI0_CS"),
- MTK_FUNCTION(5, "PWM1")
- ),
- MTK_PIN(
- PINCTRL_PIN(54, "SPI0_CK"),
- "F7", "mt7623",
- MTK_EINT_FUNCTION(0, 36),
- MTK_FUNCTION(0, "GPIO54"),
- MTK_FUNCTION(1, "SPI0_CK")
- ),
- MTK_PIN(
- PINCTRL_PIN(55, "SPI0_MI"),
- "E6", "mt7623",
- MTK_EINT_FUNCTION(0, 37),
- MTK_FUNCTION(0, "GPIO55"),
- MTK_FUNCTION(1, "SPI0_MI"),
- MTK_FUNCTION(2, "SPI0_MO"),
- MTK_FUNCTION(3, "MSDC1_WP"),
- MTK_FUNCTION(5, "PWM2")
- ),
- MTK_PIN(
- PINCTRL_PIN(56, "SPI0_MO"),
- "G7", "mt7623",
- MTK_EINT_FUNCTION(0, 38),
- MTK_FUNCTION(0, "GPIO56"),
- MTK_FUNCTION(1, "SPI0_MO"),
- MTK_FUNCTION(2, "SPI0_MI")
- ),
- MTK_PIN(
- PINCTRL_PIN(57, "GPIO57"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO57")
- ),
- MTK_PIN(
- PINCTRL_PIN(58, "GPIO58"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO58")
- ),
- MTK_PIN(
- PINCTRL_PIN(59, "GPIO59"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO59")
- ),
- MTK_PIN(
- PINCTRL_PIN(60, "WB_RSTB"),
- "Y21", "mt7623",
- MTK_EINT_FUNCTION(0, 41),
- MTK_FUNCTION(0, "GPIO60"),
- MTK_FUNCTION(1, "WB_RSTB")
- ),
- MTK_PIN(
- PINCTRL_PIN(61, "GPIO61"),
- "AA21", "mt7623",
- MTK_EINT_FUNCTION(0, 42),
- MTK_FUNCTION(0, "GPIO61"),
- MTK_FUNCTION(1, "TEST_FD")
- ),
- MTK_PIN(
- PINCTRL_PIN(62, "GPIO62"),
- "AB22", "mt7623",
- MTK_EINT_FUNCTION(0, 43),
- MTK_FUNCTION(0, "GPIO62"),
- MTK_FUNCTION(1, "TEST_FC")
- ),
- MTK_PIN(
- PINCTRL_PIN(63, "WB_SCLK"),
- "AC23", "mt7623",
- MTK_EINT_FUNCTION(0, 44),
- MTK_FUNCTION(0, "GPIO63"),
- MTK_FUNCTION(1, "WB_SCLK")
- ),
- MTK_PIN(
- PINCTRL_PIN(64, "WB_SDATA"),
- "AB21", "mt7623",
- MTK_EINT_FUNCTION(0, 45),
- MTK_FUNCTION(0, "GPIO64"),
- MTK_FUNCTION(1, "WB_SDATA")
- ),
- MTK_PIN(
- PINCTRL_PIN(65, "WB_SEN"),
- "AB24", "mt7623",
- MTK_EINT_FUNCTION(0, 46),
- MTK_FUNCTION(0, "GPIO65"),
- MTK_FUNCTION(1, "WB_SEN")
- ),
- MTK_PIN(
- PINCTRL_PIN(66, "WB_CRTL0"),
- "AB20", "mt7623",
- MTK_EINT_FUNCTION(0, 47),
- MTK_FUNCTION(0, "GPIO66"),
- MTK_FUNCTION(1, "WB_CRTL0")
- ),
- MTK_PIN(
- PINCTRL_PIN(67, "WB_CRTL1"),
- "AC20", "mt7623",
- MTK_EINT_FUNCTION(0, 48),
- MTK_FUNCTION(0, "GPIO67"),
- MTK_FUNCTION(1, "WB_CRTL1")
- ),
- MTK_PIN(
- PINCTRL_PIN(68, "WB_CRTL2"),
- "AB19", "mt7623",
- MTK_EINT_FUNCTION(0, 49),
- MTK_FUNCTION(0, "GPIO68"),
- MTK_FUNCTION(1, "WB_CRTL2")
- ),
- MTK_PIN(
- PINCTRL_PIN(69, "WB_CRTL3"),
- "AC19", "mt7623",
- MTK_EINT_FUNCTION(0, 50),
- MTK_FUNCTION(0, "GPIO69"),
- MTK_FUNCTION(1, "WB_CRTL3")
- ),
- MTK_PIN(
- PINCTRL_PIN(70, "WB_CRTL4"),
- "AD19", "mt7623",
- MTK_EINT_FUNCTION(0, 51),
- MTK_FUNCTION(0, "GPIO70"),
- MTK_FUNCTION(1, "WB_CRTL4")
- ),
- MTK_PIN(
- PINCTRL_PIN(71, "WB_CRTL5"),
- "AE19", "mt7623",
- MTK_EINT_FUNCTION(0, 52),
- MTK_FUNCTION(0, "GPIO71"),
- MTK_FUNCTION(1, "WB_CRTL5")
- ),
- MTK_PIN(
- PINCTRL_PIN(72, "I2S0_DATA_IN"),
- "AA20", "mt7623",
- MTK_EINT_FUNCTION(0, 53),
- MTK_FUNCTION(0, "GPIO72"),
- MTK_FUNCTION(1, "I2S0_DATA_IN"),
- MTK_FUNCTION(3, "PCM_RX"),
- MTK_FUNCTION(4, "PWM0"),
- MTK_FUNCTION(5, "DISP_PWM"),
- MTK_FUNCTION(6, "AP_I2S_DI")
- ),
- MTK_PIN(
- PINCTRL_PIN(73, "I2S0_LRCK"),
- "Y20", "mt7623",
- MTK_EINT_FUNCTION(0, 54),
- MTK_FUNCTION(0, "GPIO73"),
- MTK_FUNCTION(1, "I2S0_LRCK"),
- MTK_FUNCTION(3, "PCM_SYNC"),
- MTK_FUNCTION(6, "AP_I2S_LRCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(74, "I2S0_BCK"),
- "Y19", "mt7623",
- MTK_EINT_FUNCTION(0, 55),
- MTK_FUNCTION(0, "GPIO74"),
- MTK_FUNCTION(1, "I2S0_BCK"),
- MTK_FUNCTION(3, "PCM_CLK0"),
- MTK_FUNCTION(6, "AP_I2S_BCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(75, "SDA0"),
- "K19", "mt7623",
- MTK_EINT_FUNCTION(0, 56),
- MTK_FUNCTION(0, "GPIO75"),
- MTK_FUNCTION(1, "SDA0")
- ),
- MTK_PIN(
- PINCTRL_PIN(76, "SCL0"),
- "K20", "mt7623",
- MTK_EINT_FUNCTION(0, 57),
- MTK_FUNCTION(0, "GPIO76"),
- MTK_FUNCTION(1, "SCL0")
- ),
- MTK_PIN(
- PINCTRL_PIN(77, "GPIO77"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO77")
- ),
- MTK_PIN(
- PINCTRL_PIN(78, "GPIO78"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO78")
- ),
- MTK_PIN(
- PINCTRL_PIN(79, "GPIO79"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO79")
- ),
- MTK_PIN(
- PINCTRL_PIN(80, "GPIO80"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO80")
- ),
- MTK_PIN(
- PINCTRL_PIN(81, "GPIO81"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO81")
- ),
- MTK_PIN(
- PINCTRL_PIN(82, "GPIO82"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO82")
- ),
- MTK_PIN(
- PINCTRL_PIN(83, "LCM_RST"),
- "V16", "mt7623",
- MTK_EINT_FUNCTION(0, 64),
- MTK_FUNCTION(0, "GPIO83"),
- MTK_FUNCTION(1, "LCM_RST")
- ),
- MTK_PIN(
- PINCTRL_PIN(84, "DSI_TE"),
- "V14", "mt7623",
- MTK_EINT_FUNCTION(0, 65),
- MTK_FUNCTION(0, "GPIO84"),
- MTK_FUNCTION(1, "DSI_TE")
- ),
- MTK_PIN(
- PINCTRL_PIN(85, "GPIO85"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO85")
- ),
- MTK_PIN(
- PINCTRL_PIN(86, "GPIO86"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO86")
- ),
- MTK_PIN(
- PINCTRL_PIN(87, "GPIO87"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO87")
- ),
- MTK_PIN(
- PINCTRL_PIN(88, "GPIO88"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO88")
- ),
- MTK_PIN(
- PINCTRL_PIN(89, "GPIO89"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO89")
- ),
- MTK_PIN(
- PINCTRL_PIN(90, "GPIO90"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO90")
- ),
- MTK_PIN(
- PINCTRL_PIN(91, "GPIO91"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO91")
- ),
- MTK_PIN(
- PINCTRL_PIN(92, "GPIO92"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO92")
- ),
- MTK_PIN(
- PINCTRL_PIN(93, "GPIO93"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO93")
- ),
- MTK_PIN(
- PINCTRL_PIN(94, "GPIO94"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO94")
- ),
- MTK_PIN(
- PINCTRL_PIN(95, "MIPI_TCN"),
- "AB14", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO95"),
- MTK_FUNCTION(1, "TCN")
- ),
- MTK_PIN(
- PINCTRL_PIN(96, "MIPI_TCP"),
- "AC14", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO96"),
- MTK_FUNCTION(1, "TCP")
- ),
- MTK_PIN(
- PINCTRL_PIN(97, "MIPI_TDN1"),
- "AE15", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO97"),
- MTK_FUNCTION(1, "TDN1")
- ),
- MTK_PIN(
- PINCTRL_PIN(98, "MIPI_TDP1"),
- "AD15", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO98"),
- MTK_FUNCTION(1, "TDP1")
- ),
- MTK_PIN(
- PINCTRL_PIN(99, "MIPI_TDN0"),
- "AB15", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO99"),
- MTK_FUNCTION(1, "TDN0")
- ),
- MTK_PIN(
- PINCTRL_PIN(100, "MIPI_TDP0"),
- "AC15", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO100"),
- MTK_FUNCTION(1, "TDP0")
- ),
- MTK_PIN(
- PINCTRL_PIN(101, "GPIO101"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO101")
- ),
- MTK_PIN(
- PINCTRL_PIN(102, "GPIO102"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO102")
- ),
- MTK_PIN(
- PINCTRL_PIN(103, "GPIO103"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO103")
- ),
- MTK_PIN(
- PINCTRL_PIN(104, "GPIO104"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO104")
- ),
- MTK_PIN(
- PINCTRL_PIN(105, "MSDC1_CMD"),
- "AD2", "mt7623",
- MTK_EINT_FUNCTION(0, 78),
- MTK_FUNCTION(0, "GPIO105"),
- MTK_FUNCTION(1, "MSDC1_CMD"),
- MTK_FUNCTION(3, "SDA1"),
- MTK_FUNCTION(6, "I2SOUT_BCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(106, "MSDC1_CLK"),
- "AD3", "mt7623",
- MTK_EINT_FUNCTION(0, 79),
- MTK_FUNCTION(0, "GPIO106"),
- MTK_FUNCTION(1, "MSDC1_CLK"),
- MTK_FUNCTION(3, "SCL1"),
- MTK_FUNCTION(6, "I2SOUT_LRCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(107, "MSDC1_DAT0"),
- "AE2", "mt7623",
- MTK_EINT_FUNCTION(0, 80),
- MTK_FUNCTION(0, "GPIO107"),
- MTK_FUNCTION(1, "MSDC1_DAT0"),
- MTK_FUNCTION(5, "UTXD0"),
- MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
- ),
- MTK_PIN(
- PINCTRL_PIN(108, "MSDC1_DAT1"),
- "AC1", "mt7623",
- MTK_EINT_FUNCTION(0, 81),
- MTK_FUNCTION(0, "GPIO108"),
- MTK_FUNCTION(1, "MSDC1_DAT1"),
- MTK_FUNCTION(3, "PWM0"),
- MTK_FUNCTION(5, "URXD0"),
- MTK_FUNCTION(6, "PWM1")
- ),
- MTK_PIN(
- PINCTRL_PIN(109, "MSDC1_DAT2"),
- "AC3", "mt7623",
- MTK_EINT_FUNCTION(0, 82),
- MTK_FUNCTION(0, "GPIO109"),
- MTK_FUNCTION(1, "MSDC1_DAT2"),
- MTK_FUNCTION(3, "SDA2"),
- MTK_FUNCTION(5, "UTXD1"),
- MTK_FUNCTION(6, "PWM2")
- ),
- MTK_PIN(
- PINCTRL_PIN(110, "MSDC1_DAT3"),
- "AC4", "mt7623",
- MTK_EINT_FUNCTION(0, 83),
- MTK_FUNCTION(0, "GPIO110"),
- MTK_FUNCTION(1, "MSDC1_DAT3"),
- MTK_FUNCTION(3, "SCL2"),
- MTK_FUNCTION(5, "URXD1"),
- MTK_FUNCTION(6, "PWM3")
- ),
- MTK_PIN(
- PINCTRL_PIN(111, "MSDC0_DAT7"),
- "A2", "mt7623",
- MTK_EINT_FUNCTION(0, 84),
- MTK_FUNCTION(0, "GPIO111"),
- MTK_FUNCTION(1, "MSDC0_DAT7"),
- MTK_FUNCTION(4, "NLD7")
- ),
- MTK_PIN(
- PINCTRL_PIN(112, "MSDC0_DAT6"),
- "B3", "mt7623",
- MTK_EINT_FUNCTION(0, 85),
- MTK_FUNCTION(0, "GPIO112"),
- MTK_FUNCTION(1, "MSDC0_DAT6"),
- MTK_FUNCTION(4, "NLD6")
- ),
- MTK_PIN(
- PINCTRL_PIN(113, "MSDC0_DAT5"),
- "C4", "mt7623",
- MTK_EINT_FUNCTION(0, 86),
- MTK_FUNCTION(0, "GPIO113"),
- MTK_FUNCTION(1, "MSDC0_DAT5"),
- MTK_FUNCTION(4, "NLD5")
- ),
- MTK_PIN(
- PINCTRL_PIN(114, "MSDC0_DAT4"),
- "A4", "mt7623",
- MTK_EINT_FUNCTION(0, 87),
- MTK_FUNCTION(0, "GPIO114"),
- MTK_FUNCTION(1, "MSDC0_DAT4"),
- MTK_FUNCTION(4, "NLD4")
- ),
- MTK_PIN(
- PINCTRL_PIN(115, "MSDC0_RSTB"),
- "C5", "mt7623",
- MTK_EINT_FUNCTION(0, 88),
- MTK_FUNCTION(0, "GPIO115"),
- MTK_FUNCTION(1, "MSDC0_RSTB"),
- MTK_FUNCTION(4, "NLD8")
- ),
- MTK_PIN(
- PINCTRL_PIN(116, "MSDC0_CMD"),
- "D5", "mt7623",
- MTK_EINT_FUNCTION(0, 89),
- MTK_FUNCTION(0, "GPIO116"),
- MTK_FUNCTION(1, "MSDC0_CMD"),
- MTK_FUNCTION(4, "NALE")
- ),
- MTK_PIN(
- PINCTRL_PIN(117, "MSDC0_CLK"),
- "B1", "mt7623",
- MTK_EINT_FUNCTION(0, 90),
- MTK_FUNCTION(0, "GPIO117"),
- MTK_FUNCTION(1, "MSDC0_CLK"),
- MTK_FUNCTION(4, "NWEB")
- ),
- MTK_PIN(
- PINCTRL_PIN(118, "MSDC0_DAT3"),
- "D6", "mt7623",
- MTK_EINT_FUNCTION(0, 91),
- MTK_FUNCTION(0, "GPIO118"),
- MTK_FUNCTION(1, "MSDC0_DAT3"),
- MTK_FUNCTION(4, "NLD3")
- ),
- MTK_PIN(
- PINCTRL_PIN(119, "MSDC0_DAT2"),
- "B2", "mt7623",
- MTK_EINT_FUNCTION(0, 92),
- MTK_FUNCTION(0, "GPIO119"),
- MTK_FUNCTION(1, "MSDC0_DAT2"),
- MTK_FUNCTION(4, "NLD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(120, "MSDC0_DAT1"),
- "A3", "mt7623",
- MTK_EINT_FUNCTION(0, 93),
- MTK_FUNCTION(0, "GPIO120"),
- MTK_FUNCTION(1, "MSDC0_DAT1"),
- MTK_FUNCTION(4, "NLD1")
- ),
- MTK_PIN(
- PINCTRL_PIN(121, "MSDC0_DAT0"),
- "B4", "mt7623",
- MTK_EINT_FUNCTION(0, 94),
- MTK_FUNCTION(0, "GPIO121"),
- MTK_FUNCTION(1, "MSDC0_DAT0"),
- MTK_FUNCTION(4, "NLD0"),
- MTK_FUNCTION(5, "WATCHDOG")
- ),
- MTK_PIN(
- PINCTRL_PIN(122, "GPIO122"),
- "H17", "mt7623",
- MTK_EINT_FUNCTION(0, 95),
- MTK_FUNCTION(0, "GPIO122"),
- MTK_FUNCTION(1, "TEST"),
- MTK_FUNCTION(4, "SDA2"),
- MTK_FUNCTION(5, "URXD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(123, "GPIO123"),
- "F17", "mt7623",
- MTK_EINT_FUNCTION(0, 96),
- MTK_FUNCTION(0, "GPIO123"),
- MTK_FUNCTION(1, "TEST"),
- MTK_FUNCTION(4, "SCL2"),
- MTK_FUNCTION(5, "UTXD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(124, "GPIO124"),
- "H18", "mt7623",
- MTK_EINT_FUNCTION(0, 97),
- MTK_FUNCTION(0, "GPIO124"),
- MTK_FUNCTION(1, "TEST"),
- MTK_FUNCTION(4, "SDA1"),
- MTK_FUNCTION(5, "PWM3")
- ),
- MTK_PIN(
- PINCTRL_PIN(125, "GPIO125"),
- "G17", "mt7623",
- MTK_EINT_FUNCTION(0, 98),
- MTK_FUNCTION(0, "GPIO125"),
- MTK_FUNCTION(1, "TEST"),
- MTK_FUNCTION(4, "SCL1"),
- MTK_FUNCTION(5, "PWM4")
- ),
- MTK_PIN(
- PINCTRL_PIN(126, "I2S0_MCLK"),
- "AA19", "mt7623",
- MTK_EINT_FUNCTION(0, 99),
- MTK_FUNCTION(0, "GPIO126"),
- MTK_FUNCTION(1, "I2S0_MCLK"),
- MTK_FUNCTION(6, "AP_I2S_MCLK")
- ),
- MTK_PIN(
- PINCTRL_PIN(127, "GPIO127"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO127")
- ),
- MTK_PIN(
- PINCTRL_PIN(128, "GPIO128"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO128")
- ),
- MTK_PIN(
- PINCTRL_PIN(129, "GPIO129"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO129")
- ),
- MTK_PIN(
- PINCTRL_PIN(130, "GPIO130"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO130")
- ),
- MTK_PIN(
- PINCTRL_PIN(131, "GPIO131"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO131")
- ),
- MTK_PIN(
- PINCTRL_PIN(132, "GPIO132"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO132")
- ),
- MTK_PIN(
- PINCTRL_PIN(133, "GPIO133"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO133")
- ),
- MTK_PIN(
- PINCTRL_PIN(134, "GPIO134"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO134")
- ),
- MTK_PIN(
- PINCTRL_PIN(135, "GPIO135"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO135")
- ),
- MTK_PIN(
- PINCTRL_PIN(136, "GPIO136"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO136")
- ),
- MTK_PIN(
- PINCTRL_PIN(137, "GPIO137"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO137")
- ),
- MTK_PIN(
- PINCTRL_PIN(138, "GPIO138"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO138")
- ),
- MTK_PIN(
- PINCTRL_PIN(139, "GPIO139"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO139")
- ),
- MTK_PIN(
- PINCTRL_PIN(140, "GPIO140"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO140")
- ),
- MTK_PIN(
- PINCTRL_PIN(141, "GPIO141"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO141")
- ),
- MTK_PIN(
- PINCTRL_PIN(142, "GPIO142"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO142")
- ),
- MTK_PIN(
- PINCTRL_PIN(143, "GPIO143"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO143")
- ),
- MTK_PIN(
- PINCTRL_PIN(144, "GPIO144"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO144")
- ),
- MTK_PIN(
- PINCTRL_PIN(145, "GPIO145"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO145")
- ),
- MTK_PIN(
- PINCTRL_PIN(146, "GPIO146"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO146")
- ),
- MTK_PIN(
- PINCTRL_PIN(147, "GPIO147"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO147")
- ),
- MTK_PIN(
- PINCTRL_PIN(148, "GPIO148"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO148")
- ),
- MTK_PIN(
- PINCTRL_PIN(149, "GPIO149"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO149")
- ),
- MTK_PIN(
- PINCTRL_PIN(150, "GPIO150"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO150")
- ),
- MTK_PIN(
- PINCTRL_PIN(151, "GPIO151"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO151")
- ),
- MTK_PIN(
- PINCTRL_PIN(152, "GPIO152"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO152")
- ),
- MTK_PIN(
- PINCTRL_PIN(153, "GPIO153"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO153")
- ),
- MTK_PIN(
- PINCTRL_PIN(154, "GPIO154"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO154")
- ),
- MTK_PIN(
- PINCTRL_PIN(155, "GPIO155"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO155")
- ),
- MTK_PIN(
- PINCTRL_PIN(156, "GPIO156"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO156")
- ),
- MTK_PIN(
- PINCTRL_PIN(157, "GPIO157"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO157")
- ),
- MTK_PIN(
- PINCTRL_PIN(158, "GPIO158"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO158")
- ),
- MTK_PIN(
- PINCTRL_PIN(159, "GPIO159"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO159")
- ),
- MTK_PIN(
- PINCTRL_PIN(160, "GPIO160"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO160")
- ),
- MTK_PIN(
- PINCTRL_PIN(161, "GPIO161"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO161")
- ),
- MTK_PIN(
- PINCTRL_PIN(162, "GPIO162"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO162")
- ),
- MTK_PIN(
- PINCTRL_PIN(163, "GPIO163"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO163")
- ),
- MTK_PIN(
- PINCTRL_PIN(164, "GPIO164"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO164")
- ),
- MTK_PIN(
- PINCTRL_PIN(165, "GPIO165"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO165")
- ),
- MTK_PIN(
- PINCTRL_PIN(166, "GPIO166"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO166")
- ),
- MTK_PIN(
- PINCTRL_PIN(167, "GPIO167"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO167")
- ),
- MTK_PIN(
- PINCTRL_PIN(168, "GPIO168"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO168")
- ),
- MTK_PIN(
- PINCTRL_PIN(169, "GPIO169"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO169")
- ),
- MTK_PIN(
- PINCTRL_PIN(170, "GPIO170"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO170")
- ),
- MTK_PIN(
- PINCTRL_PIN(171, "GPIO171"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO171")
- ),
- MTK_PIN(
- PINCTRL_PIN(172, "GPIO172"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO172")
- ),
- MTK_PIN(
- PINCTRL_PIN(173, "GPIO173"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO173")
- ),
- MTK_PIN(
- PINCTRL_PIN(174, "GPIO174"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO174")
- ),
- MTK_PIN(
- PINCTRL_PIN(175, "GPIO175"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO175")
- ),
- MTK_PIN(
- PINCTRL_PIN(176, "GPIO176"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO176")
- ),
- MTK_PIN(
- PINCTRL_PIN(177, "GPIO177"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO177")
- ),
- MTK_PIN(
- PINCTRL_PIN(178, "GPIO178"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO178")
- ),
- MTK_PIN(
- PINCTRL_PIN(179, "GPIO179"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO179")
- ),
- MTK_PIN(
- PINCTRL_PIN(180, "GPIO180"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO180")
- ),
- MTK_PIN(
- PINCTRL_PIN(181, "GPIO181"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO181")
- ),
- MTK_PIN(
- PINCTRL_PIN(182, "GPIO182"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO182")
- ),
- MTK_PIN(
- PINCTRL_PIN(183, "GPIO183"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO183")
- ),
- MTK_PIN(
- PINCTRL_PIN(184, "GPIO184"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO184")
- ),
- MTK_PIN(
- PINCTRL_PIN(185, "GPIO185"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO185")
- ),
- MTK_PIN(
- PINCTRL_PIN(186, "GPIO186"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO186")
- ),
- MTK_PIN(
- PINCTRL_PIN(187, "GPIO187"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO187")
- ),
- MTK_PIN(
- PINCTRL_PIN(188, "GPIO188"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO188")
- ),
- MTK_PIN(
- PINCTRL_PIN(189, "GPIO189"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO189")
- ),
- MTK_PIN(
- PINCTRL_PIN(190, "GPIO190"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO190")
- ),
- MTK_PIN(
- PINCTRL_PIN(191, "GPIO191"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO191")
- ),
- MTK_PIN(
- PINCTRL_PIN(192, "GPIO192"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO192")
- ),
- MTK_PIN(
- PINCTRL_PIN(193, "GPIO193"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO193")
- ),
- MTK_PIN(
- PINCTRL_PIN(194, "GPIO194"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO194")
- ),
- MTK_PIN(
- PINCTRL_PIN(195, "GPIO195"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO195")
- ),
- MTK_PIN(
- PINCTRL_PIN(196, "GPIO196"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO196")
- ),
- MTK_PIN(
- PINCTRL_PIN(197, "GPIO197"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO197")
- ),
- MTK_PIN(
- PINCTRL_PIN(198, "GPIO198"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO198")
- ),
- MTK_PIN(
- PINCTRL_PIN(199, "SPI1_CK"),
- "E19", "mt7623",
- MTK_EINT_FUNCTION(0, 111),
- MTK_FUNCTION(0, "GPIO199"),
- MTK_FUNCTION(1, "SPI1_CK")
- ),
- MTK_PIN(
- PINCTRL_PIN(200, "URXD2"),
- "K18", "mt7623",
- MTK_EINT_FUNCTION(0, 112),
- MTK_FUNCTION(0, "GPIO200"),
- MTK_FUNCTION(6, "URXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(201, "UTXD2"),
- "L18", "mt7623",
- MTK_EINT_FUNCTION(0, 113),
- MTK_FUNCTION(0, "GPIO201"),
- MTK_FUNCTION(6, "UTXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(202, "GPIO202"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO202")
- ),
- MTK_PIN(
- PINCTRL_PIN(203, "PWM0"),
- "AA16", "mt7623",
- MTK_EINT_FUNCTION(0, 115),
- MTK_FUNCTION(0, "GPIO203"),
- MTK_FUNCTION(1, "PWM0"),
- MTK_FUNCTION(2, "DISP_PWM")
- ),
- MTK_PIN(
- PINCTRL_PIN(204, "PWM1"),
- "Y16", "mt7623",
- MTK_EINT_FUNCTION(0, 116),
- MTK_FUNCTION(0, "GPIO204"),
- MTK_FUNCTION(1, "PWM1")
- ),
- MTK_PIN(
- PINCTRL_PIN(205, "PWM2"),
- "AA15", "mt7623",
- MTK_EINT_FUNCTION(0, 117),
- MTK_FUNCTION(0, "GPIO205"),
- MTK_FUNCTION(1, "PWM2")
- ),
- MTK_PIN(
- PINCTRL_PIN(206, "PWM3"),
- "AA17", "mt7623",
- MTK_EINT_FUNCTION(0, 118),
- MTK_FUNCTION(0, "GPIO206"),
- MTK_FUNCTION(1, "PWM3")
- ),
- MTK_PIN(
- PINCTRL_PIN(207, "PWM4"),
- "Y15", "mt7623",
- MTK_EINT_FUNCTION(0, 119),
- MTK_FUNCTION(0, "GPIO207"),
- MTK_FUNCTION(1, "PWM4")
- ),
- MTK_PIN(
- PINCTRL_PIN(208, "AUD_EXT_CK1"),
- "W14", "mt7623",
- MTK_EINT_FUNCTION(0, 120),
- MTK_FUNCTION(0, "GPIO208"),
- MTK_FUNCTION(1, "AUD_EXT_CK1"),
- MTK_FUNCTION(2, "PWM0"),
- MTK_FUNCTION(3, "PCIE0_PERST_N"),
- MTK_FUNCTION(5, "DISP_PWM")
- ),
- MTK_PIN(
- PINCTRL_PIN(209, "AUD_EXT_CK2"),
- "V15", "mt7623",
- MTK_EINT_FUNCTION(0, 121),
- MTK_FUNCTION(0, "GPIO209"),
- MTK_FUNCTION(1, "AUD_EXT_CK2"),
- MTK_FUNCTION(2, "MSDC1_WP"),
- MTK_FUNCTION(3, "PCIE1_PERST_N"),
- MTK_FUNCTION(5, "PWM1")
- ),
- MTK_PIN(
- PINCTRL_PIN(210, "GPIO210"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO210")
- ),
- MTK_PIN(
- PINCTRL_PIN(211, "GPIO211"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO211")
- ),
- MTK_PIN(
- PINCTRL_PIN(212, "GPIO212"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO212")
- ),
- MTK_PIN(
- PINCTRL_PIN(213, "GPIO213"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO213")
- ),
- MTK_PIN(
- PINCTRL_PIN(214, "GPIO214"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO214")
- ),
- MTK_PIN(
- PINCTRL_PIN(215, "GPIO215"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO215")
- ),
- MTK_PIN(
- PINCTRL_PIN(216, "GPIO216"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO216")
- ),
- MTK_PIN(
- PINCTRL_PIN(217, "GPIO217"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO217")
- ),
- MTK_PIN(
- PINCTRL_PIN(218, "GPIO218"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO218")
- ),
- MTK_PIN(
- PINCTRL_PIN(219, "GPIO219"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO219")
- ),
- MTK_PIN(
- PINCTRL_PIN(220, "GPIO220"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO220")
- ),
- MTK_PIN(
- PINCTRL_PIN(221, "GPIO221"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO221")
- ),
- MTK_PIN(
- PINCTRL_PIN(222, "GPIO222"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO222")
- ),
- MTK_PIN(
- PINCTRL_PIN(223, "GPIO223"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO223")
- ),
- MTK_PIN(
- PINCTRL_PIN(224, "GPIO224"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO224")
- ),
- MTK_PIN(
- PINCTRL_PIN(225, "GPIO225"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO225")
- ),
- MTK_PIN(
- PINCTRL_PIN(226, "GPIO226"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO226")
- ),
- MTK_PIN(
- PINCTRL_PIN(227, "GPIO227"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO227")
- ),
- MTK_PIN(
- PINCTRL_PIN(228, "GPIO228"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO228")
- ),
- MTK_PIN(
- PINCTRL_PIN(229, "GPIO229"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO229")
- ),
- MTK_PIN(
- PINCTRL_PIN(230, "GPIO230"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO230")
- ),
- MTK_PIN(
- PINCTRL_PIN(231, "GPIO231"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO231")
- ),
- MTK_PIN(
- PINCTRL_PIN(232, "GPIO232"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO232")
- ),
- MTK_PIN(
- PINCTRL_PIN(233, "GPIO233"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO233")
- ),
- MTK_PIN(
- PINCTRL_PIN(234, "GPIO234"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO234")
- ),
- MTK_PIN(
- PINCTRL_PIN(235, "GPIO235"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO235")
- ),
- MTK_PIN(
- PINCTRL_PIN(236, "EXT_SDIO3"),
- "A8", "mt7623",
- MTK_EINT_FUNCTION(0, 122),
- MTK_FUNCTION(0, "GPIO236"),
- MTK_FUNCTION(1, "EXT_SDIO3"),
- MTK_FUNCTION(2, "IDDIG")
- ),
- MTK_PIN(
- PINCTRL_PIN(237, "EXT_SDIO2"),
- "D8", "mt7623",
- MTK_EINT_FUNCTION(0, 123),
- MTK_FUNCTION(0, "GPIO237"),
- MTK_FUNCTION(1, "EXT_SDIO2"),
- MTK_FUNCTION(2, "DRV_VBUS")
- ),
- MTK_PIN(
- PINCTRL_PIN(238, "EXT_SDIO1"),
- "D9", "mt7623",
- MTK_EINT_FUNCTION(0, 124),
- MTK_FUNCTION(0, "GPIO238"),
- MTK_FUNCTION(1, "EXT_SDIO1")
- ),
- MTK_PIN(
- PINCTRL_PIN(239, "EXT_SDIO0"),
- "B8", "mt7623",
- MTK_EINT_FUNCTION(0, 125),
- MTK_FUNCTION(0, "GPIO239"),
- MTK_FUNCTION(1, "EXT_SDIO0")
- ),
- MTK_PIN(
- PINCTRL_PIN(240, "EXT_XCS"),
- "C9", "mt7623",
- MTK_EINT_FUNCTION(0, 126),
- MTK_FUNCTION(0, "GPIO240"),
- MTK_FUNCTION(1, "EXT_XCS")
- ),
- MTK_PIN(
- PINCTRL_PIN(241, "EXT_SCK"),
- "C8", "mt7623",
- MTK_EINT_FUNCTION(0, 127),
- MTK_FUNCTION(0, "GPIO241"),
- MTK_FUNCTION(1, "EXT_SCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(242, "URTS2"),
- "G18", "mt7623",
- MTK_EINT_FUNCTION(0, 128),
- MTK_FUNCTION(0, "GPIO242"),
- MTK_FUNCTION(1, "URTS2"),
- MTK_FUNCTION(2, "UTXD3"),
- MTK_FUNCTION(3, "URXD3"),
- MTK_FUNCTION(4, "SCL1")
- ),
- MTK_PIN(
- PINCTRL_PIN(243, "UCTS2"),
- "H19", "mt7623",
- MTK_EINT_FUNCTION(0, 129),
- MTK_FUNCTION(0, "GPIO243"),
- MTK_FUNCTION(1, "UCTS2"),
- MTK_FUNCTION(2, "URXD3"),
- MTK_FUNCTION(3, "UTXD3"),
- MTK_FUNCTION(4, "SDA1")
- ),
- MTK_PIN(
- PINCTRL_PIN(244, "GPIO244"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO244")
- ),
- MTK_PIN(
- PINCTRL_PIN(245, "GPIO245"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO245")
- ),
- MTK_PIN(
- PINCTRL_PIN(246, "GPIO246"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO246")
- ),
- MTK_PIN(
- PINCTRL_PIN(247, "GPIO247"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO247")
- ),
- MTK_PIN(
- PINCTRL_PIN(248, "GPIO248"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO248")
- ),
- MTK_PIN(
- PINCTRL_PIN(249, "GPIO249"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO249")
- ),
- MTK_PIN(
- PINCTRL_PIN(250, "GPIO250"),
- "A15", "mt7623",
- MTK_EINT_FUNCTION(0, 135),
- MTK_FUNCTION(0, "GPIO250"),
- MTK_FUNCTION(1, "TEST_MD7"),
- MTK_FUNCTION(6, "PCIE0_CLKREQ_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(251, "GPIO251"),
- "B15", "mt7623",
- MTK_EINT_FUNCTION(0, 136),
- MTK_FUNCTION(0, "GPIO251"),
- MTK_FUNCTION(1, "TEST_MD6"),
- MTK_FUNCTION(6, "PCIE0_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(252, "GPIO252"),
- "C16", "mt7623",
- MTK_EINT_FUNCTION(0, 137),
- MTK_FUNCTION(0, "GPIO252"),
- MTK_FUNCTION(1, "TEST_MD5"),
- MTK_FUNCTION(6, "PCIE1_CLKREQ_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(253, "GPIO253"),
- "D17", "mt7623",
- MTK_EINT_FUNCTION(0, 138),
- MTK_FUNCTION(0, "GPIO253"),
- MTK_FUNCTION(1, "TEST_MD4"),
- MTK_FUNCTION(6, "PCIE1_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(254, "GPIO254"),
- "D16", "mt7623",
- MTK_EINT_FUNCTION(0, 139),
- MTK_FUNCTION(0, "GPIO254"),
- MTK_FUNCTION(1, "TEST_MD3"),
- MTK_FUNCTION(6, "PCIE2_CLKREQ_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(255, "GPIO255"),
- "C17", "mt7623",
- MTK_EINT_FUNCTION(0, 140),
- MTK_FUNCTION(0, "GPIO255"),
- MTK_FUNCTION(1, "TEST_MD2"),
- MTK_FUNCTION(6, "PCIE2_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(256, "GPIO256"),
- "B17", "mt7623",
- MTK_EINT_FUNCTION(0, 141),
- MTK_FUNCTION(0, "GPIO256"),
- MTK_FUNCTION(1, "TEST_MD1")
- ),
- MTK_PIN(
- PINCTRL_PIN(257, "GPIO257"),
- "C15", "mt7623",
- MTK_EINT_FUNCTION(0, 142),
- MTK_FUNCTION(0, "GPIO257"),
- MTK_FUNCTION(1, "TEST_MD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(258, "GPIO258"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO258")
- ),
- MTK_PIN(
- PINCTRL_PIN(259, "GPIO259"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO259")
- ),
- MTK_PIN(
- PINCTRL_PIN(260, "GPIO260"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO260")
- ),
- MTK_PIN(
- PINCTRL_PIN(261, "MSDC1_INS"),
- "AD1", "mt7623",
- MTK_EINT_FUNCTION(0, 146),
- MTK_FUNCTION(0, "GPIO261"),
- MTK_FUNCTION(1, "MSDC1_INS")
- ),
- MTK_PIN(
- PINCTRL_PIN(262, "G2_TXEN"),
- "A23", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO262"),
- MTK_FUNCTION(1, "G2_TXEN")
- ),
- MTK_PIN(
- PINCTRL_PIN(263, "G2_TXD3"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO263"),
- MTK_FUNCTION(1, "G2_TXD3")
- ),
- MTK_PIN(
- PINCTRL_PIN(264, "G2_TXD2"),
- "C24", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO264"),
- MTK_FUNCTION(1, "G2_TXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(265, "G2_TXD1"),
- "B25", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO265"),
- MTK_FUNCTION(1, "G2_TXD1")
- ),
- MTK_PIN(
- PINCTRL_PIN(266, "G2_TXD0"),
- "A24", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO266"),
- MTK_FUNCTION(1, "G2_TXD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(267, "G2_TXCLK"),
- "C23", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO267"),
- MTK_FUNCTION(1, "G2_TXC")
- ),
- MTK_PIN(
- PINCTRL_PIN(268, "G2_RXCLK"),
- "B23", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO268"),
- MTK_FUNCTION(1, "G2_RXC")
- ),
- MTK_PIN(
- PINCTRL_PIN(269, "G2_RXD0"),
- "D21", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO269"),
- MTK_FUNCTION(1, "G2_RXD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(270, "G2_RXD1"),
- "B22", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO270"),
- MTK_FUNCTION(1, "G2_RXD1")
- ),
- MTK_PIN(
- PINCTRL_PIN(271, "G2_RXD2"),
- "A22", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO271"),
- MTK_FUNCTION(1, "G2_RXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(272, "G2_RXD3"),
- "C22", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO272"),
- MTK_FUNCTION(1, "G2_RXD3")
- ),
- MTK_PIN(
- PINCTRL_PIN(273, "GPIO273"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO273")
- ),
- MTK_PIN(
- PINCTRL_PIN(274, "G2_RXDV"),
- "C21", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO274"),
- MTK_FUNCTION(1, "G2_RXDV")
- ),
- MTK_PIN(
- PINCTRL_PIN(275, "G2_MDC"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO275"),
- MTK_FUNCTION(1, "MDC")
- ),
- MTK_PIN(
- PINCTRL_PIN(276, "G2_MDIO"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO276"),
- MTK_FUNCTION(1, "MDIO")
- ),
- MTK_PIN(
- PINCTRL_PIN(277, "GPIO277"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO277")
- ),
- MTK_PIN(
- PINCTRL_PIN(278, "JTAG_RESET"),
- "H20", "mt7623",
- MTK_EINT_FUNCTION(0, 147),
- MTK_FUNCTION(0, "GPIO278"),
- MTK_FUNCTION(1, "JTAG_RESET")
- ),
-};
-
-#endif /* __PINCTRL_MTK_MT7623_H */
static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) };
static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) };
+static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) };
+static const unsigned int pwm_b_x_pins[] = { PIN(GPIOX_11, 0) };
+
/* bank Y */
static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) };
static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) };
static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) };
static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) };
+static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, 0) };
+
+static const unsigned int i2s_out_ch45_pins[] = { PIN(GPIOY_0, 0) };
+static const unsigned int i2s_out_ch23_pins[] = { PIN(GPIOY_1, 0) };
+static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOY_4, 0) };
+static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOY_5, 0) };
+static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOY_6, 0) };
+static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOY_7, 0) };
+static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOY_8, 0) };
+static const unsigned int i2s_out_ch78_pins[] = { PIN(GPIOY_9, 0) };
+
+static const unsigned int spdif_in_pins[] = { PIN(GPIOY_2, 0) };
+static const unsigned int spdif_out_pins[] = { PIN(GPIOY_3, 0) };
+
/* bank DV */
static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0),
PIN(GPIODV_2, 0), PIN(GPIODV_3, 0),
static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) };
static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) };
+static const unsigned int pwm_c_dv9_pins[] = { PIN(GPIODV_9, 0) };
+static const unsigned int pwm_c_dv29_pins[] = { PIN(GPIODV_29, 0) };
+static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) };
+
/* bank H */
static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) };
static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) };
static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) };
static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) };
+static const unsigned int pwm_a_z0_pins[] = { PIN(GPIOZ_0, 0) };
+static const unsigned int pwm_a_z7_pins[] = { PIN(GPIOZ_7, 0) };
+static const unsigned int pwm_b_z_pins[] = { PIN(GPIOZ_1, 0) };
+static const unsigned int pwm_c_z_pins[] = { PIN(GPIOZ_8, 0) };
+
/* bank BOOT */
static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) };
static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) };
static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) };
static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) };
+static const unsigned int remote_output_ao_pins[] = { PIN(GPIOAO_13, AO_OFF) };
static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
+static const unsigned int pwm_f_ao_pins[] = { PIN(GPIO_TEST_N, AO_OFF) };
+
+static const unsigned int i2s_am_clk_out_ao_pins[] = { PIN(GPIOAO_8, AO_OFF) };
+static const unsigned int i2s_ao_clk_out_ao_pins[] = { PIN(GPIOAO_9, AO_OFF) };
+static const unsigned int i2s_lr_clk_out_ao_pins[] = { PIN(GPIOAO_10, AO_OFF) };
+static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, AO_OFF) };
+
+static const unsigned int hdmi_cec_ao_pins[] = { PIN(GPIOAO_12, AO_OFF) };
+
static struct meson_pmx_group meson8_cbus_groups[] = {
GPIO_GROUP(GPIOX_0, 0),
GPIO_GROUP(GPIOX_1, 0),
GROUP(xtal_32k_out, 3, 22),
GROUP(xtal_24m_out, 3, 23),
+ GROUP(pwm_e, 9, 19),
+ GROUP(pwm_b_x, 2, 3),
+
/* bank Y */
GROUP(uart_tx_c, 1, 19),
GROUP(uart_rx_c, 1, 18),
GROUP(i2c_sda_c0, 1, 15),
GROUP(i2c_sck_c0, 1, 14),
+ GROUP(pwm_a_y, 9, 14),
+
+ GROUP(i2s_out_ch45, 1, 10),
+ GROUP(i2s_out_ch23, 1, 19),
+ GROUP(i2s_out_ch01, 1, 6),
+ GROUP(i2s_in_ch01, 1, 5),
+ GROUP(i2s_lr_clk_in, 1, 4),
+ GROUP(i2s_ao_clk_in, 1, 2),
+ GROUP(i2s_am_clk, 1, 0),
+ GROUP(i2s_out_ch78, 1, 11),
+
+ GROUP(spdif_in, 1, 8),
+ GROUP(spdif_out, 1, 7),
+
/* bank DV */
GROUP(dvin_rgb, 0, 6),
GROUP(dvin_vs, 0, 9),
GROUP(vga_vs, 0, 21),
GROUP(vga_hs, 0, 20),
+ GROUP(pwm_c_dv9, 3, 24),
+ GROUP(pwm_c_dv29, 3, 25),
+ GROUP(pwm_d, 3, 26),
+
/* bank H */
GROUP(hdmi_hpd, 1, 26),
GROUP(hdmi_sda, 1, 25),
GROUP(i2c_sda_a2, 5, 7),
GROUP(i2c_sck_a2, 5, 6),
+ GROUP(pwm_a_z0, 9, 16),
+ GROUP(pwm_a_z7, 2, 0),
+ GROUP(pwm_b_z, 9, 15),
+ GROUP(pwm_c_z, 2, 1),
+
/* bank BOOT */
GROUP(sd_d0_c, 6, 29),
GROUP(sd_d1_c, 6, 28),
GROUP(uart_rts_ao_a, 0, 9),
GROUP(remote_input, 0, 0),
+ GROUP(remote_output_ao, 0, 31),
GROUP(i2c_slave_sck_ao, 0, 2),
GROUP(i2c_slave_sda_ao, 0, 1),
GROUP(i2c_mst_sck_ao, 0, 6),
GROUP(i2c_mst_sda_ao, 0, 5),
+
+ GROUP(pwm_f_ao, 0, 19),
+
+ GROUP(i2s_am_clk_out_ao, 0, 30),
+ GROUP(i2s_ao_clk_out_ao, 0, 29),
+ GROUP(i2s_lr_clk_out_ao, 0, 28),
+ GROUP(i2s_out_ch01_ao, 0, 27),
+
+ GROUP(hdmi_cec_ao, 0, 17),
};
static const char * const gpio_groups[] = {
"i2c_sda_b", "i2c_sck_b"
};
+static const char * const i2s_groups[] = {
+ "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins",
+ "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins",
+ "i2s_am_clk_pins", "i2s_out_ch78_pins"
+};
+
static const char * const sd_c_groups[] = {
"sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
"sd_cmd_c", "sd_clk_c"
"nor_d", "nor_q", "nor_c", "nor_cs"
};
+static const char * const pwm_a_groups[] = {
+ "pwm_a_y", "pwm_a_z0", "pwm_a_z7"
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b_x", "pwm_b_z"
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c_dv9", "pwm_c_dv29", "pwm_c_z"
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d"
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e"
+};
+
static const char * const sd_b_groups[] = {
"sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
"sd_d3_b", "sd_d2_b"
"sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
};
+static const char * const spdif_groups[] = {
+ "spdif_in", "spdif_out"
+};
+
static const char * const uart_ao_groups[] = {
"uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
};
static const char * const remote_groups[] = {
- "remote_input"
+ "remote_input", "remote_output_ao"
};
static const char * const i2c_slave_ao_groups[] = {
"i2c_mst_sck_ao", "i2c_mst_sda_ao"
};
+static const char * const pwm_f_ao_groups[] = {
+ "pwm_f_ao"
+};
+
+static const char * const i2s_ao_groups[] = {
+ "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao",
+ "i2s_out_ch01_ao"
+};
+
+static const char * const hdmi_cec_ao_groups[] = {
+ "hdmi_cec_ao"
+};
+
static struct meson_pmx_func meson8_cbus_functions[] = {
FUNCTION(gpio),
FUNCTION(sd_a),
FUNCTION(nor),
FUNCTION(sd_b),
FUNCTION(sdxc_b),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(i2s),
+ FUNCTION(spdif),
};
static struct meson_pmx_func meson8_aobus_functions[] = {
FUNCTION(i2c_slave_ao),
FUNCTION(uart_ao_b),
FUNCTION(i2c_mst_ao),
+ FUNCTION(pwm_f_ao),
+ FUNCTION(i2s_ao),
+ FUNCTION(hdmi_cec_ao),
};
static struct meson_bank meson8_cbus_banks[] = {
#include <linux/gpio/driver.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_device.h>
+#include <linux/of_irq.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#define OUTPUT_CTL 0x20
#define SELECTION 0x30
+#define IRQ_EN 0x0
+#define IRQ_POL 0x08
+#define IRQ_STATUS 0x10
+#define IRQ_WKUP 0x18
+
#define NB_FUNCS 2
#define GPIO_PER_REG 32
struct armada_37xx_pinctrl {
struct regmap *regmap;
+ void __iomem *base;
const struct armada_37xx_pin_data *data;
struct device *dev;
struct gpio_chip gpio_chip;
+ struct irq_chip irq_chip;
+ spinlock_t irq_lock;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct armada_37xx_pin_group *groups;
return armada_37xx_pmx_set_by_name(pctldev, name, grp);
}
+static inline void armada_37xx_irq_update_reg(unsigned int *reg,
+ struct irq_data *d)
+{
+ int offset = irqd_to_hwirq(d);
+
+ armada_37xx_update_reg(reg, offset);
+}
+
static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
.owner = THIS_MODULE,
};
+static void armada_37xx_irq_ack(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 reg = IRQ_STATUS;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(®, d);
+ spin_lock_irqsave(&info->irq_lock, flags);
+ writel(d->mask, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+}
+
+static void armada_37xx_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(®, d);
+ spin_lock_irqsave(&info->irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val & ~d->mask, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+}
+
+static void armada_37xx_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(®, d);
+ spin_lock_irqsave(&info->irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val | d->mask, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+}
+
+static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_WKUP;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(®, d);
+ spin_lock_irqsave(&info->irq_lock, flags);
+ val = readl(info->base + reg);
+ if (on)
+ val |= d->mask;
+ else
+ val &= ~d->mask;
+ writel(val, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+
+ return 0;
+}
+
+static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_POL;
+ unsigned long flags;
+
+ spin_lock_irqsave(&info->irq_lock, flags);
+ armada_37xx_irq_update_reg(®, d);
+ val = readl(info->base + reg);
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ val &= ~d->mask;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ val |= d->mask;
+ break;
+ default:
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+ return -EINVAL;
+ }
+ writel(val, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+
+ return 0;
+}
+
+
+static void armada_37xx_irq_handler(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
+ struct irq_domain *d = gc->irqdomain;
+ int i;
+
+ chained_irq_enter(chip, desc);
+ for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
+ u32 status;
+ unsigned long flags;
+
+ spin_lock_irqsave(&info->irq_lock, flags);
+ status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
+ /* Manage only the interrupt that was enabled */
+ status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+ while (status) {
+ u32 hwirq = ffs(status) - 1;
+ u32 virq = irq_find_mapping(d, hwirq +
+ i * GPIO_PER_REG);
+
+ generic_handle_irq(virq);
+
+ /* Update status in case a new IRQ appears */
+ spin_lock_irqsave(&info->irq_lock, flags);
+ status = readl_relaxed(info->base +
+ IRQ_STATUS + 4 * i);
+ /* Manage only the interrupt that was enabled */
+ status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+ }
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static int armada_37xx_irqchip_register(struct platform_device *pdev,
+ struct armada_37xx_pinctrl *info)
+{
+ struct device_node *np = info->dev->of_node;
+ int nrirqs = info->data->nr_pins;
+ struct gpio_chip *gc = &info->gpio_chip;
+ struct irq_chip *irqchip = &info->irq_chip;
+ struct resource res;
+ int ret = -ENODEV, i, nr_irq_parent;
+
+ /* Check if we have at least one gpio-controller child node */
+ for_each_child_of_node(info->dev->of_node, np) {
+ if (of_property_read_bool(np, "gpio-controller")) {
+ ret = 0;
+ break;
+ }
+ };
+ if (ret)
+ return ret;
+
+ nr_irq_parent = of_irq_count(np);
+ spin_lock_init(&info->irq_lock);
+
+ if (!nr_irq_parent) {
+ dev_err(&pdev->dev, "Invalid or no IRQ\n");
+ return 0;
+ }
+
+ if (of_address_to_resource(info->dev->of_node, 1, &res)) {
+ dev_err(info->dev, "cannot find IO resource\n");
+ return -ENOENT;
+ }
+
+ info->base = devm_ioremap_resource(info->dev, &res);
+ if (IS_ERR(info->base))
+ return PTR_ERR(info->base);
+
+ irqchip->irq_ack = armada_37xx_irq_ack;
+ irqchip->irq_mask = armada_37xx_irq_mask;
+ irqchip->irq_unmask = armada_37xx_irq_unmask;
+ irqchip->irq_set_wake = armada_37xx_irq_set_wake;
+ irqchip->irq_set_type = armada_37xx_irq_set_type;
+ irqchip->name = info->data->name;
+
+ ret = gpiochip_irqchip_add(gc, irqchip, 0,
+ handle_edge_irq, IRQ_TYPE_NONE);
+ if (ret) {
+ dev_info(&pdev->dev, "could not add irqchip\n");
+ return ret;
+ }
+
+ /*
+ * Many interrupts are connected to the parent interrupt
+ * controller. But we do not take advantage of this and use
+ * the chained irq with all of them.
+ */
+ for (i = 0; i < nrirqs; i++) {
+ struct irq_data *d = irq_get_irq_data(gc->irq_base + i);
+
+ /*
+ * The mask field is a "precomputed bitmask for
+ * accessing the chip registers" which was introduced
+ * for the generic irqchip framework. As we don't use
+ * this framework, we can reuse this field for our own
+ * usage.
+ */
+ d->mask = BIT(i % GPIO_PER_REG);
+ }
+
+ for (i = 0; i < nr_irq_parent; i++) {
+ int irq = irq_of_parse_and_map(np, i);
+
+ if (irq < 0)
+ continue;
+
+ gpiochip_set_chained_irqchip(gc, irqchip, irq,
+ armada_37xx_irq_handler);
+ }
+
+ return 0;
+}
+
static int armada_37xx_gpiochip_register(struct platform_device *pdev,
struct armada_37xx_pinctrl *info)
{
gc->label = info->data->name;
ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
+ if (ret)
+ return ret;
+ ret = armada_37xx_irqchip_register(pdev, info);
if (ret)
return ret;
ops = pctldev->desc->confops;
if (!ops || !ops->pin_config_group_get) {
- dev_dbg(pctldev->dev, "cannot get configuration for pin "
- "group, missing group config get function in "
- "driver\n");
+ dev_dbg(pctldev->dev,
+ "cannot get configuration for pin group, missing group config get function in driver\n");
ret = -ENOTSUPP;
goto unlock;
}
configs[i]);
else
seq_printf(s, "%08lx", configs[i]);
- seq_puts(s, "\n");
+ seq_putc(s, '\n');
}
}
switch (map->type) {
case PIN_MAP_TYPE_CONFIGS_PIN:
- seq_printf(s, "pin ");
+ seq_puts(s, "pin ");
break;
case PIN_MAP_TYPE_CONFIGS_GROUP:
- seq_printf(s, "group ");
+ seq_puts(s, "group ");
break;
default:
break;
pin = pctldev->desc->pins[i].number;
desc = pin_desc_get(pctldev, pin);
/* Skip if we cannot search the pin */
- if (desc == NULL)
+ if (!desc)
continue;
seq_printf(s, "pin %d (%s): ", pin, desc->name);
pinconf_dump_pin(pctldev, s, pin);
-
- seq_printf(s, "\n");
+ seq_putc(s, '\n');
}
mutex_unlock(&pctldev->mutex);
seq_printf(s, "%u (%s): ", selector, gname);
pinconf_dump_group(pctldev, s, selector, gname);
- seq_printf(s, "\n");
-
+ seq_putc(s, '\n');
selector++;
}
struct dbg_cfg {
enum pinctrl_map_type map_type;
- char dev_name[MAX_NAME_LEN+1];
- char state_name[MAX_NAME_LEN+1];
- char pin_name[MAX_NAME_LEN+1];
+ char dev_name[MAX_NAME_LEN + 1];
+ char state_name[MAX_NAME_LEN + 1];
+ char pin_name[MAX_NAME_LEN + 1];
};
/*
const struct pinconf_ops *confops = NULL;
struct dbg_cfg *dbg = &pinconf_dbg_conf;
const struct pinctrl_map_configs *configs;
- char config[MAX_NAME_LEN+1];
+ char config[MAX_NAME_LEN + 1];
char buf[128];
char *b = &buf[0];
int buf_size;
/* get arg 'device_name' */
token = strsep(&b, " ");
- if (token == NULL)
+ if (!token)
return -EINVAL;
if (strlen(token) >= MAX_NAME_LEN)
return -EINVAL;
/* get arg 'state_name' */
token = strsep(&b, " ");
- if (token == NULL)
+ if (!token)
return -EINVAL;
if (strlen(token) >= MAX_NAME_LEN)
return -EINVAL;
/* get arg 'pin_name' */
token = strsep(&b, " ");
- if (token == NULL)
+ if (!token)
return -EINVAL;
if (strlen(token) >= MAX_NAME_LEN)
return -EINVAL;
/* get new_value of config' */
token = strsep(&b, " ");
- if (token == NULL)
+ if (!token)
return -EINVAL;
if (strlen(token) >= MAX_NAME_LEN)
return -EINVAL;
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
+ *
+ * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
+ * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
+ *
*/
#include <linux/err.h>
--- /dev/null
+/*
+ * Ingenic SoCs pinctrl driver
+ *
+ * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/compiler.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "pinconf.h"
+#include "pinmux.h"
+
+#define JZ4740_GPIO_DATA 0x10
+#define JZ4740_GPIO_PULL_DIS 0x30
+#define JZ4740_GPIO_FUNC 0x40
+#define JZ4740_GPIO_SELECT 0x50
+#define JZ4740_GPIO_DIR 0x60
+#define JZ4740_GPIO_TRIG 0x70
+#define JZ4740_GPIO_FLAG 0x80
+
+#define JZ4770_GPIO_INT 0x10
+#define JZ4770_GPIO_MSK 0x20
+#define JZ4770_GPIO_PAT1 0x30
+#define JZ4770_GPIO_PAT0 0x40
+#define JZ4770_GPIO_FLAG 0x50
+#define JZ4770_GPIO_PEN 0x70
+
+#define REG_SET(x) ((x) + 0x4)
+#define REG_CLEAR(x) ((x) + 0x8)
+
+#define PINS_PER_GPIO_CHIP 32
+
+enum jz_version {
+ ID_JZ4740,
+ ID_JZ4770,
+ ID_JZ4780,
+};
+
+struct ingenic_chip_info {
+ unsigned int num_chips;
+
+ const struct group_desc *groups;
+ unsigned int num_groups;
+
+ const struct function_desc *functions;
+ unsigned int num_functions;
+
+ const u32 *pull_ups, *pull_downs;
+};
+
+struct ingenic_pinctrl {
+ struct device *dev;
+ struct regmap *map;
+ struct pinctrl_dev *pctl;
+ struct pinctrl_pin_desc *pdesc;
+ enum jz_version version;
+
+ const struct ingenic_chip_info *info;
+};
+
+static const u32 jz4740_pull_ups[4] = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+};
+
+static const u32 jz4740_pull_downs[4] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
+static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
+static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
+static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
+static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
+static int jz4740_lcd_8bit_pins[] = {
+ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
+};
+static int jz4740_lcd_16bit_pins[] = {
+ 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
+};
+static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
+static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
+static int jz4740_nand_cs1_pins[] = { 0x39, };
+static int jz4740_nand_cs2_pins[] = { 0x3a, };
+static int jz4740_nand_cs3_pins[] = { 0x3b, };
+static int jz4740_nand_cs4_pins[] = { 0x3c, };
+static int jz4740_pwm_pwm0_pins[] = { 0x77, };
+static int jz4740_pwm_pwm1_pins[] = { 0x78, };
+static int jz4740_pwm_pwm2_pins[] = { 0x79, };
+static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
+static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
+static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
+static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
+static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
+
+static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, };
+static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, };
+static int jz4740_uart0_data_funcs[] = { 1, 1, };
+static int jz4740_uart0_hwflow_funcs[] = { 1, 1, };
+static int jz4740_uart1_data_funcs[] = { 2, 2, };
+static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4740_lcd_18bit_funcs[] = { 0, 0, };
+static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, };
+static int jz4740_nand_cs1_funcs[] = { 0, };
+static int jz4740_nand_cs2_funcs[] = { 0, };
+static int jz4740_nand_cs3_funcs[] = { 0, };
+static int jz4740_nand_cs4_funcs[] = { 0, };
+static int jz4740_pwm_pwm0_funcs[] = { 0, };
+static int jz4740_pwm_pwm1_funcs[] = { 0, };
+static int jz4740_pwm_pwm2_funcs[] = { 0, };
+static int jz4740_pwm_pwm3_funcs[] = { 0, };
+static int jz4740_pwm_pwm4_funcs[] = { 0, };
+static int jz4740_pwm_pwm5_funcs[] = { 0, };
+static int jz4740_pwm_pwm6_funcs[] = { 0, };
+static int jz4740_pwm_pwm7_funcs[] = { 0, };
+
+#define INGENIC_PIN_GROUP(name, id) \
+ { \
+ name, \
+ id##_pins, \
+ ARRAY_SIZE(id##_pins), \
+ id##_funcs, \
+ }
+
+static const struct group_desc jz4740_groups[] = {
+ INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
+ INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
+ INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
+ INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
+ INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
+ INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
+ INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
+ INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
+ INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
+ { "lcd-no-pins", },
+ INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
+ INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
+ INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
+ INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
+ INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
+ INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
+ INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
+ INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3),
+ INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4),
+ INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5),
+ INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6),
+ INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
+};
+
+static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
+static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
+static const char *jz4740_uart1_groups[] = { "uart1-data", };
+static const char *jz4740_lcd_groups[] = {
+ "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
+};
+static const char *jz4740_nand_groups[] = {
+ "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
+};
+static const char *jz4740_pwm0_groups[] = { "pwm0", };
+static const char *jz4740_pwm1_groups[] = { "pwm1", };
+static const char *jz4740_pwm2_groups[] = { "pwm2", };
+static const char *jz4740_pwm3_groups[] = { "pwm3", };
+static const char *jz4740_pwm4_groups[] = { "pwm4", };
+static const char *jz4740_pwm5_groups[] = { "pwm5", };
+static const char *jz4740_pwm6_groups[] = { "pwm6", };
+static const char *jz4740_pwm7_groups[] = { "pwm7", };
+
+static const struct function_desc jz4740_functions[] = {
+ { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
+ { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
+ { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
+ { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
+ { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
+ { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
+ { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
+ { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
+ { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
+ { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
+ { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
+ { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
+ { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
+};
+
+static const struct ingenic_chip_info jz4740_chip_info = {
+ .num_chips = 4,
+ .groups = jz4740_groups,
+ .num_groups = ARRAY_SIZE(jz4740_groups),
+ .functions = jz4740_functions,
+ .num_functions = ARRAY_SIZE(jz4740_functions),
+ .pull_ups = jz4740_pull_ups,
+ .pull_downs = jz4740_pull_downs,
+};
+
+static const u32 jz4770_pull_ups[6] = {
+ 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
+};
+
+static const u32 jz4770_pull_downs[6] = {
+ 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
+};
+
+static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
+static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
+static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
+static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
+static int jz4770_uart2_data_pins[] = { 0x66, 0x67, };
+static int jz4770_uart2_hwflow_pins[] = { 0x65, 0x64, };
+static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
+static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
+static int jz4770_uart4_data_pins[] = { 0x54, 0x4a, };
+static int jz4770_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
+static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
+static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
+static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
+static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
+static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4770_nemc_data_pins[] = {
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+};
+static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
+static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
+static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
+static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
+static int jz4770_nemc_cs1_pins[] = { 0x15, };
+static int jz4770_nemc_cs2_pins[] = { 0x16, };
+static int jz4770_nemc_cs3_pins[] = { 0x17, };
+static int jz4770_nemc_cs4_pins[] = { 0x18, };
+static int jz4770_nemc_cs5_pins[] = { 0x19, };
+static int jz4770_nemc_cs6_pins[] = { 0x1a, };
+static int jz4770_i2c0_pins[] = { 0x6e, 0x6f, };
+static int jz4770_i2c1_pins[] = { 0x8e, 0x8f, };
+static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
+static int jz4770_i2c3_pins[] = { 0x6a, 0x6b, };
+static int jz4770_i2c4_e_pins[] = { 0x8c, 0x8d, };
+static int jz4770_i2c4_f_pins[] = { 0xb9, 0xb8, };
+static int jz4770_cim_pins[] = {
+ 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+};
+static int jz4770_lcd_32bit_pins[] = {
+ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
+ 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
+ 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
+ 0x58, 0x59, 0x51,
+};
+static int jz4770_pwm_pwm0_pins[] = { 0x80, };
+static int jz4770_pwm_pwm1_pins[] = { 0x81, };
+static int jz4770_pwm_pwm2_pins[] = { 0x82, };
+static int jz4770_pwm_pwm3_pins[] = { 0x83, };
+static int jz4770_pwm_pwm4_pins[] = { 0x84, };
+static int jz4770_pwm_pwm5_pins[] = { 0x85, };
+static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
+static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
+
+static int jz4770_uart0_data_funcs[] = { 0, 0, };
+static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
+static int jz4770_uart1_data_funcs[] = { 0, 0, };
+static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
+static int jz4770_uart2_data_funcs[] = { 1, 1, };
+static int jz4770_uart2_hwflow_funcs[] = { 1, 1, };
+static int jz4770_uart3_data_funcs[] = { 0, 1, };
+static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
+static int jz4770_uart4_data_funcs[] = { 2, 2, };
+static int jz4770_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
+static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
+static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
+static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
+static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
+static int jz4770_nemc_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
+static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
+static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
+static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
+static int jz4770_nemc_cs1_funcs[] = { 0, };
+static int jz4770_nemc_cs2_funcs[] = { 0, };
+static int jz4770_nemc_cs3_funcs[] = { 0, };
+static int jz4770_nemc_cs4_funcs[] = { 0, };
+static int jz4770_nemc_cs5_funcs[] = { 0, };
+static int jz4770_nemc_cs6_funcs[] = { 0, };
+static int jz4770_i2c0_funcs[] = { 0, 0, };
+static int jz4770_i2c1_funcs[] = { 0, 0, };
+static int jz4770_i2c2_funcs[] = { 2, 2, };
+static int jz4770_i2c3_funcs[] = { 1, 1, };
+static int jz4770_i2c4_e_funcs[] = { 1, 1, };
+static int jz4770_i2c4_f_funcs[] = { 1, 1, };
+static int jz4770_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_lcd_32bit_funcs[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0,
+};
+static int jz4770_pwm_pwm0_funcs[] = { 0, };
+static int jz4770_pwm_pwm1_funcs[] = { 0, };
+static int jz4770_pwm_pwm2_funcs[] = { 0, };
+static int jz4770_pwm_pwm3_funcs[] = { 0, };
+static int jz4770_pwm_pwm4_funcs[] = { 0, };
+static int jz4770_pwm_pwm5_funcs[] = { 0, };
+static int jz4770_pwm_pwm6_funcs[] = { 0, };
+static int jz4770_pwm_pwm7_funcs[] = { 0, };
+
+static const struct group_desc jz4770_groups[] = {
+ INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
+ INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
+ INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
+ INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
+ INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
+ INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
+ INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
+ INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
+ INGENIC_PIN_GROUP("uart4-data", jz4770_uart4_data),
+ INGENIC_PIN_GROUP("mmc0-8bit-a", jz4770_mmc0_8bit_a),
+ INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
+ INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
+ INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+ INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
+ INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
+ INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
+ INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+ INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
+ INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_data),
+ INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
+ INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
+ INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
+ INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
+ INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
+ INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
+ INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
+ INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
+ INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
+ INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
+ INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
+ INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
+ INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
+ INGENIC_PIN_GROUP("i2c3-data", jz4770_i2c3),
+ INGENIC_PIN_GROUP("i2c4-data-e", jz4770_i2c4_e),
+ INGENIC_PIN_GROUP("i2c4-data-f", jz4770_i2c4_f),
+ INGENIC_PIN_GROUP("cim-data", jz4770_cim),
+ INGENIC_PIN_GROUP("lcd-32bit", jz4770_lcd_32bit),
+ { "lcd-no-pins", },
+ INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
+ INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
+ INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
+ INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
+ INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
+ INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
+ INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
+ INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
+};
+
+static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
+static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
+static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
+static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
+static const char *jz4770_uart4_groups[] = { "uart4-data", };
+static const char *jz4770_mmc0_groups[] = {
+ "mmc0-8bit-a", "mmc0-4bit-a", "mmc0-1bit-a",
+ "mmc0-1bit-e", "mmc0-4bit-e",
+};
+static const char *jz4770_mmc1_groups[] = {
+ "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
+};
+static const char *jz4770_nemc_groups[] = {
+ "nemc-data", "nemc-cle-ale", "nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
+};
+static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
+static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
+static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
+static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
+static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
+static const char *jz4770_i2c3_groups[] = { "i2c3-data", };
+static const char *jz4770_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
+static const char *jz4770_cim_groups[] = { "cim-data", };
+static const char *jz4770_lcd_groups[] = { "lcd-32bit", "lcd-no-pins", };
+static const char *jz4770_pwm0_groups[] = { "pwm0", };
+static const char *jz4770_pwm1_groups[] = { "pwm1", };
+static const char *jz4770_pwm2_groups[] = { "pwm2", };
+static const char *jz4770_pwm3_groups[] = { "pwm3", };
+static const char *jz4770_pwm4_groups[] = { "pwm4", };
+static const char *jz4770_pwm5_groups[] = { "pwm5", };
+static const char *jz4770_pwm6_groups[] = { "pwm6", };
+static const char *jz4770_pwm7_groups[] = { "pwm7", };
+
+static const struct function_desc jz4770_functions[] = {
+ { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
+ { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
+ { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
+ { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
+ { "uart4", jz4770_uart4_groups, ARRAY_SIZE(jz4770_uart4_groups), },
+ { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
+ { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
+ { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
+ { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
+ { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
+ { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
+ { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
+ { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
+ { "i2c3", jz4770_i2c3_groups, ARRAY_SIZE(jz4770_i2c3_groups), },
+ { "i2c4", jz4770_i2c4_groups, ARRAY_SIZE(jz4770_i2c4_groups), },
+ { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
+ { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
+ { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
+ { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
+ { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
+ { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
+ { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
+ { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
+ { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
+ { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
+};
+
+static const struct ingenic_chip_info jz4770_chip_info = {
+ .num_chips = 6,
+ .groups = jz4770_groups,
+ .num_groups = ARRAY_SIZE(jz4770_groups),
+ .functions = jz4770_functions,
+ .num_functions = ARRAY_SIZE(jz4770_functions),
+ .pull_ups = jz4770_pull_ups,
+ .pull_downs = jz4770_pull_downs,
+};
+
+static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
+ unsigned int pin, u8 reg, bool set)
+{
+ unsigned int idx = pin % PINS_PER_GPIO_CHIP;
+ unsigned int offt = pin / PINS_PER_GPIO_CHIP;
+
+ regmap_write(jzpc->map, offt * 0x100 +
+ (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
+}
+
+static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
+ unsigned int pin, u8 reg)
+{
+ unsigned int idx = pin % PINS_PER_GPIO_CHIP;
+ unsigned int offt = pin / PINS_PER_GPIO_CHIP;
+ unsigned int val;
+
+ regmap_read(jzpc->map, offt * 0x100 + reg, &val);
+
+ return val & BIT(idx);
+}
+
+static struct pinctrl_ops ingenic_pctlops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+ .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
+ int pin, int func)
+{
+ unsigned int idx = pin % PINS_PER_GPIO_CHIP;
+ unsigned int offt = pin / PINS_PER_GPIO_CHIP;
+
+ dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
+ 'A' + offt, idx, func);
+
+ if (jzpc->version >= ID_JZ4770) {
+ ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
+ ingenic_config_pin(jzpc, pin, JZ4770_GPIO_MSK, false);
+ ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
+ ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
+ } else {
+ ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
+ ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
+ ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0);
+ }
+
+ return 0;
+}
+
+static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int selector, unsigned int group)
+{
+ struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
+ struct function_desc *func;
+ struct group_desc *grp;
+ unsigned int i;
+
+ func = pinmux_generic_get_function(pctldev, selector);
+ if (!func)
+ return -EINVAL;
+
+ grp = pinctrl_generic_get_group(pctldev, group);
+ if (!grp)
+ return -EINVAL;
+
+ dev_dbg(pctldev->dev, "enable function %s group %s\n",
+ func->name, grp->name);
+
+ for (i = 0; i < grp->num_pins; i++) {
+ int *pin_modes = grp->data;
+
+ ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
+ }
+
+ return 0;
+}
+
+static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin, bool input)
+{
+ struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int idx = pin % PINS_PER_GPIO_CHIP;
+ unsigned int offt = pin / PINS_PER_GPIO_CHIP;
+
+ dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
+ 'A' + offt, idx, input ? "in" : "out");
+
+ if (jzpc->version >= ID_JZ4770) {
+ ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
+ ingenic_config_pin(jzpc, pin, JZ4770_GPIO_MSK, true);
+ ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
+ } else {
+ ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
+ ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, input);
+ ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
+ }
+
+ return 0;
+}
+
+static struct pinmux_ops ingenic_pmxops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = ingenic_pinmux_set_mux,
+ .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
+};
+
+static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ unsigned int idx = pin % PINS_PER_GPIO_CHIP;
+ unsigned int offt = pin / PINS_PER_GPIO_CHIP;
+ bool pull;
+
+ if (jzpc->version >= ID_JZ4770)
+ pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
+ else
+ pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (pull)
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
+ return -EINVAL;
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, 1);
+ return 0;
+}
+
+static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
+ unsigned int pin, bool enabled)
+{
+ if (jzpc->version >= ID_JZ4770)
+ ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !enabled);
+ else
+ ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled);
+}
+
+static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int idx = pin % PINS_PER_GPIO_CHIP;
+ unsigned int offt = pin / PINS_PER_GPIO_CHIP;
+ unsigned int cfg;
+
+ for (cfg = 0; cfg < num_configs; cfg++) {
+ switch (pinconf_to_config_param(configs[cfg])) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ continue;
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ for (cfg = 0; cfg < num_configs; cfg++) {
+ switch (pinconf_to_config_param(configs[cfg])) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
+ 'A' + offt, idx);
+ ingenic_set_bias(jzpc, pin, false);
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
+ return -EINVAL;
+ dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
+ 'A' + offt, idx);
+ ingenic_set_bias(jzpc, pin, true);
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
+ return -EINVAL;
+ dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
+ 'A' + offt, idx);
+ ingenic_set_bias(jzpc, pin, true);
+ break;
+
+ default:
+ unreachable();
+ }
+ }
+
+ return 0;
+}
+
+static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned int group, unsigned long *config)
+{
+ const unsigned int *pins;
+ unsigned int i, npins, old = 0;
+ int ret;
+
+ ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < npins; i++) {
+ if (ingenic_pinconf_get(pctldev, pins[i], config))
+ return -ENOTSUPP;
+
+ /* configs do not match between two pins */
+ if (i && (old != *config))
+ return -ENOTSUPP;
+
+ old = *config;
+ }
+
+ return 0;
+}
+
+static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned int group, unsigned long *configs,
+ unsigned int num_configs)
+{
+ const unsigned int *pins;
+ unsigned int i, npins;
+ int ret;
+
+ ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < npins; i++) {
+ ret = ingenic_pinconf_set(pctldev,
+ pins[i], configs, num_configs);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct pinconf_ops ingenic_confops = {
+ .is_generic = true,
+ .pin_config_get = ingenic_pinconf_get,
+ .pin_config_set = ingenic_pinconf_set,
+ .pin_config_group_get = ingenic_pinconf_group_get,
+ .pin_config_group_set = ingenic_pinconf_group_set,
+};
+
+static const struct regmap_config ingenic_pinctrl_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static const struct of_device_id ingenic_pinctrl_of_match[] = {
+ { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 },
+ { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 },
+ { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
+ {},
+};
+
+int ingenic_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ingenic_pinctrl *jzpc;
+ struct pinctrl_desc *pctl_desc;
+ void __iomem *base;
+ const struct platform_device_id *id = platform_get_device_id(pdev);
+ const struct of_device_id *of_id = of_match_device(
+ ingenic_pinctrl_of_match, dev);
+ const struct ingenic_chip_info *chip_info;
+ unsigned int i;
+ int err;
+
+ jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
+ if (!jzpc)
+ return -ENOMEM;
+
+ base = devm_ioremap_resource(dev,
+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
+ if (IS_ERR(base)) {
+ dev_err(dev, "Failed to ioremap registers\n");
+ return PTR_ERR(base);
+ }
+
+ jzpc->map = devm_regmap_init_mmio(dev, base,
+ &ingenic_pinctrl_regmap_config);
+ if (IS_ERR(jzpc->map)) {
+ dev_err(dev, "Failed to create regmap\n");
+ return PTR_ERR(jzpc->map);
+ }
+
+ jzpc->dev = dev;
+
+ if (of_id)
+ jzpc->version = (enum jz_version)of_id->data;
+ else
+ jzpc->version = (enum jz_version)id->driver_data;
+
+ if (jzpc->version >= ID_JZ4770)
+ chip_info = &jz4770_chip_info;
+ else
+ chip_info = &jz4740_chip_info;
+ jzpc->info = chip_info;
+
+ pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
+ if (!pctl_desc)
+ return -ENOMEM;
+
+ /* fill in pinctrl_desc structure */
+ pctl_desc->name = dev_name(dev);
+ pctl_desc->owner = THIS_MODULE;
+ pctl_desc->pctlops = &ingenic_pctlops;
+ pctl_desc->pmxops = &ingenic_pmxops;
+ pctl_desc->confops = &ingenic_confops;
+ pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
+ pctl_desc->pins = jzpc->pdesc = devm_kzalloc(&pdev->dev,
+ sizeof(*jzpc->pdesc) * pctl_desc->npins, GFP_KERNEL);
+ if (!jzpc->pdesc)
+ return -ENOMEM;
+
+ for (i = 0; i < pctl_desc->npins; i++) {
+ jzpc->pdesc[i].number = i;
+ jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
+ 'A' + (i / PINS_PER_GPIO_CHIP),
+ i % PINS_PER_GPIO_CHIP);
+ }
+
+ jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
+ if (!jzpc->pctl) {
+ dev_err(dev, "Failed to register pinctrl\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < chip_info->num_groups; i++) {
+ const struct group_desc *group = &chip_info->groups[i];
+
+ err = pinctrl_generic_add_group(jzpc->pctl, group->name,
+ group->pins, group->num_pins, group->data);
+ if (err) {
+ dev_err(dev, "Failed to register group %s\n",
+ group->name);
+ return err;
+ }
+ }
+
+ for (i = 0; i < chip_info->num_functions; i++) {
+ const struct function_desc *func = &chip_info->functions[i];
+
+ err = pinmux_generic_add_function(jzpc->pctl, func->name,
+ func->group_names, func->num_group_names,
+ func->data);
+ if (err) {
+ dev_err(dev, "Failed to register function %s\n",
+ func->name);
+ return err;
+ }
+ }
+
+ dev_set_drvdata(dev, jzpc->map);
+
+ if (dev->of_node) {
+ err = of_platform_populate(dev->of_node, NULL, NULL, dev);
+ if (err) {
+ dev_err(dev, "Failed to probe GPIO devices\n");
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+static const struct platform_device_id ingenic_pinctrl_ids[] = {
+ { "jz4740-pinctrl", ID_JZ4740 },
+ { "jz4770-pinctrl", ID_JZ4770 },
+ { "jz4780-pinctrl", ID_JZ4780 },
+ {},
+};
+
+static struct platform_driver ingenic_pinctrl_driver = {
+ .driver = {
+ .name = "pinctrl-ingenic",
+ .of_match_table = of_match_ptr(ingenic_pinctrl_of_match),
+ .suppress_bind_attrs = true,
+ },
+ .probe = ingenic_pinctrl_probe,
+ .id_table = ingenic_pinctrl_ids,
+};
+
+static int __init ingenic_pinctrl_drv_register(void)
+{
+ return platform_driver_register(&ingenic_pinctrl_driver);
+}
+postcore_initcall(ingenic_pinctrl_drv_register);
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rv1108-pinctrl",
- .data = (void *)&rv1108_pin_ctrl },
+ .data = &rv1108_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",
- .data = (void *)&rk2928_pin_ctrl },
+ .data = &rk2928_pin_ctrl },
{ .compatible = "rockchip,rk3036-pinctrl",
- .data = (void *)&rk3036_pin_ctrl },
+ .data = &rk3036_pin_ctrl },
{ .compatible = "rockchip,rk3066a-pinctrl",
- .data = (void *)&rk3066a_pin_ctrl },
+ .data = &rk3066a_pin_ctrl },
{ .compatible = "rockchip,rk3066b-pinctrl",
- .data = (void *)&rk3066b_pin_ctrl },
+ .data = &rk3066b_pin_ctrl },
{ .compatible = "rockchip,rk3188-pinctrl",
- .data = (void *)&rk3188_pin_ctrl },
+ .data = &rk3188_pin_ctrl },
{ .compatible = "rockchip,rk3228-pinctrl",
- .data = (void *)&rk3228_pin_ctrl },
+ .data = &rk3228_pin_ctrl },
{ .compatible = "rockchip,rk3288-pinctrl",
- .data = (void *)&rk3288_pin_ctrl },
+ .data = &rk3288_pin_ctrl },
{ .compatible = "rockchip,rk3328-pinctrl",
- .data = (void *)&rk3328_pin_ctrl },
+ .data = &rk3328_pin_ctrl },
{ .compatible = "rockchip,rk3368-pinctrl",
- .data = (void *)&rk3368_pin_ctrl },
+ .data = &rk3368_pin_ctrl },
{ .compatible = "rockchip,rk3399-pinctrl",
- .data = (void *)&rk3399_pin_ctrl },
+ .data = &rk3399_pin_ctrl },
{},
};
--- /dev/null
+config PINCTRL_ZX
+ bool
+ select PINMUX
+ select GENERIC_PINCONF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+
+config PINCTRL_ZX296718
+ bool "ZTE ZX296718 pinctrl driver"
+ depends on OF && ARCH_ZX
+ select PINCTRL_ZX
+ help
+ Say Y here to enable the ZX296718 pinctrl driver
--- /dev/null
+obj-$(CONFIG_PINCTRL_ZX) += pinctrl-zx.o
+obj-$(CONFIG_PINCTRL_ZX296718) += pinctrl-zx296718.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * Copyright 2017 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "../pinmux.h"
+#include "pinctrl-zx.h"
+
+#define ZX_PULL_DOWN BIT(0)
+#define ZX_PULL_UP BIT(1)
+#define ZX_INPUT_ENABLE BIT(3)
+#define ZX_DS_SHIFT 4
+#define ZX_DS_MASK (0x7 << ZX_DS_SHIFT)
+#define ZX_DS_VALUE(x) (((x) << ZX_DS_SHIFT) & ZX_DS_MASK)
+#define ZX_SLEW BIT(8)
+
+struct zx_pinctrl {
+ struct pinctrl_dev *pctldev;
+ struct device *dev;
+ void __iomem *base;
+ void __iomem *aux_base;
+ spinlock_t lock;
+ struct zx_pinctrl_soc_info *info;
+};
+
+static int zx_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map, u32 *num_maps)
+{
+ return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
+ num_maps, PIN_MAP_TYPE_INVALID);
+}
+
+static const struct pinctrl_ops zx_pinctrl_ops = {
+ .dt_node_to_map = zx_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_free_map,
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+};
+
+#define NONAON_MVAL 2
+
+static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
+ unsigned int group_selector)
+{
+ struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
+ struct zx_pinctrl_soc_info *info = zpctl->info;
+ const struct pinctrl_pin_desc *pindesc = info->pins + group_selector;
+ struct zx_pin_data *data = pindesc->drv_data;
+ struct zx_mux_desc *mux = data->muxes;
+ u32 mask = (1 << data->width) - 1;
+ u32 offset = data->offset;
+ u32 bitpos = data->bitpos;
+ struct function_desc *func;
+ unsigned long flags;
+ u32 val, mval;
+
+ /* Skip reserved pin */
+ if (!data)
+ return -EINVAL;
+
+ func = pinmux_generic_get_function(pctldev, func_selector);
+ if (!func)
+ return -EINVAL;
+
+ while (mux->name) {
+ if (strcmp(mux->name, func->name) == 0)
+ break;
+ mux++;
+ }
+
+ /* Found mux value to be written */
+ mval = mux->muxval;
+
+ spin_lock_irqsave(&zpctl->lock, flags);
+
+ if (data->aon_pin) {
+ /*
+ * It's an AON pin, whose mux register offset and bit position
+ * can be caluculated from pin number. Each register covers 16
+ * pins, and each pin occupies 2 bits.
+ */
+ u16 aoffset = pindesc->number / 16 * 4;
+ u16 abitpos = (pindesc->number % 16) * 2;
+
+ if (mval & AON_MUX_FLAG) {
+ /*
+ * This is a mux value that needs to be written into
+ * AON pinmux register. Write it and then we're done.
+ */
+ val = readl(zpctl->aux_base + aoffset);
+ val &= ~(0x3 << abitpos);
+ val |= (mval & 0x3) << abitpos;
+ writel(val, zpctl->aux_base + aoffset);
+ } else {
+ /*
+ * It's a mux value that needs to be written into TOP
+ * pinmux register.
+ */
+ val = readl(zpctl->base + offset);
+ val &= ~(mask << bitpos);
+ val |= (mval & mask) << bitpos;
+ writel(val, zpctl->base + offset);
+
+ /*
+ * In this case, the AON pinmux register needs to be
+ * set up to select non-AON function.
+ */
+ val = readl(zpctl->aux_base + aoffset);
+ val &= ~(0x3 << abitpos);
+ val |= NONAON_MVAL << abitpos;
+ writel(val, zpctl->aux_base + aoffset);
+ }
+
+ } else {
+ /*
+ * This is a TOP pin, and we only need to set up TOP pinmux
+ * register and then we're done with it.
+ */
+ val = readl(zpctl->base + offset);
+ val &= ~(mask << bitpos);
+ val |= (mval & mask) << bitpos;
+ writel(val, zpctl->base + offset);
+ }
+
+ spin_unlock_irqrestore(&zpctl->lock, flags);
+
+ return 0;
+}
+
+static const struct pinmux_ops zx_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = zx_set_mux,
+};
+
+static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
+ struct zx_pinctrl_soc_info *info = zpctl->info;
+ const struct pinctrl_pin_desc *pindesc = info->pins + pin;
+ struct zx_pin_data *data = pindesc->drv_data;
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u32 val;
+
+ /* Skip reserved pin */
+ if (!data)
+ return -EINVAL;
+
+ val = readl(zpctl->aux_base + data->coffset);
+ val = val >> data->cbitpos;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ val &= ZX_PULL_DOWN;
+ val = !!val;
+ if (val == 0)
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ val &= ZX_PULL_UP;
+ val = !!val;
+ if (val == 0)
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ val &= ZX_INPUT_ENABLE;
+ val = !!val;
+ if (val == 0)
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ val &= ZX_DS_MASK;
+ val = val >> ZX_DS_SHIFT;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ val &= ZX_SLEW;
+ val = !!val;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, val);
+
+ return 0;
+}
+
+static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
+ struct zx_pinctrl_soc_info *info = zpctl->info;
+ const struct pinctrl_pin_desc *pindesc = info->pins + pin;
+ struct zx_pin_data *data = pindesc->drv_data;
+ enum pin_config_param param;
+ u32 val, arg;
+ int i;
+
+ /* Skip reserved pin */
+ if (!data)
+ return -EINVAL;
+
+ val = readl(zpctl->aux_base + data->coffset);
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ val |= ZX_PULL_DOWN << data->cbitpos;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ val |= ZX_PULL_UP << data->cbitpos;
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ val |= ZX_INPUT_ENABLE << data->cbitpos;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ val &= ~(ZX_DS_MASK << data->cbitpos);
+ val |= ZX_DS_VALUE(arg) << data->cbitpos;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (arg)
+ val |= ZX_SLEW << data->cbitpos;
+ else
+ val &= ~ZX_SLEW << data->cbitpos;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ writel(val, zpctl->aux_base + data->coffset);
+ return 0;
+}
+
+static const struct pinconf_ops zx_pinconf_ops = {
+ .pin_config_set = zx_pin_config_set,
+ .pin_config_get = zx_pin_config_get,
+ .is_generic = true,
+};
+
+static int zx_pinctrl_build_state(struct platform_device *pdev)
+{
+ struct zx_pinctrl *zpctl = platform_get_drvdata(pdev);
+ struct zx_pinctrl_soc_info *info = zpctl->info;
+ struct pinctrl_dev *pctldev = zpctl->pctldev;
+ struct function_desc *functions;
+ int nfunctions;
+ struct group_desc *groups;
+ int ngroups;
+ int i;
+
+ /* Every single pin composes a group */
+ ngroups = info->npins;
+ groups = devm_kzalloc(&pdev->dev, ngroups * sizeof(*groups),
+ GFP_KERNEL);
+ if (!groups)
+ return -ENOMEM;
+
+ for (i = 0; i < ngroups; i++) {
+ const struct pinctrl_pin_desc *pindesc = info->pins + i;
+ struct group_desc *group = groups + i;
+ int id = pindesc->number;
+
+ group->name = pindesc->name;
+ group->pins = &id;
+ radix_tree_insert(&pctldev->pin_group_tree, i, group);
+ }
+
+ pctldev->num_groups = ngroups;
+
+ /* Build function list from pin mux functions */
+ functions = devm_kzalloc(&pdev->dev, info->npins * sizeof(*functions),
+ GFP_KERNEL);
+ if (!functions)
+ return -ENOMEM;
+
+ nfunctions = 0;
+ for (i = 0; i < info->npins; i++) {
+ const struct pinctrl_pin_desc *pindesc = info->pins + i;
+ struct zx_pin_data *data = pindesc->drv_data;
+ struct zx_mux_desc *mux;
+
+ /* Reserved pins do not have a drv_data at all */
+ if (!data)
+ continue;
+
+ /* Loop over all muxes for the pin */
+ mux = data->muxes;
+ while (mux->name) {
+ struct function_desc *func = functions;
+
+ /* Search function list for given mux */
+ while (func->name) {
+ if (strcmp(mux->name, func->name) == 0) {
+ /* Function exists */
+ func->num_group_names++;
+ break;
+ }
+ func++;
+ }
+
+ if (!func->name) {
+ /* New function */
+ func->name = mux->name;
+ func->num_group_names = 1;
+ radix_tree_insert(&pctldev->pin_function_tree,
+ nfunctions++, func);
+ }
+
+ mux++;
+ }
+ }
+
+ pctldev->num_functions = nfunctions;
+ functions = krealloc(functions, nfunctions * sizeof(*functions),
+ GFP_KERNEL);
+
+ /* Find pin groups for every single function */
+ for (i = 0; i < info->npins; i++) {
+ const struct pinctrl_pin_desc *pindesc = info->pins + i;
+ struct zx_pin_data *data = pindesc->drv_data;
+ struct zx_mux_desc *mux;
+
+ if (!data)
+ continue;
+
+ mux = data->muxes;
+ while (mux->name) {
+ struct function_desc *func;
+ const char **group;
+ int j;
+
+ /* Find function for given mux */
+ for (j = 0; j < nfunctions; j++)
+ if (strcmp(functions[j].name, mux->name) == 0)
+ break;
+
+ func = functions + j;
+ if (!func->group_names) {
+ func->group_names = devm_kzalloc(&pdev->dev,
+ func->num_group_names *
+ sizeof(*func->group_names),
+ GFP_KERNEL);
+ if (!func->group_names)
+ return -ENOMEM;
+ }
+
+ group = func->group_names;
+ while (*group)
+ group++;
+ *group = pindesc->name;
+
+ mux++;
+ }
+ }
+
+ return 0;
+}
+
+int zx_pinctrl_init(struct platform_device *pdev,
+ struct zx_pinctrl_soc_info *info)
+{
+ struct pinctrl_desc *pctldesc;
+ struct zx_pinctrl *zpctl;
+ struct device_node *np;
+ struct resource *res;
+ int ret;
+
+ zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL);
+ if (!zpctl)
+ return -ENOMEM;
+
+ spin_lock_init(&zpctl->lock);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ zpctl->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(zpctl->base))
+ return PTR_ERR(zpctl->base);
+
+ np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0);
+ if (!np) {
+ dev_err(&pdev->dev, "failed to find auxiliary controller\n");
+ return -ENODEV;
+ }
+
+ zpctl->aux_base = of_iomap(np, 0);
+ if (!zpctl->aux_base)
+ return -ENOMEM;
+
+ zpctl->dev = &pdev->dev;
+ zpctl->info = info;
+
+ pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL);
+ if (!pctldesc)
+ return -ENOMEM;
+
+ pctldesc->name = dev_name(&pdev->dev);
+ pctldesc->owner = THIS_MODULE;
+ pctldesc->pins = info->pins;
+ pctldesc->npins = info->npins;
+ pctldesc->pctlops = &zx_pinctrl_ops;
+ pctldesc->pmxops = &zx_pinmux_ops;
+ pctldesc->confops = &zx_pinconf_ops;
+
+ zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl);
+ if (IS_ERR(zpctl->pctldev)) {
+ ret = PTR_ERR(zpctl->pctldev);
+ dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, zpctl);
+
+ ret = zx_pinctrl_build_state(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to build state: %d\n", ret);
+ return ret;
+ }
+
+ dev_info(&pdev->dev, "initialized pinctrl driver\n");
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * Copyright 2017 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PINCTRL_ZX_H
+#define __PINCTRL_ZX_H
+
+/**
+ * struct zx_mux_desc - hardware mux descriptor
+ * @name: mux function name
+ * @muxval: mux register bit value
+ */
+struct zx_mux_desc {
+ const char *name;
+ u8 muxval;
+};
+
+/**
+ * struct zx_pin_data - hardware per-pin data
+ * @aon_pin: whether it's an AON pin
+ * @offset: register offset within TOP pinmux controller
+ * @bitpos: bit position within TOP pinmux register
+ * @width: bit width within TOP pinmux register
+ * @coffset: pinconf register offset within AON controller
+ * @cbitpos: pinconf bit position within AON register
+ * @muxes: available mux function names and corresponding register values
+ *
+ * Unlike TOP pinmux and AON pinconf registers which are arranged pretty
+ * arbitrarily, AON pinmux register bits are well organized per pin id, and
+ * each pin occupies two bits, so that we can calculate the AON register offset
+ * and bit position from pin id. Thus, we only need to define TOP pinmux and
+ * AON pinconf register data for the pin.
+ */
+struct zx_pin_data {
+ bool aon_pin;
+ u16 offset;
+ u16 bitpos;
+ u16 width;
+ u16 coffset;
+ u16 cbitpos;
+ struct zx_mux_desc *muxes;
+};
+
+struct zx_pinctrl_soc_info {
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+};
+
+#define TOP_PIN(pin, off, bp, wd, coff, cbp, ...) { \
+ .number = pin, \
+ .name = #pin, \
+ .drv_data = &(struct zx_pin_data) { \
+ .aon_pin = false, \
+ .offset = off, \
+ .bitpos = bp, \
+ .width = wd, \
+ .coffset = coff, \
+ .cbitpos = cbp, \
+ .muxes = (struct zx_mux_desc[]) { \
+ __VA_ARGS__, { } }, \
+ }, \
+}
+
+#define AON_PIN(pin, off, bp, wd, coff, cbp, ...) { \
+ .number = pin, \
+ .name = #pin, \
+ .drv_data = &(struct zx_pin_data) { \
+ .aon_pin = true, \
+ .offset = off, \
+ .bitpos = bp, \
+ .width = wd, \
+ .coffset = coff, \
+ .cbitpos = cbp, \
+ .muxes = (struct zx_mux_desc[]) { \
+ __VA_ARGS__, { } }, \
+ }, \
+}
+
+#define ZX_RESERVED(pin) PINCTRL_PIN(pin, #pin)
+
+#define TOP_MUX(_val, _name) { \
+ .name = _name, \
+ .muxval = _val, \
+}
+
+/*
+ * When the flag is set, it's a mux configuration for an AON pin that sits in
+ * AON register. Otherwise, it's one for AON pin but sitting in TOP register.
+ */
+#define AON_MUX_FLAG BIT(7)
+
+#define AON_MUX(_val, _name) { \
+ .name = _name, \
+ .muxval = _val | AON_MUX_FLAG, \
+}
+
+int zx_pinctrl_init(struct platform_device *pdev,
+ struct zx_pinctrl_soc_info *info);
+
+#endif /* __PINCTRL_ZX_H */
--- /dev/null
+/*
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * Copyright 2017 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-zx.h"
+
+#define TOP_REG0 0x00
+#define TOP_REG1 0x04
+#define TOP_REG2 0x08
+#define TOP_REG3 0x0c
+#define TOP_REG4 0x10
+#define TOP_REG5 0x14
+#define TOP_REG6 0x18
+#define TOP_REG7 0x1c
+#define TOP_REG8 0x20
+
+/*
+ * The pin numbering starts from AON pins with reserved ones included,
+ * so that register data like offset and bit position for AON pins can
+ * be calculated from pin number.
+ */
+enum zx296718_pin {
+ /* aon_pmm_reg_0 */
+ I2C3_SCL = 0,
+ I2C3_SDA = 1,
+ AON_RESERVED0 = 2,
+ AON_RESERVED1 = 3,
+ SEC_EN = 4,
+ UART0_RXD = 5,
+ UART0_TXD = 6,
+ IR_IN = 7,
+ SPI0_CLK = 8,
+ SPI0_CS = 9,
+ SPI0_TXD = 10,
+ SPI0_RXD = 11,
+ KEY_COL0 = 12,
+ KEY_COL1 = 13,
+ KEY_COL2 = 14,
+ KEY_ROW0 = 15,
+
+ /* aon_pmm_reg_1 */
+ KEY_ROW1 = 16,
+ KEY_ROW2 = 17,
+ HDMI_SCL = 18,
+ HDMI_SDA = 19,
+ JTAG_TCK = 20,
+ JTAG_TRSTN = 21,
+ JTAG_TMS = 22,
+ JTAG_TDI = 23,
+ JTAG_TDO = 24,
+ I2C0_SCL = 25,
+ I2C0_SDA = 26,
+ I2C1_SCL = 27,
+ I2C1_SDA = 28,
+ AON_RESERVED2 = 29,
+ AON_RESERVED3 = 30,
+ AON_RESERVED4 = 31,
+
+ /* aon_pmm_reg_2 */
+ SPI1_CLK = 32,
+ SPI1_CS = 33,
+ SPI1_TXD = 34,
+ SPI1_RXD = 35,
+ AON_RESERVED5 = 36,
+ AON_RESERVED6 = 37,
+ AUDIO_DET = 38,
+ SPDIF_OUT = 39,
+ HDMI_CEC = 40,
+ HDMI_HPD = 41,
+ GMAC_25M_OUT = 42,
+ BOOT_SEL0 = 43,
+ BOOT_SEL1 = 44,
+ BOOT_SEL2 = 45,
+ DEEP_SLEEP_OUT_N = 46,
+ AON_RESERVED7 = 47,
+
+ /* top_pmm_reg_0 */
+ GMII_GTX_CLK = 48,
+ GMII_TX_CLK = 49,
+ GMII_TXD0 = 50,
+ GMII_TXD1 = 51,
+ GMII_TXD2 = 52,
+ GMII_TXD3 = 53,
+ GMII_TXD4 = 54,
+ GMII_TXD5 = 55,
+ GMII_TXD6 = 56,
+ GMII_TXD7 = 57,
+ GMII_TX_ER = 58,
+ GMII_TX_EN = 59,
+ GMII_RX_CLK = 60,
+ GMII_RXD0 = 61,
+ GMII_RXD1 = 62,
+ GMII_RXD2 = 63,
+
+ /* top_pmm_reg_1 */
+ GMII_RXD3 = 64,
+ GMII_RXD4 = 65,
+ GMII_RXD5 = 66,
+ GMII_RXD6 = 67,
+ GMII_RXD7 = 68,
+ GMII_RX_ER = 69,
+ GMII_RX_DV = 70,
+ GMII_COL = 71,
+ GMII_CRS = 72,
+ GMII_MDC = 73,
+ GMII_MDIO = 74,
+ SDIO1_CLK = 75,
+ SDIO1_CMD = 76,
+ SDIO1_DATA0 = 77,
+ SDIO1_DATA1 = 78,
+ SDIO1_DATA2 = 79,
+
+ /* top_pmm_reg_2 */
+ SDIO1_DATA3 = 80,
+ SDIO1_CD = 81,
+ SDIO1_WP = 82,
+ USIM1_CD = 83,
+ USIM1_CLK = 84,
+ USIM1_RST = 85,
+
+ /* top_pmm_reg_3 */
+ USIM1_DATA = 86,
+ SDIO0_CLK = 87,
+ SDIO0_CMD = 88,
+ SDIO0_DATA0 = 89,
+ SDIO0_DATA1 = 90,
+ SDIO0_DATA2 = 91,
+ SDIO0_DATA3 = 92,
+ SDIO0_CD = 93,
+ SDIO0_WP = 94,
+
+ /* top_pmm_reg_4 */
+ TSI0_DATA0 = 95,
+ SPINOR_CLK = 96,
+ TSI2_DATA = 97,
+ TSI2_CLK = 98,
+ TSI2_SYNC = 99,
+ TSI2_VALID = 100,
+ SPINOR_CS = 101,
+ SPINOR_DQ0 = 102,
+ SPINOR_DQ1 = 103,
+ SPINOR_DQ2 = 104,
+ SPINOR_DQ3 = 105,
+ VGA_HS = 106,
+ VGA_VS = 107,
+ TSI3_DATA = 108,
+
+ /* top_pmm_reg_5 */
+ TSI3_CLK = 109,
+ TSI3_SYNC = 110,
+ TSI3_VALID = 111,
+ I2S1_WS = 112,
+ I2S1_BCLK = 113,
+ I2S1_MCLK = 114,
+ I2S1_DIN0 = 115,
+ I2S1_DOUT0 = 116,
+ SPI3_CLK = 117,
+ SPI3_CS = 118,
+ SPI3_TXD = 119,
+ NAND_LDO_MS18_SEL = 120,
+
+ /* top_pmm_reg_6 */
+ SPI3_RXD = 121,
+ I2S0_MCLK = 122,
+ I2S0_BCLK = 123,
+ I2S0_WS = 124,
+ I2S0_DIN0 = 125,
+ I2S0_DOUT0 = 126,
+ I2C5_SCL = 127,
+ I2C5_SDA = 128,
+ SPI2_CLK = 129,
+ SPI2_CS = 130,
+ SPI2_TXD = 131,
+
+ /* top_pmm_reg_7 */
+ SPI2_RXD = 132,
+ NAND_WP_N = 133,
+ NAND_PAGE_SIZE0 = 134,
+ NAND_PAGE_SIZE1 = 135,
+ NAND_ADDR_CYCLE = 136,
+ NAND_RB0 = 137,
+ NAND_RB1 = 138,
+ NAND_RB2 = 139,
+ NAND_RB3 = 140,
+
+ /* top_pmm_reg_8 */
+ GMAC_125M_IN = 141,
+ GMAC_50M_OUT = 142,
+ SPINOR_SSCLK_LOOPBACK = 143,
+ SPINOR_SDIO1CLK_LOOPBACK = 144,
+};
+
+static const struct pinctrl_pin_desc zx296718_pins[] = {
+ /* aon_pmm_reg_0 */
+ AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0,
+ AON_MUX(0x0, "ANMI"), /* anmi */
+ AON_MUX(0x1, "AGPIO"), /* agpio29 */
+ AON_MUX(0x2, "nonAON"), /* pin0 */
+ AON_MUX(0x3, "EXT_INT"), /* int4 */
+ TOP_MUX(0x0, "I2C3"), /* scl */
+ TOP_MUX(0x1, "SPI2"), /* txd */
+ TOP_MUX(0x2, "I2S1")), /* din0 */
+ AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9,
+ AON_MUX(0x0, "WD"), /* rst_b */
+ AON_MUX(0x1, "AGPIO"), /* agpio30 */
+ AON_MUX(0x2, "nonAON"), /* pin1 */
+ AON_MUX(0x3, "EXT_INT"), /* int5 */
+ TOP_MUX(0x0, "I2C3"), /* sda */
+ TOP_MUX(0x1, "SPI2"), /* rxd */
+ TOP_MUX(0x2, "I2S0")), /* mclk */
+ ZX_RESERVED(AON_RESERVED0),
+ ZX_RESERVED(AON_RESERVED1),
+ AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0,
+ AON_MUX(0x0, "SEC"), /* en */
+ AON_MUX(0x1, "AGPIO"), /* agpio28 */
+ AON_MUX(0x2, "nonAON"), /* pin3 */
+ AON_MUX(0x3, "EXT_INT"), /* int7 */
+ TOP_MUX(0x0, "I2C2"), /* sda */
+ TOP_MUX(0x1, "SPI2")), /* cs */
+ AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9,
+ AON_MUX(0x0, "UART0"), /* rxd */
+ AON_MUX(0x1, "AGPIO"), /* agpio20 */
+ AON_MUX(0x2, "nonAON")), /* pin34 */
+ AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18,
+ AON_MUX(0x0, "UART0"), /* txd */
+ AON_MUX(0x1, "AGPIO"), /* agpio21 */
+ AON_MUX(0x2, "nonAON")), /* pin32 */
+ AON_PIN(IR_IN, 0, 0, 0, 0x64, 0,
+ AON_MUX(0x0, "IR"), /* in */
+ AON_MUX(0x1, "AGPIO"), /* agpio0 */
+ AON_MUX(0x2, "nonAON")), /* pin27 */
+ AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9,
+ AON_MUX(0x0, "EXT_INT"), /* int0 */
+ AON_MUX(0x1, "AGPIO"), /* agpio23 */
+ AON_MUX(0x2, "nonAON"), /* pin5 */
+ AON_MUX(0x3, "PCU"), /* test6 */
+ TOP_MUX(0x0, "SPI0"), /* clk */
+ TOP_MUX(0x1, "ISP")), /* flash_trig */
+ AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18,
+ AON_MUX(0x0, "EXT_INT"), /* int1 */
+ AON_MUX(0x1, "AGPIO"), /* agpio24 */
+ AON_MUX(0x2, "nonAON"), /* pin6 */
+ AON_MUX(0x3, "PCU"), /* test0 */
+ TOP_MUX(0x0, "SPI0"), /* cs */
+ TOP_MUX(0x1, "ISP")), /* prelight_trig */
+ AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0,
+ AON_MUX(0x0, "EXT_INT"), /* int2 */
+ AON_MUX(0x1, "AGPIO"), /* agpio25 */
+ AON_MUX(0x2, "nonAON"), /* pin7 */
+ AON_MUX(0x3, "PCU"), /* test1 */
+ TOP_MUX(0x0, "SPI0"), /* txd */
+ TOP_MUX(0x1, "ISP")), /* shutter_trig */
+ AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9,
+ AON_MUX(0x0, "EXT_INT"), /* int3 */
+ AON_MUX(0x1, "AGPIO"), /* agpio26 */
+ AON_MUX(0x2, "nonAON"), /* pin8 */
+ AON_MUX(0x3, "PCU"), /* test2 */
+ TOP_MUX(0x0, "SPI0"), /* rxd */
+ TOP_MUX(0x1, "ISP")), /* shutter_open */
+ AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18,
+ AON_MUX(0x0, "KEY"), /* col0 */
+ AON_MUX(0x1, "AGPIO"), /* agpio5 */
+ AON_MUX(0x2, "nonAON"), /* pin9 */
+ AON_MUX(0x3, "PCU"), /* test3 */
+ TOP_MUX(0x0, "UART3"), /* rxd */
+ TOP_MUX(0x1, "I2S0")), /* din1 */
+ AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0,
+ AON_MUX(0x0, "KEY"), /* col1 */
+ AON_MUX(0x1, "AGPIO"), /* agpio6 */
+ AON_MUX(0x2, "nonAON"), /* pin10 */
+ TOP_MUX(0x0, "UART3"), /* txd */
+ TOP_MUX(0x1, "I2S0"), /* din2 */
+ TOP_MUX(0x2, "VGA")), /* scl */
+ AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9,
+ AON_MUX(0x0, "KEY"), /* col2 */
+ AON_MUX(0x1, "AGPIO"), /* agpio7 */
+ AON_MUX(0x2, "nonAON"), /* pin11 */
+ TOP_MUX(0x0, "PWM"), /* out1 */
+ TOP_MUX(0x1, "I2S0"), /* din3 */
+ TOP_MUX(0x2, "VGA")), /* sda */
+ AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18,
+ AON_MUX(0x0, "KEY"), /* row0 */
+ AON_MUX(0x1, "AGPIO"), /* agpio8 */
+ AON_MUX(0x2, "nonAON"), /* pin33 */
+ AON_MUX(0x3, "WD")), /* rst_b */
+
+ /* aon_pmm_reg_1 */
+ AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0,
+ AON_MUX(0x0, "KEY"), /* row1 */
+ AON_MUX(0x1, "AGPIO"), /* agpio9 */
+ AON_MUX(0x2, "nonAON"), /* pin12 */
+ TOP_MUX(0x0, "LCD"), /* port0 lcd_te */
+ TOP_MUX(0x1, "I2S0"), /* dout2 */
+ TOP_MUX(0x2, "PWM"), /* out2 */
+ TOP_MUX(0x3, "VGA")), /* hs1 */
+ AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9,
+ AON_MUX(0x0, "KEY"), /* row2 */
+ AON_MUX(0x1, "AGPIO"), /* agpio10 */
+ AON_MUX(0x2, "nonAON"), /* pin13 */
+ TOP_MUX(0x0, "LCD"), /* port1 lcd_te */
+ TOP_MUX(0x1, "I2S0"), /* dout3 */
+ TOP_MUX(0x2, "PWM"), /* out3 */
+ TOP_MUX(0x3, "VGA")), /* vs1 */
+ AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18,
+ AON_MUX(0x0, "PCU"), /* test7 */
+ AON_MUX(0x1, "AGPIO"), /* agpio3 */
+ AON_MUX(0x2, "nonAON"), /* pin14 */
+ TOP_MUX(0x0, "HDMI"), /* scl */
+ TOP_MUX(0x1, "UART3")), /* rxd */
+ AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0,
+ AON_MUX(0x0, "PCU"), /* test8 */
+ AON_MUX(0x1, "AGPIO"), /* agpio4 */
+ AON_MUX(0x2, "nonAON"), /* pin15 */
+ TOP_MUX(0x0, "HDMI"), /* sda */
+ TOP_MUX(0x1, "UART3")), /* txd */
+ AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18,
+ AON_MUX(0x0, "JTAG"), /* tck */
+ AON_MUX(0x1, "AGPIO"), /* agpio11 */
+ AON_MUX(0x2, "nonAON"), /* pin22 */
+ AON_MUX(0x3, "EXT_INT"), /* int4 */
+ TOP_MUX(0x0, "SPI4"), /* clk */
+ TOP_MUX(0x1, "UART1")), /* rxd */
+ AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0,
+ AON_MUX(0x0, "JTAG"), /* trstn */
+ AON_MUX(0x1, "AGPIO"), /* agpio12 */
+ AON_MUX(0x2, "nonAON"), /* pin23 */
+ AON_MUX(0x3, "EXT_INT"), /* int5 */
+ TOP_MUX(0x0, "SPI4"), /* cs */
+ TOP_MUX(0x1, "UART1")), /* txd */
+ AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9,
+ AON_MUX(0x0, "JTAG"), /* tms */
+ AON_MUX(0x1, "AGPIO"), /* agpio13 */
+ AON_MUX(0x2, "nonAON"), /* pin24 */
+ AON_MUX(0x3, "EXT_INT"), /* int6 */
+ TOP_MUX(0x0, "SPI4"), /* txd */
+ TOP_MUX(0x1, "UART2")), /* rxd */
+ AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18,
+ AON_MUX(0x0, "JTAG"), /* tdi */
+ AON_MUX(0x1, "AGPIO"), /* agpio14 */
+ AON_MUX(0x2, "nonAON"), /* pin25 */
+ AON_MUX(0x3, "EXT_INT"), /* int7 */
+ TOP_MUX(0x0, "SPI4"), /* rxd */
+ TOP_MUX(0x1, "UART2")), /* txd */
+ AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0,
+ AON_MUX(0x0, "JTAG"), /* tdo */
+ AON_MUX(0x1, "AGPIO"), /* agpio15 */
+ AON_MUX(0x2, "nonAON")), /* pin26 */
+ AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9,
+ AON_MUX(0x0, "I2C0"), /* scl */
+ AON_MUX(0x1, "AGPIO"), /* agpio16 */
+ AON_MUX(0x2, "nonAON")), /* pin28 */
+ AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18,
+ AON_MUX(0x0, "I2C0"), /* sda */
+ AON_MUX(0x1, "AGPIO"), /* agpio17 */
+ AON_MUX(0x2, "nonAON")), /* pin29 */
+ AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0,
+ AON_MUX(0x0, "I2C1"), /* scl */
+ AON_MUX(0x1, "AGPIO"), /* agpio18 */
+ AON_MUX(0x2, "nonAON"), /* pin30 */
+ TOP_MUX(0x0, "LCD")), /* port0 lcd_te */
+ AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9,
+ AON_MUX(0x0, "I2C1"), /* sda */
+ AON_MUX(0x1, "AGPIO"), /* agpio19 */
+ AON_MUX(0x2, "nonAON"), /* pin31 */
+ TOP_MUX(0x0, "LCD")), /* port1 lcd_te */
+ ZX_RESERVED(AON_RESERVED2),
+ ZX_RESERVED(AON_RESERVED3),
+ ZX_RESERVED(AON_RESERVED4),
+
+ /* aon_pmm_reg_2 */
+ AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9,
+ AON_MUX(0x0, "EXT_INT"), /* int0 */
+ AON_MUX(0x1, "PCU"), /* test12 */
+ AON_MUX(0x2, "nonAON"), /* pin39 */
+ TOP_MUX(0x0, "SPI1"), /* clk */
+ TOP_MUX(0x1, "PCM"), /* clk */
+ TOP_MUX(0x2, "BGPIO"), /* gpio35 */
+ TOP_MUX(0x3, "I2C4"), /* scl */
+ TOP_MUX(0x4, "I2S1"), /* mclk */
+ TOP_MUX(0x5, "ISP")), /* flash_trig */
+ AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18,
+ AON_MUX(0x0, "EXT_INT"), /* int1 */
+ AON_MUX(0x1, "PCU"), /* test13 */
+ AON_MUX(0x2, "nonAON"), /* pin40 */
+ TOP_MUX(0x0, "SPI1"), /* cs */
+ TOP_MUX(0x1, "PCM"), /* fs */
+ TOP_MUX(0x2, "BGPIO"), /* gpio36 */
+ TOP_MUX(0x3, "I2C4"), /* sda */
+ TOP_MUX(0x4, "I2S1"), /* bclk */
+ TOP_MUX(0x5, "ISP")), /* prelight_trig */
+ AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0,
+ AON_MUX(0x0, "EXT_INT"), /* int2 */
+ AON_MUX(0x1, "PCU"), /* test14 */
+ AON_MUX(0x2, "nonAON"), /* pin41 */
+ TOP_MUX(0x0, "SPI1"), /* txd */
+ TOP_MUX(0x1, "PCM"), /* txd */
+ TOP_MUX(0x2, "BGPIO"), /* gpio37 */
+ TOP_MUX(0x3, "UART5"), /* rxd */
+ TOP_MUX(0x4, "I2S1"), /* ws */
+ TOP_MUX(0x5, "ISP")), /* shutter_trig */
+ AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9,
+ AON_MUX(0x0, "EXT_INT"), /* int3 */
+ AON_MUX(0x1, "PCU"), /* test15 */
+ AON_MUX(0x2, "nonAON"), /* pin42 */
+ TOP_MUX(0x0, "SPI1"), /* rxd */
+ TOP_MUX(0x1, "PCM"), /* rxd */
+ TOP_MUX(0x2, "BGPIO"), /* gpio38 */
+ TOP_MUX(0x3, "UART5"), /* txd */
+ TOP_MUX(0x4, "I2S1"), /* dout0 */
+ TOP_MUX(0x5, "ISP")), /* shutter_open */
+ ZX_RESERVED(AON_RESERVED5),
+ ZX_RESERVED(AON_RESERVED6),
+ AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18,
+ AON_MUX(0x0, "PCU"), /* test4 */
+ AON_MUX(0x1, "AGPIO"), /* agpio27 */
+ AON_MUX(0x2, "nonAON"), /* pin2 */
+ AON_MUX(0x3, "EXT_INT"), /* int16 */
+ TOP_MUX(0x0, "AUDIO"), /* detect */
+ TOP_MUX(0x1, "I2C2"), /* scl */
+ TOP_MUX(0x2, "SPI2")), /* clk */
+ AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9,
+ AON_MUX(0x0, "PCU"), /* test5 */
+ AON_MUX(0x1, "AGPIO"), /* agpio22 */
+ AON_MUX(0x2, "nonAON"), /* pin4 */
+ TOP_MUX(0x0, "SPDIF"), /* out */
+ TOP_MUX(0x1, "PWM"), /* out0 */
+ TOP_MUX(0x2, "ISP")), /* fl_trig */
+ AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9,
+ AON_MUX(0x0, "PCU"), /* test9 */
+ AON_MUX(0x1, "AGPIO"), /* agpio1 */
+ AON_MUX(0x2, "nonAON")), /* pin16 */
+ AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18,
+ AON_MUX(0x0, "PCU"), /* test10 */
+ AON_MUX(0x1, "AGPIO"), /* agpio2 */
+ AON_MUX(0x2, "nonAON")), /* pin17 */
+ AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0,
+ AON_MUX(0x0, "PCU"), /* test11 */
+ AON_MUX(0x1, "AGPIO"), /* agpio31 */
+ AON_MUX(0x2, "nonAON")), /* pin43 */
+ AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9,
+ AON_MUX(0x0, "BOOT"), /* sel0 */
+ AON_MUX(0x1, "AGPIO"), /* agpio18 */
+ AON_MUX(0x2, "nonAON")), /* pin18 */
+ AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18,
+ AON_MUX(0x0, "BOOT"), /* sel1 */
+ AON_MUX(0x1, "AGPIO"), /* agpio19 */
+ AON_MUX(0x2, "nonAON")), /* pin19 */
+ AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0,
+ AON_MUX(0x0, "BOOT"), /* sel2 */
+ AON_MUX(0x1, "AGPIO"), /* agpio20 */
+ AON_MUX(0x2, "nonAON")), /* pin20 */
+ AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9,
+ AON_MUX(0x0, "DEEPSLP"), /* deep sleep out_n */
+ AON_MUX(0x1, "AGPIO"), /* agpio21 */
+ AON_MUX(0x2, "nonAON")), /* pin21 */
+ ZX_RESERVED(AON_RESERVED7),
+
+ /* top_pmm_reg_0 */
+ TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0,
+ TOP_MUX(0x0, "GMII"), /* gtx_clk */
+ TOP_MUX(0x1, "DVI0"), /* clk */
+ TOP_MUX(0x2, "BGPIO")), /* gpio0 */
+ TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9,
+ TOP_MUX(0x0, "GMII"), /* tx_clk */
+ TOP_MUX(0x1, "DVI0"), /* vs */
+ TOP_MUX(0x2, "BGPIO")), /* gpio1 */
+ TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18,
+ TOP_MUX(0x0, "GMII"), /* txd0 */
+ TOP_MUX(0x1, "DVI0"), /* hs */
+ TOP_MUX(0x2, "BGPIO")), /* gpio2 */
+ TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0,
+ TOP_MUX(0x0, "GMII"), /* txd1 */
+ TOP_MUX(0x1, "DVI0"), /* d0 */
+ TOP_MUX(0x2, "BGPIO")), /* gpio3 */
+ TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9,
+ TOP_MUX(0x0, "GMII"), /* txd2 */
+ TOP_MUX(0x1, "DVI0"), /* d1 */
+ TOP_MUX(0x2, "BGPIO")), /* gpio4 */
+ TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18,
+ TOP_MUX(0x0, "GMII"), /* txd3 */
+ TOP_MUX(0x1, "DVI0"), /* d2 */
+ TOP_MUX(0x2, "BGPIO")), /* gpio5 */
+ TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0,
+ TOP_MUX(0x0, "GMII"), /* txd4 */
+ TOP_MUX(0x1, "DVI0"), /* d3 */
+ TOP_MUX(0x2, "BGPIO")), /* gpio6 */
+ TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9,
+ TOP_MUX(0x0, "GMII"), /* txd5 */
+ TOP_MUX(0x1, "DVI0"), /* d4 */
+ TOP_MUX(0x2, "BGPIO")), /* gpio7 */
+ TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18,
+ TOP_MUX(0x0, "GMII"), /* txd6 */
+ TOP_MUX(0x1, "DVI0"), /* d5 */
+ TOP_MUX(0x2, "BGPIO")), /* gpio8 */
+ TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0,
+ TOP_MUX(0x0, "GMII"), /* txd7 */
+ TOP_MUX(0x1, "DVI0"), /* d6 */
+ TOP_MUX(0x2, "BGPIO")), /* gpio9 */
+ TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9,
+ TOP_MUX(0x0, "GMII"), /* tx_er */
+ TOP_MUX(0x1, "DVI0"), /* d7 */
+ TOP_MUX(0x2, "BGPIO")), /* gpio10 */
+ TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18,
+ TOP_MUX(0x0, "GMII"), /* tx_en */
+ TOP_MUX(0x1, "DVI0"), /* d8 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio11 */
+ TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0,
+ TOP_MUX(0x0, "GMII"), /* rx_clk */
+ TOP_MUX(0x1, "DVI0"), /* d9 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio12 */
+ TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9,
+ TOP_MUX(0x0, "GMII"), /* rxd0 */
+ TOP_MUX(0x1, "DVI0"), /* d10 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio13 */
+ TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18,
+ TOP_MUX(0x0, "GMII"), /* rxd1 */
+ TOP_MUX(0x1, "DVI0"), /* d11 */
+ TOP_MUX(0x2, "BGPIO")), /* gpio14 */
+ TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0,
+ TOP_MUX(0x0, "GMII"), /* rxd2 */
+ TOP_MUX(0x1, "DVI1"), /* clk */
+ TOP_MUX(0x2, "BGPIO")), /* gpio15 */
+
+ /* top_pmm_reg_1 */
+ TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9,
+ TOP_MUX(0x0, "GMII"), /* rxd3 */
+ TOP_MUX(0x1, "DVI1"), /* hs */
+ TOP_MUX(0x2, "BGPIO")), /* gpio16 */
+ TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18,
+ TOP_MUX(0x0, "GMII"), /* rxd4 */
+ TOP_MUX(0x1, "DVI1"), /* vs */
+ TOP_MUX(0x2, "BGPIO")), /* gpio17 */
+ TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0,
+ TOP_MUX(0x0, "GMII"), /* rxd5 */
+ TOP_MUX(0x1, "DVI1"), /* d0 */
+ TOP_MUX(0x2, "BGPIO"), /* gpio18 */
+ TOP_MUX(0x3, "TSI0")), /* dat0 */
+ TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9,
+ TOP_MUX(0x0, "GMII"), /* rxd6 */
+ TOP_MUX(0x1, "DVI1"), /* d1 */
+ TOP_MUX(0x2, "BGPIO"), /* gpio19 */
+ TOP_MUX(0x3, "TSI0")), /* clk */
+ TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18,
+ TOP_MUX(0x0, "GMII"), /* rxd7 */
+ TOP_MUX(0x1, "DVI1"), /* d2 */
+ TOP_MUX(0x2, "BGPIO"), /* gpio20 */
+ TOP_MUX(0x3, "TSI0")), /* sync */
+ TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0,
+ TOP_MUX(0x0, "GMII"), /* rx_er */
+ TOP_MUX(0x1, "DVI1"), /* d3 */
+ TOP_MUX(0x2, "BGPIO"), /* gpio21 */
+ TOP_MUX(0x3, "TSI0")), /* valid */
+ TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9,
+ TOP_MUX(0x0, "GMII"), /* rx_dv */
+ TOP_MUX(0x1, "DVI1"), /* d4 */
+ TOP_MUX(0x2, "BGPIO"), /* gpio22 */
+ TOP_MUX(0x3, "TSI1")), /* dat0 */
+ TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18,
+ TOP_MUX(0x0, "GMII"), /* col */
+ TOP_MUX(0x1, "DVI1"), /* d5 */
+ TOP_MUX(0x2, "BGPIO"), /* gpio23 */
+ TOP_MUX(0x3, "TSI1")), /* clk */
+ TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0,
+ TOP_MUX(0x0, "GMII"), /* crs */
+ TOP_MUX(0x1, "DVI1"), /* d6 */
+ TOP_MUX(0x2, "BGPIO"), /* gpio24 */
+ TOP_MUX(0x3, "TSI1")), /* sync */
+ TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9,
+ TOP_MUX(0x0, "GMII"), /* mdc */
+ TOP_MUX(0x1, "DVI1"), /* d7 */
+ TOP_MUX(0x2, "BGPIO"), /* gpio25 */
+ TOP_MUX(0x3, "TSI1")), /* valid */
+ TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18,
+ TOP_MUX(0x0, "GMII"), /* mdio */
+ TOP_MUX(0x2, "BGPIO")), /* gpio26 */
+ TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18,
+ TOP_MUX(0x0, "SDIO1"), /* clk */
+ TOP_MUX(0x1, "USIM0"), /* clk */
+ TOP_MUX(0x2, "BGPIO"), /* gpio27 */
+ TOP_MUX(0x3, "SPINOR")), /* clk */
+ TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0,
+ TOP_MUX(0x0, "SDIO1"), /* cmd */
+ TOP_MUX(0x1, "USIM0"), /* cd */
+ TOP_MUX(0x2, "BGPIO"), /* gpio28 */
+ TOP_MUX(0x3, "SPINOR")), /* cs */
+ TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9,
+ TOP_MUX(0x0, "SDIO1"), /* dat0 */
+ TOP_MUX(0x1, "USIM0"), /* rst */
+ TOP_MUX(0x2, "BGPIO"), /* gpio29 */
+ TOP_MUX(0x3, "SPINOR")), /* dq0 */
+ TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18,
+ TOP_MUX(0x0, "SDIO1"), /* dat1 */
+ TOP_MUX(0x1, "USIM0"), /* data */
+ TOP_MUX(0x2, "BGPIO"), /* gpio30 */
+ TOP_MUX(0x3, "SPINOR")), /* dq1 */
+ TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0,
+ TOP_MUX(0x0, "SDIO1"), /* dat2 */
+ TOP_MUX(0x1, "BGPIO"), /* gpio31 */
+ TOP_MUX(0x2, "SPINOR")), /* dq2 */
+
+ /* top_pmm_reg_2 */
+ TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9,
+ TOP_MUX(0x0, "SDIO1"), /* dat3 */
+ TOP_MUX(0x1, "BGPIO"), /* gpio32 */
+ TOP_MUX(0x2, "SPINOR")), /* dq3 */
+ TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18,
+ TOP_MUX(0x0, "SDIO1"), /* cd */
+ TOP_MUX(0x1, "BGPIO"), /* gpio33 */
+ TOP_MUX(0x2, "ISP")), /* fl_trig */
+ TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0,
+ TOP_MUX(0x0, "SDIO1"), /* wp */
+ TOP_MUX(0x1, "BGPIO"), /* gpio34 */
+ TOP_MUX(0x2, "ISP")), /* ref_clk */
+ TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18,
+ TOP_MUX(0x0, "USIM1"), /* cd */
+ TOP_MUX(0x1, "UART4"), /* rxd */
+ TOP_MUX(0x2, "BGPIO"), /* gpio39 */
+ TOP_MUX(0x3, "SPI3"), /* clk */
+ TOP_MUX(0x4, "I2S0"), /* bclk */
+ TOP_MUX(0x5, "B_DVI0")), /* d8 */
+ TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18,
+ TOP_MUX(0x0, "USIM1"), /* clk */
+ TOP_MUX(0x1, "UART4"), /* txd */
+ TOP_MUX(0x2, "BGPIO"), /* gpio40 */
+ TOP_MUX(0x3, "SPI3"), /* cs */
+ TOP_MUX(0x4, "I2S0"), /* ws */
+ TOP_MUX(0x5, "B_DVI0")), /* d9 */
+ TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0,
+ TOP_MUX(0x0, "USIM1"), /* rst */
+ TOP_MUX(0x1, "UART4"), /* cts */
+ TOP_MUX(0x2, "BGPIO"), /* gpio41 */
+ TOP_MUX(0x3, "SPI3"), /* txd */
+ TOP_MUX(0x4, "I2S0"), /* dout0 */
+ TOP_MUX(0x5, "B_DVI0")), /* d10 */
+
+ /* top_pmm_reg_3 */
+ TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9,
+ TOP_MUX(0x0, "USIM1"), /* dat */
+ TOP_MUX(0x1, "UART4"), /* rst */
+ TOP_MUX(0x2, "BGPIO"), /* gpio42 */
+ TOP_MUX(0x3, "SPI3"), /* rxd */
+ TOP_MUX(0x4, "I2S0"), /* din0 */
+ TOP_MUX(0x5, "B_DVI0")), /* d11 */
+ TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0,
+ TOP_MUX(0x0, "SDIO0"), /* clk */
+ TOP_MUX(0x1, "GPIO")), /* gpio43 */
+ TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9,
+ TOP_MUX(0x0, "SDIO0"), /* cmd */
+ TOP_MUX(0x1, "GPIO")), /* gpio44 */
+ TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18,
+ TOP_MUX(0x0, "SDIO0"), /* dat0 */
+ TOP_MUX(0x1, "GPIO")), /* gpio45 */
+ TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0,
+ TOP_MUX(0x0, "SDIO0"), /* dat1 */
+ TOP_MUX(0x1, "GPIO")), /* gpio46 */
+ TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9,
+ TOP_MUX(0x0, "SDIO0"), /* dat2 */
+ TOP_MUX(0x1, "GPIO")), /* gpio47 */
+ TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18,
+ TOP_MUX(0x0, "SDIO0"), /* dat3 */
+ TOP_MUX(0x1, "GPIO")), /* gpio48 */
+ TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0,
+ TOP_MUX(0x0, "SDIO0"), /* cd */
+ TOP_MUX(0x1, "GPIO")), /* gpio49 */
+ TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9,
+ TOP_MUX(0x0, "SDIO0"), /* wp */
+ TOP_MUX(0x1, "GPIO")), /* gpio50 */
+
+ /* top_pmm_reg_4 */
+ TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18,
+ TOP_MUX(0x0, "TSI0"), /* dat0 */
+ TOP_MUX(0x1, "LCD"), /* clk */
+ TOP_MUX(0x2, "BGPIO")), /* gpio51 */
+ TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18,
+ TOP_MUX(0x0, "SPINOR"), /* clk */
+ TOP_MUX(0x1, "TSI0"), /* dat1 */
+ TOP_MUX(0x2, "LCD"), /* dat0 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio52 */
+ TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0,
+ TOP_MUX(0x0, "TSI2"), /* dat */
+ TOP_MUX(0x1, "TSI0"), /* dat2 */
+ TOP_MUX(0x2, "LCD"), /* dat1 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio53 */
+ TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9,
+ TOP_MUX(0x0, "TSI2"), /* clk */
+ TOP_MUX(0x1, "TSI0"), /* dat3 */
+ TOP_MUX(0x2, "LCD"), /* dat2 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio54 */
+ TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18,
+ TOP_MUX(0x0, "TSI2"), /* sync */
+ TOP_MUX(0x1, "TSI0"), /* dat4 */
+ TOP_MUX(0x2, "LCD"), /* dat3 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio55 */
+ TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0,
+ TOP_MUX(0x0, "TSI2"), /* valid */
+ TOP_MUX(0x1, "TSI0"), /* dat5 */
+ TOP_MUX(0x2, "LCD"), /* dat4 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio56 */
+ TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9,
+ TOP_MUX(0x0, "SPINOR"), /* cs */
+ TOP_MUX(0x1, "TSI0"), /* dat6 */
+ TOP_MUX(0x2, "LCD"), /* dat5 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio57 */
+ TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18,
+ TOP_MUX(0x0, "SPINOR"), /* dq0 */
+ TOP_MUX(0x1, "TSI0"), /* dat7 */
+ TOP_MUX(0x2, "LCD"), /* dat6 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio58 */
+ TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0,
+ TOP_MUX(0x0, "SPINOR"), /* dq1 */
+ TOP_MUX(0x1, "TSI0"), /* clk */
+ TOP_MUX(0x2, "LCD"), /* dat7 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio59 */
+ TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9,
+ TOP_MUX(0x0, "SPINOR"), /* dq2 */
+ TOP_MUX(0x1, "TSI0"), /* sync */
+ TOP_MUX(0x2, "LCD"), /* dat8 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio60 */
+ TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18,
+ TOP_MUX(0x0, "SPINOR"), /* dq3 */
+ TOP_MUX(0x1, "TSI0"), /* valid */
+ TOP_MUX(0x2, "LCD"), /* dat9 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio61 */
+ TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0,
+ TOP_MUX(0x0, "VGA"), /* hs */
+ TOP_MUX(0x1, "TSI1"), /* dat0 */
+ TOP_MUX(0x2, "LCD"), /* dat10 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio62 */
+ TOP_MUX(0x4, "I2S1"), /* din1 */
+ TOP_MUX(0x5, "B_DVI0")), /* clk */
+ TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9,
+ TOP_MUX(0x0, "VGA"), /* vs0 */
+ TOP_MUX(0x1, "TSI1"), /* dat1 */
+ TOP_MUX(0x2, "LCD"), /* dat11 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio63 */
+ TOP_MUX(0x4, "I2S1"), /* din2 */
+ TOP_MUX(0x5, "B_DVI0")), /* vs */
+ TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18,
+ TOP_MUX(0x0, "TSI3"), /* dat */
+ TOP_MUX(0x1, "TSI1"), /* dat2 */
+ TOP_MUX(0x2, "LCD"), /* dat12 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio64 */
+ TOP_MUX(0x4, "I2S1"), /* din3 */
+ TOP_MUX(0x5, "B_DVI0")), /* hs */
+
+ /* top_pmm_reg_5 */
+ TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0,
+ TOP_MUX(0x0, "TSI3"), /* clk */
+ TOP_MUX(0x1, "TSI1"), /* dat3 */
+ TOP_MUX(0x2, "LCD"), /* dat13 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio65 */
+ TOP_MUX(0x4, "I2S1"), /* dout1 */
+ TOP_MUX(0x5, "B_DVI0")), /* d0 */
+ TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9,
+ TOP_MUX(0x0, "TSI3"), /* sync */
+ TOP_MUX(0x1, "TSI1"), /* dat4 */
+ TOP_MUX(0x2, "LCD"), /* dat14 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio66 */
+ TOP_MUX(0x4, "I2S1"), /* dout2 */
+ TOP_MUX(0x5, "B_DVI0")), /* d1 */
+ TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18,
+ TOP_MUX(0x0, "TSI3"), /* valid */
+ TOP_MUX(0x1, "TSI1"), /* dat5 */
+ TOP_MUX(0x2, "LCD"), /* dat15 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio67 */
+ TOP_MUX(0x4, "I2S1"), /* dout3 */
+ TOP_MUX(0x5, "B_DVI0")), /* d2 */
+ TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0,
+ TOP_MUX(0x0, "I2S1"), /* ws */
+ TOP_MUX(0x1, "TSI1"), /* dat6 */
+ TOP_MUX(0x2, "LCD"), /* dat16 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio68 */
+ TOP_MUX(0x4, "VGA"), /* scl */
+ TOP_MUX(0x5, "B_DVI0")), /* d3 */
+ TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9,
+ TOP_MUX(0x0, "I2S1"), /* bclk */
+ TOP_MUX(0x1, "TSI1"), /* dat7 */
+ TOP_MUX(0x2, "LCD"), /* dat17 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio69 */
+ TOP_MUX(0x4, "VGA"), /* sda */
+ TOP_MUX(0x5, "B_DVI0")), /* d4 */
+ TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18,
+ TOP_MUX(0x0, "I2S1"), /* mclk */
+ TOP_MUX(0x1, "TSI1"), /* clk */
+ TOP_MUX(0x2, "LCD"), /* dat18 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio70 */
+ TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0,
+ TOP_MUX(0x0, "I2S1"), /* din0 */
+ TOP_MUX(0x1, "TSI1"), /* sync */
+ TOP_MUX(0x2, "LCD"), /* dat19 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio71 */
+ TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9,
+ TOP_MUX(0x0, "I2S1"), /* dout0 */
+ TOP_MUX(0x1, "TSI1"), /* valid */
+ TOP_MUX(0x2, "LCD"), /* dat20 */
+ TOP_MUX(0x3, "BGPIO")), /* gpio72 */
+ TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18,
+ TOP_MUX(0x0, "SPI3"), /* clk */
+ TOP_MUX(0x1, "TSO1"), /* clk */
+ TOP_MUX(0x2, "LCD"), /* dat21 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio73 */
+ TOP_MUX(0x4, "UART5"), /* rxd */
+ TOP_MUX(0x5, "PCM"), /* fs */
+ TOP_MUX(0x6, "I2S0"), /* din1 */
+ TOP_MUX(0x7, "B_DVI0")), /* d5 */
+ TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0,
+ TOP_MUX(0x0, "SPI3"), /* cs */
+ TOP_MUX(0x1, "TSO1"), /* dat0 */
+ TOP_MUX(0x2, "LCD"), /* dat22 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio74 */
+ TOP_MUX(0x4, "UART5"), /* txd */
+ TOP_MUX(0x5, "PCM"), /* clk */
+ TOP_MUX(0x6, "I2S0"), /* din2 */
+ TOP_MUX(0x7, "B_DVI0")), /* d6 */
+ TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9,
+ TOP_MUX(0x0, "SPI3"), /* txd */
+ TOP_MUX(0x1, "TSO1"), /* dat1 */
+ TOP_MUX(0x2, "LCD"), /* dat23 */
+ TOP_MUX(0x3, "BGPIO"), /* gpio75 */
+ TOP_MUX(0x4, "UART5"), /* cts */
+ TOP_MUX(0x5, "PCM"), /* txd */
+ TOP_MUX(0x6, "I2S0"), /* din3 */
+ TOP_MUX(0x7, "B_DVI0")), /* d7 */
+ TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0,
+ TOP_MUX(0x0, "NAND"), /* ldo_ms18_sel */
+ TOP_MUX(0x1, "BGPIO")), /* gpio99 */
+
+ /* top_pmm_reg_6 */
+ TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18,
+ TOP_MUX(0x0, "SPI3"), /* rxd */
+ TOP_MUX(0x1, "TSO1"), /* dat2 */
+ TOP_MUX(0x2, "LCD"), /* stvu_vsync */
+ TOP_MUX(0x3, "BGPIO"), /* gpio76 */
+ TOP_MUX(0x4, "UART5"), /* rts */
+ TOP_MUX(0x5, "PCM"), /* rxd */
+ TOP_MUX(0x6, "I2S0"), /* dout1 */
+ TOP_MUX(0x7, "B_DVI1")), /* clk */
+ TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0,
+ TOP_MUX(0x0, "I2S0"), /* mclk */
+ TOP_MUX(0x1, "TSO1"), /* dat3 */
+ TOP_MUX(0x2, "LCD"), /* stvd */
+ TOP_MUX(0x3, "BGPIO"), /* gpio77 */
+ TOP_MUX(0x4, "USIM0"), /* cd */
+ TOP_MUX(0x5, "B_DVI1")), /* vs */
+ TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9,
+ TOP_MUX(0x0, "I2S0"), /* bclk */
+ TOP_MUX(0x1, "TSO1"), /* dat4 */
+ TOP_MUX(0x2, "LCD"), /* sthl_hsync */
+ TOP_MUX(0x3, "BGPIO"), /* gpio78 */
+ TOP_MUX(0x4, "USIM0"), /* clk */
+ TOP_MUX(0x5, "B_DVI1")), /* hs */
+ TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18,
+ TOP_MUX(0x0, "I2S0"), /* ws */
+ TOP_MUX(0x1, "TSO1"), /* dat5 */
+ TOP_MUX(0x2, "LCD"), /* sthr */
+ TOP_MUX(0x3, "BGPIO"), /* gpio79 */
+ TOP_MUX(0x4, "USIM0"), /* rst */
+ TOP_MUX(0x5, "B_DVI1")), /* d0 */
+ TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0,
+ TOP_MUX(0x0, "I2S0"), /* din0 */
+ TOP_MUX(0x1, "TSO1"), /* dat6 */
+ TOP_MUX(0x2, "LCD"), /* oev_dataen */
+ TOP_MUX(0x3, "BGPIO"), /* gpio80 */
+ TOP_MUX(0x4, "USIM0"), /* dat */
+ TOP_MUX(0x5, "B_DVI1")), /* d1 */
+ TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9,
+ TOP_MUX(0x0, "I2S0"), /* dout0 */
+ TOP_MUX(0x1, "TSO1"), /* dat7 */
+ TOP_MUX(0x2, "LCD"), /* ckv */
+ TOP_MUX(0x3, "BGPIO")), /* gpio81 */
+ TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18,
+ TOP_MUX(0x0, "I2C5"), /* scl */
+ TOP_MUX(0x1, "TSO1"), /* sync */
+ TOP_MUX(0x2, "LCD"), /* ld */
+ TOP_MUX(0x3, "BGPIO"), /* gpio82 */
+ TOP_MUX(0x4, "PWM"), /* out2 */
+ TOP_MUX(0x5, "I2S0"), /* dout2 */
+ TOP_MUX(0x6, "B_DVI1")), /* d2 */
+ TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0,
+ TOP_MUX(0x0, "I2C5"), /* sda */
+ TOP_MUX(0x1, "TSO1"), /* vld */
+ TOP_MUX(0x2, "LCD"), /* pol */
+ TOP_MUX(0x3, "BGPIO"), /* gpio83 */
+ TOP_MUX(0x4, "PWM"), /* out3 */
+ TOP_MUX(0x5, "I2S0"), /* dout3 */
+ TOP_MUX(0x6, "B_DVI1")), /* d3 */
+ TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9,
+ TOP_MUX(0x0, "SPI2"), /* clk */
+ TOP_MUX(0x1, "TSO0"), /* clk */
+ TOP_MUX(0x2, "LCD"), /* degsl */
+ TOP_MUX(0x3, "BGPIO"), /* gpio84 */
+ TOP_MUX(0x4, "I2C4"), /* scl */
+ TOP_MUX(0x5, "B_DVI1")), /* d4 */
+ TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18,
+ TOP_MUX(0x0, "SPI2"), /* cs */
+ TOP_MUX(0x1, "TSO0"), /* data */
+ TOP_MUX(0x2, "LCD"), /* rev */
+ TOP_MUX(0x3, "BGPIO"), /* gpio85 */
+ TOP_MUX(0x4, "I2C4"), /* sda */
+ TOP_MUX(0x5, "B_DVI1")), /* d5 */
+ TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0,
+ TOP_MUX(0x0, "SPI2"), /* txd */
+ TOP_MUX(0x1, "TSO0"), /* sync */
+ TOP_MUX(0x2, "LCD"), /* u_d */
+ TOP_MUX(0x3, "BGPIO"), /* gpio86 */
+ TOP_MUX(0x4, "I2C4"), /* scl */
+ TOP_MUX(0x5, "B_DVI1")), /* d6 */
+
+ /* top_pmm_reg_7 */
+ TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9,
+ TOP_MUX(0x0, "SPI2"), /* rxd */
+ TOP_MUX(0x1, "TSO0"), /* vld */
+ TOP_MUX(0x2, "LCD"), /* r_l */
+ TOP_MUX(0x3, "BGPIO"), /* gpio87 */
+ TOP_MUX(0x4, "I2C3"), /* sda */
+ TOP_MUX(0x5, "B_DVI1")), /* d7 */
+ TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9,
+ TOP_MUX(0x0, "NAND"), /* wp */
+ TOP_MUX(0x1, "PWM"), /* out2 */
+ TOP_MUX(0x2, "SPI2"), /* clk */
+ TOP_MUX(0x3, "BGPIO"), /* gpio88 */
+ TOP_MUX(0x4, "TSI0"), /* dat0 */
+ TOP_MUX(0x5, "I2S1")), /* din1 */
+ TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0,
+ TOP_MUX(0x0, "NAND"), /* boot_pagesize0 */
+ TOP_MUX(0x1, "PWM"), /* out3 */
+ TOP_MUX(0x2, "SPI2"), /* cs */
+ TOP_MUX(0x3, "BGPIO"), /* gpio89 */
+ TOP_MUX(0x4, "TSI0"), /* clk */
+ TOP_MUX(0x5, "I2S1")), /* din2 */
+ TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9,
+ TOP_MUX(0x0, "NAND"), /* boot_pagesize1 */
+ TOP_MUX(0x1, "I2C4"), /* scl */
+ TOP_MUX(0x2, "SPI2"), /* txd */
+ TOP_MUX(0x3, "BGPIO"), /* gpio90 */
+ TOP_MUX(0x4, "TSI0"), /* sync */
+ TOP_MUX(0x5, "I2S1")), /* din3 */
+ TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18,
+ TOP_MUX(0x0, "NAND"), /* boot_addr_cycles */
+ TOP_MUX(0x1, "I2C4"), /* sda */
+ TOP_MUX(0x2, "SPI2"), /* rxd */
+ TOP_MUX(0x3, "BGPIO"), /* gpio91 */
+ TOP_MUX(0x4, "TSI0"), /* valid */
+ TOP_MUX(0x5, "I2S1")), /* dout1 */
+ TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0,
+ TOP_MUX(0x0, "NAND"), /* rdy_busy0 */
+ TOP_MUX(0x1, "I2C2"), /* scl */
+ TOP_MUX(0x2, "USIM0"), /* cd */
+ TOP_MUX(0x3, "BGPIO"), /* gpio92 */
+ TOP_MUX(0x4, "TSI1")), /* data0 */
+ TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9,
+ TOP_MUX(0x0, "NAND"), /* rdy_busy1 */
+ TOP_MUX(0x1, "I2C2"), /* sda */
+ TOP_MUX(0x2, "USIM0"), /* clk */
+ TOP_MUX(0x3, "BGPIO"), /* gpio93 */
+ TOP_MUX(0x4, "TSI1")), /* clk */
+ TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18,
+ TOP_MUX(0x0, "NAND"), /* rdy_busy2 */
+ TOP_MUX(0x1, "UART5"), /* rxd */
+ TOP_MUX(0x2, "USIM0"), /* rst */
+ TOP_MUX(0x3, "BGPIO"), /* gpio94 */
+ TOP_MUX(0x4, "TSI1"), /* sync */
+ TOP_MUX(0x4, "I2S1")), /* dout2 */
+ TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18,
+ TOP_MUX(0x0, "NAND"), /* rdy_busy3 */
+ TOP_MUX(0x1, "UART5"), /* txd */
+ TOP_MUX(0x2, "USIM0"), /* dat */
+ TOP_MUX(0x3, "BGPIO"), /* gpio95 */
+ TOP_MUX(0x4, "TSI1"), /* valid */
+ TOP_MUX(0x4, "I2S1")), /* dout3 */
+
+ /* top_pmm_reg_8 */
+ TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0,
+ TOP_MUX(0x0, "GMII"), /* 125m_in */
+ TOP_MUX(0x1, "USB2"), /* 0_drvvbus */
+ TOP_MUX(0x2, "ISP"), /* ref_clk */
+ TOP_MUX(0x3, "BGPIO")), /* gpio96 */
+ TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9,
+ TOP_MUX(0x0, "GMII"), /* 50m_out */
+ TOP_MUX(0x1, "USB2"), /* 1_drvvbus */
+ TOP_MUX(0x2, "BGPIO"), /* gpio97 */
+ TOP_MUX(0x3, "USB2")), /* 0_drvvbus */
+ TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9,
+ TOP_MUX(0x0, "SPINOR")), /* sdio1_clk_i */
+ TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18,
+ TOP_MUX(0x0, "SPINOR")), /* ssclk_i */
+};
+
+static struct zx_pinctrl_soc_info zx296718_pinctrl_info = {
+ .pins = zx296718_pins,
+ .npins = ARRAY_SIZE(zx296718_pins),
+};
+
+static int zx296718_pinctrl_probe(struct platform_device *pdev)
+{
+ return zx_pinctrl_init(pdev, &zx296718_pinctrl_info);
+}
+
+static const struct of_device_id zx296718_pinctrl_match[] = {
+ { .compatible = "zte,zx296718-pmm", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match);
+
+static struct platform_driver zx296718_pinctrl_driver = {
+ .probe = zx296718_pinctrl_probe,
+ .driver = {
+ .name = "zx296718-pinctrl",
+ .of_match_table = zx296718_pinctrl_match,
+ },
+};
+builtin_platform_driver(zx296718_pinctrl_driver);
+
+MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver");
+MODULE_LICENSE("GPL");
#include <linux/platform_device.h>
#include <linux/pwm.h>
-#include <asm/mach-jz4740/gpio.h>
#include <asm/mach-jz4740/timer.h>
#define NUM_PWM 8
-static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = {
- JZ_GPIO_PWM0,
- JZ_GPIO_PWM1,
- JZ_GPIO_PWM2,
- JZ_GPIO_PWM3,
- JZ_GPIO_PWM4,
- JZ_GPIO_PWM5,
- JZ_GPIO_PWM6,
- JZ_GPIO_PWM7,
-};
-
struct jz4740_pwm_chip {
struct pwm_chip chip;
struct clk *clk;
static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
- unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm];
- int ret;
-
/*
* Timers 0 and 1 are used for system tasks, so they are unavailable
* for use as PWMs.
if (pwm->hwpwm < 2)
return -EBUSY;
- ret = gpio_request(gpio, pwm->label);
- if (ret) {
- dev_err(chip->dev, "Failed to request GPIO#%u for PWM: %d\n",
- gpio, ret);
- return ret;
- }
-
- jz_gpio_set_function(gpio, JZ_GPIO_FUNC_PWM);
-
jz4740_timer_start(pwm->hwpwm);
return 0;
static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
- unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm];
-
jz4740_timer_set_ctrl(pwm->hwpwm, 0);
- jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
- gpio_free(gpio);
-
jz4740_timer_stop(pwm->hwpwm);
}
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <asm/mach-jz4740/jz4740_fb.h>
-#include <asm/mach-jz4740/gpio.h>
#define JZ_REG_LCD_CFG 0x00
#define JZ_REG_LCD_VSYNC 0x04
.accel = FB_ACCEL_NONE,
};
-static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = {
- JZ_GPIO_BULK_PIN(LCD_PCLK),
- JZ_GPIO_BULK_PIN(LCD_HSYNC),
- JZ_GPIO_BULK_PIN(LCD_VSYNC),
- JZ_GPIO_BULK_PIN(LCD_DE),
- JZ_GPIO_BULK_PIN(LCD_PS),
- JZ_GPIO_BULK_PIN(LCD_REV),
- JZ_GPIO_BULK_PIN(LCD_CLS),
- JZ_GPIO_BULK_PIN(LCD_SPL),
-};
-
-static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = {
- JZ_GPIO_BULK_PIN(LCD_DATA0),
- JZ_GPIO_BULK_PIN(LCD_DATA1),
- JZ_GPIO_BULK_PIN(LCD_DATA2),
- JZ_GPIO_BULK_PIN(LCD_DATA3),
- JZ_GPIO_BULK_PIN(LCD_DATA4),
- JZ_GPIO_BULK_PIN(LCD_DATA5),
- JZ_GPIO_BULK_PIN(LCD_DATA6),
- JZ_GPIO_BULK_PIN(LCD_DATA7),
- JZ_GPIO_BULK_PIN(LCD_DATA8),
- JZ_GPIO_BULK_PIN(LCD_DATA9),
- JZ_GPIO_BULK_PIN(LCD_DATA10),
- JZ_GPIO_BULK_PIN(LCD_DATA11),
- JZ_GPIO_BULK_PIN(LCD_DATA12),
- JZ_GPIO_BULK_PIN(LCD_DATA13),
- JZ_GPIO_BULK_PIN(LCD_DATA14),
- JZ_GPIO_BULK_PIN(LCD_DATA15),
- JZ_GPIO_BULK_PIN(LCD_DATA16),
- JZ_GPIO_BULK_PIN(LCD_DATA17),
-};
-
-static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb)
-{
- unsigned int num;
-
- switch (jzfb->pdata->lcd_type) {
- case JZ_LCD_TYPE_GENERIC_16_BIT:
- num = 4;
- break;
- case JZ_LCD_TYPE_GENERIC_18_BIT:
- num = 4;
- break;
- case JZ_LCD_TYPE_8BIT_SERIAL:
- num = 3;
- break;
- case JZ_LCD_TYPE_SPECIAL_TFT_1:
- case JZ_LCD_TYPE_SPECIAL_TFT_2:
- case JZ_LCD_TYPE_SPECIAL_TFT_3:
- num = 8;
- break;
- default:
- num = 0;
- break;
- }
- return num;
-}
-
-static unsigned int jzfb_num_data_pins(struct jzfb *jzfb)
-{
- unsigned int num;
-
- switch (jzfb->pdata->lcd_type) {
- case JZ_LCD_TYPE_GENERIC_16_BIT:
- num = 16;
- break;
- case JZ_LCD_TYPE_GENERIC_18_BIT:
- num = 18;
- break;
- case JZ_LCD_TYPE_8BIT_SERIAL:
- num = 8;
- break;
- case JZ_LCD_TYPE_SPECIAL_TFT_1:
- case JZ_LCD_TYPE_SPECIAL_TFT_2:
- case JZ_LCD_TYPE_SPECIAL_TFT_3:
- if (jzfb->pdata->bpp == 18)
- num = 18;
- else
- num = 16;
- break;
- default:
- num = 0;
- break;
- }
- return num;
-}
-
/* Based on CNVT_TOHW macro from skeletonfb.c */
static inline uint32_t jzfb_convert_color_to_hw(unsigned val,
struct fb_bitfield *bf)
clk_prepare_enable(jzfb->ldclk);
- jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
+ pinctrl_pm_select_default_state(&jzfb->pdev->dev);
writel(0, jzfb->base + JZ_REG_LCD_STATE);
ctrl = readl(jzfb->base + JZ_REG_LCD_STATE);
} while (!(ctrl & JZ_LCD_STATE_DISABLED));
- jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
+ pinctrl_pm_select_sleep_state(&jzfb->pdev->dev);
clk_disable_unprepare(jzfb->ldclk);
}
fb->mode = NULL;
jzfb_set_par(fb);
- jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
-
ret = register_framebuffer(fb);
if (ret) {
dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret);
return 0;
err_free_devmem:
- jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
-
fb_dealloc_cmap(&fb->cmap);
jzfb_free_devmem(jzfb);
err_framebuffer_release:
jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb);
- jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
- jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
-
fb_dealloc_cmap(&jzfb->fb->cmap);
jzfb_free_devmem(jzfb);
projects / karo-tx-linux.git / commitdiff