From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Tue, 28 Feb 2017 19:50:53 +0000 (-0800)
Subject: Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm
X-Git-Tag: v4.11-rc1~48
X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-linux.git;a=commitdiff_plain;h=d4f4cf77b37eaea58ef863a4cbc95dad3880b524

Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

Pull ARM updates from Russell King:

 - nommu updates from Afzal Mohammed cleaning up the vectors support

 - allow DMA memory "mapping" for nommu Benjamin Gaignard

 - fixing a correctness issue with R_ARM_PREL31 relocations in the
   module linker

 - add strlen() prototype for the decompressor

 - support for DEBUG_VIRTUAL from Florian Fainelli

 - adjusting memory bounds after memory reservations have been
   registered

 - unipher cache handling updates from Masahiro Yamada

 - initrd and Thumb Kconfig cleanups

* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (23 commits)
  ARM: mm: round the initrd reservation to page boundaries
  ARM: mm: clean up initrd initialisation
  ARM: mm: move initrd init code out of arm_memblock_init()
  ARM: 8655/1: improve NOMMU definition of pgprot_*()
  ARM: 8654/1: decompressor: add strlen prototype
  ARM: 8652/1: cache-uniphier: clean up active way setup code
  ARM: 8651/1: cache-uniphier: include <linux/errno.h> instead of <linux/types.h>
  ARM: 8650/1: module: handle negative R_ARM_PREL31 addends correctly
  ARM: 8649/2: nommu: remove Hivecs configuration is asm
  ARM: 8648/2: nommu: display vectors base
  ARM: 8647/2: nommu: dynamic exception base address setting
  ARM: 8646/1: mmu: decouple VECTORS_BASE from Kconfig
  ARM: 8644/1: Reduce "CPU: shutdown" message to debug level
  ARM: 8641/1: treewide: Replace uses of virt_to_phys with __pa_symbol
  ARM: 8640/1: Add support for CONFIG_DEBUG_VIRTUAL
  ARM: 8639/1: Define KERNEL_START and KERNEL_END
  ARM: 8638/1: mtd: lart: Rename partition defines to be prefixed with PART_
  ARM: 8637/1: Adjust memory boundaries after reservations
  ARM: 8636/1: Cleanup sanity_check_meminfo
  ARM: add CPU_THUMB_CAPABLE to indicate possible Thumb support
  ...
---

d4f4cf77b37eaea58ef863a4cbc95dad3880b524
diff --cc arch/arm/Kconfig
index fda6a46d27cf,4700294f4e09..0d4e71b42c77
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -2,11 -2,9 +2,12 @@@ config AR
  	bool
  	default y
  	select ARCH_CLOCKSOURCE_DATA
+ 	select ARCH_HAS_DEBUG_VIRTUAL
  	select ARCH_HAS_DEVMEM_IS_ALLOWED
  	select ARCH_HAS_ELF_RANDOMIZE
 +	select ARCH_HAS_SET_MEMORY
 +	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
 +	select ARCH_HAS_STRICT_MODULE_RWX if MMU
  	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  	select ARCH_HAVE_CUSTOM_GPIO_H
  	select ARCH_HAS_GCOV_PROFILE_ALL
diff --cc arch/arm/mach-exynos/suspend.c
index adf4e8f182bd,97765be2cc12..748cfb8d5212
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@@ -343,11 -386,11 +343,11 @@@ static void exynos5420_pm_prepare(void
  
  	/* ensure at least INFORM0 has the resume address */
  	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
- 		pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
+ 		pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
  
 -	tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
 -	tmp &= ~EXYNOS5_USE_RETENTION;
 -	pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
 +	tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
 +	tmp &= ~EXYNOS_L2_USE_RETENTION;
 +	pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
  
  	tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
  	tmp |= EXYNOS5420_UFS;
diff --cc arch/arm/mach-ux500/platsmp.c
index e0ee139fdebf,8c8f26389067..9b124c22035f
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@@ -73,19 -92,7 +73,19 @@@ static void __init ux500_smp_prepare_cp
  
  static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
  {
 -	wakeup_secondary();
 +	/*
 +	 * write the address of secondary startup into the backup ram register
 +	 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
 +	 * backup ram register at offset 0x1FF0, which is what boot rom code
 +	 * is waiting for. This will wake up the secondary core from WFE.
 +	 */
- 	writel(virt_to_phys(secondary_startup),
++	writel(__pa_symbol(secondary_startup),
 +	       backupram + UX500_CPU1_JUMPADDR_OFFSET);
 +	writel(0xA1FEED01,
 +	       backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
 +
 +	/* make sure write buffer is drained */
 +	mb();
  	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  	return 0;
  }