Li Jun [Thu, 15 Jan 2015 12:10:36 +0000 (20:10 +0800)]
MLK-10102-4 usb: chipidea: host: support resume usb from power lost
This patch implements the suspend and resume routine for save and restore
registers of ehci, this is to support host resume from a system sleep with
power lost.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
Li Jun [Thu, 15 Jan 2015 12:17:07 +0000 (20:17 +0800)]
MLK-10102-2 usb: chipidea: add suspend and resume routine for role driver
We may need to do extra things for system suspend/resume per different
roles(e.g. power lost during system sleep), so define system suspend/resume
handler for roles.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Li Jun [Thu, 15 Jan 2015 11:13:13 +0000 (19:13 +0800)]
MLK-10102-1 usb: chipidea: imx: usb resume from power lost during system sleep
i.MX6SX mega off can shutdown domain power supply if none of peripheral
in this domain is registered as wakeup source, this patch adds usb controller
imx specific re-init after resume from such power lost during system sleep.
Anson Huang [Fri, 16 Jan 2015 10:47:42 +0000 (18:47 +0800)]
MLK-10103-2 cpufreq: imx6: increase SOC/PU voltage for vpu 352M
When VPU is running at 352MHz, SOC/PU voltage need to be
at 1.25V for 396/792MHz setpoint, as 396M setpoint is
removed, so only increase 792M setpoint's voltage.
Anson Huang [Fri, 16 Jan 2015 10:42:08 +0000 (18:42 +0800)]
MLK-10103-1 ARM: imx: add VPU 352M for i.mx6q
When VPU freq is set to 352MHz, it needs to source clk
from PLL2_PFD2_396M, and PLL2_PFD2_396M need to change
freq to 352M, cpufreq's 396M setpoint will be removed.
Busfreq will be disabled as it needs PLL2_PFD2 to be
as 396MHz to achieve low power audio freq setpoint.
To enable VPU 352MHz feature, select it in menuconfig,
it is disabled by default.
Fugang Duan [Fri, 16 Jan 2015 05:18:00 +0000 (13:18 +0800)]
ENGR00320136 net: fec: fix rcv is not last issue when do suspend/resume test
When do suspend/resume stress test, some log shows "rcv is not +last".
The issue is that enet suspend will disable phy clock, phy link down,
after resume back, enet MAC redo initial and ready to tx/rx packet,
but phy still is not ready which is doing auto-negotiation. When phy
link is not up, don't schdule napi soft irq.
Steve Cornelius [Tue, 6 Jan 2015 23:20:15 +0000 (16:20 -0700)]
MLK-9769-26 caam: fix RNG buffer cache alignment
The hwrng output buffers (2) are cast inside of a a struct (caam_rng_ctx)
allocated in one DMA-tagged region. While the kernel's heap allocator
should place the overall struct on a cacheline aligned boundary, the 2
buffers contained within may not necessarily align. Consenquently, the ends
of unaligned buffers may not fully flush, and if so, stale data will be left
behind, resulting in small repeating patterns.
This fix aligns the buffers inside the struct.
Note that not all of the data inside caam_rng_ctx necessarily needs to be
DMA-tagged, only the buffers themselves require this. However, a fix would
incur the expense of error-handling bloat in the case of allocation failure.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Victoria Milhoan [Wed, 14 Jan 2015 18:43:12 +0000 (11:43 -0700)]
MLK-9769-23 Replace SECVIO of_irq_to_resource() with irq_of_parse_and_map()
Replace of_irq_to_resource() in the SECVIO module with the simpler
equivalent irq_of_parse_and_map(). Also, add error checking to
to the SECVIO and Job Ring modules. Based on upstream commit f7578496a671a96e501f16a5104893275e32c33a.
Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
Victoria Milhoan [Thu, 18 Dec 2014 21:06:50 +0000 (14:06 -0700)]
MLK-10036 Freescale CAAM: Add support for DSM with Mega/Fast mix on
This patch allows CAAM to be enabled as a wakeup source for the
Mega/Fast mix domain. If CAAM is enabled as a wakeup source, it
will continue to be powered on across Deep Sleep Mode (DSM). This
allows CAAM to be functional after the system resumes from DSM.
MLK-9971 Add XCBC-AES support for CAAM in i.MX6 family
Add XCBC-AES support to the CAAM crypto accelerator core in
the i.MX6 family of SoC devices.
Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ).
Thus the property names are often tied to the sec-4.0+ nomenclature.
Jason Liu [Tue, 6 Jan 2015 03:23:59 +0000 (11:23 +0800)]
Need gate the QSPI2 and GPMI_IO clock during clock init
QSPI2/GPMI_IO share the same clock source but with the
different gate, need explicitely gate the QSPI2 & GPMI_IO
during the clock init phase according to the SOC design.
The topo of the clock for the GPMI_IO and NAND as below:
mux --> pre divider --> post divider --gate-- >GPMI_IO
|-gate-- >QSPI2
(Note: i.MX6SX:GPMI_NAND and GSPI2 is PINMUX conflicts.)
The SOC design spec required that if change the parent clock
of the GPMI_IO or QSPI2, need gate the GPMI_IO and QSPI2 first
otherwise, there will have some glitch which cause the divider
malfunciton. Thus, we need explicitely gate QSPI2 & GPMI_IO at
the clock initialization phase and then later on common clock
framework will gurantee that each time, the parent clock rate
changes after the child clock is disabled(gated).
Peter Chen [Mon, 23 Sep 2013 03:20:08 +0000 (11:20 +0800)]
ENGR00320792-3 usb: gadget: mark init as late_initcall
Since we introduce -EPROBE_DEFER for udc driver, it will be
probed at late_initcall if it is defered. When the gadget
is built in, it will return "couldn't find an available UDC"
at such case. That's the problem we met at below link:
We have no driver's probe at gadget driver, so we can't return
-EPROBE_DEFER. And it is also not suitable to defer udc_bind_to_driver
if the udc is not found temporarily, since it is hard to decide the
return value for usb_gadget_probe_driver.
Due to above reasons, mark gadget's init as late_initcall may be a
moderate solution.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Li Jun [Fri, 9 Jan 2015 07:35:07 +0000 (15:35 +0800)]
MLK-10085-5 usb: chipidea: Add usb charger detect notify
- Change .notify's return value from void to int, update msm notify_event
return value accordingly.
- Add CI_HDRC_CONTROLLER_VBUS_EVENT and
CI_HDRC_CONTROLLER_CHARGER_POST_EVENT to finish the USB charger
detection flow.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <jun.li@freescale.com>
It is used to indicate whether we use SoC's usb charger
detection or not. Besides, we add anatop phandle since
we need to use anatop register to do most of charger detect operations.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Li Jun [Fri, 9 Jan 2015 03:39:33 +0000 (11:39 +0800)]
MLK-10085-1 power: imx6: add imx6 USB charger detection
Add imx6 USB charger detection, the vbus supplier will create and
remove struct usb_charger, and notify vbus connect and disconnect
event. The detail USB charger detection flow is at: "i.MX6 RM,
Chapter Universal Serial Bus 2.0 Integrated PHY (USB-PHY),
Charger detection, Charger detection software flow".
Since imx6 only has charger detection function, and no charging
current function is existed. It the user wants the detection abilities
from SoC, it can use this detection method
(add imx6-usb-charger-detection at dts). If the charger IC
already has USB charger detection function, and the user wants
to use the detection method from charger IC, please do not add
imx6-usb-charger-detection property at dts.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Allen Xu [Thu, 15 Jan 2015 02:18:29 +0000 (10:18 +0800)]
MLK-10028 QSPI dynamically alloc memory for AHB read
QSPI may failed to alloc enough memory (256MB) for AHB read in
previous implementation, especially in 3G/1G memory layout kernel.
Dynamically alloc memory to avoid such issue.
This implementation generally alloc 4MB memory for AHB read, it should
be enough for common scenarios, and the side effect (0.6% performance
drop) is minor.
Previous implementation
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=1K count=32K
32768+0 records in
32768+0 records out 33554432 bytes (34 MB) copied, 2.16006 s, 15.5 MB/s
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=32M count=1
1+0 records in
1+0 records out 33554432 bytes (34 MB) copied, 1.43149 s, 23.4 MB/s
After applied the patch
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=1K count=32K
32768+0 records in
32768+0 records out 33554432 bytes (34 MB) copied, 2.1743 s, 15.4 MB/s
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=32M count=1
1+0 records in
1+0 records out 33554432 bytes (34 MB) copied, 1.43158 s, 23.4 MB/s
NAND scans the bad blocks during kernel boots up, which invokes the
gpmi_ecc_read_oob function to check the badblock mark for each block. In
this function the oob data was raw read from NAND chip without ECC, so
it hardly to guarantee the consistency of the data considering the
possible bitflips. It found that in some MLC NAND the oob data changed
and consequently the BBT changed in different power cycles. This issue
may cause the UBIFS mount failed.
To fix this issue, add "nand_on_flash_bbt" option in dts to store the BBT
in NAND flash. On the first time kernel boot up, all bad blocks and
probably some fake bad block would be recognized and be recorded in
on-nand bad block table. From the second time boot, kernel will read BBT
from NAND Flash rather than calling gpmi_ecc_read_oob function to check
bad block.
No bad block would be missed when create BBT since the probability that
16bit bad block mark filps from 0x00 to 0xFF is extremely low.
Allen Xu [Thu, 4 Dec 2014 13:51:48 +0000 (21:51 +0800)]
MLK-9957 mtd: NAND: fix the kernel panic issue for NAND suspend/resume
The branch determined by GPMI_IS_MX6SX() should not include
acquire_dma_channels() function which causes unbalanced dma
request/release on other platform.
Removed GPMI_IS_MX6SX() to make code simple although it is not necessary
to restore GPMI/BCH registers for i.MX6Q/DL
Ye.Li [Mon, 1 Dec 2014 09:28:47 +0000 (17:28 +0800)]
MLK-9920 mtd: qspi: Add ddrsmp parameter to device tree
Since QSPI internal DDR sample point is relevant with board layout,
we can't use same value for all boards. Add ddrsmp parameter to device
tree for i.MX6SX Sabreauto/Sabresd board.
Allen Xu [Fri, 14 Nov 2014 16:36:07 +0000 (00:36 +0800)]
MLK-9851 mtd: Change the mtd device driver build order for mfgtool
i.MX6SX Sabreauto board enabled both NAND and QSPI1 drivrers, and by default,
NAND driver built first in kernel compiling, and it would be load first when
Kernel brought up.
Since we could not guarantee all boards mounted NAND chips, we wish the Kernel
could load QSPI driver first, when system mapped QSPI and NAND, the mtd device
index won't change dynamically, otherwise, the mfgtool may write images to the
inappropriate storage devices.
The code change moved the SPI driver at the prior position of NAND driver in
Makefile to solve this issue.
Allen Xu [Thu, 25 Sep 2014 10:39:09 +0000 (05:39 -0500)]
ENGR00311101 QSPI: i.MX6SX: fixed the random QSPI access failed issue
We found there is a low probability(5%) QSPI access timeout issue,
usually it happened on kernel boot stage, the first time kernel tried to
access QSPI chip. The READ_ID command was sent but not executed,
consequently the probe function failed.
Finally we located the issue by these steps.
1. Since the issue happened randomly and usually it cost half day to
reproduce, we add more debug code in driver, to create a timeout file if
the issue occurred.
2. Prepared an autorun script to keep rebooting the system and check if
the timeout file existed, if the file existed, stop reboot.
3. The system will stop rebooting when timeout error occurred, set the
CCM_CCOSR register and related IOMUX to measure QPSI clock, found there
is no clock output, while clock output can be measured when QSPI driver
successfully probed.
4. Check the code and found QSPI clock rate was changed while not
disabled clock gate, most of the multiplexers on i.MX6 are glitch ones,
clock glitch may occurred and propagated into downstream clock dividers
Based on the new clock flag(CLK_SET_RATE_GATE) and new framework, we
need to change the approach of seting clock rate. In current
implementation, there are several places in which the clock was touched.
1. probe function. prepare and enable clock before setting the QSPI
register, disable and unprepare the clock before exit.
2. nor_setup & nor_setup_last, since we change clock rate in these two
functions.
3. fsl_qspi_prep and fsl_qspi_unprep, clock was enabled only when got
QSPI access request.
4. resume function. Clock was required to restroe the setting after
resume, disable the clock before exit.
Sandor Yu [Wed, 14 Jan 2015 07:41:43 +0000 (15:41 +0800)]
MLK-10092-2 dts: Rename compatible string from ov564x to ov5640
There are two version ov5640 driver,
one is written with v4l2 int-device architecture,
and the other is written with v4l2 subdev architecture.
Rename subdev ov5640 compatible string from ov5640x
to ov5640 to distinguish with ov5640 int-device driver.
so ov564x is used for int-device architecture and
ov5640 is used for subdev architecture.
Sandor Yu [Wed, 14 Jan 2015 07:34:22 +0000 (15:34 +0800)]
MLK-10092-1 ov5640: Rename compatible string from ov564x to ov5640
There are two version ov5640 driver,
one is written with v4l2 int-device architecture,
and the other is written with v4l2 subdev architecture.
Rename subdev ov5640 compatible string from ov5640x to ov5640
to distinguish with ov5640 int-device driver.
so ov564x is used for int-device architecture and
ov5640 is used for subdev architecture.
Liu Ying [Tue, 13 Jan 2015 02:19:10 +0000 (10:19 +0800)]
MLK-10084 media: mxc vout: Correct black color filling for interleaved formats
In non-linear_bypass_pp and non-tiled_bypass_pp modes, the triple fbdev frame
buffer would be rendered with video frames in turn. We need to fill all the
three frame buffers with black color before streaming on instead of filling only
one of them.
Fugang Duan [Wed, 14 Jan 2015 08:18:58 +0000 (16:18 +0800)]
MLK-10098 ARM: imx: fix 1588 clock init
The enet clock define is changed as there has no "enet_ref" clock name.
If the tx_clk is sourced from SOC anatop PLL, user define the clock id
in devicetree. So we only to judge the ptp clock valid and then set the
related GPR bit.
According to the help text in the config SWP_EMULATE in arch/arm/mm/Kconfig:
"In some older versions of glibc [<=2.8] SWP is used during futex trylock()
operations with the assumption that the code will not be preempted. This
invalid assumption may be more likely to fail with SWP emulation enabled,
leading to deadlock of the user application."
The audio codec toolchain version is gcc-4.1.1-glibc-2.4, we need turn off
the CONFIG_SWP_EMULATE in the imx_v7_defconfig.
Victoria Milhoan [Thu, 20 Nov 2014 18:28:28 +0000 (11:28 -0700)]
MLK-9951 Update CAAM driver era interface
Add more CAAM era values to the CAAM driver's caam_get_era()
function. Read only 32 bits of data since the data required
to identify the IP_ID and MAJ_REV is located in the first 32
bits of the register. And, update the function for use with
ARM/Little Endian devices.
[<vicki.milhoan@freescale.com>: Edited to apply to 3.14] Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
(cherry picked from commit 6050d7faf2d0c063195aa9454c130548a9f8058f)
Steve Cornelius [Tue, 14 Aug 2012 22:04:11 +0000 (15:04 -0700)]
MLK-9769-22 caam: improve initalization for context state saves
Multiple function in asynchronous hashing use a saved-state block,
a.k.a. struct caam_hash_state, which holds a stash of information
between requests (init/update/final). Certain values in this state
block are loaded for processing using an inline-if, and when this
is done, the potential for uninitialized data can pose conflicts.
Therefore, this patch improves initialization of state data to
prevent false assignments using uninitialized data in the state block.
This patch addresses the following traceback, originating in
ahash_final_ctx(), although a problem like this could certainly
exhibit other symptoms:
MLK-9710-5 Unregister Secure Memory platform device upon shutdown
Unregister Secure Memory platform device when the Secure Memory
module is shut down. This allows the Secure Memory module to
be inserted again successfully.
Steve Cornelius [Mon, 17 Nov 2014 18:24:14 +0000 (11:24 -0700)]
MLK-9769-22 Detect HW features during alg registration
i.MX6 instantiates a CAAM with a low-power MDHA block, which does not
compute digests larger than 256 bits. Since the driver installs handlers
for hashes longer than 256 bits in several places, added the ability to
read and interpret the CHA version and instantiations registers, and then
only register handlers that it can support.
[<vicki.milhoan@freescale.com>: Edited to include only caamhash changes] Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
MLK-9769-20 Limit AXI pipeline to a depth of one in CAAM for i.MX6 devices
i.MX6 devices have an issue wherein AXI bus transactions may not occur
in the correct order. This isn't a problem running single descriptors,
but can be if running multiple concurrent descriptors. Reworking the CAAM
driver to throttle to single requests is impractical, so this patch limits
the AXI pipeline to a depth of one (from a default of four) to preclude
this situation from occurring.
Signed-off-by: Victoria Milhoan (b42089) <vicki.milhoan@freescale.com>
Winston Hudson [Mon, 17 Nov 2014 17:17:35 +0000 (10:17 -0700)]
MLK-9769-19 Add ARC4-ECB support for CAAM in i.MX6 family
Adds ARC4-ECB Mode support to the CAAM crypto accelerator core in
the i.MX6 family of SoC devices.
Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ).
Thus the property names are often tied to the sec-4.0+ nomenclature.
MLK-9769-18 Add 3DES-ECB-EDE support for CAAM in i.MX6 family
Adds 3DES-ECB-EDE Mode support to the CAAM crypto accelerator core in
the i.MX6 family of SoC devices.
Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ).
Thus the property names are often tied to the sec-4.0+ nomenclature.
MLK-9769-17 Add AES-ECB support for CAAM in i.MX6 family
Adds AES-ECB (Electronic Codebook) support to the CAAM crypto accelerator core in
the i.MX6 family of SoC devices.
Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ).
Thus the property names are often tied to the sec-4.0+ nomenclature.
Winston Hudson [Mon, 17 Nov 2014 16:27:30 +0000 (09:27 -0700)]
MLK-9769-16 Add DES-ECB support for CAAM in i.MX6 family
Adds DES-ECB Mode support to the CAAM crypto accelerator core in
the i.MX6 family of SoC devices.
Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ).
Thus the property names are often tied to the sec-4.0+ nomenclature.
Victoria Milhoan [Fri, 14 Nov 2014 22:32:20 +0000 (15:32 -0700)]
MLK-9769-15 Register only crypto algorithms supported by the Freescale CAAM hardware
This patch enhances the CAAM driver's registration of crypto
algorithms into the Crypto API by only registering algorithms
supported by the CAAM hardware available.
Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
MLK-9769-14 Add CRYPTO_ALG_KERN_DRIVER_ONLY flag to Freescale CAAM driver
The CRYPTO_ALG_KERN_DRIVER_ONLY flag is used to indicate that
the crypto algorithm is only available via a kernel driver.
This patch adds the flag only when the flag is available in the
kernel. Utilizing the flag based on it's availability in the
kernel allows the driver to compile on older kernel versions.
The original community patch is located at
http://permalink.gmane.org/gmane.linux.kernel.cryptoapi/6547
for reference.
Signed-off-by: Victoria Milhoan (b42089) <vicki.milhoan@freescale.com>
MLK-9769-13 Add AES-CTR support for CAAM in i.MX6 family
Adds AES-CTR (Counter Mode) support to the CAAM crypto accelerator core in
the i.MX6 family of SoC devices.
Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ).
Thus the property names are often tied to the sec-4.0+ nomenclature.
[<vicki.milhoan@freescale.com>: Edited to apply to 3.14] Signed-off-by: Winston Hudson (b45308) <winston.h.hudson@freescale.com> Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
By default, job ring 0 is the owner of the Secure Memory area
within CAAM. This patch modifies the Secure Memory module to
use job ring 0 for all accesses.
Steve Cornelius [Fri, 21 Feb 2014 17:40:52 +0000 (10:40 -0700)]
MLK-9710-16 Cache-invalidate deferred RNG buffer fill
CAAM's kernel random generator adaptor (feeding /dev/hwrng) manages
a pair of data buffers that fill with RNG-sourced data for consumption.
While one buffer is being drained through the dev, the other is filling
in the background to be used on "standby".
In the case where the completion of the buffer fill is deferred, a
cache invalidate call is required before the buffer can be put into use.
Steve Cornelius [Fri, 2 Aug 2013 03:08:19 +0000 (20:08 -0700)]
MLK-9710-14 Un-pad cache sizes for blob export/import
Blob exportation and importation functions were adding padding to
the buffer mapping and cache control functions, which resulted in
incorrect CPU-level views into a DMA-ed blob.
Also, corrected descriptor constructors to use symbolic form of
blob overhead calculation.
Steve Cornelius [Wed, 24 Jul 2013 03:56:08 +0000 (20:56 -0700)]
MLK-9710-12 Adapt sm_test as a black-key handling example
Converted sm_test to an example that can show:
- key covering
- secret encapsulation as external memory blob
- secret decapsulation from external memory blob
- checks and displays of the handling of key content
Steve Cornelius [Wed, 24 Jul 2013 03:49:29 +0000 (20:49 -0700)]
MLK-9710-11 Add internal key cover and external blob export/import to prototype SM-API
Extended/amended the prototype SM-API with the following functions:
- Added key covering (blackening) function in-place to a keyslot
- Added export operation to encapsulate data to external memory as a
secure memory blob (including descriptor capable of secure memory or
general memory blob generation)
- Removed in-place blob encapsulation
- Added import operation to decapsulate a blob from external memory into
secure memory (including descriptor capable of general memory or secure
memory content decapsulation)
- Removed in-place blob decapsulation
[<vicki.milhoan@freescale.com>: Edited to apply to 3.10] Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
(cherry picked from commit c577769ed0347bb4e3428b5696fb7f209af0a7ad)
Steve Cornelius [Thu, 25 Sep 2014 23:34:11 +0000 (16:34 -0700)]
MLK-9710-18 snvs - make SECVIO module device tree correct
Converted the prototype 3.0.x SNVS Security Violation Handler
subsystem to be device tree correct/compliant under 3.10 for ARM
platforms. Also, separated out SNVS property detection so as to make
it independent of CAAM, and corrected function namespace accordingly.
Later releases of this subsystem are likely to be separate from the
kernel's CAAM driver space.
[<vicki.milhoan@freescale.com>: Edited to apply to latest 3.10 kernel] Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
(cherry picked from commit c8c128086eae012ced0c96d66f21f36bcbd14f66)
Steve Cornelius [Fri, 19 Oct 2012 21:43:41 +0000 (14:43 -0700)]
MLK-9769-11 Add SM register defs, and expanded driver-private storage.
These add changes to the driver private areas for the CAAM
controller and CAAM Secure Memory subsystems, and expand register
definitions to include the Secure Memory subsystems as reflected
in multiple areas (controller, rings, secure memory itself).
[<vicki.milhoan@freescale.com>: Edited to apply to 3.14] Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
Dan Douglass [Wed, 27 Nov 2013 09:40:44 +0000 (03:40 -0600)]
ENGR00289885 [iMX6Q] Add Secure Memory and SECVIO support.
1. Pull in secure memory support from 3.0.35 kernel.
2. Pull in SECVIO support from 3.0.35 kernel.
3. Make changes to support device tree.
4. Add device tree setting for SECVIO sources.
[<vicki.milhoan@freescale.com>: Edited to apply to 3.14] Signed-off-by: Dan Douglass <b41520@freescale.com>
(cherry picked from commit f3bfd42e2db3af8326734bebf750e94e74734f6e) Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
Steve Cornelius [Wed, 24 Jul 2013 03:47:32 +0000 (20:47 -0700)]
MLK-9710-10 Add CCM defs for FIFO_STORE instruction
Added definitions to enable FIFO_STORE to encode options for storing
keys in AES-CCM mode
[<vicki.milhoan@freescale.com>: Edited to apply to 3.14] Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
(cherry picked from commit a3cd8e5fad274f33fc6f0030413f89a6339b1d5a) Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
MLK-9710-8 tcrypt: change memory allocation for test_ahash_speed output buffer
Change allocation of the tcrypt module's test_ahash_speed() output buffer to
use kmalloc(). This avoids a segmentation fault when the buffer is used in a
dma_map_*() call.
This patch has been backported to the 3.5.7 kernel for use with i.MX6.
Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such
as QorIQ). Thus the property names are often tied to the sec-4.0+ nomenclature.
The original patch can be found at the following link:
http://marc.info/?l=linux-crypto-vger&m=135771601829617&w=2
Test vectors were taken from existing test for CBC(DES3_EDE).
Associated data has been added to test vectors.
HMAC computed with Crypto++ has been used.
Following algos have been covered.
This patch adds support for the following tcrypt test:
(a) "authenc(hmac(md5),cbc(aes))"
Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ).
Thus the property names are often tied to the sec-4.0+ nomenclature.
MLK-9769-8 Add a test for the Freescale CAAM Random Number Generator
Freescale's CAAM includes a Random Number Generator. This change adds
a kernel configuration option to test the RNG's capabilities via the
hw_random framework.
Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
MLK-9769-5 Enable and disable clocks for the Freescale CAAM device on i.MX platforms
ARM-based systems may disable clocking to the CAAM device on the
Freescale i.MX platform for power management purposes. This patch
enables the required clocks when the CAAM module is initialized and
disables the required clocks when the CAAM module is shut down.
Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
projects / karo-tx-linux.git / log