Merge branch 'tracking-qcomlt-usb' into integration-linux-qcomlt
* tracking-qcomlt-usb:
drivers: usb: Add bus scaling suppport
usb: host: ehci-msm: Use posted data writes on AHB
usb: chipidea: msm: Use posted data writes on AHB
usb: phy: msm: Ensure that workers are initialized before use
usb: phy: msm: Disable driver runtime PM
usb: phy: msm: HACK: Make Vddc configuration optional
usb: phy: msm: fix error handling in probe.
Merge branch 'tracking-qcomlt-tsens' into integration-linux-qcomlt
* tracking-qcomlt-tsens:
thermal: qcom: tsens-8960: Add support for 8960 family of SoCs
thermal: qcom: tsens-8974: Add support for 8974 family of SoCs
thermal: qcom: tsens-8916: Add support for 8916 family of SoCs
thermal: qcom: tsens: Add a skeletal TSENS drivers
Merge branch 'tracking-qcomlt-arm64' into integration-linux-qcomlt
* tracking-qcomlt-arm64:
arm64: fixup for mm renames
arm64: dma-mapping: map sg lists into the SMMU as virtually contiguous
arm64: dma-mapping: fix DMA_ATTR_STRONGLY_ORDERED in __get_dma_pgprot
arm64: mm: Fix a bug in iommu dma-mapping
arm64: dma-mapping: add support for IOMMU mapper
arm64: Add support for DMA_ATTR_STRONGLY_ORDERED
arm: Add option to skip buffer zeroing
common: DMA-mapping: Add strongly ordered memory attribute
arm64: defconfig: add qcom specifics
arm64: qcom: add cpu operations
arm64: smp: move the pen to a header file
arm64: introduce CPU_OF_TABLES for cpu ops selection
devicetree: bindings: Document qcom,msm-id and qcom,board-id
arm64: defconfig: qcom: Enable restart driver
ARM: cpuidle: Add cpuidle support for QCOM cpus
Merge branch 'tracking-qcomlt-adm-dma' into integration-linux-qcomlt
* tracking-qcomlt-adm-dma:
dmaengine: adm: Start next DMA even if there is no ongoing transaction
dmaengine: adm: Don't reset controller during probe
dmaengine: adm: Use 'soft' flush when stopping DMA
dmaengine: adm: Fix ADM hardware descriptor creation when flow control is enabled
dmaengine: Add ADM driver
dt/bindings: qcom_adm: Fix channel specifiers
Merge branch 'tracking-qcomlt-iommu' into integration-linux-qcomlt
* tracking-qcomlt-iommu: (25 commits)
iommu: qcom: v1: move iommu-sec pgtable allocation
pci: use new of_dma_configure* apis
iommu/msm: Fix "scheduling while atomic" bug
drm/msm: temp: Add a check to be compatible against both iommuv0/v1
iommu: of: Handle IOMMU lookup failure with deferred probing or error
iommu: of: Document the of_iommu_configure() function
drivers: platform: Configure dma operations at probe time
of: dma: Split of_configure_dma() into mask and ops configuration
of: dma: Make of_dma_deconfigure() public
of: dma: Move range size workaround to of_dma_get_range()
arm: dma-mapping: Don't override dma_ops in arch_setup_dma_ops()
temp: Add dummy msm_iommu_get_ctx and fix broken build
iommu/msm: Set cacheability attributes without tex remap
iommu/msm: Add support for generic master bindings
iommu/msm: Move the contents from msm_iommu_dev.c to msm_iommu.c
iommu/msm: Add DT adaptation
DOWNSTREAM: drm/msm: use downstream iommu
qcom: iommu: Make use of domain_alloc and domain_free
arm64: provide dma cache routines with same API as 32 bit
iommu: msm: Invalidate properly from iommu_unmap
...
Merge branch 'tracking-qcomlt-panelpicker' into integration-linux-qcomlt
* tracking-qcomlt-panelpicker:
drm/msm: mdp4 lvds: Check the panel node in detect_panel()
drm/msm: mdp4 lvds: continue if the panel is not connected
drm/panel: simple-panel: Add panel picker support.
drm/edid: export edid_vendor()
drm/edid: Add support to get edid early
Ivan T. Ivanov [Wed, 13 May 2015 12:20:12 +0000 (15:20 +0300)]
usb: phy: msm: Ensure that workers are initialized before use
Charger detect and USB state detect workers could be triggered from
USB-HOST and USB cable detect notifiers. Ensure that workers are
initialized before driver register its interest for cable events.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
This driver registers for extcon events as part of its probe, but
never unregisters them in case of error in the probe path.
There were multiple issues noticed due to this missing error handling.
One of them is random crashes if the regulators are not ready yet by the
time probe is invoked.
Ivan's previous attempt [1] to fix this issue, did not really address
all the failure cases like regualtor failures.
Currently the rates of the xo and sleep clocks are hard-coded in the
GCC driver, but this is a board layout description that actually should
be in the DT. Moving them into DT also allows us to insert the RPM
controlled clocks between the DT and GCC clocks.
move the allocation of iommu-sec page table into msm_iommu_dev
in order to use properly initialised struct device.
The dma_alloc_attrs would fail to allocate memory with the fake
struct device which was the case before this change.
Ivan T. Ivanov [Fri, 15 May 2015 08:07:00 +0000 (11:07 +0300)]
amba: Defer device peripheral ID read
To be able to read peripheral ID during device create time
bus code have turn on device interface clock, but this
clock could be unavailable at this time. Fix this by defer
device ID read until driver match time.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Rajendra Nayak [Fri, 9 Oct 2015 09:41:06 +0000 (15:11 +0530)]
thermal: qcom: tsens-8960: Add support for 8960 family of SoCs
8960 family of SoCs have the TSENS device as part of GCC, hence
the driver probes the virtual child device created by GCC and
uses the parent to extract all DT properties and reuses the GCC
regmap.
Also GCC/TSENS are part of a domain thats not always ON.
Hence add .suspend and .resume hooks to save and restore some of
the inited register context.
Also 8960 family have some of the TSENS init sequence thats
required to be done by the HLOS driver (some later versions of TSENS
do not export these registers to non-secure world, and hence need
these initializations to be done by secure bootloaders)
8660 from the same family has just one sensor and hence some register
offset/layout differences which need special handling in the driver.
Based on the original code from Siddartha Mohanadoss, Stephen Boyd and
Narendran Rajan.
Rajendra Nayak [Fri, 9 Oct 2015 09:41:04 +0000 (15:11 +0530)]
thermal: qcom: tsens-8916: Add support for 8916 family of SoCs
Add support to calibrate sensors on 8916 family and also add common
functions to read temperature from sensors (This can be reused on
other SoCs having similar TSENS device)
The calibration data is read from eeprom using the generic nvmem
framework apis.
Based on the original code by Siddartha Mohanadoss and Stephen Boyd.
Rajendra Nayak [Fri, 9 Oct 2015 09:41:03 +0000 (15:11 +0530)]
thermal: qcom: tsens: Add a skeletal TSENS drivers
TSENS is Qualcomms' thermal temperature sensor device. It
supports reading temperatures from multiple thermal sensors
present on various QCOM SoCs.
Calibration data is generally read from a non-volatile memory
(eeprom) device.
Add a skeleton driver with all the necessary abstractions so
a variety of qcom device families which support TSENS can
add driver extensions.
Also add the required device tree bindings which can be used
to describe the TSENS device in DT.
Georgi Djakov [Tue, 11 Aug 2015 13:35:59 +0000 (16:35 +0300)]
soc: qcom: Add support for SAW2 regulators
The SAW2 (Subsystem Power Manager and Adaptive Voltage Scalling Wrapper)
is part of the SPM subsystem. It is a hardware block in the Qualcomm
chipsets that regulates the power to the cores.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Georgi Djakov [Wed, 18 Mar 2015 15:23:29 +0000 (17:23 +0200)]
clk: qcom: Add support for regmap mux-div clocks
Add support for hardware that support switching both parent clocks and the
divider at the same time. This avoids generating intermediate frequencies
from either the old parent clock and new divider or new parent clock and
old divider combinations.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Georgi Djakov [Thu, 3 Dec 2015 12:14:15 +0000 (14:14 +0200)]
clk: qcom: Add support for RPM Clocks
This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_rpm driver to communicate with RPM.
Such platforms are apq8064 and msm8960.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Georgi Djakov [Mon, 3 Aug 2015 13:30:30 +0000 (16:30 +0300)]
clk: qcom: Add support for SMD-RPM Clocks
This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_smd_rpm driver to communicate with RPM.
Such platforms are msm8916, apq8084 and msm8974.
The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.
This driver is based on the codeaurora.org driver:
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Stephen Boyd [Sat, 21 Mar 2015 06:45:30 +0000 (23:45 -0700)]
clk: qcom: Add Krait clock controller driver
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 21 Mar 2015 06:45:29 +0000 (23:45 -0700)]
clk: qcom: Add KPSS ACC/GCC driver
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 21 Mar 2015 06:45:28 +0000 (23:45 -0700)]
clk: qcom: Add support for Krait clocks
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 21 Mar 2015 06:45:25 +0000 (23:45 -0700)]
clk: qcom: Add HFPLL driver
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 21 Mar 2015 06:45:23 +0000 (23:45 -0700)]
clk: Add safe switch hook
Sometimes clocks can't accept their parent source turning off
while the source is reprogrammed to a different rate. Most
notably CPU clocks require a way to switch away from the current
PLL they're running on, reprogram that PLL to a new rate, and
then switch back to the PLL with the new rate once they're done.
Add a hook that drivers can implement allowing them to return a
'safe parent' and 'safe frequency' that they can switch their
parent to while the upstream source is reprogrammed to support
this.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Stephen Boyd [Sat, 21 Mar 2015 06:45:21 +0000 (23:45 -0700)]
clk: mux: Split out register accessors for reuse
We want to reuse the logic in clk-mux.c for other clock drivers
that don't use readl as register accessors. Fortunately, there
really isn't much to the mux code besides the table indirection
and quirk flags if you assume any bit shifting and masking has
been done already. Pull that logic out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 21 Mar 2015 06:45:22 +0000 (23:45 -0700)]
clk: Avoid sending high rates to downstream clocks during set_rate
If a clock is on and we call clk_set_rate() on it we may get into
a situation where the clock temporarily increases in rate
dramatically while we walk the tree and call .set_rate() ops. For
example, consider a case where a PLL feeds into a divider.
Initially the divider is set to divide by 1 and the PLL is
running fairly slow (100MHz). The downstream consumer of the
divider output can only handle rates =< 400 MHz, but the divider
can only choose between divisors of 1 and 4.
+-----+ +----------------+
| PLL |-->| div 1 or div 4 |---> consumer device
+-----+ +----------------+
To achieve a rate of 400MHz on the output of the divider, we
would have to set the rate of the PLL to 1.6 GHz and then divide
it by 4. The current code would set the PLL to 1.6GHz first while
the divider is still set to 1, thus causing the downstream
consumer of the clock to receive a few clock cycles of 1.6GHz
clock (far beyond it's maximum acceptable rate). We should be
changing the divider first before increasing the PLL rate to
avoid this problem.
Therefore, set the rate of any child clocks that are increasing
in rate from their current rate so that they can increase their
dividers if necessary. We assume that there isn't such a thing as
minimum rate requirements.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Conflicts:
drivers/clk/clk.c
Stephen Boyd [Sat, 21 Mar 2015 06:45:20 +0000 (23:45 -0700)]
ARM: Add Krait L2 register accessor functions
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.
Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Courtney Cavin <courtney.cavin@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Georgi Djakov [Thu, 19 Nov 2015 13:57:56 +0000 (15:57 +0200)]
clk: qcom: msm8916: Move xo and sleep clocks into DT
Move the xo and sleep clocks to device-tree, instead of hard-coding
them in the driver. This allows us to insert the RPM clocks (if they
are enabled) in between the on-board oscillators and the actual clock.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Tue, 27 Oct 2015 01:10:09 +0000 (18:10 -0700)]
clk: qcom: Move cxo/pxo/xo into dt files
Put these clocks into the dt files instead of registering them
from C code. This provides a few benefits. It allows us to
specify the frequency of these clocks at the board level instead
of hard-coding them in the driver. It allows us to insert an RPM
clock in between the consumers of the crystals and the actual
clock. And finally, it helps us transition the GCC driver to use
RPM clocks when that configuration is enabled.
Cc: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Tue, 27 Oct 2015 00:11:32 +0000 (17:11 -0700)]
clk: qcom: common: Add API to register board clocks backwards compatibly
We want to put the XO board clocks into the dt files, but we also
need to be backwards compatible with an older dtb. Add an API to
the common code to do this. This also makes a place for us to
handle the case when the RPM clock driver is enabled and we don't
want to register the fixed factor clock.
Cc: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Rajendra Nayak [Thu, 6 Aug 2015 10:37:54 +0000 (16:07 +0530)]
clk: qcom: gdsc: Manage clocks with !CONFIG_PM
With CONFIG_PM disabled, turn the devices clocks on during
driver binding to the device, and turn them off when the
driver is unbound from the device. Platforms can specify
all the clocks that need to be managed in !CONFIG_PM case
using qcom_pm_add_notifier().
The use of pm_clk_add_notifier() isn't appropriate here since we need
to only manage clocks with valid power domain associations done via
DT, instead of what pm_clk_add_notifier() does, which is manage clocks
for all on SoC/off SoC devices associating all of them to a dummy power
domain instead
Rajendra Nayak [Thu, 6 Aug 2015 10:37:53 +0000 (16:07 +0530)]
clk: qcom: gdsc: Enable an RCG before turing on the gdsc
Some gdsc instances require a certain root clock (RCG) to be turned on
*before* the power domain itself can be turned on. Handle this as part
of the gdsc enable/disable callbacks.
Rajendra Nayak [Thu, 6 Aug 2015 10:37:52 +0000 (16:07 +0530)]
clk: qcom: gdsc: Use PM clocks to control gdsc clocks
The devices within a gdsc power domain, quite often have additional
clocks to be turned on/off along with the power domain itself.
Once the drivers for these devices are converted to use runtime PM,
it would be possible to remove all clock handling from the drivers if
the gdsc driver can handle it.
Use PM clocks to add support for this. A list of clock ids specified
per gdsc would be the clocks turned on/off on every device start/stop
callbacks.
drm/i2c: adv7511: setup CEC registers during power off-power-on sequence
This patch sets up the CEC register during power up sequence, the reason
to do this because during power dowm the bridge can put audio pins in to
low power state.
Orignally the issue was detected on ubuntu image, where in after first
logout the audio was totally disabled.
Reported-by: Nicolas Dechesne <nicolas.dechesne@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
drm/i2c: adv7511: Create mipi_dsi_device for ADV7533
In order to pass DSI specific parameters to the DSI host, we need the
driver to create a mipi_dsi_device that attaches to the host.
Use of_graph helpers to get the DSI host DT node. Create a dummy dsi
device using this host. Finally, attach this device to the host.
Populate few other DT parameters (number of data lanes etc) that are
required for DSI RX to work correctly. Hardcode few other parameters
(rgb, embedded_sync) for now.
drm/i2c: adv7511: Add drm_bridge/connector for ADV7533
Create bridge and connector helper functions. These internally refer to
the ADV75xx helper functions.
The driver registers a drm_bridge object during probe. The bridge, in
turn registers a HDMI connector when a user attaches the bridge.
Therefore, when the device type is ADV7533, we create bridge and
connector entities, and when it's ADV7511, we create a slave encoder as
before.
Since the i2c driver is still wrapped around by the drm_i2c_slave_encoder
struct. We make sure the encoder_init op returns an error when the device
type is ADV7533.
ADV7511 is represented as an i2c drm slave encoder device. ADV7533, on
the other hand, is going be a normal i2c client device creating bridge
and connector entities.
Move the code in encoder slave functions to generate helpers that are
agnostic to the drm object type. These helpers will later also be used
by bridge and connecter helper functions.
ADV7533 is a DSI to HDMI encoder chip. It is a derivative of ADV7511,
with additional blocks to translate input DSI data to parallel RGB
data. Besides the ADV7511 i2c register map, it has additional registers
that require to be configured to activate the DSI blocks.
Use DT compatible strings to populate the adv7533 type enum. Add minimal
register configurations belonging to the DSI/CEC register map.
drm/i2c: adv7511: Fix mutex deadlock when interrupts are disabled
When the adv7511 i2c client doesn't have an interrupt line, we observe a
deadlock on caused by trying to lock drm device's mode_config.mutex twice
in the same context.
mipi_dsi_devices are inherently aware of their host because they
share a parent-child hierarchy in the device tree.
Non-dsi drivers that create a dummy dsi device don't have this data.
In order to get this information, they require to a phandle to the dsi
host in the device tree.
Maintain a list of all the hosts DSI that are currently registered.
This list will be used to find the mipi_dsi_host corresponding to the
device_node passed in of_find_mipi_dsi_host_by_node.
We can have devices where the data bus is MIPI DSI, but the control bus
is something else (i2c, spi etc). A typical example is i2c controlled
encoder bridge chips.
Such devices too require passing DSI specific parameters (number of data
lanes, DSI mode flags, color format etc) to their DSI host. For a device
that isn't 'mipi_dsi_device', there is no way of passing such parameters.
Provide the option of creating a dummy DSI device. The main purpose of
this would be to attach to a DSI host by calling mipi_dsi_attach, and
pass DSI params.
Create mipi_dsi_new_dummy for creating a dummy dsi device. The driver
calling this needs to be aware of the mipi_dsi_host it wants to attach
to, and also the DSI virtual channel the DSI device intends to use.
Archit Taneja [Wed, 19 Aug 2015 10:44:09 +0000 (16:14 +0530)]
drm/mipi_dsi: refactor device creation
Create a helper function mipi_dsi_device_new which takes in struct
mipi_dsi_device_info and the mipi_dsi_host. This will be called by
of_mipi_dsi_device_add.
Instead of calling device_initialize and device_add separately, merge
it into a single device_register call. This will remove the need of
having two separate funcs mipi_dsi_device_alloc and mipi_dsi_device_add.
The reason for creating mipi_dsi_device_new is that it can also be used
as a standalone way for creating a dsi device that isn't available via
DT.
arm64: dma-mapping: map sg lists into the SMMU as virtually contiguous
In arm_iommu_map_sg, currently we map each individual link in the given
scatterlist into the SMMU individually such that they may or may not be
virtually contiguous. However, in most (all?) of our use cases we
actually want the entire sg list mapped into the SMMU as a single
contiguous range. Use iommu_map_range to accomplish this.
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
[Forward Ported this from msm3.14] Signed-off-by: Sricharan R <sricharan@codeaurora.org>
[added iommu_map_range in generic dma code] Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Sricharan R [Tue, 21 Apr 2015 14:30:37 +0000 (20:00 +0530)]
arm64: mm: Fix a bug in iommu dma-mapping
iommu_alloc_attrs and arm_iommu_mmap_attrs calls
dma_pgprot with device type set to always 'coherent'
which is wrong. Should be based on the device type.
Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
On systems with IOMMUs, it's useful to handle IOMMU mappings in the
dma-mapping layer. This is currently supported on arm but not arm64. Add
support in arm64 by gratuitously lifting most of the IOMMU-related stuff
from dma-mapping.c in arm.
The original arm work was done by Marek Szyprowski in [4ce63fcd919c32:
"ARM: dma-mapping: add support for IOMMU mapper"].
Change-Id: I1c3c8fe15049fe456751074398fd179ebd2ec64e Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
[forward ported from 3.14 tree] Signed-off-by: R Sricharan <sricharan@codeaurora.org> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Laura Abbott [Wed, 6 Aug 2014 02:39:38 +0000 (19:39 -0700)]
arm: Add option to skip buffer zeroing
The DMA framework currently zeros all buffers because it (righfully so)
assumes that drivers will soon need to pass the memory to a device.
Some devices/use case may not require zeroed memory and there can
be an increase in performance if we skip the zeroing. Add a DMA_ATTR
to allow skipping of DMA zeroing.
Note: only the header file was modified to add the enum to allow the code to
compile, however the arm32 implementation was not pulled, and the arm64
implementation is missing as well
Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Nicolas Dechesne <nicolas.dechesne@linaro.org> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Abhimanyu Kapur [Tue, 18 Feb 2014 17:36:37 +0000 (09:36 -0800)]
arm64: smp: move the pen to a header file
Move the secondary_pen_release variable and the secondary_holding_pen
entry function to asm/smp_plat.h so that the other cpu ops implementations
can share them.
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Kumar Gala [Tue, 3 Mar 2015 21:39:07 +0000 (15:39 -0600)]
devicetree: bindings: Document qcom,msm-id and qcom,board-id
The top level qcom,msm-id and qcom,board-id are utilized by bootloaders
on Qualcomm MSM platforms to determine which device tree should be
utilized and passed to the kernel.
Cc: <devicetree@vger.kernel.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
projects / karo-tx-linux.git / log