ENGR00306875-2 video: mxc_hdmi: Set hdmi cable state a bit earilier
During hdmi hotplug test, there's a possibility that X-server unblanks
the frame buffer while HDMI-audio just gets the signal to start playback.
Then audio would get an unblanked state right before the playback and
bypassed the DMA enabling code. So this issue is caused by the race
between unblank and set_cable_state().
This patch sets the hdmi cable state a bit earilier so as to let audio
play first. If unblank happens later, the hdmi core and hdmi audio would
be robust enough to handle that case as long as it's not racing with the
other parts.
ENGR00306875-1 Revert "ENGR00305624-2 ASoC: imx-hdmi-dma: Correct the appl pointer"
After change the pointer, ALSA lib would re-copy the initial data to
DMA buffer because the pointer is pointing the zero position at the
beginning, which results an audiable duplicated playback at the first
eight periods.
Even though dropping this patch would cause pointer being incorrectly
estimated. But to maintain the sanity of basic playback, we revert
the previous patch.
Dan Douglass [Wed, 2 Apr 2014 19:01:26 +0000 (14:01 -0500)]
ENGR00298286 arm: dts: imx6qdl: add clock to CAAM.
CAAM depends on the clock used by WEIM interface. This patch supplied by
Haung Shijie corrects the issue by adding the clock as a resource for
the CAAM driver.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
Dan Douglass [Wed, 2 Apr 2014 19:00:08 +0000 (14:00 -0500)]
ENGR00298286 arm: dts: imx6qdl: add clock to CAAM.
CAAM depends on the clock used by WEIM interface. This patch supplied by
Haung Shijie corrects the issue by adding the clock to the device tree
entry for CAAM.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
Ming Lei [Mon, 11 Mar 2013 12:52:12 +0000 (13:52 +0100)]
ARM: 7669/1: keep __my_cpu_offset consistent with generic one
Commit 14318efb(ARM: 7587/1: implement optimized percpu variable access)
introduces arm's __my_cpu_offset to optimize percpu vaiable access,
which really works well on hackbench, but will cause __my_cpu_offset
to return garbage value before it is initialized in cpu_init() called
by setup_arch, so accessing percpu variable before setup_arch may cause
kernel hang. But generic __my_cpu_offset always returns zero before
percpu area is brought up, and won't hang kernel.
So the patch tries to clear __my_cpu_offset on boot CPU early
to avoid boot hang.
At least now percpu variable is accessed by lockdep before
setup_arch(), and enabling CONFIG_LOCK_STAT or CONFIG_DEBUG_LOCKDEP
can trigger kernel hang.
Signed-off-by: Ming Lei <tom.leiming@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 9394c1c65e61eb6f4c1c99f342b49e451ec337b6)
The res variable is written before we've finished with the input
operands (namely the lock address), so ensure that we mark it as `early
clobber' to avoid unintended register sharing.
Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Wang Weidong <wangweidong1@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Commit 15e7e5c1ebf5 ("ARM: 7749/1: spinlock: retry trylock operation if
strex fails on free lock") modifying our arch_spin_trylock to retry the
acquisition if the lock appeared uncontended, but the strex failed.
This patch does the same for rwlocks, which were missed by the original
patch.
Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Li Zefan <lizefan@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
An exclusive store instruction may fail for reasons other than lock
contention (e.g. a cache eviction during the critical section) so, in
line with other architectures using similar exclusive instructions
(alpha, mips, powerpc), retry the trylock operation if the lock appears
to be free but the strex reported failure.
Reported-by: Tony Thompson <anthony.thompson@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Li Zefan <lizefan@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
During __v{6,7}_setup, we invalidate the TLBs since we are about to
enable the MMU on return to head.S. Unfortunately, without a subsequent
dsb instruction, the invalidation is not guaranteed to have completed by
the time we write to the sctlr, potentially exposing us to junk/stale
translations cached in the TLB.
This patch reworks the init functions so that the dsb used to ensure
completion of cache/predictor maintenance is also used to ensure
completion of the TLB invalidation.
Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ENGR00306309 ARM:imx:imx6qdl: Fix procedure to switch the parent of LDB_DI_CLK
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.
Richard Liu [Tue, 1 Apr 2014 01:58:49 +0000 (09:58 +0800)]
ENGR00306257 [#1027]fix system hang up issue caused by GPU
This issue happens when multiple thread is trying to idle GPU at the
same time, root cause is some wrong logic related with powerMutex which
cause cpu still access GPU AHB register after GPU is suspend(clock off),
that cause the bus lockup and make the whole system hang.
Nicolin Chen [Tue, 25 Mar 2014 03:46:35 +0000 (11:46 +0800)]
ENGR00305624-2 ASoC: imx-hdmi-dma: Correct the appl pointer
We might not be able to get appl_ptr, so we estimated it by using hw_ptr,
while the distance between then should not be 2 * priv->period_bytes
initially but 8 * priv->period_bytes as we pri-filled one entire buffer
size at the beginning. The driver's memory access might be overlapped
with ALSA's buffer updating. So this patch fixes this inaccurate distance.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Nicolin Chen [Thu, 6 Mar 2014 11:04:30 +0000 (19:04 +0800)]
ENGR00305624-1 ASoC: imx-hdmi-dma: Use neon data copy function
Use neon data copy function as default to improve data copy performance so that
we can prevent some noise issue happening to HDMI audio due to the performance
issue.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
-Updated the outstanding request limit to 12.
-Refined the 2D chip feature check.
-Refine the 2D cache flush operation
(avoid FE and PE access memory through the same port).
-Enable cache flush for filterblt.
-Dynamic enabling SPLIT_RECT by checking chip feature(disable for us)
-Use brush stretch blt for clear operation.
Nicolin Chen [Fri, 21 Mar 2014 09:30:44 +0000 (17:30 +0800)]
ENGR00304914-1 ASoC: imx-hdmi-dma: Limit period size for 6DQ
The HDMI IP in i.MX6DQ has a bug that it limits the dma period size within 8K.
Patch 'ENGR00300188-1 ASoC: imx-hdmi-dma: Double the buffer and period sizes'
doubled the period size which works great with Dual Lite but broke the HDMI
audio function on DQ. Thus fix it for 6DQ case.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Liu Ying [Mon, 17 Mar 2014 03:28:53 +0000 (11:28 +0800)]
ENGR00303663 mxc v4l2 capture: Don't return error if we cannot get mipi csi2
The mipi csi2 code is ugly present in the capture pipeline setup/disable
routions with '#ifdef CONFIG_MXC_MIPI_CSI2/#endif' protected. Whenever
it finds mipi_csi2_info is not gotten correctly, it will return error to
callers. This breaks the normally routines in which mipi csi2 is not used
and mipi csi2 driver is disabled in its devicetree node(but with the
Kconfig CONFIG_MXC_MIPI_CSI2 defined). A real example is the capture
feature on the MX6 Sabreauto platforms. We have only parallel CSI input
on it and the mipi csi2 driver is disabled in its devicetree node but with
the Kconfig CONFIG_MXC_MIPI_CSI2 defined. So, a reasonable choice at present
is not to return error if mipi_csi2_info cannot be gotten, though we could
eventually re-organize the capture code for a better total solution in the
future.
Sandor Yu [Thu, 13 Mar 2014 09:44:41 +0000 (17:44 +0800)]
ENGR00303308 hdmi:update default video mode setting required by xserver
xserver will read default video mode in command line by sysfs node
/sys/class/graphics/fb0/mode, but the sysfs node is not initialized
when system bootup without hdmi cable plugin
or frame buffer register in blank state.
Fixed:
- Remove unused previous_mode
- Add default_mode, initialize in disp_init function.
- Initialize fbi->mode in disp_init function and hdmi_setup function.
commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57 added a hard
coding for csi_parma.mclk setting to 27MHz. The comment added by
that commit is totally wrong by telling that csi_param.mclk
would be a kind of 'pixel clock' set in 'csi_data_dest' register.
This patch removes the unnecessary mclk setting for csi_param.mclk
variable, since it is only valid for CSI test mode.
Liu Ying [Fri, 8 Mar 2013 08:33:35 +0000 (16:33 +0800)]
ENGR00243315-2 IPUv3 CSI:Remove test mode clock setting
This patch removes test mode clock setting in function
ipu_csi_init_interface(), since the setting is only
necessary for function _ipu_csi_set_test_generator().
This unnecessary setting is added wrongly by commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57.
As the sabreauto CPU board schematics mentions, the MIPI connector
isn't mechanically compatible with Freescale MIPI display and camera
board, then we have no way to support MIPI features currently on
this platform. So, let's disable MIPI CSI.
As the sabreauto CPU board schematics mentions, the MIPI connector
isn't mechanically compatible with Freescale MIPI display and camera
board, then we have only the parallel CSI video input that is supported
by the v4l2_cap_0 node. So, let's remove the orphan one - v4l2_cap_1.
Root cause analysis:
It only happens when HDMI is not used/enabled. There is a clock named
video_27m which are needed by HDMI (as isfrclk's parent) and MIPI-CSI2 (as
cfg_clk's parent). MIPI-CSI2 driver is lack of enabling this clock before
start to work and only happen to work when HDMI driver enables this clock.
Shengjiu Wang [Fri, 7 Mar 2014 09:32:41 +0000 (17:32 +0800)]
ENGR00302531 Noise come out after change the HDMI resolution when video pause
After change the resolution, the blank state will be changed, the audio will
be triggered to start. which didn't care about the audio is running or not
before changing the resolution.
Add hdmi_abort_state for this special case.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
Nicolin Chen [Thu, 6 Mar 2014 11:14:29 +0000 (19:14 +0800)]
ENGR00300188-2 ASoC: imx-hdmi-dma: Clear offset in the trigger init
The offset reflects the current position of DMA access in the ALSA ring buffer.
So we should clear it before re-start DMA engine becasue the DMA access should
re-start its job from the 0 position. If we don't do this, the driver might get
a wrong idea about current position of DMA access. Thus fix it.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 8f265543ffda0a19e3f469967a7d61d8b344f080)
Nicolin Chen [Fri, 7 Mar 2014 11:59:04 +0000 (19:59 +0800)]
ENGR00300188-1 ASoC: imx-hdmi-dma: Double the buffer and period sizes
We found HDMI Audio has a performance issue when playback 8 channels 192KHz
files, CPU might lag its interrupt responsing while SDMA continues updating
HDMI internal AHB DMA's address and restarting AHB DMA, which resulted the
noise when AHB DMA access overlaps with the data copy procedures in this
driver.
Thus we here double the buffer size and period size of HDMI Audio to chop
the CPU interrupt to its half in the same span of time so that we can keep
the data copy procedures safe and provent it from overlapping access with
AHB DMA.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 04af1a351e016f52276ae002fd9f64b6b2962168)
ENGR00299939-3 USB: imx6x: Add dummy LDO2p5 regulator for VBUS wakeup
LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
ENGR00299939-2 ARM: imx6sl: Add dummy LDO2p5 regulator to support VBUS wakeup
LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
This patch ensures that the low power idle code checks the status of the
dummy ldo2p5 regulator before disabling LDO2p5.
ENGR00299939-1 ARM: dts: imx6sl:Add dummy LDO2p5 regulator to support vbus wakeup
LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
This patch adds the dummy regulator to the dts files.
Loren Huang [Thu, 27 Feb 2014 07:44:49 +0000 (15:44 +0800)]
ENGR00301095 gpu:gpu hang when dma memory is used up
When dma zone memory used up, gckOS_AllocateNonPagedMemory() will try to
free non paged memory cache and allocate again. Such operation will cause
twice memory mutex request and cause gpu driver hang.
The solution is free the memory mutex at first before trying to free non
paged memory cache.
Dan Douglass [Thu, 20 Feb 2014 17:25:56 +0000 (11:25 -0600)]
ENGR00292341 imx6sl hwrng
Add hwrng support for i.MX6SL.
1. Add RNG driver. This driver originated as fsl-rngc.c. It
has been modified to support device tree. The name has been
changed since it supports both b and c variants of RNG.
2. Added clock and compatible info to the device tree data.
3. Added the entry in the options in the Kconfig for hwrng.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
Oliver Brown [Wed, 19 Feb 2014 23:32:48 +0000 (17:32 -0600)]
ENGR00290659 IPUv3: Fix a flashing vert. line when downsizing 1080i to 300x400.
When split mode deinterlacing is the ipu_calc_stripes_sizes() was failing due
to an unnecessary test. Added logic to use the maximal_stripe_width only if
the flag parameter has the bit 0 clear for not equal stripe sizes.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
Sandor Yu [Wed, 19 Feb 2014 08:40:49 +0000 (16:40 +0800)]
ENGR00299600 hdmi:yocto gui can not show to some TV on ard board
For i.MX6 ARD board, the board not support read EDID from TV,
so HDMI driver will create a default support mode list when system
bootup.
Because yocto xserver can not get video mode information from
framebuffer now, and xserver will set default video mode XGA
to framebuffer, but XGA mode is not support by hdmi.
Remove XGA and SXGA from default support list.
HDMI driver will find a nearest match video mode in support list.
It is VGA mode. HDMI support VGA mode well.
Issue is fixed.
Nicolin Chen [Tue, 18 Feb 2014 12:54:25 +0000 (20:54 +0800)]
ENGR00299756-3 ARM: imx6q: Add the clock route from external OSC to ESAI clock
This patch mainly adds the clock route from external 24.576MHz OSC to internal
ESAI clock via analog clock2 PADs on the SoC and pll4 so that ESAI can get an
entirely synchronous clock source against CS42888.
[ 1, We found if using pll4 to generate a 24.576MHz from inernal 24.0MHz OSC,
we would get noise during the audio playback via ESAI->CS42888 even though
this generated clock's rate is equal to the external one statistically. It
might be resulted from the tiny difference between two clock source, which
might be crucial to the sensitive CODEC we use -- CS42888. So we here apply
the old 3.0.35 way to feed ESAI the same clock source as CS42888.
2, Ideally, we should use bypass mode for pll4 since we only need to get
the raw rate (24.576MHz) while currently bypass mode in clk-pllv3.c isn't
entirely supported: The clock rate would be fixed to 24.0MHz if setting to
bypass, which would cause child clock get an incorrect rate and the driver
who uses the child clock fail to derive a needed clock rate, and it might
be dangerous to involve the clk-pllv3.c driver to this fix. Thus we here
apply 3.0.35 way provisionally. ]
Nicolin Chen [Tue, 18 Feb 2014 12:27:06 +0000 (20:27 +0800)]
ENGR00299756-2 ARM: imx6q: Add missing lvds2 clock to the clock tree
We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.
So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.
[ To reduce the risk from code changing. This patch only takes care of pll4
related part. We might later need to add the relationship with pll5 too. ]
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 5b74b6b26e4b44d265090fc6ad15b15ccb7b5cff)
Nicolin Chen [Tue, 18 Feb 2014 10:40:33 +0000 (18:40 +0800)]
ENGR00299756-1 ASoC: fsl_esai: Add missing clock enabler to ASoC interfaces
All of these functions might be called before we enable the core clock in the
startup() by set_bias_level() or late_probe() in machine driver for example.
To make it safe, we here add pair of clock en/disabling to each function.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit e6df36df2bc8062f3d1c0a19d18acc843a77619d)
Liu Ying [Tue, 18 Feb 2014 04:49:32 +0000 (12:49 +0800)]
ENGR00298052-7 ARM: imx6q: remove function imx6q_lvds_cabc_init()
This patch removes the function imx6q_lvds_cabc_init() from the
machine layer since we have a dedicated Hannstar CABC driver to
control the CABC feature.
Liu Ying [Tue, 18 Feb 2014 04:44:35 +0000 (12:44 +0800)]
ENGR00298052-5 ARM: dts: imx6qdl-sabresd: support Hannstar CABC
This patch adds a device tree node for the Hannstar CABC function.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.
Liu Ying [Tue, 18 Feb 2014 02:59:09 +0000 (10:59 +0800)]
ENGR00298052-4 ARM: dts: imx6qdl-sabreauto: support Hannstar CABC
This patch adds a device tree node for the Hannstar CABC function.
The LVDS0 and LVDS1 interfaces of the i.MX6dql Sabreauto platform
shares a control pin for the CABC function, but LVDS1's control
wire is invalid for the unpopulated resistor R265 on the main board.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.
This patch adds Hannstar CABC driver support. The CABC
function turns the backlight density of a display panel
automatically according to the content shown on the panel.
It is controlled(enabled/disabled) by a GPIO.
ENGR00297285-1 [MX6x] Support IRAM page table when DDR is in self-refresh.
Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.
The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.
This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the IRAM page table.
We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1
Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible.
Richard Zhu [Mon, 10 Feb 2014 06:56:46 +0000 (14:56 +0800)]
ENGR00298392 pcie: imx pcie ep rc msi demo
- add one imx pcie ep simple skeleton driver to demo
the msi trigger capability in imx6 pcie rc/ep validation
system
- in order to avoid the modification of common codes,
force the msi address to be 0x01ff8000
Test howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images
- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000
root@sabresd_6dq:/ #
Richard Zhu [Mon, 10 Feb 2014 04:34:33 +0000 (12:34 +0800)]
ENGR00298389 pcie: let rc can access mem of ep
- setup one new outbound memory region at rc side, used
to let imx6 pcie rc can access the memory of imx6 pcie ep
in imx6 pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000
NOTE:
- default address 0x4000_0000 of ep side would be
accessed in this demo.
Test howto:
step1:
EP side:
1.1:
echo 0x40000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/ep_bar0_addr
1.2:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000
Peter Chen [Fri, 24 Jan 2014 06:59:30 +0000 (14:59 +0800)]
ENGR00296519 USB: EHCI: wait more than 3ms until the device enters full-speed idle
If the high-speed device does not enter full-speed idle after
wakeup on disconnect logic has effected, there will be an
unexpected disconnect wakeup interrupt due to the bus is still SE0.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Yuanyuan Zhong [Wed, 30 Oct 2013 16:31:49 +0000 (17:31 +0100)]
ARM: 7873/1: vfp: clear vfp_current_hw_state for dying cpu
The CPU_DYING notifier is called by cpu stopper task which
does not own the context held in the VFP hardware. Calling
vfp_force_reload() has no effect.
Replace it with clearing vfp_current_hw_state.
Signed-off-by: Yuanyuan Zhong <zyy@motorola.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 384b38b66947b06999b3e39a596d4f2fb94f77e4)
Huang Shijie [Fri, 24 Jan 2014 07:49:26 +0000 (15:49 +0800)]
ENGR00296510 ARM: dts: imx6qdl-sabreauto: use the gpio5_4 to enable the EIM_D18
The WEIN NOR needs the pin EIM_D18 which is controlled by the steering.
So we have to configurate the EIM_A24 to GPIO, and select the GPIO to LOW
status.
Richard Zhu [Fri, 10 Jan 2014 07:54:26 +0000 (15:54 +0800)]
ENGR00284938 sata: cr-rst workaround sata phy link issues
- add sata phy cr(offset:0x7f3f) reset in sata resume to
workaround imx6q sata kinds of suspend resume link
issues.
- add sata phy cr reset during imx6q sata initialization,
to initialize the sata phy to be an initialized state.
- add about 100us delay between mpll_clk enable and cr-rst,
make sure that the mpll_clk is stable.
- add about 100us delay between cr-rst and waiting for rx_pll
stable too, make sure that the cr-rst is finished.
- change the tx level setting from 1.025v to be the default
value 1.104v
- make sure the sata phy internal pll ref clk enable is
cleared before it is set, otherwise, the sata phy link
maybe failed when some devices are used.
Sandor Yu [Wed, 22 Jan 2014 07:09:37 +0000 (15:09 +0800)]
ENGR00296050 mxsfb: fb failed to work after suspend in console mode
When device boot into console, frame buffer failed to work after
suspend/resume.
That is caused by LCDIF IP lost all registers configuration
in suspend mode, and console didn't reconfiguration fb after resume.
Same issue didn't found with Yocto UI.
Reinitialize frame buffer driver after resume to fix the issue.
Sandor Yu [Wed, 15 Jan 2014 08:50:04 +0000 (16:50 +0800)]
ENGR00295201 ipuv3: vdic: kernel dump when run deinterlace stress test
Kernel will dump when run deinterlace stress test.
It is caused by vditmpbuf being reallocated by another thread
when one thread accesses it.
Issue is fixed by putting these code in mutex.
Sandor Yu [Fri, 27 Dec 2013 09:10:03 +0000 (17:10 +0800)]
ENGR00293488 ipu: vdi: Support more memory type
__va function only can handle frame buffer from low memory.
Use page_address function to replace it, that can handle
frame buffer from both lower and high memory.
Use ioremap_nocache function to handle Frame buffer
from GPU reserve memory pool.
Correct vdi data save buffer size, save both luma and chroma part for
interleaved YUV format.
For non-interleaved and partial-interleaved YUV format,
save luma part data, chroma part is not covered in the patch.
Robin Gong [Tue, 21 Jan 2014 02:41:46 +0000 (10:41 +0800)]
ENGR00295892-1: leds: leds-gpio: keep charger led state while system suspended
gpio-leds driver common framework didn't take care of this case if use CONFIG_OF
, add property "retain-state-suspended" in dts and check it while gpio-leds
device created.
Jay Monkman [Fri, 17 Jan 2014 19:06:46 +0000 (13:06 -0600)]
ENGR00291086 crypto kernel module speed test in single fail
The tcrypt module is used to test the crypto API by being passed a
mode=<value> during module load. The test runs to completion before
insmod/modprobe returns. That makes the RCU stall detection in newer
kernels unhappy.
The simple fix is to add CONFIG_PREEMPT to the kernel config. That's
what this patch does. If that introduces other problems,
crypto/tcrypt.c can be modified to call schedule() in the correct
places. Here's a patch that should work if this one has to be
reverted:
Dong Aisheng [Fri, 17 Jan 2014 02:23:22 +0000 (10:23 +0800)]
ENGR00295564 mmc: sdhci-esdhc-imx: no need busfreq for imx6qdl
The usdhc of i.MX6Q/DL can work well under low power mode without
request high bus freq. So we do not need request bus freq for i.MX6Q/DL.
It can save power for i.MX6D/DL due to it saves a lot busfreq switch
cost as well as the CPU time runing on high bus freq after switch
during low power mode.
A new flag ESDHC_FLAG_BUSFREQ is added to indicated this requirement.
Currently only i.MX6SL is using it.
The root cause of playback slow issue should be trying to get DSPCLK_DIV
before enabling SYSCLK of WM8962. Since we have a patch fixed it, we can
revert this work round.
This reverts commit 49a3ca545a88cdf4aa597c4dd7d904b4faaea555.
Nicolin Chen [Mon, 6 Jan 2014 09:25:09 +0000 (17:25 +0800)]
ENGR00295423-4 ASoC: fsl_ssi: Set the default slot number in startup()
Set a default slot number in startup() so that those who use I2S or other
2-channel DAI format would not need to call set_dai_tdm_slot() in their
machine drivers.
Nicolin Chen [Mon, 6 Jan 2014 08:55:07 +0000 (16:55 +0800)]
ENGR00295423-3 ASoC: fsl_ssi: Don't disable SSIEN if SSI is already enabled
If disabling SSI when SSI is already in the working state, the whole running
substream would be broken. Thus we here replace it to a safer way -- saving
the current SSIEN value and restore it afterward.
This patch also adds a slot number checking code before setting slot number.
Nicolin Chen [Mon, 6 Jan 2014 08:28:51 +0000 (16:28 +0800)]
ENGR00295423-1 ASoC: fsl_ssi: Implement full symmetry for synchronous mode
Since we introduced symmetric_channels and symmetric_samplebits, we can
implement these new feature to SSI synchronous mode and drop the useless
code accordingly.
Nicolin Chen [Wed, 4 Dec 2013 09:22:16 +0000 (17:22 +0800)]
ASoC: wm8962: Enable SYSCLK provisonally before fetching generated DSPCLK_DIV
DSPCLK_DIV can be only generated correctly after enabling SYSCLK. But if the
current bias_level hasn't reached SND_SOC_BIAS_ON, DAPM won't enable SYSCLK,
which would cause the calculation result from DSPCLK_DIV invalid since bit
DSPCLK_DIV will be finally turned to its true value after DAPM enables SYSCLK
while the driver won't calculate it again for the current instance. In this
circumstance, a playback which needs non-zero DSPCLK_DIV would be distorted
due to unexpected clock frequency resulted from an invalid DSPCLK_DIV value.
So this patch provisionally enables the SYSCLK to get a valid DSPCLK_DIV for
calculation and then disables it afterward.
Nicolin Chen [Wed, 20 Nov 2013 10:37:09 +0000 (18:37 +0800)]
ASoC: soc-pcm: move DAIs parameters cleaning into hw_free()
We're now applying soc_hw_params_symmetry() to reject unmatched parameters
while we clear parameters in soc_pcm_close(). So here's a use case might be
broken by this mechanism: aplay -Dhw:0 44100.wav 48000.wav 32000.wav
In this case, we call soc_pcm_open()->soc_pcm_hw_params()->soc_pcm_hw_free()
->soc_pcm_hw_params()->soc_pcm_hw_free()->soc_pcm_close() in order. As we
only clear parameters in soc_pcm_close(). The parameters would be remained
in the system even if the playback of 44100.wav is finished.
Thus, this patch is trying to move parameters cleaning into hw_free() so that
the system can continue to serve this kind of use case.
Also, since we set them in hw_params(), it should be better to clear them in
hw_free() for symmetry.
Nicolin Chen [Wed, 13 Nov 2013 10:56:24 +0000 (18:56 +0800)]
ASoC: soc-pcm: add symmetry for channels and sample bits
Some SoCs can only work in mono or stereo mode at one time. So if
we let them capture a mono stream while playing a stereo stream,
there might be a problem occur to one of these two streams: double
paced or slowed down.
In soc-pcm.c, we have soc_pcm_apply_symmetry() to apply the rate
symmetry. But we don't have one for channels.
Likewise, we can treat symmetric_rate as a solution for those SoCs
or CODECs which can not handle asymmetrical LRCLK. But it's also
impossible for them to handle asymmetrical BCLK. And accodring to
BCLK = LRCLK * channel number * slot size(fixed or sample bits),
sample bits might also be a problem if they are not using a fixed
slot size.
Thus, this patch applys symmetry for channels and sample bits.
Meanwhile, there might be a race between two substreams if starting
simultaneously. Previously, we only added warning to compalin but
still using conservative way to let it carry on. However, this patch
rejects the second stream with any unmatched parameter to make sure
the first existing stream won't be broken.
projects / karo-tx-linux.git / log