From 5d4754a6369ee09242b17ce47d2c56f4ccb107d2 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 10 Nov 2015 19:58:45 +0100 Subject: [PATCH] ARM: dts: tx6ul: adjust pixel clock polarity --- arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index 6753342fc460..37bdc964870c 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -742,7 +742,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <0>; + pixelclk-active = <1>; }; ETV570 { @@ -758,7 +758,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <0>; + pixelclk-active = <1>; }; ET0350 { @@ -774,7 +774,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <0>; + pixelclk-active = <1>; }; ET0430 { @@ -790,7 +790,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <1>; + pixelclk-active = <0>; }; ET0500 { @@ -806,7 +806,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <0>; + pixelclk-active = <1>; }; ET0700 { /* same as ET0500 */ @@ -822,7 +822,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <0>; + pixelclk-active = <1>; }; ETQ570 { @@ -838,7 +838,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <0>; + pixelclk-active = <1>; }; }; }; -- 2.39.2