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85 NAME="HAL-DEFAULT-INTERRUPT-HANDLING">Default Interrupt Handling</H1
87 >Most asynchronous external interrupt vectors will point to a default
88 interrupt VSR which decodes the actual interrupt being delivered from
89 the interrupt controller and invokes the appropriate ISR.</P
91 >The default interrupt VSR has a number of responsibilities if it is
92 going to interact with the Kernel cleanly and allow interrupts to
93 cause thread preemption.</P
95 >To support this VSR an ISR vector table is needed. For each valid
96 vector three pointers need to be stored: the ISR, its data pointer and
97 an opaque (to the HAL) interrupt object pointer needed by the
98 kernel. It is implementation defined whether these are stored in a
99 single table of triples, or in three separate tables.</P
101 >The VSR follows the following approximate plan:</P
108 > Save the CPU state. In non-debug configurations, it may be
109 possible to get away with saving less than the entire machine
113 >CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT</TT
115 is supported in some targets to do this.
120 > Increment the kernel scheduler lock. This is a static member of
121 the Cyg_Scheduler class, however it has also been aliased to
124 >cyg_scheduler_sched_lock</TT
126 accessed from assembly code.
131 > (Optional) Switch to an interrupt stack if not already running on
132 it. This allows nested interrupts to be delivered without needing
133 every thread to have a stack large enough to take the maximum
134 possible nesting. It is implementation defined how to detect
135 whether this is a nested interrupt but there are two basic
136 techniques. The first is to inspect the stack pointer and switch
137 only if it is not currently within the interrupt stack range; the
138 second is to maintain a counter of the interrupt nesting level and
139 switch only if it is zero. The option
142 >CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK</TT
144 controls whether this happens.
149 > Decode the actual external interrupt being delivered from
150 the interrupt controller. This will yield the ISR vector
151 number. The code to do this usually needs to come from the
152 variant or platform HAL, so is usually present in the form of a
153 macro or procedure callout.
158 > (Optional) Re-enable interrupts to permit nesting. At this point
159 we can potentially allow higher priority interrupts to occur. It
160 depends on the interrupt architecture of the CPU and platform
161 whether more interrupts will occur at this point, or whether they
162 will only be delivered after the current interrupt has been
163 acknowledged (by a call to
166 >HAL_INTERRUPT_ACKNOWLEDGE()</TT
172 > Using the ISR vector number as an index, retrieve the
173 ISR pointer and its data pointer from the ISR vector table.
178 > Construct a C call stack frame. This may involve making stack
179 space for call frames, and arguments, and initializing the back
180 pointers to halt a GDB backtrace operation.
185 > Call the ISR, passing the vector number and data pointer. The
186 vector number and a pointer to the saved state should be preserved
187 across this call, preferably by storing them in registers that are
188 defined to be callee-saved by the calling conventions.
193 > If this is an un-nested interrupt and a separate interrupt
194 stack is being used, switch back to the interrupted thread's
200 > Use the saved ISR vector number to get the interrupt object
201 pointer from the ISR vector table.
209 > passing it the return
210 value from the ISR, the interrupt object pointer and a pointer to
211 the saved CPU state. This function is implemented by the Kernel
212 and is responsible for finishing off the interrupt
213 handling. Specifically, it may post a DSR depending on the ISR
214 return value, and will decrement the scheduler lock. If the lock
215 is zeroed by this operation then any posted DSRs may be called and
216 may in turn result in a thread context switch.
221 > The return from <TT
225 some time after the call. Many other threads may have executed in
226 the meantime. So here all we may do is restore the machine state
227 and resume execution of the interrupted thread. Depending on the
228 architecture, it may be necessary to disable interrupts again for
234 >The detailed order of these steps may vary slightly depending on the
235 architecture, in particular where interrupts are enabled and disabled.</P
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