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12 >Variant HAL Porting</TITLE
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22 TITLE=" Porting Guide"
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49 >eCos Reference Manual</TH
57 HREF="hal-porting-platform.html"
65 >Chapter 11. Porting Guide</TD
71 HREF="hal-porting-architecture.html"
85 NAME="HAL-PORTING-VARIANT">Variant HAL Porting</H1
87 >A variant port can be a fairly limited job, but can also
88 require quite a lot of work. A variant HAL describes how a specific
89 CPU variant differs from the generic CPU architecture. The variant HAL
90 can re-define cache, MMU, interrupt, and other features which override
91 the default implementation provided by the architecture HAL.</P
93 >Doing a variant port requires a preexisting architecture HAL port. It
94 is also likely that a platform port will have to be done at the same
95 time if it is to be tested.</P
101 NAME="AEN9745">HAL Variant Porting Process</H2
103 >The easiest way to make a new variant HAL is simply to copy an
104 existing variant HAL and change all the files to match the new
105 variant. If this is the first variant for an architecture, it may be
106 hard to decide which parts should be put in the variant - knowledge of
107 other variants of the architecture is required.</P
109 >Looking at existing variant HALs (e.g., MIPS tx39, tx49) may be a
110 help - usually things such as caching, interrupt and exception
111 handling differ between variants. Initialization code, and code for
112 handling various core components (FPU, DSP, MMU, etc.) may also differ
113 or be missing altogether on some variants. Linker scripts may also require
114 specific variant versions.</P
122 >Some CPU variants may require specific compiler
123 support. That support must be in place before you can undertake the
124 eCos variant port.</P
133 NAME="AEN9752">HAL Variant CDL</H2
135 >The CDL in a variant HAL tends to depend on the exact functionality
136 supported by the variant. If it implements some of the devices
137 described in the platform HAL, then the CDL for those will be here
138 rather than there (for example the real-time clock).</P
140 >There may also be CDL to select options in the architecture HAL to
141 configure it to a particular architectural variant.</P
143 >Each variant needs an entry in the <TT
147 file. This is the one for the SH3:</P
155 CLASS="PROGRAMLISTING"
156 >package CYGPKG_HAL_SH_SH3 {
157 alias { "SH3 architecture" hal_sh_sh3 }
159 script hal_sh_sh3.cdl
162 The SH3 (SuperH 3) variant HAL package provides generic
163 support for SH3 variant CPUs."
169 >As you can see, it is very similar to the platform entry.</P
171 >The variant CDL file will contain a package entry named for the
172 architecture and variant, matching the package name in the
176 > file. Here is the initial part of the
177 MIPS VR4300 CDL file:</P
185 CLASS="PROGRAMLISTING"
186 >cdl_package CYGPKG_HAL_MIPS_VR4300 {
187 display "VR4300 variant"
188 parent CYGPKG_HAL_MIPS
189 implements CYGINT_HAL_MIPS_VARIANT
192 define_header hal_mips_vr4300.h
194 The VR4300 variant HAL package provides generic support
195 for this processor architecture. It is also necessary to
196 select a specific target platform HAL package."</PRE
201 >This defines the package, placing it under the MIPS architecture
202 package in the hierarchy. The <TT
206 indicates that this is a MIPS variant. The architecture package uses
207 this to check that exactly one variant is configured in.</P
209 >The variant defines some options that cause the architecture HAL to
210 configure itself to support this variant.</P
218 CLASS="PROGRAMLISTING"
219 > cdl_option CYGHWR_HAL_MIPS_64BIT {
220 display "Variant 64 bit architecture support"
224 cdl_option CYGHWR_HAL_MIPS_FPU {
225 display "Variant FPU support"
229 cdl_option CYGHWR_HAL_MIPS_FPU_64BIT {
230 display "Variant 64 bit FPU support"
237 >These tell the architecture that this is a 64 bit MIPS architecture,
238 that it has a floating point unit, and that we are going to use it in
239 64 bit mode rather than 32 bit mode.</P
241 >The CDL file finishes off with some build options.</P
249 CLASS="PROGRAMLISTING"
251 puts $::cdl_header "#include <pkgconf/hal_mips.h>"
257 <PREFIX>/lib/target.ld: <PACKAGE>/src/mips_vr4300.ld
258 $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
259 @echo $@ ": \\" > $(notdir $@).deps
260 @tail +2 target.tmp >> $(notdir $@).deps
261 @echo >> $(notdir $@).deps
265 cdl_option CYGBLD_LINKER_SCRIPT {
266 display "Linker script"
269 calculated { "src/mips_vr4300.ld" }
280 > causes the architecture
281 configuration file to be included into the configuration file for the
285 > causes the single source file
286 for this variant, <TT
289 > to be compiled. The
293 > command emits makefile rules to combine the
294 linker script with the <TT
301 >. Finally, in the MIPS HALs, the main
302 linker script is defined in the variant, rather than the architecture,
305 >CYGBLD_LINKER_SCRIPT</TT
306 > is defined here.</P
313 NAME="AEN9778">Cache Support</H2
315 >The main area where the variant is likely to be involved is in cache
316 support. Often the only thing that distinguishes one CPU variant from
317 another is the size of its caches.</P
319 >In architectures such as the MIPS and PowerPC where cache instructions
320 are part of the ISA, most of the actual cache operations are
321 implemented in the architecture HAL. In this case the variant HAL only
322 needs to define the cache dimensions. The following are the cache
323 dimensions defined in the MIPS VR4300 variant
335 CLASS="PROGRAMLISTING"
337 #define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
338 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
339 #define HAL_DCACHE_WAYS 1 // Associativity of the cache
342 #define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
343 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
344 #define HAL_ICACHE_WAYS 1 // Associativity of the cache
346 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
347 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))</PRE
352 >Additional cache macros, or overrides for the defaults, may also
353 appear in here. While some architectures have instructions for
354 managing cache lines, overall enable/disable operations may be handled
355 via variant specific registers. If so then
359 > should also define the
362 >HAL_XCACHE_ENABLE()</TT
366 >HAL_XCACHE_DISABLE()</TT
369 >If there are any generic features that the variant does not support
370 (cache locking is a typical example) then
374 > may need to disable definitions of
375 certain operations. It is architecture dependent exactly how this is
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423 >Platform HAL Porting</TD
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437 >Architecture HAL Porting</TD