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12 >ARM/Xscale Cyclone IQ80310</TITLE
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19 TITLE="eCos Reference Manual"
20 HREF="ecos-ref.html"><LINK
22 TITLE="Installation and Testing"
23 HREF="installation-and-testing.html"><LINK
25 TITLE="ARM/StrongARM(SA11X0) Intrinsyc CerfCube"
26 HREF="cerfcube.html"><LINK
28 TITLE="ARM/Xscale Intel IQ80321"
29 HREF="iq80321.html"></HEAD
40 SUMMARY="Header navigation table"
49 >eCos Reference Manual</TH
65 >Chapter 5. Installation and Testing</TD
85 NAME="IQ80310">ARM/Xscale Cyclone IQ80310</H1
91 NAME="AEN6164">Overview</H2
94 both serial ports and the built-in ethernet port for communication and downloads.
95 The default serial port settings are 115200,8,N,1. RedBoot also supports flash
96 management for the onboard 8MB flash.</P
98 >The following RedBoot configurations are supported:
101 CLASS="INFORMALTABLE"
141 >RedBoot running from the board's flash boot
160 >RedBoot running from RAM with RedBoot in the
161 flash boot sector.</TD
179 >RedBoot running from flash address 0x40000, with
180 ARM bootloader in flash boot sector.</TD
184 >redboot_ROMA.ecm</TD
198 >RedBoot running from RAM with ARM bootloader in
199 flash boot sector.</TD
203 >redboot_RAMA.ecm</TD
217 NAME="AEN6203">Initial Installation Method</H2
219 >The board manufacturer provides a DOS application which is
220 capable of programming the flash over the PCI bus, and this is
221 required for initial installations of RedBoot. Please see the board
222 manual for information on using this utility. In general, the process
223 involves programming one of the two flash based RedBoot images to
224 flash. The ROM mode RedBoot (which runs from the flash boot sector)
225 should be programmed to flash address 0x00000000. The ROMA RedBoot
226 mode (which is started by the ARM bootloader) should be programmed to
227 flash address 0x00004000.</P
229 > To install RedBoot to run from the flash boot sector, use the manufacturer's
230 flash utility to install the ROM mode image at address zero.</P
232 >To install RedBoot to run from address 0x40000 with the ARM bootloader
233 in the flash boot sector, use the manufacturer's flash utility to install
234 the ROMA mode image at address 0x40000. </P
236 >After booting the initial installation of RedBoot, this warning may
245 >flash configuration checksum error or invalid key</PRE
249 >This is normal, and indicates that the flash must be configured
250 for use by RedBoot. Even if the above message is not printed, it may be a
251 good idea to reinitialize the flash anyway. Do this with the <B
268 About to initialize [format] flash image system - continue (y/n)? <TT
274 *** Initialize flash Image System
275 Warning: device contents not erased, some blocks may not be usable
276 ... Unlock from 0x007e0000-0x00800000: .
277 ... Erase from 0x007e0000-0x00800000: .
278 ... Program from 0xa1fd0000-0xa1fd0400 at 0x007e0000: .
279 ... Lock from 0x007e0000-0x00800000: .
280 Followed by the fconfig command:
287 Run script at boot: <TT
293 Use BOOTP for network configuration: <TT
299 Local IP address: <TT
305 Default server IP address: <TT
311 GDB connection port: <TT
317 Network debug at boot time: <TT
323 Update RedBoot non-volatile configuration - continue (y/n)? <TT
329 ... Unlock from 0x007c0000-0x007e0000: .
330 ... Erase from 0x007c0000-0x007e0000: .
331 ... Program from 0xa0013018-0xa0013418 at 0x007c0000: .
332 ... Lock from 0x007c0000-0x007e0000: .</PRE
344 >When later updating RedBoot in situ, it is important to
345 use a matching ROM and RAM mode pair of images. So use either RAM/ROM
346 or RAMA/ROMA images. Do not mix them.</P
355 NAME="AEN6224">Error codes</H2
357 >RedBoot uses the two digit LED display to indicate errors during board
358 initialization. Possible error codes are: <P
359 CLASS="LITERALLAYOUT"
360 >88 - Unknown Error<br>
361 55 - I2C Error<br>
362 FF - SDRAM Error<br>
363 01 - No Error</P
371 NAME="AEN6228">Using RedBoot with ARM Bootloader</H2
373 >RedBoot can coexist with ARM tools in flash on the IQ80310 board. In
374 this configuration, the ARM bootloader will occupy the flash boot sector while
375 RedBoot is located at flash address 0x40000. The sixteen position rotary switch
376 is used to tell the ARM bootloader to jump to the RedBoot image located at
377 address 0x40000. RedBoot is selected by switch position 0 or 1. Other switch
378 positions are used by the ARM firmware and RedBoot will not be started. </P
385 NAME="AEN6231">Special RedBoot Commands</H2
387 >A special RedBoot command, <B
391 access a set of hardware diagnostics provided by the board
392 manufacturer. To access the diagnostic menu, enter diag at the RedBoot prompt:
407 Entering Hardware Diagnostics - Disabling Data Cache!
409 2 - Repeating Memory Tests
410 3 - 16C552 DUART Serial Port Tests
411 4 - Rotary Switch S1 Test for positions 0-3
412 5 - seven Segment LED Tests
413 6 - Backplane Detection Test
414 7 - Battery Status Test
415 8 - External Timer Test
416 9 - i82559 Ethernet Configuration
417 10 - i82559 Ethernet Test
418 11 - Secondary PCI Bus Test
419 12 - Primary PCI Bus Test
420 13 - i960Rx/303 PCI Interrupt Test
421 14 - Internal Timer Test
423 0 - quit Enter the menu item number (0 to quit):</PRE
428 Tests for various hardware subsystems are provided, and some
429 tests require special hardware in order to execute normally. The Ethernet
430 Configuration item may be used to set the board ethernet address.</P
437 NAME="AEN6237">IQ80310 Hardware Tests</H2
448 2 - Repeating Memory Tests
449 3 - 16C552 DUART Serial Port Tests
450 4 - Rotary Switch S1 Test for positions 0-3
451 5 - 7 Segment LED Tests
452 6 - Backplane Detection Test
453 7 - Battery Status Test
454 8 - External Timer Test
455 9 - i82559 Ethernet Configuration
456 10 - i82559 Ethernet Test
457 11 - i960Rx/303 PCI Interrupt Test
458 12 - Internal Timer Test
459 13 - Secondary PCI Bus Test
460 14 - Primary PCI Bus Test
461 15 - Battery Backup SDRAM Memory Test
463 17 - Repeat-On-Fail Memory Test
464 18 - Coyonosa Cache Loop (No return)
465 19 - Show Software and Hardware Revision
467 Enter the menu item number (0 to quit): </PRE
473 >Tests for various hardware subsystems are provided, and some tests require
474 special hardware in order to execute normally. The Ethernet Configuration
475 item may be used to set the board ethernet address.</P
482 NAME="AEN6242">Rebuilding RedBoot</H2
484 >These shell variables provide the platform-specific information
485 needed for building RedBoot according to the procedure described in
487 HREF="rebuilding-redboot.html"
497 CLASS="PROGRAMLISTING"
498 >export TARGET=iq80310
500 export PLATFORM_DIR=iq80310</PRE
506 >The names of configuration files are listed above with the
507 description of the associated modes.</P
514 NAME="AEN6248">Interrupts</H2
516 >RedBoot uses an interrupt vector table which is located at address 0xA000A004.
517 Entries in this table are pointers to functions with this protoype:: <TABLE
524 CLASS="PROGRAMLISTING"
525 >int irq_handler( unsigned vector, unsigned data )</PRE
530 board, the vector argument is one of 49 interrupts defined in <TT
531 CLASS="COMPUTEROUTPUT"
532 >hal/arm/iq80310/current/include/hal_platform_ints.h:</TT
540 CLASS="PROGRAMLISTING"
541 >// *** 80200 CPU ***
542 #define CYGNUM_HAL_INTERRUPT_reserved0 0
543 #define CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL 1 // See Ch.12 - Performance Mon.
544 #define CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL 2 // PMU counter 0/1 overflow
545 #define CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL 3 // PMU clock overflow
546 #define CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT 4 // See Ch.11 - Bus Control Unit
547 #define CYGNUM_HAL_INTERRUPT_NIRQ 5 // external IRQ
548 #define CYGNUM_HAL_INTERRUPT_NFIQ 6 // external FIQ
551 // *** XINT6 interrupts ***
552 #define CYGNUM_HAL_INTERRUPT_DMA_0 7
553 #define CYGNUM_HAL_INTERRUPT_DMA_1 8
554 #define CYGNUM_HAL_INTERRUPT_DMA_2 9
555 #define CYGNUM_HAL_INTERRUPT_GTSC 10 // Global Time Stamp Counter
556 #define CYGNUM_HAL_INTERRUPT_PEC 11 // Performance Event Counter
557 #define CYGNUM_HAL_INTERRUPT_AAIP 12 // application accelerator unit
560 // *** XINT7 interrupts ***
562 #define CYGNUM_HAL_INTERRUPT_I2C_TX_EMPTY 13
563 #define CYGNUM_HAL_INTERRUPT_I2C_RX_FULL 14
564 #define CYGNUM_HAL_INTERRUPT_I2C_BUS_ERR 15
565 #define CYGNUM_HAL_INTERRUPT_I2C_STOP 16
566 #define CYGNUM_HAL_INTERRUPT_I2C_LOSS 17
567 #define CYGNUM_HAL_INTERRUPT_I2C_ADDRESS 18
570 // Messaging Unit interrupts
571 #define CYGNUM_HAL_INTERRUPT_MESSAGE_0 19
572 #define CYGNUM_HAL_INTERRUPT_MESSAGE_1 20
573 #define CYGNUM_HAL_INTERRUPT_DOORBELL 21
574 #define CYGNUM_HAL_INTERRUPT_NMI_DOORBELL 22
575 #define CYGNUM_HAL_INTERRUPT_QUEUE_POST 23
576 #define CYGNUM_HAL_INTERRUPT_OUTBOUND_QUEUE_FULL 24
577 #define CYGNUM_HAL_INTERRUPT_INDEX_REGISTER 25
578 // PCI Address Translation Unit
579 #define CYGNUM_HAL_INTERRUPT_BIST 26
582 // *** External board interrupts (XINT3) ***
583 #define CYGNUM_HAL_INTERRUPT_TIMER 27 // external timer
584 #define CYGNUM_HAL_INTERRUPT_ETHERNET 28 // onboard enet
585 #define CYGNUM_HAL_INTERRUPT_SERIAL_A 29 // 16x50 uart A
586 #define CYGNUM_HAL_INTERRUPT_SERIAL_B 30 // 16x50 uart B
587 #define CYGNUM_HAL_INTERRUPT_PCI_S_INTD 31 // secondary PCI INTD
588 // The hardware doesn't (yet?) provide masking or status for these
589 // even though they can trigger cpu interrupts. ISRs will need to
590 // poll the device to see if the device actually triggered the
592 #define CYGNUM_HAL_INTERRUPT_PCI_S_INTC 32 // secondary PCI INTC
593 #define CYGNUM_HAL_INTERRUPT_PCI_S_INTB 33 // secondary PCI INTB
594 #define CYGNUM_HAL_INTERRUPT_PCI_S_INTA 34 // secondary PCI INTA
597 // *** NMI Interrupts go to FIQ ***
598 #define CYGNUM_HAL_INTERRUPT_MCU_ERR 35
599 #define CYGNUM_HAL_INTERRUPT_PATU_ERR 36
600 #define CYGNUM_HAL_INTERRUPT_SATU_ERR 37
601 #define CYGNUM_HAL_INTERRUPT_PBDG_ERR 38
602 #define CYGNUM_HAL_INTERRUPT_SBDG_ERR 39
603 #define CYGNUM_HAL_INTERRUPT_DMA0_ERR 40
604 #define CYGNUM_HAL_INTERRUPT_DMA1_ERR 41
605 #define CYGNUM_HAL_INTERRUPT_DMA2_ERR 42
606 #define CYGNUM_HAL_INTERRUPT_MU_ERR 43
607 #define CYGNUM_HAL_INTERRUPT_reserved52 44
608 #define CYGNUM_HAL_INTERRUPT_AAU_ERR 45
609 #define CYGNUM_HAL_INTERRUPT_BIU_ERR 46
612 // *** ATU FIQ sources ***
613 #define CYGNUM_HAL_INTERRUPT_P_SERR 47
614 #define CYGNUM_HAL_INTERRUPT_S_SERR 48</PRE
619 to the ISR is pulled from a data table <TT
620 CLASS="COMPUTEROUTPUT"
621 >(hal_interrupt_data)</TT
622 > which immediately follows the interrupt vector table. With
623 49 interrupts, the data table starts at address 0xA000A0C8. </P
625 >An application may create a normal C function with the above prototype
626 to be an ISR. Just poke its address into the table at the correct index and
627 enable the interrupt at its source. The return value of the ISR is ignored
635 NAME="AEN6256">Memory Maps</H2
637 >The first level page table is located at 0xa0004000. Two second level
638 tables are also used. One second level table is located at 0xa0008000 and
639 maps the first 1MB of flash. The other second level table is at 0xa0008400,
640 and maps the first 1MB of SDRAM. <DIV
647 >The virtual memory maps in this section use a C and B column to indicate
648 whether or not the region is cached (C) or buffered (B).</P
660 CLASS="PROGRAMLISTING"
661 >Physical Address Range Description
662 ----------------------- ----------------------------------
663 0x00000000 - 0x00000fff flash Memory
664 0x00001000 - 0x00001fff 80312 Internal Registers
665 0x00002000 - 0x007fffff flash Memory
666 0x00800000 - 0x7fffffff PCI ATU Outbound Direct Window
667 0x80000000 - 0x83ffffff Primary PCI 32-bit Memory
668 0x84000000 - 0x87ffffff Primary PCI 64-bit Memory
669 0x88000000 - 0x8bffffff Secondary PCI 32-bit Memory
670 0x8c000000 - 0x8fffffff Secondary PCI 64-bit Memory
671 0x90000000 - 0x9000ffff Primary PCI IO Space
672 0x90010000 - 0x9001ffff Secondary PCI IO Space
673 0x90020000 - 0x9fffffff Unused
674 0xa0000000 - 0xbfffffff SDRAM
675 0xc0000000 - 0xefffffff Unused
676 0xf0000000 - 0xffffffff 80200 Internal Registers
679 Virtual Address Range C B Description
680 ----------------------- - - ----------------------------------
681 0x00000000 - 0x00000fff Y Y SDRAM
682 0x00001000 - 0x00001fff N N 80312 Internal Registers
683 0x00002000 - 0x007fffff Y N flash Memory
684 0x00800000 - 0x7fffffff N N PCI ATU Outbound Direct Window
685 0x80000000 - 0x83ffffff N N Primary PCI 32-bit Memory
686 0x84000000 - 0x87ffffff N N Primary PCI 64-bit Memory
687 0x88000000 - 0x8bffffff N N Secondary PCI 32-bit Memory
688 0x8c000000 - 0x8fffffff N N Secondary PCI 64-bit Memory
689 0x90000000 - 0x9000ffff N N Primary PCI IO Space
690 0x90010000 - 0x9001ffff N N Secondary PCI IO Space
691 0xa0000000 - 0xbfffffff Y Y SDRAM
692 0xc0000000 - 0xcfffffff Y Y Cache Flush Region
693 0xd0000000 - 0xd0000fff Y N first 4k page of flash
694 0xf0000000 - 0xffffffff N N 80200 Internal Registers </PRE
705 NAME="AEN6264">Platform Resource Usage</H2
707 >The external timer is used as a polled timer to provide timeout support
708 for networking and XModem file transfers.</P
716 SUMMARY="Footer navigation table"
755 >ARM/StrongARM(SA11X0) Intrinsyc CerfCube</TD
761 HREF="installation-and-testing.html"
769 >ARM/Xscale Intel IQ80321</TD