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12 >ARM/Xscale Intel IQ80321</TITLE
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16 CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
19 TITLE="eCos Reference Manual"
20 HREF="ecos-ref.html"><LINK
22 TITLE="Installation and Testing"
23 HREF="installation-and-testing.html"><LINK
25 TITLE="ARM/Xscale Cyclone IQ80310"
26 HREF="iq80310.html"><LINK
28 TITLE="CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board "
29 HREF="calmrisc16.html"></HEAD
40 SUMMARY="Header navigation table"
49 >eCos Reference Manual</TH
65 >Chapter 5. Installation and Testing</TD
71 HREF="calmrisc16.html"
85 NAME="IQ80321">ARM/Xscale Intel IQ80321</H1
91 NAME="AEN6269">Overview</H2
94 the serial port and the built-in ethernet port for communication and downloads.
95 The default serial port settings are 115200,8,N,1. RedBoot also supports flash
96 management for the onboard 8MB flash.</P
98 >The following RedBoot configurations are supported:
101 CLASS="INFORMALTABLE"
141 >RedBoot running from the board's flash boot
160 >RedBoot running from RAM with RedBoot in the
161 flash boot sector.</TD
179 NAME="AEN6298">Initial Installation Method</H2
181 >The board manufacturer provides a DOS application which is capable of
182 programming the flash over the PCI bus, and this is required for initial installations
183 of RedBoot. Please see the board manual for information on using this utility.
184 In general, the process involves programming the ROM mode RedBoot
185 image to flash. RedBoot should be programmed to flash address
186 0x00000000 using the DOS utility.</P
188 >After booting the initial installation of RedBoot, this warning may
197 >flash configuration checksum error or invalid key</PRE
201 >This is normal, and indicates that the flash must be configured
202 for use by RedBoot. Even if the above message is not printed, it may be a
203 good idea to reinitialize the flash anyway. Do this with the <B
220 About to initialize [format] FLASH image system - continue (y/n)? <TT
226 *** Initialize FLASH Image System
227 Warning: device contents not erased, some blocks may not be usable
228 ... Unlock from 0xf07e0000-0xf0800000: .
229 ... Erase from 0xf07e0000-0xf0800000: .
230 ... Program from 0x01ddf000-0x01ddf400 at 0xf07e0000: .
231 ... Lock from 0xf07e0000-0xf0800000: .</PRE
242 NAME="AEN6307">Switch Settings</H2
244 >The 80321 board is highly configurable through a number of switches and jumpers.
245 RedBoot makes some assumptions about board configuration and attention must be paid
246 to these assumptions for reliable RedBoot operation:
252 >The onboard ethernet and the secondary slot may be placed in a
253 private space so that they are not seen by a PC BIOS. If the board is to be used
254 in a PC with BIOS, then the ethernet should be placed in this private space so that
255 RedBoot and the BIOS do not conflict.</P
259 >RedBoot assumes that the board is plugged into a PC with BIOS. This
260 requires RedBoot to detect when the BIOS has configured the PCI-X secondary bus. If
261 the board is placed in a backplane, RedBoot will never see the BIOS configure the
262 secondary bus. To prevent this wait, set switch S7E1-3 to ON when using the board
267 >For the remaining switch settings, the following is a known good
270 CLASS="INFORMALTABLE"
296 >7 is ON, all others OFF</TD
306 >2,3,5,6 are ON, all others OFF</TD
316 >2,3 are ON, all others OFF</TD
326 >3 is ON, all others OFF</TD
336 >1,3 are ON, all others OFF</TD
366 >Nothing jumpered</TD
403 NAME="AEN6353">LED Codes</H2
405 >RedBoot uses the two digit LED display to indicate status during board
406 initialization. Possible codes are:</P
408 CLASS="LITERALLAYOUT"
409 >LED Actions<br>
410 -------------------------------------------------------------<br>
411 Power-On/Reset<br>
413 Set the CPSR<br>
414 Enable coprocessor access<br>
415 Drain write and fill buffer<br>
416 Setup PBIU chip selects<br>
418 Enable the Icache<br>
420 Move FLASH chip select from 0x0 to 0xF0000000<br>
421 Jump to new FLASH location<br>
423 Setup and enable the MMU<br>
425 I2C interface initialization<br>
427 Wait for I2C initialization to complete<br>
429 Send address (via I2C) to the DIMM<br>
431 Wait for transmit complete<br>
433 Read SDRAM PD data from DIMM<br>
435 Read remainder of EEPROM data.<br>
436 An error will result in one of the following<br>
437 error codes on the LEDs:<br>
438 77 BAD EEPROM checksum<br>
439 55 I2C protocol error<br>
440 FF bank size error<br>
442 Setup DDR memory interface<br>
444 Enable branch target buffer<br>
445 Drain the write & fill buffers<br>
446 Flush Icache, Dcache and BTB<br>
447 Flush instuction and data TLBs<br>
448 Drain the write & fill buffers<br>
450 ECC Scrub Loop<br>
453 Clean, drain, flush the main Dcache<br>
455 Clean, drain, flush the mini Dcache<br>
456 Flush Dcache<br>
457 Drain the write & fill buffers<br>
459 Enable ECC<br>
461 Save SDRAM size<br>
462 Move MMU tables into RAM<br>
464 Clean, drain, flush the main Dcache<br>
465 Clean, drain, flush the mini Dcache<br>
466 Drain the write & fill buffers<br>
468 Set the TTB register to DRAM mmu_table<br>
470 Set mode to IRQ mode<br>
472 Move SWI & Undefined "vectors" to RAM (at 0x0)<br>
474 Switch to supervisor mode<br>
476 Move remaining "vectors" to RAM (at 0x0)<br>
478 Copy DATA to RAM<br>
479 Initialize interrupt exception environment<br>
480 Initialize stack<br>
481 Clear BSS section<br>
483 Call platform specific hardware initialization<br>
485 Run through static constructors<br>
487 Start up the eCos kernel or RedBoot</P
494 NAME="AEN6357">Special RedBoot Commands</H2
496 >A special RedBoot command, <B
500 access a set of hardware diagnostics. To access the diagnostic menu,
504 > at the RedBoot prompt:
519 Entering Hardware Diagnostics - Disabling Data Cache!
521 IQ80321 Hardware Tests
524 2 - Repeating Memory Tests
525 3 - Repeat-On-Fail Memory Tests
526 4 - Rotary Switch S1 Test
527 5 - 7 Segment LED Tests
528 6 - i82544 Ethernet Configuration
529 7 - Baterry Status Test
530 8 - Battery Backup SDRAM Memory Test
533 11 - CPU Cache Loop (No Return)
535 Enter the menu item number (0 to quit):</PRE
540 Tests for various hardware subsystems are provided, and some tests require
541 special hardware in order to execute normally. The Ethernet Configuration
542 item may be used to set the board ethernet address.</P
548 NAME="AEN6364">Memory Tests</H3
550 >This test is used to test installed DDR SDRAM memory. Five different
551 tests are run over the given address ranges. If errors are encountered, the
552 test is aborted and information about the failure is printed. When selected,
553 the user will be prompted to enter the base address of the test range and its
554 size. The numbers must be in hex with no leading “0x”</P
563 >Enter the menu item number (0 to quit): <TT
570 Base address of memory to test (in hex): <TT
577 Size of memory to test (in hex): <TT
584 Testing memory from 0x00100000 to 0x002fffff.
587 0000000100000002000000040000000800000010000000200000004000000080
588 0000010000000200000004000000080000001000000020000000400000008000
589 0001000000020000000400000008000000100000002000000040000000800000
590 0100000002000000040000000800000010000000200000004000000080000000
592 32-bit address test: passed
593 32-bit address bar test: passed
594 8-bit address test: passed
595 Byte address bar test: passed
596 Memory test done.</PRE
606 NAME="AEN6371">Repeating Memory Tests</H3
608 >The repeating memory tests are exactly the same as the above memory tests,
609 except that the tests are automatically rerun after completion. The only way out
610 of this test is to reset the board.</P
617 NAME="AEN6374">Repeat-On-Fail Memory Tests</H3
619 >This is similar to the repeating memory tests except that when an error
620 is found, the failing test continuously retries on the failing address.</P
627 NAME="AEN6377">Rotary Switch S1 Test</H3
629 >This tests the operation of the sixteen position rotary switch. When run,
630 this test will display the current position of the rotary switch on the LED
631 display. Slowly dial through each position and confirm reading on LED.</P
638 NAME="AEN6380">7 Segment LED Tests</H3
640 >This tests the operation of the seven segment displays. When run, each
641 LED cycles through 0 through F and a decimal point.</P
648 NAME="AEN6383">i82544 Ethernet Configuration</H3
650 >This test initializes the ethernet controller’s serial EEPROM if
651 the current contents are invalid. In any case, this test will also allow the
652 user to enter a six byte ethernet MAC address into the serial EEPROM.</P
661 >Enter the menu item number (0 to quit): <TT
669 Current MAC address: 00:80:4d:46:00:02
670 Enter desired MAC address: <TT
673 >00:80:4d:46:00:01</B
676 Writing to the Serial EEPROM... Done
678 ******** Reset The Board To Have Changes Take Effect ********</PRE
688 NAME="AEN6389">Battery Status Test</H3
690 >This tests the current status of the battery. First, the test checks to
691 see if the battery is installed and reports that finding. If the battery is
692 installed, the test further determines whether the battery status is one or
693 more of the following:
699 >Battery is charging.</P
703 >Battery is fully discharged.</P
707 >Battery voltage measures within normal operating range.</P
717 NAME="AEN6399">Battery Backup SDRAM Memory Test</H3
719 >This tests the battery backup of SDRAM memory. This test is a three
727 >Select Battery backup test from main diag menu, then write
732 >Turn off power for 60 seconds, then repower the board.</P
736 >Select Battery backup test from main diag menu, then check
737 data that was written in step 1.</P
746 NAME="AEN6409">Timer Test</H3
748 >This tests the internal timer by printing a number of dots at one
756 NAME="AEN6412">PCI Bus Test</H3
758 >This tests the secondary PCI-X bus and socket. This test requires that
759 an IQ80310 board be plugged into the secondary slot of the IOP80321 board.
760 The test assumes at least 32MB of installed memory on the IQ80310. That memory
761 is mapped into the IOP80321 address space and the memory tests are run on that
769 NAME="AEN6415">CPU Cache Loop</H3
771 >This test puts the CPU into a tight loop run entirely from the ICache.
772 This should prevent all external bus accesses.</P
780 NAME="AEN6418">Rebuilding RedBoot</H2
782 >These shell variables provide the platform-specific information
783 needed for building RedBoot according to the procedure described in
785 HREF="rebuilding-redboot.html"
795 CLASS="PROGRAMLISTING"
796 >export TARGET=iq80321
798 export PLATFORM_DIR=xscale/iq80321</PRE
804 >The names of configuration files are listed above with the
805 description of the associated modes.</P
812 NAME="AEN6424">Interrupts</H2
814 >RedBoot uses an interrupt vector table which is located at address 0x8004.
815 Entries in this table are pointers to functions with this protoype:: <TABLE
822 CLASS="PROGRAMLISTING"
823 >int irq_handler( unsigned vector, unsigned data )</PRE
828 board, the vector argument is one of 32 interrupts defined in <TT
829 CLASS="COMPUTEROUTPUT"
830 >hal/arm/xscale/verde/current/include/hal_var_ints.h:</TT
838 CLASS="PROGRAMLISTING"
839 >// *** 80200 CPU ***
840 #define CYGNUM_HAL_INTERRUPT_DMA0_EOT 0
841 #define CYGNUM_HAL_INTERRUPT_DMA0_EOC 1
842 #define CYGNUM_HAL_INTERRUPT_DMA1_EOT 2
843 #define CYGNUM_HAL_INTERRUPT_DMA1_EOC 3
844 #define CYGNUM_HAL_INTERRUPT_RSVD_4 4
845 #define CYGNUM_HAL_INTERRUPT_RSVD_5 5
846 #define CYGNUM_HAL_INTERRUPT_AA_EOT 6
847 #define CYGNUM_HAL_INTERRUPT_AA_EOC 7
848 #define CYGNUM_HAL_INTERRUPT_CORE_PMON 8
849 #define CYGNUM_HAL_INTERRUPT_TIMER0 9
850 #define CYGNUM_HAL_INTERRUPT_TIMER1 10
851 #define CYGNUM_HAL_INTERRUPT_I2C_0 11
852 #define CYGNUM_HAL_INTERRUPT_I2C_1 12
853 #define CYGNUM_HAL_INTERRUPT_MESSAGING 13
854 #define CYGNUM_HAL_INTERRUPT_ATU_BIST 14
855 #define CYGNUM_HAL_INTERRUPT_PERFMON 15
856 #define CYGNUM_HAL_INTERRUPT_CORE_PMU 16
857 #define CYGNUM_HAL_INTERRUPT_BIU_ERR 17
858 #define CYGNUM_HAL_INTERRUPT_ATU_ERR 18
859 #define CYGNUM_HAL_INTERRUPT_MCU_ERR 19
860 #define CYGNUM_HAL_INTERRUPT_DMA0_ERR 20
861 #define CYGNUM_HAL_INTERRUPT_DMA1_ERR 22
862 #define CYGNUM_HAL_INTERRUPT_AA_ERR 23
863 #define CYGNUM_HAL_INTERRUPT_MSG_ERR 24
864 #define CYGNUM_HAL_INTERRUPT_SSP 25
865 #define CYGNUM_HAL_INTERRUPT_RSVD_26 26
866 #define CYGNUM_HAL_INTERRUPT_XINT0 27
867 #define CYGNUM_HAL_INTERRUPT_XINT1 28
868 #define CYGNUM_HAL_INTERRUPT_XINT2 29
869 #define CYGNUM_HAL_INTERRUPT_XINT3 30
870 #define CYGNUM_HAL_INTERRUPT_HPI 31</PRE
875 The data passed to the ISR is pulled from a data table <TT
876 CLASS="COMPUTEROUTPUT"
877 >(hal_interrupt_data)</TT
878 > which immediately follows the interrupt vector table. With
879 32 interrupts, the data table starts at address 0x8084. </P
881 >An application may create a normal C function with the above prototype
882 to be an ISR. Just poke its address into the table at the correct index and
883 enable the interrupt at its source. The return value of the ISR is ignored
891 NAME="AEN6432">Memory Maps</H2
893 >The RAM based page table is located at RAM start + 0x4000. RedBoot may be configured
894 for one of two memory maps. The difference between them is the location of RAM and the
895 PCI outbound windows. The alternative memory map may be used when
896 building RedBoot or eCos by using the <TT
903 > startup types in the configuration.
911 >The virtual memory maps in this section use a C, B, and X column to indicate
912 the caching policy for the region..</P
924 CLASS="PROGRAMLISTING"
926 - - - ---------------------------------------------
927 0 0 0 Uncached/Unbuffered
928 0 0 1 Uncached/Buffered
929 0 1 0 Cached/Buffered Write Through, Read Allocate
930 0 1 1 Cached/Buffered Write Back, Read Allocate
931 1 0 0 Invalid -- not used
932 1 0 1 Uncached/Buffered No write buffer coalescing
933 1 1 0 Mini DCache - Policy set by Aux Ctl Register
934 1 1 1 Cached/Buffered Write Back, Read/Write Allocate
936 Physical Address Range Description
937 ----------------------- ----------------------------------
938 0x00000000 - 0x7fffffff ATU Outbound Direct Window
939 0x80000000 - 0x900fffff ATU Outbound Translate Windows
940 0xa0000000 - 0xbfffffff SDRAM
941 0xf0000000 - 0xf0800000 FLASH (PBIU CS0)
942 0xfe800000 - 0xfe800fff UART (PBIU CS1)
943 0xfe840000 - 0xfe840fff Left 7-segment LED (PBIU CS3)
944 0xfe850000 - 0xfe850fff Right 7-segment LED (PBIU CS2)
945 0xfe8d0000 - 0xfe8d0fff Rotary Switch (PBIU CS4)
946 0xfe8f0000 - 0xfe8f0fff Baterry Status (PBIU CS5)
947 0xfff00000 - 0xffffffff Verde Memory mapped Registers
950 Default Virtual Map X C B Description
951 ----------------------- - - - ----------------------------------
952 0x00000000 - 0x1fffffff 1 1 1 SDRAM
953 0x20000000 - 0x9fffffff 0 0 0 ATU Outbound Direct Window
954 0xa0000000 - 0xb00fffff 0 0 0 ATU Outbound Translate Windows
955 0xc0000000 - 0xdfffffff 0 0 0 Uncached alias for SDRAM
956 0xe0000000 - 0xe00fffff 1 1 1 Cache flush region (no phys mem)
957 0xf0000000 - 0xf0800000 0 1 0 FLASH (PBIU CS0)
958 0xfe800000 - 0xfe800fff 0 0 0 UART (PBIU CS1)
959 0xfe840000 - 0xfe840fff 0 0 0 Left 7-segment LED (PBIU CS3)
960 0xfe850000 - 0xfe850fff 0 0 0 Right 7-segment LED (PBIU CS2)
961 0xfe8d0000 - 0xfe8d0fff 0 0 0 Rotary Switch (PBIU CS4)
962 0xfe8f0000 - 0xfe8f0fff 0 0 0 Baterry Status (PBIU CS5)
963 0xfff00000 - 0xffffffff 0 0 0 Verde Memory mapped Registers
965 Alternate Virtual Map X C B Description
966 ----------------------- - - - ----------------------------------
967 0x00000000 - 0x000fffff 1 1 1 Alias for 1st MB of SDRAM
968 0x00100000 - 0x7fffffff 0 0 0 ATU Outbound Direct Window
969 0x80000000 - 0x900fffff 0 0 0 ATU Outbound Translate Windows
970 0xa0000000 - 0xbfffffff 1 1 1 SDRAM
971 0xc0000000 - 0xdfffffff 0 0 0 Uncached alias for SDRAM
972 0xe0000000 - 0xe00fffff 1 1 1 Cache flush region (no phys mem)
973 0xf0000000 - 0xf0800000 0 1 0 FLASH (PBIU CS0)
974 0xfe800000 - 0xfe800fff 0 0 0 UART (PBIU CS1)
975 0xfe840000 - 0xfe840fff 0 0 0 Left 7-segment LED (PBIU CS3)
976 0xfe850000 - 0xfe850fff 0 0 0 Right 7-segment LED (PBIU CS2)
977 0xfe8d0000 - 0xfe8d0fff 0 0 0 Rotary Switch (PBIU CS4)
978 0xfe8f0000 - 0xfe8f0fff 0 0 0 Baterry Status (PBIU CS5)
979 0xfff00000 - 0xffffffff 0 0 0 Verde Memory mapped Registers </PRE
990 NAME="AEN6442">Platform Resource Usage</H2
992 >The Verde programmable timer0 is used for timeout support
993 for networking and XModem file transfers.</P
1001 SUMMARY="Footer navigation table"
1021 HREF="ecos-ref.html"
1030 HREF="calmrisc16.html"
1040 >ARM/Xscale Cyclone IQ80310</TD
1046 HREF="installation-and-testing.html"
1054 >CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board</TD
projects / karo-tx-redboot.git / blob