3 //==========================================================================
7 // ARM specific processor defines
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
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19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
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36 // this file might be covered by the GNU General Public License.
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39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
46 // Contributors: gthomas
48 // Purpose: ARM specific processor defines
49 // Description: ARM is a Registered Trademark of Advanced RISC Machines
51 // Other Brands and Trademarks are the property of their
54 //####DESCRIPTIONEND####
56 //=========================================================================
61 #include <cyg/hal/hal_arch.h>
65 * Only define __NEED_UNDERSCORE__ for arm-coff targets
68 # define __NEED_UNDERSCORE__
72 * Macros to glue together two tokens.
75 # define XGLUE(a,b) a##b
77 # define XGLUE(a,b) a/**/b
80 # define GLUE(a,b) XGLUE(a,b)
83 * Symbol Names with leading underscore if necessary
85 # ifdef __NEED_UNDERSCORE__
86 # define SYM_NAME(name) GLUE(_,name)
88 # define SYM_NAME(name) name
89 # endif /* __NEED_UNDERSCORE__ */
92 * Various macros to better handle assembler/object format differences
94 #if defined(__ASSEMBLER__)
97 * Assembly function start definition
99 #ifdef __NEED_UNDERSCORE__
100 .macro FUNC_START name
106 .macro FUNC_START name
114 * Assembly function end definition
116 #ifdef __NEED_UNDERSCORE__
127 # ifndef __REGISTER_PREFIX__
128 # define __REGISTER_PREFIX__
129 # endif /* __REGISTER_PREFIX__ */
134 # ifndef __IMM_PREFIX__
135 # define __IMM_PREFIX__ #
136 # endif /* __IMM_PREFIX__ */
139 * use the right prefix for registers.
141 # define REG(x) GLUE(__REGISTER_PREFIX__,x)
144 * use the right prefix for immediate values.
146 # define IMM(x) GLUE(__IMM_PREFIX__,x)
148 #endif /* defined(__ASSEMBLER__) */
152 * Setup register defines and such
154 #if defined(__ASSEMBLER__)
167 # define r10 REG (r10)
168 # define r11 REG (r11)
169 # define r12 REG (r12)
170 # define r13 REG (r13)
172 # define r14 REG (r14)
184 # define fps REG (fps)
186 # define cpsr REG (cpsr)
187 # define spsr REG (spsr)
190 * Register offset definitions
191 * These numbers are offsets into the ex_regs_t struct.
224 # define ARM_EX_REGS_T_SIZE 172
226 #else /* !defined(__ASSEMBLER__) */
229 * Register name that is used in help strings and such
231 # define REGNAME_EXAMPLE "r0"
234 * Register numbers. These are assumed to match the
235 * register numbers used by GDB.
273 * 12-byte struct for storing Floating point registers
278 unsigned long middle;
283 * How registers are stored for exceptions.
286 #define ex_regs_t HAL_SavedRegisters
336 unsigned long _spsvc; /* saved svc mode sp */
343 extern void __icache_flush(void *addr, int nbytes);
344 extern void __dcache_flush(void *addr, int nbytes);
346 #endif /* __ASSEMBLER__ */
350 * Program Status Register Definitions
352 #if defined(__ASSEMBLER__)
353 # define ARM_PSR_NEGATIVE 0x80000000 /* Negative Bit */
354 # define ARM_PSR_ZERO 0x40000000 /* Zero Bit */
355 # define ARM_PSR_CARRY 0x20000000 /* Carry Bit */
356 # define ARM_PSR_OVERFLOW 0x10000000 /* Overflow Bit */
357 # define ARM_PSR_IRQ 0x00000080 /* IRQ Bit */
358 # define ARM_PSR_FIQ 0x00000040 /* FIQ Bit */
359 # define ARM_PSR_THUMB_STATE 0x00000020 /* Thumb/ARM(R) Execution */
360 # define ARM_PSR_MODE_MASK 0x0000001F /* ARM(R) Processor Mode Mask */
361 #else /* ! defined(__ASSEMBLER__) */
367 unsigned rsv1 : 20; /* == 0x00000 */
376 struct psr_struct psr;
378 #endif /* __ASSEMBLER__ */
383 #define ARM_PSR_MODE_USER 0x00000010 /* User mode */
384 #define ARM_PSR_MODE_FIQ 0x00000011 /* FIQ mode */
385 #define ARM_PSR_MODE_IRQ 0x00000012 /* IRQ mode */
386 #define ARM_PSR_MODE_SVC 0x00000013 /* SVC mode */
387 #define ARM_PSR_MODE_ABORT 0x00000017 /* ABORT mode */
388 #define ARM_PSR_MODE_UNDEF 0x0000001B /* UNDEF mode */
389 #define ARM_PSR_MODE_SYSTEM 0x0000001F /* System Mode */
390 #define ARM_PSR_NUM_MODES 7
393 * Core Exception vectors.
395 #define BSP_CORE_EXC_RESET 0
396 #define BSP_CORE_EXC_UNDEFINED_INSTRUCTION 1
397 #define BSP_CORE_EXC_SOFTWARE_INTERRUPT 2
398 #define BSP_CORE_EXC_PREFETCH_ABORT 3
399 #define BSP_CORE_EXC_DATA_ABORT 4
400 #define BSP_CORE_EXC_ADDRESS_ERROR_26_BIT 5
401 #define BSP_CORE_EXC_IRQ 6
402 #define BSP_CORE_EXC_FIQ 7
403 #define BSP_MAX_EXCEPTIONS 8
404 #define BSP_CORE_EXC(vec_num) (unsigned long*)(vec_num << 2)
406 #define BREAKPOINT_INSN 0xE7FFDEFE /* Illegal inst opcode */
407 #define SYSCALL_SWI 0x00180001
409 #if defined(__ASSEMBLER__)
411 .word BREAKPOINT_INSN
419 bic r0, r0, IMM(ARM_PSR_IRQ | ARM_PSR_FIQ)
426 orr r0, r0, IMM(ARM_PSR_IRQ | ARM_PSR_FIQ)
433 * Use this code to verify a particular processing mode
436 and r0, r0, IMM(ARM_PSR_MODE_MASK)
437 ldr r1, =ARM_PSR_MODE_IRQ
443 #else /* !defined(__ASSEMBLER__) */
445 # define BREAKPOINT() asm volatile(" .word 0xE7FFDEFE")
446 # define SYSCALL() asm volatile(" swi %0" : /* No outputs */ : "i" (SYSCALL_SWI))
447 # define __cli() asm volatile("
450 bic r0, r0, #0x000000C0
453 # define __sti() asm volatile("
456 orr r0, r0, #0x000000C0
459 # define __mcr(cp_num, opcode1, Rd, CRn, CRm, opcode2) \
460 asm volatile (" mcr " cp_num ", " \
465 opcode2 : /* no outputs */ : "r" (Rd))
466 # define __mrc(cp_num, opcode1, Rd, CRn, CRm, opcode2) \
467 asm volatile (" mrc " cp_num ", " \
472 opcode2 : "=r" (Rd) : /* no inputs */)
474 static inline unsigned __get_cpsr(void)
476 unsigned long retval;
477 asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
481 static inline void __set_cpsr(unsigned val)
483 asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
486 static inline unsigned __get_spsr(void)
488 unsigned long retval;
489 asm volatile (" mrs %0, spsr" : "=r" (retval) : /* no inputs */ );
493 static inline void __set_spsr(unsigned val)
495 asm volatile (" msr spsr, %0" : /* no outputs */ : "r" (val) );
498 static inline unsigned __get_sp(void)
500 unsigned long retval;
501 asm volatile (" mov %0, sp" : "=r" (retval) : /* no inputs */ );
505 static inline void __set_sp(unsigned val)
507 asm volatile (" mov sp, %0" : /* no outputs */ : "r" (val) );
510 static inline unsigned __get_fp(void)
512 unsigned long retval;
513 asm volatile (" mov %0, fp" : "=r" (retval) : /* no inputs */ );
517 static inline void __set_fp(unsigned val)
519 asm volatile (" mov fp, %0" : /* no outputs */ : "r" (val) );
522 static inline unsigned __get_pc(void)
524 unsigned long retval;
525 asm volatile (" mov %0, pc" : "=r" (retval) : /* no inputs */ );
529 static inline void __set_pc(unsigned val)
531 asm volatile (" mov pc, %0" : /* no outputs */ : "r" (val) );
534 static inline unsigned __get_lr(void)
536 unsigned long retval;
537 asm volatile (" mov %0, lr" : "=r" (retval) : /* no inputs */ );
541 static inline void __set_lr(unsigned val)
543 asm volatile (" mov lr, %0" : /* no outputs */ : "r" (val) );
546 static inline unsigned __get_r8(void)
548 unsigned long retval;
549 asm volatile (" mov %0, r8" : "=r" (retval) : /* no inputs */ );
553 static inline void __set_r8(unsigned val)
555 asm volatile (" mov r8, %0" : /* no outputs */ : "r" (val) );
558 static inline unsigned __get_r9(void)
560 unsigned long retval;
561 asm volatile (" mov %0, r9" : "=r" (retval) : /* no inputs */ );
565 static inline void __set_r9(unsigned val)
567 asm volatile (" mov r9, %0" : /* no outputs */ : "r" (val) );
570 static inline unsigned __get_r10(void)
572 unsigned long retval;
573 asm volatile (" mov %0, r10" : "=r" (retval) : /* no inputs */ );
577 static inline void __set_r10(unsigned val)
579 asm volatile (" mov r10, %0" : /* no outputs */ : "r" (val) );
582 static inline unsigned __get_r11(void)
584 unsigned long retval;
585 asm volatile (" mov %0, r11" : "=r" (retval) : /* no inputs */ );
589 static inline void __set_r11(unsigned val)
591 asm volatile (" mov r11, %0" : /* no outputs */ : "r" (val) );
594 static inline unsigned __get_r12(void)
596 unsigned long retval;
597 asm volatile (" mov %0, r12" : "=r" (retval) : /* no inputs */ );
601 static inline void __set_r12(unsigned val)
603 asm volatile (" mov r12, %0" : /* no outputs */ : "r" (val) );
606 #endif /* defined(__ASSEMBLER__) */
608 #define GDB_BREAKPOINT_VECTOR BSP_CORE_EXC_UNDEFINED_INSTRUCTION
609 #define GDB_SYSCALL_VECTOR BSP_CORE_EXC_SOFTWARE_INTERRUPT
611 #define ARM_INST_SIZE sizeof(unsigned long)
612 #define GDB_BREAKPOINT_INST_SIZE ARM_INST_SIZE
614 #ifdef __CPU_LH77790A__
615 # include <bsp/lh77790a.h>
616 #endif /* __CPU_LH77790A__ */
618 #if !defined(__ASSEMBLER__)
620 * Define the CPU specific data
622 #ifdef __CPU_LH77790A__
624 unsigned char lh77790a_port_control_shadow;
626 #endif /* __CPU_LH77790A__ */
627 #endif /* !defined(__ASSEMBLER__) */
630 #include <bsp/sa-110.h>
631 #endif /* __CPU_SA110__ */
633 #ifdef __CPU_SA1100__
634 #include <bsp/sa-1100.h>
635 #endif /* __CPU_SA110__ */
638 #include <bsp/arm710t.h>
639 #endif /* __CPU_710T__ */
643 * ARM(R) MMU Definitions
646 #ifndef __ASSEMBLER__
648 #endif /* __ASSEMBLER__ */
651 * ARM(R) Cache and MMU Control Registers
653 * Accessed through coprocessor instructions.
656 # define ARM_CACHE_COPROCESSOR_NUM p15
657 # define ARM_COPROCESSOR_OPCODE_DONT_CARE 0x0
658 # define ARM_COPROCESSOR_RM_DONT_CARE c0
659 #else /* __ASSEMBLER__ */
660 # define ARM_CACHE_COPROCESSOR_NUM "p15"
661 # define ARM_COPROCESSOR_OPCODE_DONT_CARE "0x0"
662 # define ARM_COPROCESSOR_RM_DONT_CARE "c0"
663 #endif /* __ASSEMBLER__ */
666 # define ARM_ID_REGISTER c0
667 # define ARM_CONTROL_REGISTER c1
668 # define ARM_TRANSLATION_TABLE_BASE_REGISTER c2
669 # define ARM_DOMAIN_ACCESS_CONTROL_REGISTER c3
670 # define ARM_FAULT_STATUS_REGISTER c5
671 # define ARM_FAULT_ADDRESS_REGISTER c6
672 # define ARM_CACHE_OPERATIONS_REGISTER c7
673 # define ARM_TLB_OPERATIONS_REGISTER c8
674 # define ARM_READ_BUFFER_OPERATIONS_REGISTER c9
675 #else /* __ASSEMBLER__ */
676 # define ARM_ID_REGISTER "c0"
677 # define ARM_CONTROL_REGISTER "c1"
678 # define ARM_TRANSLATION_TABLE_BASE_REGISTER "c2"
679 # define ARM_DOMAIN_ACCESS_CONTROL_REGISTER "c3"
680 # define ARM_FAULT_STATUS_REGISTER "c5"
681 # define ARM_FAULT_ADDRESS_REGISTER "c6"
682 # define ARM_CACHE_OPERATIONS_REGISTER "c7"
683 # define ARM_TLB_OPERATIONS_REGISTER "c8"
684 # define ARM_READ_BUFFER_OPERATIONS_REGISTER "c9"
685 #endif /* __ASSEMBLER__ */
688 * SA-1100 Cache and MMU ID Register value
690 #define ARM_ID_MASK 0xFFFFFFF0
691 #define ARM_ID_VALUE 0x4401a110
694 * SA-1100 Cache Control Register Bit Fields and Masks
696 #define ARM_MMU_DISABLED 0x00000000
697 #define ARM_MMU_ENABLED 0x00000001
698 #define ARM_MMU_MASK 0x00000001
699 #define ARM_ADDRESS_FAULT_DISABLED 0x00000000
700 #define ARM_ADDRESS_FAULT_ENABLED 0x00000002
701 #define ARM_ADDRESS_FAULT_MASK 0x00000002
702 #define ARM_DATA_CACHE_DISABLED 0x00000000
703 #define ARM_DATA_CACHE_ENABLED 0x00000004
704 #define ARM_DATA_CACHE_MASK 0x00000004
705 #define ARM_WRITE_BUFFER_DISABLED 0x00000000
706 #define ARM_WRITE_BUFFER_ENABLED 0x00000008
707 #define ARM_WRITE_BUFFER_MASK 0x00000008
708 #define ARM_LITTLE_ENDIAN 0x00000000
709 #define ARM_BIG_ENDIAN 0x00000080
710 #define ARM_ACCESS_CHECKS_NONE 0x00000000
711 #define ARM_ACCESS_CHECKS_SYSTEM 0x00000100
712 #define ARM_ACCESS_CHECKS_ROM 0x00000200
713 #define ARM_INSTRUCTION_CACHE_DISABLED 0x00000000
714 #define ARM_INSTRUCTION_CACHE_ENABLED 0x00001000
715 #define ARM_INSTRUCTION_CACHE_MASK 0x00001000
716 #define ARM_VIRTUAL_IVR_BASE_00000000 0x00000000
717 #define ARM_VIRTUAL_IVR_BASE_FFFF0000 0x00002000
718 #define ARM_CONTROL_SBZ_MASK 0x00001FFF
721 * SA-1100 Translation Table Base Bit Masks
723 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
726 * SA-1100 Domain Access Control Bit Masks
728 #define ARM_DOMAIN_0_MASK 0x00000003
729 #define ARM_DOMAIN_1_MASK 0x0000000C
730 #define ARM_DOMAIN_2_MASK 0x00000030
731 #define ARM_DOMAIN_3_MASK 0x000000C0
732 #define ARM_DOMAIN_4_MASK 0x00000300
733 #define ARM_DOMAIN_5_MASK 0x00000C00
734 #define ARM_DOMAIN_6_MASK 0x00003000
735 #define ARM_DOMAIN_7_MASK 0x0000C000
736 #define ARM_DOMAIN_8_MASK 0x00030000
737 #define ARM_DOMAIN_9_MASK 0x000C0000
738 #define ARM_DOMAIN_10_MASK 0x00300000
739 #define ARM_DOMAIN_11_MASK 0x00C00000
740 #define ARM_DOMAIN_12_MASK 0x03000000
741 #define ARM_DOMAIN_13_MASK 0x0C000000
742 #define ARM_DOMAIN_14_MASK 0x30000000
743 #define ARM_DOMAIN_15_MASK 0xC0000000
745 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num))
746 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num))
747 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num))
750 * SA-1100 Fault Status Bit Masks
752 #define ARM_FAULT_STATUS_MASK 0x0000000F
753 #define ARM_DOMAIN_MASK 0x000000F0
754 #define ARM_DATA_BREAKPOINT_MASK 0x00000200
757 * SA-1100 Cache Control Operations Definitions
760 # define ARM_FLUSH_CACHE_INST_DATA_OPCODE 0x0
761 # define ARM_FLUSH_CACHE_INST_DATA_RM c7
762 # define ARM_FLUSH_CACHE_INST_OPCODE 0x0
763 # define ARM_FLUSH_CACHE_INST_RM c5
764 # define ARM_FLUSH_CACHE_DATA_OPCODE 0x0
765 # define ARM_FLUSH_CACHE_DATA_RM c6
766 # define ARM_FLUSH_CACHE_DATA_SINGLE_OPCODE 0x1
767 # define ARM_FLUSH_CACHE_DATA_SINGLE_RM c6
768 # define ARM_CLEAN_CACHE_DATA_ENTRY_OPCODE 0x1
769 # define ARM_CLEAN_CACHE_DATA_ENTRY_RM c10
770 # define ARM_DRAIN_CACHE_WRITE_BUFFER_OPCODE 0x4
771 # define ARM_DRAIN_CACHE_WRITE_BUFFER_RM c10
772 #else /* __ASSEMBLER__ */
773 # define ARM_FLUSH_CACHE_INST_DATA_OPCODE "0x0"
774 # define ARM_FLUSH_CACHE_INST_DATA_RM "c7"
775 # define ARM_FLUSH_CACHE_INST_OPCODE "0x0"
776 # define ARM_FLUSH_CACHE_INST_RM "c5"
777 # define ARM_FLUSH_CACHE_DATA_OPCODE "0x0"
778 # define ARM_FLUSH_CACHE_DATA_RM "c6"
779 # define ARM_FLUSH_CACHE_DATA_SINGLE_OPCODE "0x1"
780 # define ARM_FLUSH_CACHE_DATA_SINGLE_RM "c6"
781 # define ARM_CLEAN_CACHE_DATA_ENTRY_OPCODE "0x1"
782 # define ARM_CLEAN_CACHE_DATA_ENTRY_RM "c10"
783 # define ARM_DRAIN_CACHE_WRITE_BUFFER_OPCODE "0x4"
784 # define ARM_DRAIN_CACHE_WRITE_BUFFER_RM "c10"
785 #endif /* __ASSEMBLER__ */
788 * SA-1100 TLB Operations Definitions
791 # define ARM_FLUSH_INST_DATA_TLB_OPCODE 0x0
792 # define ARM_FLUSH_INST_DATA_TLB_RM c7
793 # define ARM_FLUSH_INST_TLB_OPCODE 0x0
794 # define ARM_FLUSH_INST_TLB_RM c5
795 # define ARM_FLUSH_DATA_TLB_OPCODE 0x0
796 # define ARM_FLUSH_DATA_TLB_RM c6
797 # define ARM_FLUSH_DATA_ENTRY_TLB_OPCODE 0x1
798 # define ARM_FLUSH_DATA_ENTRY_TLB_RM c6
799 #else /* __ASSEMBLER__ */
800 # define ARM_FLUSH_INST_DATA_TLB_OPCODE "0x0"
801 # define ARM_FLUSH_INST_DATA_TLB_RM "c7"
802 # define ARM_FLUSH_INST_TLB_OPCODE "0x0"
803 # define ARM_FLUSH_INST_TLB_RM "c5"
804 # define ARM_FLUSH_DATA_TLB_OPCODE "0x0"
805 # define ARM_FLUSH_DATA_TLB_RM "c6"
806 # define ARM_FLUSH_DATA_ENTRY_TLB_OPCODE "0x1"
807 # define ARM_FLUSH_DATA_ENTRY_TLB_RM "c6"
808 #endif /* __ASSEMBLER__ */
811 * SA-1100 Read-Buffer Operations Definitions
814 # define ARM_FLUSH_ALL_BUFFERS_OPCODE 0x0
815 # define ARM_FLUSH_ALL_BUFFERS_RM c0
816 # define ARM_FLUSH_BUFFER_0_OPCODE 0x1
817 # define ARM_FLUSH_BUFFER_0_RM c0
818 # define ARM_FLUSH_BUFFER_1_OPCODE 0x1
819 # define ARM_FLUSH_BUFFER_1_RM c1
820 # define ARM_FLUSH_BUFFER_2_OPCODE 0x1
821 # define ARM_FLUSH_BUFFER_2_RM c2
822 # define ARM_FLUSH_BUFFER_3_OPCODE 0x1
823 # define ARM_FLUSH_BUFFER_3_RM c3
824 # define ARM_LOAD_BUFFER_0_1_WORD_OPCODE 0x2
825 # define ARM_LOAD_BUFFER_0_1_WORD_RM c0
826 # define ARM_LOAD_BUFFER_0_4_WORD_OPCODE 0x2
827 # define ARM_LOAD_BUFFER_0_4_WORD_RM c4
828 # define ARM_LOAD_BUFFER_0_8_WORD_OPCODE 0x2
829 # define ARM_LOAD_BUFFER_0_8_WORD_RM c8
830 # define ARM_LOAD_BUFFER_1_1_WORD_OPCODE 0x2
831 # define ARM_LOAD_BUFFER_1_1_WORD_RM c1
832 # define ARM_LOAD_BUFFER_1_4_WORD_OPCODE 0x2
833 # define ARM_LOAD_BUFFER_1_4_WORD_RM c5
834 # define ARM_LOAD_BUFFER_1_8_WORD_OPCODE 0x2
835 # define ARM_LOAD_BUFFER_1_8_WORD_RM c9
836 # define ARM_LOAD_BUFFER_2_1_WORD_OPCODE 0x2
837 # define ARM_LOAD_BUFFER_2_1_WORD_RM c2
838 # define ARM_LOAD_BUFFER_2_4_WORD_OPCODE 0x2
839 # define ARM_LOAD_BUFFER_2_4_WORD_RM c6
840 # define ARM_LOAD_BUFFER_2_8_WORD_OPCODE 0x2
841 # define ARM_LOAD_BUFFER_2_8_WORD_RM cA
842 # define ARM_LOAD_BUFFER_3_1_WORD_OPCODE 0x2
843 # define ARM_LOAD_BUFFER_3_1_WORD_RM c3
844 # define ARM_LOAD_BUFFER_3_4_WORD_OPCODE 0x2
845 # define ARM_LOAD_BUFFER_3_4_WORD_RM c7
846 # define ARM_LOAD_BUFFER_3_8_WORD_OPCODE 0x2
847 # define ARM_LOAD_BUFFER_3_8_WORD_RM cB
848 # define ARM_DISABLE_USER_MCR_ACCESS_OPCODE 0x4
849 # define ARM_DISABLE_USER_MCR_ACCESS_RM c0
850 # define ARM_ENABLE_USER_MCR_ACCESS_OPCODE 0x5
851 # define ARM_ENABLE_USER_MCR_ACCESS_RM c0
852 #else /* __ASSEMBLER__ */
853 # define ARM_FLUSH_ALL_BUFFERS_OPCODE "0x0"
854 # define ARM_FLUSH_ALL_BUFFERS_RM "c0"
855 # define ARM_FLUSH_BUFFER_0_OPCODE "0x1"
856 # define ARM_FLUSH_BUFFER_0_RM "c0"
857 # define ARM_FLUSH_BUFFER_1_OPCODE "0x1"
858 # define ARM_FLUSH_BUFFER_1_RM "c1"
859 # define ARM_FLUSH_BUFFER_2_OPCODE "0x1"
860 # define ARM_FLUSH_BUFFER_2_RM "c2"
861 # define ARM_FLUSH_BUFFER_3_OPCODE "0x1"
862 # define ARM_FLUSH_BUFFER_3_RM "c3"
863 # define ARM_LOAD_BUFFER_0_1_WORD_OPCODE "0x2"
864 # define ARM_LOAD_BUFFER_0_1_WORD_RM "c0"
865 # define ARM_LOAD_BUFFER_0_4_WORD_OPCODE "0x2"
866 # define ARM_LOAD_BUFFER_0_4_WORD_RM "c4"
867 # define ARM_LOAD_BUFFER_0_8_WORD_OPCODE "0x2"
868 # define ARM_LOAD_BUFFER_0_8_WORD_RM "c8"
869 # define ARM_LOAD_BUFFER_1_1_WORD_OPCODE "0x2"
870 # define ARM_LOAD_BUFFER_1_1_WORD_RM "c1"
871 # define ARM_LOAD_BUFFER_1_4_WORD_OPCODE "0x2"
872 # define ARM_LOAD_BUFFER_1_4_WORD_RM "c5"
873 # define ARM_LOAD_BUFFER_1_8_WORD_OPCODE "0x2"
874 # define ARM_LOAD_BUFFER_1_8_WORD_RM "c9"
875 # define ARM_LOAD_BUFFER_2_1_WORD_OPCODE "0x2"
876 # define ARM_LOAD_BUFFER_2_1_WORD_RM "c2"
877 # define ARM_LOAD_BUFFER_2_4_WORD_OPCODE "0x2"
878 # define ARM_LOAD_BUFFER_2_4_WORD_RM "c6"
879 # define ARM_LOAD_BUFFER_2_8_WORD_OPCODE "0x2"
880 # define ARM_LOAD_BUFFER_2_8_WORD_RM "cA"
881 # define ARM_LOAD_BUFFER_3_1_WORD_OPCODE "0x2"
882 # define ARM_LOAD_BUFFER_3_1_WORD_RM "c3"
883 # define ARM_LOAD_BUFFER_3_4_WORD_OPCODE "0x2"
884 # define ARM_LOAD_BUFFER_3_4_WORD_RM "c7"
885 # define ARM_LOAD_BUFFER_3_8_WORD_OPCODE "0x2"
886 # define ARM_LOAD_BUFFER_3_8_WORD_RM "cB"
887 # define ARM_DISABLE_USER_MCR_ACCESS_OPCODE "0x4"
888 # define ARM_DISABLE_USER_MCR_ACCESS_RM "c0"
889 # define ARM_ENABLE_USER_MCR_ACCESS_OPCODE "0x5"
890 # define ARM_ENABLE_USER_MCR_ACCESS_RM "c0"
891 #endif /* __ASSEMBLER__ */
894 * ARM(R) First Level Descriptor Format Definitions
896 #ifndef __ASSEMBLER__
897 struct ARM_MMU_FIRST_LEVEL_FAULT {
901 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
903 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
908 int base_address : 23;
910 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
912 struct ARM_MMU_FIRST_LEVEL_SECTION {
921 int base_address : 12;
923 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
925 struct ARM_MMU_FIRST_LEVEL_RESERVED {
929 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
931 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
932 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
933 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, cacheable, bufferable, perm) \
935 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
938 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
939 desc.section.domain = 0; \
940 desc.section.c = (cacheable); \
941 desc.section.b = (bufferable); \
942 desc.section.ap = (perm); \
943 desc.section.base_address = (actual_base); \
944 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) = desc.word; \
947 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
949 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
950 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
951 struct ARM_MMU_FIRST_LEVEL_SECTION section;
952 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
955 #endif /* __ASSEMBLER__ */
957 #define ARM_UNCACHEABLE 0
958 #define ARM_CACHEABLE 1
959 #define ARM_UNBUFFERABLE 0
960 #define ARM_BUFFERABLE 1
962 #define ARM_ACCESS_PERM_NONE_NONE 0
963 #define ARM_ACCESS_PERM_RO_NONE 0
964 #define ARM_ACCESS_PERM_RO_RO 0
965 #define ARM_ACCESS_PERM_RW_NONE 1
966 #define ARM_ACCESS_PERM_RW_RO 2
967 #define ARM_ACCESS_PERM_RW_RW 3
969 #define ARM_SECTION_SIZE SZ_1M
970 #define ARM_SMALL_PAGE_SIZE SZ_4K
971 #define ARM_LARGE_PAGE_SIZE SZ_64K
973 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE SZ_16K
974 #define ARM_SECOND_LEVEL_PAGE_TABLE_SIZE SZ_1K
978 #endif // __ARM_CPU_H__