packages/devs/eth/arm/at91/v2_0/src/if_at91.c

   1 //==========================================================================
   2 //
   3 //      if_at91.c
   4 //
   5 //
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 // Copyright (C) 2006 Andrew Lunn <andrew.lunn@ascom.ch>
  13 //
  14 // eCos is free software; you can redistribute it and/or modify it under
  15 // the terms of the GNU General Public License as published by the Free
  16 // Software Foundation; either version 2 or (at your option) any later version.
  17 //
  18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  21 // for more details.
  22 //
  23 // You should have received a copy of the GNU General Public License along
  24 // with eCos; if not, write to the Free Software Foundation, Inc.,
  25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  26 //
  27 // As a special exception, if other files instantiate templates or use macros
  28 // or inline functions from this file, or you compile this file and link it
  29 // with other works to produce a work based on this file, this file does not
  30 // by itself cause the resulting work to be covered by the GNU General Public
  31 // License. However the source code for this file must still be made available
  32 // in accordance with section (3) of the GNU General Public License.
  33 //
  34 // This exception does not invalidate any other reasons why a work based on
  35 // this file might be covered by the GNU General Public License.
  36 // -------------------------------------------
  37 //####ECOSGPLCOPYRIGHTEND####
  38 //==========================================================================
  39 //#####DESCRIPTIONBEGIN####
  40 //
  41 // Author(s):    Andrew Lunn, John Eigelaar
  42 // Contributors:
  43 // Date:         2006-05-10
  44 // Purpose:
  45 // Description:
  46 //
  47 //####DESCRIPTIONEND####
  48 //
  49 //========================================================================*/
  50
  51 #include <pkgconf/system.h>
  52 #include <pkgconf/hal.h>
  53 #include <pkgconf/devs_eth_arm_at91.h>
  54 #include <pkgconf/io_eth_drivers.h>
  55 #if defined(CYGPKG_REDBOOT)
  56    #include <pkgconf/redboot.h>
  57 #endif
  58
  59 #include <cyg/hal/hal_io.h>
  60 #include <cyg/hal/hal_intr.h>
  61 #include <cyg/hal/hal_arch.h>
  62 #include <cyg/hal/drv_api.h>
  63 #include <cyg/hal/hal_diag.h>
  64 #include <cyg/infra/cyg_type.h>
  65 #include <cyg/infra/cyg_ass.h>
  66 #include <cyg/infra/diag.h>
  67 #include <cyg/io/eth/netdev.h>
  68 #include <cyg/io/eth/eth_drv.h>
  69 #include <cyg/io/eth/eth_drv_stats.h>
  70 #include <cyg/io/eth_phy.h>
  71 #include <errno.h>
  72 #include <string.h>
  73
  74 // Set up the level of debug output
  75 #if CYGPKG_DEVS_ETH_ARM_AT91_DEBUG_LEVEL > 0
  76    #define debug1_printf(args...) diag_printf(args)
  77 #else
  78    #define debug1_printf(args...)
  79 #endif
  80 #if CYGPKG_DEVS_ETH_ARM_AT91_DEBUG_LEVEL > 1
  81    #define debug2_printf(args...) diag_printf(args)
  82 #else
  83    #define debug2_printf(args...)
  84 #endif
  85
  86 //Driver interface callbacks
  87 #define _eth_drv_init(sc,mac)                   \
  88   (sc->funs->eth_drv->init)(sc,(unsigned char *)mac)
  89 #define _eth_drv_tx_done(sc,key,status)         \
  90   (sc->funs->eth_drv->tx_done)(sc,key,status)
  91 #define _eth_drv_recv(sc,len)                   \
  92   (sc->funs->eth_drv->recv)(sc,len)
  93
  94 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
  95 static cyg_uint32
  96 at91_eth_isr (cyg_vector_t vector, cyg_addrword_t data);
  97 #endif
  98
  99 // --------------------------------------------------------------
 100 // RedBoot configuration options for managing ESAs for us
 101
 102 // Decide whether to have redboot config vars for it...
 103 #if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYGPKG_REDBOOT_NETWORKING)
 104    #include <redboot.h>
 105    #include <flash_config.h>
 106
 107    #ifdef CYGSEM_DEVS_ETH_ARM_AT91_REDBOOT_HOLDS_ESA_ETH0
 108 RedBoot_config_option("Network hardware address [MAC] for eth0",
 109                       eth0_esa_data,
 110                       ALWAYS_ENABLED, true,
 111                       CONFIG_ESA, 0);
 112    #endif
 113
 114 #endif  // CYGPKG_REDBOOT_NETWORKING && CYGSEM_REDBOOT_FLASH_CONFIG
 115
 116 // and initialization code to read them
 117 // - independent of whether we are building RedBoot right now:
 118 #ifdef CYGPKG_DEVS_ETH_ARM_AT91_REDBOOT_HOLDS_ESA
 119
 120    #include <cyg/hal/hal_if.h>
 121
 122    #ifndef CONFIG_ESA
 123       #define CONFIG_ESA (6)
 124    #endif
 125
 126   #define CYGHWR_DEVS_ETH_ARM_AT91_GET_ESA( mac_address, ok )           \
 127   CYG_MACRO_START                                                       \
 128   ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,       \
 129                                     "eth0_esa_data",                    \
 130                                     mac_address,                        \
 131                                     CONFIG_ESA);                        \
 132   CYG_MACRO_END
 133
 134 #endif // CYGPKG_DEVS_ETH_AT91_ETH_REDBOOT_HOLDS_ESA
 135
 136 //============================================================================
 137
 138 // Private Data structures
 139
 140 #ifndef AT91_EMAC_RX_BUFF_SIZE
 141 #define AT91_EMAC_RX_BUFF_SIZE  128
 142 #endif
 143
 144 // Receive Buffer Descriptor
 145 typedef struct rbd_s
 146 {
 147    cyg_uint32 addr;
 148    cyg_uint32 sr;
 149 } rbd_t;
 150
 151 // Receive Buffer
 152 typedef struct rb_s
 153 {
 154    cyg_uint8 rb[AT91_EMAC_RX_BUFF_SIZE];
 155 } rb_t;
 156
 157 // Transmit Buffer Descriptor
 158 typedef struct tbd_s
 159 {
 160    cyg_uint32 addr;
 161    cyg_uint32 sr;
 162 } tbd_t;
 163
 164 // AT91 Ethernet private data
 165 typedef struct at91_eth_priv_s
 166 {
 167    cyg_uint32    intr_vector;
 168    char *esa_key;      // RedBoot 'key' for device ESA
 169    cyg_uint8 *enaddr;
 170    cyg_uint32 base;    // Base address of device
 171    eth_phy_access_t *phy;
 172    rbd_t rbd[CYGNUM_DEVS_ETH_ARM_AT91_RX_BUFS];
 173    rb_t  rb[CYGNUM_DEVS_ETH_ARM_AT91_RX_BUFS];
 174    tbd_t tbd[CYGNUM_DEVS_ETH_ARM_AT91_TX_BUFS];
 175    unsigned long curr_tx_key;
 176    cyg_bool tx_busy;
 177    cyg_uint32 last_tbd_idx;
 178    cyg_uint32 curr_tbd_idx;
 179    cyg_uint32 curr_rbd_idx;
 180 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
 181    cyg_interrupt intr;
 182    cyg_handle_t  intr_handle;
 183 #endif
 184 } at91_eth_priv_t;
 185
 186 //============================================================================
 187 // PHY access bits and pieces
 188 //
 189
 190 static void
 191 at91_mdio_enable(void)
 192 {
 193    cyg_uint32 val;
 194    HAL_READ_UINT32(AT91_EMAC + AT91_EMAC_NCR, val);
 195    val |= AT91_EMAC_NCR_MPE;    /* enable management port */
 196    HAL_WRITE_UINT32(AT91_EMAC + AT91_EMAC_NCR, val);
 197 }
 198
 199 static void
 200 at91_mdio_disable(void)
 201 {
 202    cyg_uint32 val;
 203    HAL_READ_UINT32(AT91_EMAC + AT91_EMAC_NCR, val);
 204    val &= ~AT91_EMAC_NCR_MPE;    /* disable management port */
 205    HAL_WRITE_UINT32(AT91_EMAC + AT91_EMAC_NCR, val);
 206 }
 207
 208 // Write one of the PHY registers via the MII bus
 209 static void
 210 at91_write_phy(int reg_addr, int phy_addr, unsigned short data)
 211 {
 212    cyg_uint32 val, cnt=0;
 213
 214    CYG_ASSERTC(reg_addr >= 0 && reg_addr <= AT91_EMAC_MAN_REGA_MASK);
 215    CYG_ASSERTC(phy_addr >= 0 && phy_addr <= AT91_EMAC_MAN_PHY_MASK);
 216
 217    val = (AT91_EMAC_MAN_SOF  |
 218          AT91_EMAC_MAN_WR   |
 219          AT91_EMAC_MAN_CODE |
 220          AT91_EMAC_MAN_PHYA(phy_addr) |
 221          AT91_EMAC_MAN_REGA(reg_addr) |
 222          AT91_EMAC_MAN_DATA(data));
 223
 224    HAL_WRITE_UINT32(AT91_EMAC + AT91_EMAC_MAN, val);
 225
 226    /* Wait until IDLE bit in Network Status register is cleared */
 227    while (cnt < 1000000)
 228    {
 229       HAL_READ_UINT32((AT91_EMAC + AT91_EMAC_NSR), val);
 230       if (!(val & AT91_EMAC_NSR_IDLE))
 231          break;
 232    }
 233    CYG_ASSERTC(cnt < 1000000);
 234 }
 235
 236
 237 // Read one of the PHY registers via the MII bus
 238 static bool
 239 at91_read_phy(int reg_addr, int phy_addr, unsigned short *data)
 240 {
 241    cyg_uint32 val;
 242
 243    CYG_ASSERTC(reg_addr >= 0 && reg_addr <= AT91_EMAC_MAN_REGA_MASK);
 244    CYG_ASSERTC(phy_addr >= 0 && phy_addr <= AT91_EMAC_MAN_PHY_MASK);
 245
 246    val = (AT91_EMAC_MAN_SOF  |
 247          AT91_EMAC_MAN_RD   |
 248          AT91_EMAC_MAN_CODE |
 249          AT91_EMAC_MAN_PHYA(phy_addr) |
 250          AT91_EMAC_MAN_REGA(reg_addr));
 251
 252
 253    HAL_WRITE_UINT32(AT91_EMAC + AT91_EMAC_MAN, val);
 254    /* Wait until IDLE bit in Network Status register is cleared */
 255    do
 256    {
 257       HAL_READ_UINT32((AT91_EMAC + AT91_EMAC_NSR), val);
 258    }while(val & AT91_EMAC_NSR_IDLE);
 259
 260    HAL_DELAY_US(50);
 261
 262    HAL_READ_UINT32(AT91_EMAC + AT91_EMAC_MAN, val);
 263    *data = val & AT91_EMAC_MAN_DATA_MASK;
 264
 265    return (true);
 266 }
 267
 268 // Enable the MDIO bit in MAC control register so that we can talk to
 269 // the PHY. Also set the clock divider so that MDC is less than 2.5MHz.
 270 static void
 271 at91_init_phy(void)
 272 {
 273    cyg_uint32 cfg;
 274    cyg_uint32 div;
 275
 276    HAL_READ_UINT32(AT91_EMAC + AT91_EMAC_NCFG, cfg);
 277    cfg &=~ AT91_EMAC_NCFG_CLK_MASK;
 278
 279    div = (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / 2500000);
 280    if (div < 8)
 281    {
 282       cfg |= AT91_EMAC_NCFG_CLK_HCLK_8;
 283    }
 284    else if (div < 16)
 285    {
 286       cfg |= AT91_EMAC_NCFG_CLK_HCLK_16;
 287    }
 288    else if (div < 32)
 289    {
 290       cfg |= AT91_EMAC_NCFG_CLK_HCLK_32;
 291    }
 292    else if (div < 64)
 293    {
 294       cfg |= AT91_EMAC_NCFG_CLK_HCLK_64;
 295    }
 296    else
 297    {
 298       CYG_FAIL("Unable to program MII clock");
 299    }
 300
 301    HAL_WRITE_UINT32(AT91_EMAC + AT91_EMAC_NCFG, cfg);
 302 }
 303
 304 ETH_PHY_REG_LEVEL_ACCESS_FUNS(at91_phy,
 305                               at91_init_phy,
 306                               NULL,
 307                               at91_write_phy,
 308                               at91_read_phy);
 309
 310 //======================================================================
 311 // Receiver buffer handling
 312
 313 // Initialize the receiver buffers and descriptors
 314 static void
 315 at91_rb_init(at91_eth_priv_t *priv)
 316 {
 317    int i;
 318    for (i = 0 ; i < CYGNUM_DEVS_ETH_ARM_AT91_RX_BUFS; i++)
 319    {
 320       priv->rbd[i].addr = ((cyg_uint32)&priv->rb[i]) & AT91_EMAC_RBD_ADDR_MASK;
 321       priv->rbd[i].sr = 0;
 322    }
 323    // Set the wrap bit on the last entry
 324    priv->rbd[CYGNUM_DEVS_ETH_ARM_AT91_RX_BUFS-1].addr |=
 325      AT91_EMAC_RBD_ADDR_WRAP;
 326 }
 327
 328 //======================================================================
 329 // Transmit buffer handling
 330
 331 // Initialize the transmit buffer descriptors
 332 static void
 333 at91_tb_init(at91_eth_priv_t *priv)
 334 {
 335    int i;
 336    for (i = 0 ; i < CYGNUM_DEVS_ETH_ARM_AT91_TX_BUFS; i++)
 337    {
 338       priv->tbd[i].addr = 0;
 339       priv->tbd[i].sr = AT91_EMAC_TBD_SR_USED;
 340    }
 341    // Set the wrap bit on the last entry
 342    priv->tbd[CYGNUM_DEVS_ETH_ARM_AT91_TX_BUFS-1].sr |= AT91_EMAC_TBD_SR_WRAP;
 343 }
 344
 345 //======================================================================
 346 // Enable and Disable of the receiver and transmitter.
 347
 348 static void
 349 at91_disable_rx(at91_eth_priv_t *priv)
 350 {
 351    cyg_uint32 ctl;
 352
 353    HAL_READ_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 354    ctl &= ~AT91_EMAC_NCR_RE;
 355    HAL_WRITE_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 356 }
 357
 358 static void
 359 at91_disable_tx(at91_eth_priv_t *priv)
 360 {
 361    cyg_uint32 ctl;
 362
 363    HAL_READ_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 364    ctl &= ~AT91_EMAC_NCR_TX;
 365    HAL_WRITE_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 366 }
 367
 368 static void
 369 at91_enable_rx(at91_eth_priv_t *priv)
 370 {
 371    cyg_uint32 ctl;
 372
 373    HAL_READ_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 374    ctl |= AT91_EMAC_NCR_RE;
 375    HAL_WRITE_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 376 }
 377
 378 static void
 379 at91_enable_tx(at91_eth_priv_t *priv)
 380 {
 381    cyg_uint32 ctl;
 382
 383    HAL_READ_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 384    ctl |= AT91_EMAC_NCR_TX;
 385    HAL_WRITE_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 386 }
 387
 388 static void
 389 at91_enable(at91_eth_priv_t *priv)
 390 {
 391    at91_enable_tx(priv);
 392    at91_enable_rx(priv);
 393 }
 394
 395 static void
 396 at91_disable(at91_eth_priv_t *priv)
 397 {
 398    at91_disable_tx(priv);
 399    at91_disable_rx(priv);
 400 }
 401
 402 static void
 403 at91_start_transmitter(at91_eth_priv_t *priv)
 404 {
 405    cyg_uint32 ctl;
 406
 407    HAL_READ_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 408    ctl |= AT91_EMAC_NCR_TSTART;
 409    HAL_WRITE_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 410 }
 411
 412
 413 //======================================================================
 414 // Initialization code
 415
 416 // Configure the pins so that the EMAC has control of them. This
 417 // assumes the MII is used, not the RMII
 418 static void
 419 at91_cfg_pins(void)
 420 {
 421    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_EREFCK);
 422    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ECRS);
 423    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ECOL);
 424
 425    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ERXDV);
 426    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ERX0);
 427    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ERX1);
 428    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ERX2);
 429    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ERX3);
 430    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ERXER);
 431    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ERXCK);
 432
 433    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ETXEN);
 434    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ETX0);
 435    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ETX1);
 436    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ETX2);
 437    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ETX3);
 438    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_ETXER);
 439
 440    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_EMDC);
 441    HAL_ARM_AT91_PIO_CFG(AT91_EMAC_EMDIO);
 442 }
 443
 444 // Set a specific address match to a given address. Packets received which
 445 // match this address will be passed on.
 446 static void
 447 at91_set_mac(at91_eth_priv_t * priv, cyg_uint8 * enaddr, int sa)
 448 {
 449    cyg_uint32 hi, lo;
 450
 451    CYG_ASSERTC(sa > 0 && sa < 5);
 452    sa--;
 453
 454    lo = ((enaddr[3] << 24) |
 455          (enaddr[2] << 16) |
 456          (enaddr[1] <<  8) |
 457          (enaddr[0]));
 458
 459    hi = ((enaddr[5] <<  8) |
 460          (enaddr[4]));
 461
 462    HAL_WRITE_UINT32(priv->base + AT91_EMAC_SA1L + (8*sa), lo);
 463    HAL_WRITE_UINT32(priv->base + AT91_EMAC_SA1H + (8*sa), hi);
 464 }
 465
 466 static void
 467 at91_clear_stats(at91_eth_priv_t *priv)
 468 {
 469    cyg_uint32 ctl;
 470
 471    HAL_READ_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 472    ctl |= AT91_EMAC_NCR_CSR;
 473    HAL_WRITE_UINT32(priv->base + AT91_EMAC_NCR, ctl);
 474 }
 475
 476 // Enable and Disable of the receiver and transmitter.
 477 // Initialize the interface. This configures the interface ready for use.
 478 // Interrupts are grabbed etc. This means the start function has
 479 // little to do except enable the receiver
 480 static bool
 481 at91_eth_init(struct cyg_netdevtab_entry *tab)
 482 {
 483    struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
 484    at91_eth_priv_t *priv = (at91_eth_priv_t *)sc->driver_private;
 485    bool esa_ok = false;
 486    unsigned char enaddr[6] = { CYGPKG_DEVS_ETH_ARM_AT91_MACADDR};
 487    unsigned char enzero[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
 488    unsigned short phy_state = 0;
 489    cyg_uint32 ncfg = 0;
 490
 491    debug1_printf("\nAT91_ETH: Initialising @ %x\n",priv->base);
 492
 493    priv->tx_busy = false;
 494    priv->curr_tbd_idx = 0;
 495    priv->curr_rbd_idx = 0;
 496
 497    // Enable the clock to the EMAC
 498    HAL_WRITE_UINT32(AT91_PMC + AT91_PMC_PCER, AT91_PMC_PCER_EMAC);
 499    HAL_WRITE_UINT32(AT91_PMC + AT91_PMC_PCER, AT91_PMC_PCER_PIOB);
 500    HAL_WRITE_UINT32(AT91_PMC + AT91_PMC_PCER, AT91_PMC_PCER_PIOA);
 501
 502    //at91_disable(priv);
 503    at91_cfg_pins();
 504
 505    /* Enable  IO Clock */
 506    HAL_WRITE_UINT32(priv->base+AT91_EMAC_USRIO,AT91_EMAC_USRIO_CLKEN);
 507
 508    /* Disable all the interrupts for the moment            */
 509    /* The Start function actually enables all that we need */
 510    //HAL_WRITE_UINT32(priv->base + AT91_EMAC_IDR, 0x3FFF);
 511
 512    // If we are building an interrupt enabled version, install the
 513    // interrupt handler
 514 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
 515    debug1_printf("AT91_ETH: Installing Interrupts on IRQ %d\n",
 516                  priv->intr_vector);
 517    cyg_drv_interrupt_create(priv->intr_vector,
 518                             4,
 519                             (cyg_addrword_t)sc,
 520                             at91_eth_isr,
 521                             eth_drv_dsr,
 522                             &priv->intr_handle,
 523                             &priv->intr);
 524
 525    cyg_drv_interrupt_attach(priv->intr_handle);
 526    cyg_drv_interrupt_unmask(priv->intr_vector);
 527 #endif
 528
 529 #ifdef CYGHWR_DEVS_ETH_ARM_AT91_GET_ESA
 530    // Get MAC address from RedBoot configuration variables
 531    CYGHWR_DEVS_ETH_ARM_AT91_GET_ESA(&enaddr[0], esa_ok);
 532    // If this call fails myMacAddr is unchanged and MAC address from
 533    // CDL is used
 534 #endif
 535
 536    if (!esa_ok)
 537    {
 538       // Can't figure out ESA
 539       debug1_printf("AT91_ETH - Warning! ESA unknown\n");
 540    }
 541    debug1_printf("AT91_ETH: %02x:%02x:%02x:%02x:%02x:%02x\n",
 542                  enaddr[0],enaddr[1],enaddr[2],
 543                  enaddr[3],enaddr[4],enaddr[5]);
 544
 545    // Give the EMAC its address
 546    at91_set_mac(priv, enaddr, 1);
 547    at91_set_mac(priv, enzero, 2);
 548    at91_set_mac(priv, enzero, 3);
 549    at91_set_mac(priv, enzero, 4);
 550
 551    // Setup the receiver buffers and descriptors
 552    at91_rb_init(priv);
 553
 554    // And tell the EMAC where the first receive buffer descriptor is
 555    HAL_WRITE_UINT32(priv->base + AT91_EMAC_RBQP, (cyg_uint32)priv->rbd);
 556
 557    // Setup the transmit descriptors
 558    at91_tb_init(priv);
 559
 560    // And tell the EMAC where the first transmit buffer descriptor is
 561    HAL_WRITE_UINT32(priv->base + AT91_EMAC_TBQP, (cyg_uint32)priv->tbd);
 562
 563    // Setup the PHY
 564    CYG_ASSERTC(priv->phy);
 565
 566    at91_mdio_enable();
 567    if (!_eth_phy_init(priv->phy))
 568    {
 569       at91_mdio_disable();
 570       return (false);
 571    }
 572
 573    // Get the current mode and print it
 574    phy_state = _eth_phy_state(priv->phy);
 575    at91_mdio_disable();
 576
 577    HAL_READ_UINT32(priv->base + AT91_EMAC_NCFG,ncfg);
 578
 579
 580    if ((phy_state & ETH_PHY_STAT_LINK) != 0)
 581    {
 582       if (((phy_state & ETH_PHY_STAT_100MB) != 0))
 583       {
 584          debug1_printf("AT91_ETH: 100Mbyte/s");
 585          ncfg |= AT91_EMAC_NCFG_SPD_100Mbps;
 586       }
 587       else
 588       {
 589          debug1_printf("AT91_ETH: 10Mbyte/s");
 590          ncfg &= ~(AT91_EMAC_NCFG_SPD_100Mbps);
 591       }
 592       if((phy_state & ETH_PHY_STAT_FDX))
 593       {
 594          debug1_printf(" Full Duplex\n");
 595          ncfg |= AT91_EMAC_NCFG_FD;
 596       }
 597       else
 598       {
 599          debug1_printf(" Half Duplex\n");
 600          ncfg &= ~(AT91_EMAC_NCFG_FD);
 601       }
 602    }
 603    else
 604    {
 605       debug1_printf("AT91_ETH: No Link\n");
 606    }
 607
 608
 609    //Setup the network configuration
 610    ncfg |= (AT91_EMAC_NCFG_RLCE);
 611
 612    HAL_WRITE_UINT32(priv->base + AT91_EMAC_NCFG,ncfg);
 613
 614    // Clear the Statistics counters;
 615    at91_clear_stats(priv);
 616
 617
 618    /* Clear the status registers */
 619    HAL_READ_UINT32(priv->base + AT91_EMAC_ISR,ncfg);
 620    HAL_READ_UINT32(priv->base + AT91_EMAC_RSR,ncfg);
 621    HAL_WRITE_UINT32(priv->base + AT91_EMAC_RSR,ncfg);
 622    HAL_READ_UINT32(priv->base + AT91_EMAC_TSR,ncfg);
 623    HAL_WRITE_UINT32(priv->base + AT91_EMAC_TSR,ncfg);
 624
 625    // Initialize the upper layer driver
 626    _eth_drv_init(sc,enaddr);
 627
 628    return (true);
 629 }
 630
 631 // This function is called to stop the interface.
 632 static void
 633 at91_eth_stop(struct eth_drv_sc *sc)
 634 {
 635    at91_eth_priv_t *priv = (at91_eth_priv_t *)sc->driver_private;
 636
 637    at91_disable(priv);
 638 }
 639
 640 // This function is called to "start up" the interface. It may be called
 641 // multiple times, even when the hardware is already running.
 642 static void
 643 at91_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
 644 {
 645    at91_eth_priv_t *priv = (at91_eth_priv_t *)sc->driver_private;
 646    cyg_uint32 bits;
 647
 648    // Enable the interrupts we are interested in
 649    // TODO: We probably need to add at least the RBNA interrupt here
 650    //       as well in order to do some error handling
 651    bits = (AT91_EMAC_ISR_RCOM | AT91_EMAC_ISR_TCOM);
 652
 653    HAL_WRITE_UINT32(priv->base + AT91_EMAC_IER, bits);
 654
 655    // Enable the receiver and transmitter
 656    at91_enable(priv);
 657 }
 658
 659 // This function is called for low level "control" operations
 660 static int
 661 at91_eth_control(struct eth_drv_sc *sc, unsigned long key,
 662                  void *data, int length)
 663 {
 664
 665    switch (key)
 666    {
 667       case ETH_DRV_SET_MAC_ADDRESS:
 668          {
 669             if(length >= ETHER_ADDR_LEN)
 670             {
 671                at91_eth_stop(sc);
 672
 673                cyg_uint8 * enaddr = (cyg_uint8 *)data;
 674                debug1_printf("AT91_ETH: %02x:%02x:%02x:%02x:%02x:%02x\n",
 675                              enaddr[0],enaddr[1],enaddr[2],
 676                              enaddr[3],enaddr[4],enaddr[5]);
 677
 678                at91_set_mac((at91_eth_priv_t *)sc->driver_private,enaddr,1);
 679                at91_eth_start(sc,enaddr,0);
 680                return 0;
 681             }
 682             return 1;
 683          }
 684       default:
 685          {
 686             diag_printf("%s.%d: key %lx\n", __FUNCTION__, __LINE__, key);
 687             return (1);
 688          }
 689    }
 690
 691 }
 692
 693 // This function is called to see if another packet can be sent.
 694 // It should return the number of packets which can be handled.
 695 // Zero should be returned if the interface is busy and can not send
 696 // any more.
 697 //
 698 // We allocate one buffer descriptor per scatter/gather entry. We assume that
 699 // a typical packet will not have more than 3 such entries, and so we say we
 700 // can send a packet when we have 3 or more buffer descriptors free
 701 //
 702 // TODO: Implement what the comment actually says!
 703 static int
 704 at91_eth_can_send(struct eth_drv_sc *sc)
 705 {
 706    int can_send;
 707    at91_eth_priv_t *priv = (at91_eth_priv_t *)sc->driver_private;
 708    if(priv->tx_busy)
 709    {
 710       can_send = 0;
 711    }
 712    else
 713    {
 714       can_send = 1;
 715    }
 716    return (can_send);
 717 }
 718
 719 // This routine is called to send data to the hardware
 720 static void
 721 at91_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
 722               int total_len, unsigned long key)
 723 {
 724    at91_eth_priv_t *priv = (at91_eth_priv_t *)sc->driver_private;
 725    int i;
 726    cyg_uint32 sr;
 727
 728    priv->tx_busy = true;
 729
 730    priv->last_tbd_idx = priv->curr_tbd_idx;
 731
 732    for(i = 0;i<sg_len;i++)
 733    {
 734       priv->tbd[priv->curr_tbd_idx].addr = sg_list[i].buf;
 735
 736       sr = (sg_list[i].len & AT91_EMAC_TBD_SR_LEN_MASK);
 737       // Set the End Of Frame bit in the last descriptor
 738       if(i == (sg_len-1))
 739       {
 740          sr |= AT91_EMAC_TBD_SR_EOF;
 741       }
 742
 743       if(priv->curr_tbd_idx < (CYGNUM_DEVS_ETH_ARM_AT91_TX_BUFS-1))
 744       {
 745          priv->tbd[priv->curr_tbd_idx].sr = sr;
 746          priv->curr_tbd_idx++;
 747       }
 748       else
 749       {
 750          priv->tbd[priv->curr_tbd_idx].sr = (sr | AT91_EMAC_TBD_SR_WRAP);
 751          priv->curr_tbd_idx = 0;
 752       }
 753    }
 754
 755    // Store away the key for when the transmit has completed
 756    // and we need to tell the stack which transmit has completed.
 757    priv->curr_tx_key = key;
 758
 759    at91_start_transmitter(priv);
 760 }
 761
 762 static void at91_reset_tbd(at91_eth_priv_t *priv)
 763 {
 764      while(priv->curr_tbd_idx != priv->last_tbd_idx)
 765      {
 766         if(priv->last_tbd_idx == (CYGNUM_DEVS_ETH_ARM_AT91_TX_BUFS-1))
 767         {
 768            priv->tbd[priv->last_tbd_idx].sr =
 769              (AT91_EMAC_TBD_SR_USED|AT91_EMAC_TBD_SR_WRAP);
 770            priv->last_tbd_idx = 0;
 771         }
 772         else
 773         {
 774            priv->tbd[priv->last_tbd_idx].sr = AT91_EMAC_TBD_SR_USED;
 775            priv->last_tbd_idx++;
 776         }
 777      }
 778 }
 779
 780
 781 //======================================================================
 782
 783 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
 784 static cyg_uint32
 785 at91_eth_isr (cyg_vector_t vector, cyg_addrword_t data)
 786 {
 787    struct eth_drv_sc *sc = (struct eth_drv_sc *)data;
 788    at91_eth_priv_t *priv = (at91_eth_priv_t *)sc->driver_private;
 789    cyg_uint32 ret;
 790    cyg_uint32 isr;
 791
 792    /* Get the interrupt status */
 793    HAL_READ_UINT32(priv->base+AT91_EMAC_ISR,isr);
 794
 795    ret = CYG_ISR_HANDLED;
 796
 797    //TODO: We should probably be handling some of the error interrupts as well
 798    if(isr & AT91_EMAC_ISR_TCOM)
 799    {
 800       ret = CYG_ISR_CALL_DSR;
 801    }
 802
 803    if(isr & AT91_EMAC_ISR_RCOM)
 804    {
 805       ret = CYG_ISR_CALL_DSR;
 806    }
 807    cyg_interrupt_acknowledge(vector);
 808    return(ret);
 809 }
 810 #endif
 811
 812 static void
 813 at91_eth_deliver(struct eth_drv_sc *sc)
 814 {
 815    at91_eth_priv_t *priv = (at91_eth_priv_t *)sc->driver_private;
 816
 817    cyg_uint32 tsr;
 818    cyg_uint32 rsr;
 819
 820    cyg_uint32 ctr;
 821    cyg_uint32 cnt;
 822    cyg_uint32 idx;
 823
 824    /* Get the Transmit Status */
 825    HAL_READ_UINT32(priv->base+AT91_EMAC_TSR,tsr);
 826    HAL_WRITE_UINT32(priv->base+AT91_EMAC_TSR,tsr);
 827
 828    /* Get the Receive Status */
 829    HAL_READ_UINT32(priv->base+AT91_EMAC_RSR,rsr);
 830    HAL_WRITE_UINT32(priv->base+AT91_EMAC_RSR,rsr);
 831
 832
 833    //TODO: The interrupts other than RCOMP and TCOMP needs to be
 834    //      handled properly especially stuff like RBNA which could have
 835    //      serious effects on driver performance
 836
 837    /* Service the TX buffers */
 838    if (tsr&AT91_EMAC_TSR_COL)  //1
 839    {
 840       debug1_printf("AT91_ETH: Tx COL\n");
 841    }
 842
 843    if (tsr&AT91_EMAC_TSR_RLE)  //2
 844    {
 845       debug1_printf("AT91_ETH: Tx RLE\n");
 846    }
 847
 848    if (tsr&AT91_EMAC_TSR_BNQ)  //4
 849    {
 850       debug1_printf("AT91_ETH: Tx BEX\n");
 851    }
 852
 853    if (tsr&AT91_EMAC_TSR_UND)  //6
 854    {
 855       debug1_printf("AT91_ETH: Tx UND\n");
 856    }
 857
 858    /* Check that the last transmission is completed */
 859    if (tsr&AT91_EMAC_TSR_COMP) //5
 860    {
 861       at91_reset_tbd(priv);
 862       _eth_drv_tx_done(sc,priv->curr_tx_key,0);
 863       priv->tx_busy = false;
 864    }
 865
 866    /* Service the RX buffers when we get something */
 867    if (rsr&AT91_EMAC_RSR_REC)
 868    {
 869       /* Do this all until we find the first EMAC Buffer */
 870       while (priv->rbd[priv->curr_rbd_idx].addr & AT91_EMAC_RBD_ADDR_OWNER_SW)
 871       {
 872
 873          //Firstly walk through to either the first buffer that belongs
 874          // to the controller or the first SOF
 875          while ((priv->rbd[priv->curr_rbd_idx].addr &
 876                  AT91_EMAC_RBD_ADDR_OWNER_SW) &&
 877                 !(priv->rbd[priv->curr_rbd_idx].sr &
 878                   AT91_EMAC_RBD_SR_SOF))
 879          {
 880             priv->rbd[priv->curr_rbd_idx].addr &=
 881               ~(AT91_EMAC_RBD_ADDR_OWNER_SW);
 882             priv->curr_rbd_idx++;
 883             if (priv->curr_rbd_idx >= CYGNUM_DEVS_ETH_ARM_AT91_RX_BUFS)
 884             {
 885                priv->curr_rbd_idx = 0;
 886             }
 887          }
 888
 889          /* Check that we did find a SOF*/
 890          if ((priv->rbd[priv->curr_rbd_idx].addr &
 891               AT91_EMAC_RBD_ADDR_OWNER_SW) &&
 892              (priv->rbd[priv->curr_rbd_idx].sr & AT91_EMAC_RBD_SR_SOF))
 893          {
 894             cnt = 0;
 895             for (ctr=0;ctr<CYGNUM_DEVS_ETH_ARM_AT91_RX_BUFS;ctr++)
 896             {
 897                idx = (ctr+priv->curr_rbd_idx)%CYGNUM_DEVS_ETH_ARM_AT91_RX_BUFS;
 898                cnt += (priv->rbd[idx].sr & AT91_EMAC_RBD_SR_LEN_MASK);
 899                if (priv->rbd[idx].sr & AT91_EMAC_RBD_SR_EOF)
 900                {
 901                   /* The recv function will adjust the current buffer idx
 902                      after the buffer has been cleared
 903                    */
 904                   if (cnt)
 905                      _eth_drv_recv(sc,cnt);
 906                   break;
 907                }
 908             }
 909          }
 910       }
 911    }
 912
 913    if (rsr&AT91_EMAC_RSR_BNA)
 914    {
 915       debug1_printf("AT91_ETH: Rx BNA\n");
 916    }
 917    if (rsr&AT91_EMAC_RSR_OVR)
 918    {
 919       debug1_printf("AT91_ETH: Rx OVR\n");
 920    }
 921
 922 }
 923
 924 static void
 925 at91_eth_recv(struct eth_drv_sc *sc,
 926               struct eth_drv_sg *sg_list,
 927               int sg_len)
 928 {
 929    at91_eth_priv_t *priv = (at91_eth_priv_t *)sc->driver_private;
 930    int i;
 931    cyg_uint32 bytes_in_buffer;
 932    cyg_uint32 bytes_in_list = 0;
 933    cyg_uint32 bytes_needed_list = 0;
 934    cyg_uint32 buffer_pos = 0;
 935    cyg_uint8 * sg_buf;
 936    cyg_uint32 total_bytes = 0;
 937
 938    for(i = 0;i<sg_len;i++)
 939    {
 940       while(bytes_in_list < sg_list[i].len)
 941       {
 942          bytes_needed_list = sg_list[i].len - bytes_in_list;
 943
 944          if(priv->rbd[priv->curr_rbd_idx].sr & AT91_EMAC_RBD_SR_EOF)
 945          {
 946               bytes_in_buffer =
 947                 ((priv->rbd[priv->curr_rbd_idx].sr & AT91_EMAC_RBD_SR_LEN_MASK)
 948                  - total_bytes) - buffer_pos;
 949          }
 950          else
 951          {
 952             bytes_in_buffer = AT91_EMAC_RX_BUFF_SIZE - buffer_pos;
 953          }
 954
 955          sg_buf = (cyg_uint8 *)(sg_list[i].buf);
 956
 957          if(bytes_needed_list < bytes_in_buffer)
 958          {
 959             if(sg_buf != NULL)
 960                memcpy(&sg_buf[bytes_in_list],
 961                       &priv->rb[priv->curr_rbd_idx].rb[buffer_pos],
 962                       bytes_needed_list);
 963             bytes_in_list += bytes_needed_list;
 964             buffer_pos += bytes_needed_list;
 965             total_bytes += bytes_needed_list;
 966          }
 967          else
 968          {
 969             if(sg_buf != NULL)
 970               memcpy(&sg_buf[bytes_in_list],
 971                      &priv->rb[priv->curr_rbd_idx].rb[buffer_pos],
 972                      bytes_in_buffer);
 973             bytes_in_list += bytes_in_buffer;
 974             total_bytes += bytes_in_buffer;
 975
 976             /* Step our buffer on one */
 977             priv->rbd[priv->curr_rbd_idx].addr &=
 978               ~(AT91_EMAC_RBD_ADDR_OWNER_SW);
 979             priv->curr_rbd_idx++;
 980             if(priv->curr_rbd_idx >= CYGNUM_DEVS_ETH_ARM_AT91_RX_BUFS)
 981             {
 982                priv->curr_rbd_idx = 0;
 983             }
 984             buffer_pos = 0;
 985          }
 986       }
 987    }
 988 }
 989
 990 // routine called to handle ethernet controller in polled mode
 991 static void
 992 at91_eth_poll(struct eth_drv_sc *sc)
 993 {
 994    /* Service the buffers */
 995    at91_eth_deliver(sc);
 996 }
 997
 998 static int
 999 at91_eth_int_vector(struct eth_drv_sc *sc)
1000 {
1001    return(CYGNUM_HAL_INTERRUPT_EMAC);
1002 }
1003
1004 at91_eth_priv_t at91_priv_data =
1005 {
1006    .intr_vector = CYGNUM_HAL_INTERRUPT_EMAC,
1007    .base = AT91_EMAC,
1008    .phy = &at91_phy
1009 };
1010
1011 ETH_DRV_SC(at91_sc,
1012            &at91_priv_data,       // Driver specific data
1013            "eth0",                // Name for this interface
1014            at91_eth_start,
1015            at91_eth_stop,
1016            at91_eth_control,
1017            at91_eth_can_send,
1018            at91_eth_send,
1019            at91_eth_recv,
1020            at91_eth_deliver,
1021            at91_eth_poll,
1022            at91_eth_int_vector);
1023
1024 NETDEVTAB_ENTRY(at91_netdev,
1025                 "at91",
1026                 at91_eth_init,
1027                 &at91_sc);
1028
1029 // EOF if_at91.c