packages/devs/eth/arm/ebsa285/v2_0/include/devs_eth_ebsa285.inl

   1 //==========================================================================
   2 //
   3 //      devs/eth/arm/ebsa285/..../include/devs_eth_ebsa285.inl
   4 //
   5 //      EBSA-285 ethernet I/O definitions.
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
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  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
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  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //==========================================================================
  41 //#####DESCRIPTIONBEGIN####
  42 //
  43 // Author(s):    jskov, hmt
  44 // Contributors: jskov, gthomas
  45 // Date:         2001-02-28
  46 // Purpose:      EBSA285 ethernet defintions
  47 //####DESCRIPTIONEND####
  48 //==========================================================================
  49
  50 #include <cyg/hal/hal_intr.h>           // CYGNUM_HAL_INTERRUPT_...
  51 #include <pkgconf/hal_arm_ebsa285.h>
  52 #include <cyg/hal/hal_cache.h>          // hal_virt_to_phys_address()
  53
  54 // --------------------------------------------------------------
  55 // Platform specifics:
  56
  57 // support SDRAM with gaps in it.
  58 #define CYGHWR_DEVS_ETH_INTEL_I82559_PCIMEM_DISCONTIGUOUS
  59
  60 // Interrupts are multiplex onto one interrupt pin.
  61 #define CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT \
  62           CYGNUM_HAL_INTERRUPT_PCI_IRQ
  63
  64 // This brings on code to perform a selective reset on the device if the CU
  65 // wedges.
  66
  67 #define CYGHWR_DEVS_ETH_INTEL_I82559_DEAD_TO (368640) // 0.1S of OS timer
  68
  69 // The mask on an SA110 is really an enable: 1 => enabled, 0 => masked.
  70 // So to behave nestedly, we only need save the old value of the bits
  71 // of interest.
  72
  73 #define CYGPRI_DEVS_ETH_INTEL_I82559_MASK_INTERRUPTS(p_i82559,old)      \
  74 CYG_MACRO_START                                                         \
  75     int cpu_intr;                                                       \
  76     int mybits =                                                        \
  77         (1 << (p_i82559->vector)) |                                     \
  78         (1 << CYGNUM_HAL_INTERRUPT_PCI_IRQ);                            \
  79                                                                         \
  80     HAL_DISABLE_INTERRUPTS( cpu_intr );                                 \
  81     old = *SA110_IRQCONT_IRQENABLE;                                     \
  82     *SA110_IRQCONT_IRQENABLECLEAR = mybits; /* clear mybits */          \
  83     HAL_RESTORE_INTERRUPTS( cpu_intr );                                 \
  84 CYG_MACRO_END
  85
  86 // We must only unmask (enable) those which were unmasked before,
  87 // according to the bits in old.
  88 #define CYGPRI_DEVS_ETH_INTEL_I82559_UNMASK_INTERRUPTS(p_i82559,old)    \
  89 CYG_MACRO_START                                                         \
  90     *SA110_IRQCONT_IRQENABLESET = old &                                 \
  91         ((1 << (p_i82559->vector)) |                                    \
  92          (1 << CYGNUM_HAL_INTERRUPT_PCI_IRQ));                          \
  93 CYG_MACRO_END
  94
  95 #define CYGPRI_DEVS_ETH_INTEL_I82559_ACK_INTERRUPTS(p_i82559)   \
  96 CYG_MACRO_START                                                 \
  97 CYG_MACRO_END
  98
  99
 100 // --------------------------------------------------------------
 101
 102 #define CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE
 103 #define CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE
 104
 105 #define CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ ) virt_to_bus((cyg_uint32)_x_)
 106 static inline cyg_uint32 virt_to_bus(cyg_uint32 p_memory)
 107 {    return (p_memory - CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE);    }
 108
 109 // --------------------------------------------------------------
 110 // Construct the two interfaces
 111
 112 #ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
 113
 114 static I82559 i82559_eth0_priv_data = {
 115 #ifdef CYGSEM_DEVS_ETH_ARM_EBSA285_ETH0_SET_ESA
 116     hardwired_esa: 1,
 117     mac_address: CYGDAT_DEVS_ETH_ARM_EBSA285_ETH0_ESA
 118 #else
 119     hardwired_esa: 0,
 120 #endif
 121 };
 122
 123 ETH_DRV_SC(i82559_sc0,
 124            &i82559_eth0_priv_data,      // Driver specific data
 125            CYGDAT_DEVS_ETH_ARM_EBSA285_ETH0_NAME, // Name for device
 126            i82559_start,
 127            i82559_stop,
 128            i82559_ioctl,
 129            i82559_can_send,
 130            i82559_send,
 131            i82559_recv,
 132            i82559_deliver,
 133            i82559_poll,
 134            i82559_int_vector
 135     );
 136
 137 NETDEVTAB_ENTRY(i82559_netdev0,
 138                 "i82559_" CYGDAT_DEVS_ETH_ARM_EBSA285_ETH0_NAME,
 139                 i82559_init,
 140                 &i82559_sc0);
 141
 142 #endif // CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
 143
 144 #ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
 145
 146 static I82559 i82559_eth1_priv_data = {
 147 #ifdef CYGSEM_DEVS_ETH_ARM_EBSA285_ETH1_SET_ESA
 148     hardwired_esa: 1,
 149     mac_address: CYGDAT_DEVS_ETH_ARM_EBSA285_ETH1_ESA
 150 #else
 151     hardwired_esa: 0,
 152 #endif
 153 };
 154
 155 ETH_DRV_SC(i82559_sc1,
 156            &i82559_eth1_priv_data,      // Driver specific data
 157            CYGDAT_DEVS_ETH_ARM_EBSA285_ETH1_NAME, // Name for device
 158            i82559_start,
 159            i82559_stop,
 160            i82559_ioctl,
 161            i82559_can_send,
 162            i82559_send,
 163            i82559_recv,
 164            i82559_deliver,
 165            i82559_poll,
 166            i82559_int_vector
 167     );
 168
 169 NETDEVTAB_ENTRY(i82559_netdev1,
 170                 "i82559_" CYGDAT_DEVS_ETH_ARM_EBSA285_ETH1_NAME,
 171                 i82559_init,
 172                 &i82559_sc1);
 173
 174 #endif // CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
 175
 176 // --------------------------------------------------------------
 177 // These arrays are used for sanity checking of pointers
 178 I82559 *
 179 i82559_priv_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
 180 #ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
 181     &i82559_eth0_priv_data,
 182 #endif
 183 #ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
 184     &i82559_eth1_priv_data,
 185 #endif
 186 };
 187
 188 #ifdef CYGDBG_USE_ASSERTS
 189 // These are only used when assertions are enabled
 190 cyg_netdevtab_entry_t *
 191 i82559_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
 192 #ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
 193     &i82559_netdev0,
 194 #endif
 195 #ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
 196     &i82559_netdev1,
 197 #endif
 198 };
 199
 200 struct eth_drv_sc *
 201 i82559_sc_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
 202 #ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH0
 203     &i82559_sc0,
 204 #endif
 205 #ifdef CYGPKG_DEVS_ETH_ARM_EBSA285_ETH1
 206     &i82559_sc1,
 207 #endif
 208 };
 209 #endif // CYGDBG_USE_ASSERTS
 210
 211 // --------------------------------------------------------------
 212 // Debugging
 213
 214 //#define CYGDBG_DEVS_ETH_INTEL_I82559_CHATTER 1
 215
 216 // --------------------------------------------------------------
 217 // RedBoot configuration options for managing ESAs for us
 218
 219 #define CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM 0
 220 #define CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM_MAC_ADJUST (1)
 221
 222 // --------------------------------------------------------------
 223
 224 // EOF devs_eth_ebsa285.inl