1 //==========================================================================
3 // devs/eth/arm/nano/..../include/devs_eth_nano.inl
5 // nanoBridge ethernet I/O definitions.
7 //==========================================================================
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40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): jskov, hmt
44 // Contributors: jskov
46 // Purpose: nanoBridge ethernet defintions
47 //####DESCRIPTIONEND####
48 //==========================================================================
50 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_...
52 // --------------------------------------------------------------
53 // Platform specifics:
55 #if 1 < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT
56 #define CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
57 #endif // multiple devs, so demux_all needed
59 // define multiple interrupt handling anyway:
61 #define CYGHWR_DEVS_ETH_INTRS (SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1)
63 // This brings in code to ensure missed interrupts are properly
64 // acknowledged so that another interrupt can occur in future.
65 // Only a problem with edge-triggered systems.
67 #define CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559) \
68 (CYGHWR_DEVS_ETH_INTRS != (CYGHWR_DEVS_ETH_INTRS & *SA11X0_GPIO_PIN_LEVEL))
70 // This brings on code to perform a selective reset on the device if the CU
73 #define CYGHWR_DEVS_ETH_INTEL_I82559_DEAD_TO (368640) // 0.1S of OS timer
75 #define CYGHWR_DEVS_ETH_INTEL_I82559_RESET_TIMEOUT( anon_uint ) \
77 (anon_uint) = *SA11X0_OSCR; \
80 #define CYGHWR_DEVS_ETH_INTEL_I82559_TIMEOUT_FIRED( anon_uint ) \
81 ((*SA11X0_OSCR - (anon_uint)) > CYGHWR_DEVS_ETH_INTEL_I82559_DEAD_TO)
83 // The mask on an SA1110 is really an enable: 1 => enabled, 0 => masked.
84 // So to behave nestedly, we only need save the old value of the bits
87 #define CYGPRI_DEVS_ETH_INTEL_I82559_MASK_INTERRUPTS(p_i82559,old) \
90 HAL_DISABLE_INTERRUPTS( cpu ); \
92 *SA11X0_ICMR = old & ~CYGHWR_DEVS_ETH_INTRS; \
93 old &= CYGHWR_DEVS_ETH_INTRS; /* old val */ \
94 HAL_RESTORE_INTERRUPTS( cpu ); \
97 #define CYGPRI_DEVS_ETH_INTEL_I82559_UNMASK_INTERRUPTS(p_i82559,old) \
100 HAL_DISABLE_INTERRUPTS( cpu ); \
101 (*SA11X0_ICMR |= (old & CYGHWR_DEVS_ETH_INTRS)); \
102 HAL_RESTORE_INTERRUPTS( cpu ); \
105 #define CYGPRI_DEVS_ETH_INTEL_I82559_ACK_INTERRUPTS(p_i82559) \
107 /* Remove the latched edge in the PIC: */ \
108 *SA11X0_GPIO_EDGE_DETECT_STATUS = CYGHWR_DEVS_ETH_INTRS; \
112 // --------------------------------------------------------------
114 #define CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_BASE
115 #define CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_SIZE
117 #define CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ ) \
118 (((cyg_uint32)(_x_)) - CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_BASE + cyg_pci_window_real_base)
120 // support SDRAM with gaps in it cos of the way PCI window is laid out.
121 #define CYGHWR_DEVS_ETH_INTEL_I82559_PCIMEM_DISCONTIGUOUS
123 // --------------------------------------------------------------
124 // Construct the two interfaces
126 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH0
128 static I82559 i82559_eth0_priv_data = {
129 #ifdef CYGSEM_DEVS_ETH_ARM_NANO_ETH0_SET_ESA
131 mac_address: CYGDAT_DEVS_ETH_ARM_NANO_ETH0_ESA
137 ETH_DRV_SC(i82559_sc0,
138 &i82559_eth0_priv_data, // Driver specific data
139 CYGDAT_DEVS_ETH_ARM_NANO_ETH0_NAME, // Name for device
151 NETDEVTAB_ENTRY(i82559_netdev0,
152 "i82559_" CYGDAT_DEVS_ETH_ARM_NANO_ETH0_NAME,
156 #endif // CYGPKG_DEVS_ETH_ARM_NANO_ETH0
158 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH1
160 static I82559 i82559_eth1_priv_data = {
161 #ifdef CYGSEM_DEVS_ETH_ARM_NANO_ETH1_SET_ESA
163 mac_address: CYGDAT_DEVS_ETH_ARM_NANO_ETH1_ESA
169 ETH_DRV_SC(i82559_sc1,
170 &i82559_eth1_priv_data, // Driver specific data
171 CYGDAT_DEVS_ETH_ARM_NANO_ETH1_NAME, // Name for device
183 NETDEVTAB_ENTRY(i82559_netdev1,
184 "i82559_" CYGDAT_DEVS_ETH_ARM_NANO_ETH1_NAME,
188 #endif // CYGPKG_DEVS_ETH_ARM_NANO_ETH1
190 // --------------------------------------------------------------
191 // These arrays are used for sanity checking of pointers
193 i82559_priv_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
194 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH0
195 &i82559_eth0_priv_data,
197 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH1
198 &i82559_eth1_priv_data,
202 #ifdef CYGDBG_USE_ASSERTS
203 // These are only used when assertions are enabled
204 cyg_netdevtab_entry_t *
205 i82559_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
206 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH0
209 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH1
215 i82559_sc_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
216 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH0
219 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH1
223 #endif // CYGDBG_USE_ASSERTS
225 // --------------------------------------------------------------
228 //#define CYGDBG_DEVS_ETH_INTEL_I82559_CHATTER 1
230 // --------------------------------------------------------------
231 // RedBoot configuration options for managing ESAs for us
233 // tell the driver there is no EEPROM on this board
234 #define CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
236 // Decide whether to have redboot config vars for it...
237 #ifdef CYGPKG_REDBOOT
238 #include <pkgconf/redboot.h>
239 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
240 #ifdef CYGPKG_REDBOOT_NETWORKING
242 #include <flash_config.h>
244 #ifdef CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH0
245 RedBoot_config_option("Network hardware address [MAC] for eth0",
247 ALWAYS_ENABLED, true,
252 #ifdef CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH1
253 RedBoot_config_option("Network hardware address [MAC] for eth1",
255 ALWAYS_ENABLED, true,
264 // and initialization code to read them
265 // - independent of whether we are building RedBoot right now:
266 #ifdef CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA
268 #include <cyg/hal/hal_if.h>
271 #define CONFIG_ESA (6)
274 #define CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA( p_i82559, mac_address, ok ) \
277 if ( 0 == p_i82559->index ) \
278 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, \
279 "eth0_esa", mac_address, CONFIG_ESA); \
280 else if ( 1 == p_i82559->index ) \
281 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, \
282 "eth1_esa", mac_address, CONFIG_ESA); \
285 #endif // CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA
287 // --------------------------------------------------------------
289 // EOF devs_eth_nano.inl