packages/devs/eth/arm/nano/v2_0/include/devs_eth_nano.inl

   1 //==========================================================================
   2 //
   3 //      devs/eth/arm/nano/..../include/devs_eth_nano.inl
   4 //
   5 //      nanoBridge ethernet I/O definitions.
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //==========================================================================
  41 //#####DESCRIPTIONBEGIN####
  42 //
  43 // Author(s):    jskov, hmt
  44 // Contributors: jskov
  45 // Date:         2001-02-28
  46 // Purpose:      nanoBridge ethernet defintions
  47 //####DESCRIPTIONEND####
  48 //==========================================================================
  49
  50 #include <cyg/hal/hal_intr.h>           // CYGNUM_HAL_INTERRUPT_...
  51
  52 // --------------------------------------------------------------
  53 // Platform specifics:
  54
  55 #if 1 < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT
  56 #define CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
  57 #endif // multiple devs, so demux_all needed
  58
  59 // define multiple interrupt handling anyway:
  60
  61 #define CYGHWR_DEVS_ETH_INTRS (SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1)
  62
  63 // This brings in code to ensure missed interrupts are properly
  64 // acknowledged so that another interrupt can occur in future.
  65 // Only a problem with edge-triggered systems.
  66
  67 #define CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559) \
  68  (CYGHWR_DEVS_ETH_INTRS != (CYGHWR_DEVS_ETH_INTRS & *SA11X0_GPIO_PIN_LEVEL))
  69
  70 // This brings on code to perform a selective reset on the device if the CU
  71 // wedges.
  72
  73 #define CYGHWR_DEVS_ETH_INTEL_I82559_DEAD_TO (368640) // 0.1S of OS timer
  74
  75 #define CYGHWR_DEVS_ETH_INTEL_I82559_RESET_TIMEOUT( anon_uint ) \
  76 CYG_MACRO_START                                                 \
  77     (anon_uint) = *SA11X0_OSCR;                                 \
  78 CYG_MACRO_END
  79
  80 #define CYGHWR_DEVS_ETH_INTEL_I82559_TIMEOUT_FIRED( anon_uint )         \
  81   ((*SA11X0_OSCR - (anon_uint)) > CYGHWR_DEVS_ETH_INTEL_I82559_DEAD_TO)
  82
  83 // The mask on an SA1110 is really an enable: 1 => enabled, 0 => masked.
  84 // So to behave nestedly, we only need save the old value of the bits
  85 // of interest.
  86
  87 #define CYGPRI_DEVS_ETH_INTEL_I82559_MASK_INTERRUPTS(p_i82559,old)      \
  88 CYG_MACRO_START                                                         \
  89     int cpu;                                                            \
  90     HAL_DISABLE_INTERRUPTS( cpu );                                      \
  91     old = *SA11X0_ICMR;                                                 \
  92     *SA11X0_ICMR = old & ~CYGHWR_DEVS_ETH_INTRS;                        \
  93     old &= CYGHWR_DEVS_ETH_INTRS; /* old val */                         \
  94     HAL_RESTORE_INTERRUPTS( cpu );                                      \
  95 CYG_MACRO_END
  96
  97 #define CYGPRI_DEVS_ETH_INTEL_I82559_UNMASK_INTERRUPTS(p_i82559,old)    \
  98 CYG_MACRO_START                                                         \
  99     int cpu;                                                            \
 100     HAL_DISABLE_INTERRUPTS( cpu );                                      \
 101     (*SA11X0_ICMR |= (old & CYGHWR_DEVS_ETH_INTRS));                    \
 102     HAL_RESTORE_INTERRUPTS( cpu );                                      \
 103 CYG_MACRO_END
 104
 105 #define CYGPRI_DEVS_ETH_INTEL_I82559_ACK_INTERRUPTS(p_i82559)   \
 106 CYG_MACRO_START                                                 \
 107     /* Remove the latched edge in the PIC: */                   \
 108     *SA11X0_GPIO_EDGE_DETECT_STATUS = CYGHWR_DEVS_ETH_INTRS;    \
 109 CYG_MACRO_END
 110
 111
 112 // --------------------------------------------------------------
 113
 114 #define CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_BASE
 115 #define CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_SIZE
 116
 117 #define CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ ) \
 118   (((cyg_uint32)(_x_)) - CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_BASE + cyg_pci_window_real_base)
 119
 120 // support SDRAM with gaps in it cos of the way PCI window is laid out.
 121 #define CYGHWR_DEVS_ETH_INTEL_I82559_PCIMEM_DISCONTIGUOUS
 122
 123 // --------------------------------------------------------------
 124 // Construct the two interfaces
 125
 126 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH0
 127
 128 static I82559 i82559_eth0_priv_data = {
 129 #ifdef CYGSEM_DEVS_ETH_ARM_NANO_ETH0_SET_ESA
 130     hardwired_esa: 1,
 131     mac_address: CYGDAT_DEVS_ETH_ARM_NANO_ETH0_ESA
 132 #else
 133     hardwired_esa: 0,
 134 #endif
 135 };
 136
 137 ETH_DRV_SC(i82559_sc0,
 138            &i82559_eth0_priv_data,      // Driver specific data
 139            CYGDAT_DEVS_ETH_ARM_NANO_ETH0_NAME, // Name for device
 140            i82559_start,
 141            i82559_stop,
 142            i82559_ioctl,
 143            i82559_can_send,
 144            i82559_send,
 145            i82559_recv,
 146            i82559_deliver,
 147            i82559_poll,
 148            i82559_int_vector
 149     );
 150
 151 NETDEVTAB_ENTRY(i82559_netdev0,
 152                 "i82559_" CYGDAT_DEVS_ETH_ARM_NANO_ETH0_NAME,
 153                 i82559_init,
 154                 &i82559_sc0);
 155
 156 #endif // CYGPKG_DEVS_ETH_ARM_NANO_ETH0
 157
 158 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH1
 159
 160 static I82559 i82559_eth1_priv_data = {
 161 #ifdef CYGSEM_DEVS_ETH_ARM_NANO_ETH1_SET_ESA
 162     hardwired_esa: 1,
 163     mac_address: CYGDAT_DEVS_ETH_ARM_NANO_ETH1_ESA
 164 #else
 165     hardwired_esa: 0,
 166 #endif
 167 };
 168
 169 ETH_DRV_SC(i82559_sc1,
 170            &i82559_eth1_priv_data,      // Driver specific data
 171            CYGDAT_DEVS_ETH_ARM_NANO_ETH1_NAME, // Name for device
 172            i82559_start,
 173            i82559_stop,
 174            i82559_ioctl,
 175            i82559_can_send,
 176            i82559_send,
 177            i82559_recv,
 178            i82559_deliver,
 179            i82559_poll,
 180            i82559_int_vector
 181     );
 182
 183 NETDEVTAB_ENTRY(i82559_netdev1,
 184                 "i82559_" CYGDAT_DEVS_ETH_ARM_NANO_ETH1_NAME,
 185                 i82559_init,
 186                 &i82559_sc1);
 187
 188 #endif // CYGPKG_DEVS_ETH_ARM_NANO_ETH1
 189
 190 // --------------------------------------------------------------
 191 // These arrays are used for sanity checking of pointers
 192 I82559 *
 193 i82559_priv_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
 194 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH0
 195     &i82559_eth0_priv_data,
 196 #endif
 197 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH1
 198     &i82559_eth1_priv_data,
 199 #endif
 200 };
 201
 202 #ifdef CYGDBG_USE_ASSERTS
 203 // These are only used when assertions are enabled
 204 cyg_netdevtab_entry_t *
 205 i82559_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
 206 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH0
 207     &i82559_netdev0,
 208 #endif
 209 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH1
 210     &i82559_netdev1,
 211 #endif
 212 };
 213
 214 struct eth_drv_sc *
 215 i82559_sc_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
 216 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH0
 217     &i82559_sc0,
 218 #endif
 219 #ifdef CYGPKG_DEVS_ETH_ARM_NANO_ETH1
 220     &i82559_sc1,
 221 #endif
 222 };
 223 #endif // CYGDBG_USE_ASSERTS
 224
 225 // --------------------------------------------------------------
 226 // Debugging
 227
 228 //#define CYGDBG_DEVS_ETH_INTEL_I82559_CHATTER 1
 229
 230 // --------------------------------------------------------------
 231 // RedBoot configuration options for managing ESAs for us
 232
 233 // tell the driver there is no EEPROM on this board
 234 #define CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
 235
 236 // Decide whether to have redboot config vars for it...
 237 #ifdef CYGPKG_REDBOOT
 238 #include <pkgconf/redboot.h>
 239 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
 240 #ifdef CYGPKG_REDBOOT_NETWORKING
 241 #include <redboot.h>
 242 #include <flash_config.h>
 243
 244 #ifdef CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH0
 245 RedBoot_config_option("Network hardware address [MAC] for eth0",
 246                       eth0_esa,
 247                       ALWAYS_ENABLED, true,
 248                       CONFIG_ESA, 0
 249     );
 250 #endif
 251
 252 #ifdef CYGVAR_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA_ETH1
 253 RedBoot_config_option("Network hardware address [MAC] for eth1",
 254                       eth1_esa,
 255                       ALWAYS_ENABLED, true,
 256                       CONFIG_ESA, 0
 257     );
 258 #endif
 259
 260 #endif
 261 #endif
 262 #endif
 263
 264 // and initialization code to read them
 265 // - independent of whether we are building RedBoot right now:
 266 #ifdef CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA
 267
 268 #include <cyg/hal/hal_if.h>
 269
 270 #ifndef CONFIG_ESA
 271 #define CONFIG_ESA (6)
 272 #endif
 273
 274 #define CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA( p_i82559, mac_address, ok )       \
 275 CYG_MACRO_START                                                                 \
 276     ok = false;                                                                 \
 277     if ( 0 == p_i82559->index )                                                 \
 278         ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,         \
 279                                           "eth0_esa", mac_address, CONFIG_ESA); \
 280     else if ( 1 == p_i82559->index )                                            \
 281         ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,         \
 282                                           "eth1_esa", mac_address, CONFIG_ESA); \
 283 CYG_MACRO_END
 284
 285 #endif // CYGPKG_DEVS_ETH_I82559_ETH_REDBOOT_HOLDS_ESA
 286
 287 // --------------------------------------------------------------
 288
 289 // EOF devs_eth_nano.inl