1 diff -Naur orig/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl new/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl
2 --- orig/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl 2004-11-29 17:35:46.000000000 +0100
3 +++ new/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl 2005-03-10 14:54:13.903367200 +0100
5 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_netarm.h>"
8 + cdl_option CYGSEM_HAL_INSTRUCTION_CACHE_SETS {
9 + display "Sets for Instruction Cache"
10 + parent CYGPKG_HAL_CACHE_CONTROL
11 + active_if CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
13 + legal_values 0 to 15
15 + description "MSB: SET1 | SET2 | SET3 | SET4"
18 + cdl_option CYGSEM_HAL_DATA_CACHE_SETS {
19 + display "Sets for Data Cache"
20 + parent CYGPKG_HAL_CACHE_CONTROL
21 + active_if CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
23 + legal_values 0 to 15
25 + description "MSB: SET1 | SET2 | SET3 | SET4"
28 cdl_component CYG_HAL_STARTUP {
29 display "Startup type"
31 diff -Naur orig/hal/arm/netarm/current/include/hal_cache.h new/hal/arm/netarm/current/include/hal_cache.h
32 --- orig/hal/arm/netarm/current/include/hal_cache.h 2004-11-29 17:35:46.000000000 +0100
33 +++ new/hal/arm/netarm/current/include/hal_cache.h 2005-03-10 14:41:51.032173600 +0100
35 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
36 #define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line
38 -#define HAL_ICACHE_BASE 0x08000000
39 -#define HAL_ICACHE_MASK 0xfe000000
40 +#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_RAM)
41 + #define HAL_ICACHE_BASE 0x04000000
42 + #define HAL_DCACHE_BASE 0x08000000
44 + #define HAL_ICACHE_BASE 0x02000000
45 + #define HAL_DCACHE_BASE 0x04000000
48 +#define HAL_ICACHE_MASK 0xff000000
49 +#define HAL_DCACHE_MASK 0xff000000
52 +#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
53 + #define HAL_ICACHE_ENABLE() \
55 + *(CCR0)=(HAL_ICACHE_BASE) | \
56 + (HAL_ICACHE_MASK >> 8) | \
59 + (CYGSEM_HAL_INSTRUCTION_CACHE_SETS); \
62 + #define HAL_ICACHE_ENABLE() (*(CCR0)=0)
65 -#define HAL_ICACHE_ENABLE() \
66 +#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
67 + #define HAL_DCACHE_ENABLE() \
69 + *(CCR1)=(HAL_DCACHE_BASE) | \
70 + (HAL_DCACHE_MASK >> 8) | \
73 + (CYGSEM_HAL_DATA_CACHE_SETS); \
76 + #define HAL_DCACHE_ENABLE() (*(CCR1)=0)
79 +#define HAL_CACHE_ENABLE() \
84 *(SYSCON)|=SYSCON_CINIT|SYSCON_CACHE; \
85 p=(unsigned int *)0xfff00000; \
86 - for(i=0;i<(0x2000/4);i++,p++) \
87 + for(i=0;i<(0x4000/4);i++,p++) \
90 - *(SYSCON)&=~(SYSCON_CINIT); \
91 - *(CCR0)=(HAL_ICACHE_BASE) | \
92 - (HAL_ICACHE_MASK >> 8) | \
94 - (CCR_SET1 | CCR_SET2 | CCR_SET3 | CCR_SET4); \
96 + HAL_ICACHE_ENABLE(); \
97 + HAL_DCACHE_ENABLE(); \
99 *(SYSCON)|=SYSCON_CACHE; \
100 *(SYSCON)&=~SYSCON_WB; \
103 #define HAL_ICACHE_DISABLE() \
106 - *(SYSCON)&=~SYSCON_CACHE; \
107 + if (HAL_DCACHE_IS_ENABLED == 0) \
108 + *(SYSCON)&=~SYSCON_CACHE; \
111 -#define HAL_ICACHE_IS_ENABLED(_state_) _state_ = ((*(CCR0) & CCR_ENABLE) >> 15)
112 +#define HAL_DCACHE_DISABLE() \
115 + if (HAL_ICACHE_IS_ENABLED == 0) \
116 + *(SYSCON)&=~SYSCON_CACHE; \
119 +#define HAL_ICACHE_IS_ENABLED ((*(CCR0) & CCR_ENABLE) >> 15)
121 -#define HAL_ICACHE_INVALIDATE_ALL() \
122 +#define HAL_CACHE_INVALIDATE_ALL() \
125 *(SYSCON)|=SYSCON_CINIT; \
126 for(p=(unsigned int*)0xfff00000; \
127 - (unsigned int)p<0xfff02000; \
128 + (unsigned int)p<0xfff04000; \
134 #define HAL_ICACHE_SYNC()
136 -#define HAL_ICACHE_PURGE_ALL() HAL_ICACHE_INVALIDATE_ALL()
138 -#define HAL_DCACHE_LINE_SIZE 0
139 -#define HAL_DCACHE_WAYS 0
140 -#define HAL_DCACHE_SETS 0
142 -#define HAL_DCACHE_ENABLE()
143 +#define HAL_CACHE_PURGE_ALL() HAL_ICACHE_INVALIDATE_ALL()
145 -#define HAL_DCACHE_DISABLE()
147 -#define HAL_DCACHE_INVALIDATE_ALL()
148 +#define HAL_DCACHE_LINE_SIZE 4
149 +#define HAL_DCACHE_WAYS 4
151 #define HAL_DCACHE_SYNC()
153 -#define HAL_DCACHE_IS_ENABLED(_state_) 0
155 -#define HAL_DCACHE_FLUSH( _base_ , _size_ )
157 -#define HAL_DCACHE_STORE( _base_ , _size_ )
158 +#define HAL_DCACHE_IS_ENABLED ((*(CCR1) & CCR_ENABLE) >> 15)
162 diff -Naur orig/hal/arm/netarm/current/include/hal_platform_setup.h new/hal/arm/netarm/current/include/hal_platform_setup.h
163 --- orig/hal/arm/netarm/current/include/hal_platform_setup.h 2004-11-29 17:35:46.000000000 +0100
164 +++ new/hal/arm/netarm/current/include/hal_platform_setup.h 2005-03-14 17:10:01.542675500 +0100
166 // Usage: #include <cyg/hal/hal_platform_setup.h>
168 //####DESCRIPTIONEND####
171 //===========================================================================*/
173 #include <pkgconf/system.h> // System-wide configuration info
175 bic r0,r0, #((\x & 3)<<1); \
178 -#if defined(CYG_HAL_STARTUP_ROMRAM)
179 +#if defined(CYG_HAL_STARTUP_ROMRAM)
180 #define HAL_FLASH_PHYS_ADDR 0x02000000
181 -#define UNMAPPED(x) ((x)-0x08000000)
182 +#define UNMAPPED(x) ((x)-0x04000000)
183 #elif defined(CYG_HAL_STARTUP_ROM)
184 #define HAL_FLASH_PHYS_ADDR 0x02000000
185 #define UNMAPPED(x) ((x)-0x02000000)
187 .macro PLATFORM_SETUP1
190 + ldr r1,=0xffb0000c // software reset
207 #if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_ROM)
210 ldr r0,=0x4004a800 /* System control register */
213 +#ifdef CYG_HAL_STARTUP_ROM
214 mov r0,#0 /* PLL config */
220 ldr r0,=0xfff00000 /* PORT A mode & dir */
224 add r1,r1,#0x100000 /* Setup MEM Module base addr */
227 ldr r0,=0x148C0000 /* Memory Module Config register */
231 ldr r0,=0xf3f00304 /* CS0 Option register */
234 - ldr r0,=0x02000001 /* CS0 Base Address register */
235 + ldr r0,=0x02000001 /* CS0 Base Address register */
238 mov pc,r2 /* Jump to new flash base */
241 /* Configure SDRAM */
243 - ldr r0,=0xf38000b0 /* CS1 Option register, BLEN=11 */
244 + ldr r0,=0xf3000070 /* CS1 Option register, BLEN=11 (0xf38000b0)*/
247 ldr r0,=0x0000022d /* CS1 Base Address register */
249 #if defined(CYG_HAL_STARTUP_ROMRAM)
251 mov r2,#HAL_FLASH_PHYS_ADDR
252 - ldr r3,=(__heap1 - 0x04000000 + HAL_FLASH_PHYS_ADDR)
253 + ldr r3,=(__heap1 - 0x08000000 + HAL_FLASH_PHYS_ADDR)
257 @@ -129,11 +149,11 @@
271 diff -Naur orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi
272 --- orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi 2004-11-29 17:35:46.000000000 +0100
273 +++ new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi 2005-03-10 14:56:07.137708600 +0100
277 noncacheram : ORIGIN = 0, LENGTH = 16*1024*1024
278 - dataram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
279 - codecacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
280 + codecacheram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
281 + datacacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
287 - _dataram = 0x4000000;
288 + _dataram = 0x8000000;
289 SECTION_rom_vectors (nocacheram, 0x0, LMA_EQ_VMA)
290 SECTION_fixed_vectors (nocacheram, ALIGN (0x4), LMA_EQ_VMA)
291 - code_start = . + 0x8000000;
292 - SECTION_text (codecacheram, code_start, AT (code_start - 0x8000000))
293 + code_start = . + 0x4000000;
294 + SECTION_text (codecacheram, code_start, AT (code_start - 0x4000000))
296 - SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x8000000))
297 + SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x4000000))
299 - SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x8000000))
300 + SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x4000000))
302 - SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x8000000))
303 + SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x4000000))
305 - SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x8000000))
306 + SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x4000000))
308 - SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x8000000))
309 - data_start = ALIGN(0x4) - 0x4000000;
310 - SECTION_data (dataram, data_start, AT (data_start - 0x4000000))
311 + SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x4000000))
312 + data_start = ALIGN(0x4) + 0x4000000;
313 + SECTION_data (datacacheram, data_start, AT (data_start - 0x8000000))
315 - SECTION_bss (dataram, ALIGN (0x4), AT (bss - 0x4000000))
316 + SECTION_bss (datacacheram, ALIGN (0x4), AT (bss - 0x8000000))
317 CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
322 diff -Naur orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi
323 --- orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi 2004-11-29 17:35:46.000000000 +0100
324 +++ new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi 2005-03-10 14:56:18.184583600 +0100
328 noncacheram : ORIGIN = 0, LENGTH = 16*1024*1024
329 - dataram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
330 - codecacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
331 + codecacheram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
332 + datacacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
338 - _dataram = 0x4000000;
339 + _dataram = 0x8000000;
340 SECTION_rom_vectors (nocacheram, 0x0, LMA_EQ_VMA)
341 SECTION_fixed_vectors (nocacheram, ALIGN (0x4), LMA_EQ_VMA)
342 - code_start = . + 0x8000000;
343 - SECTION_text (codecacheram, code_start, AT (code_start - 0x8000000))
344 + code_start = . + 0x4000000;
345 + SECTION_text (codecacheram, code_start, AT (code_start - 0x4000000))
347 - SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x8000000))
348 + SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x4000000))
350 - SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x8000000))
351 + SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x4000000))
353 - SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x8000000))
354 + SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x4000000))
356 - SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x8000000))
357 - gcc_except_table = .;
358 - SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x8000000))
359 - data_start = . - 0x4000000;
360 - SECTION_data (dataram, data_start, AT (data_start - 0x4000000))
361 + SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x4000000))
362 + gcc_except_table =.;
363 + SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x4000000))
364 + data_start = ALIGN(0x4) + 0x4000000;
365 + SECTION_data (datacacheram, data_start, AT (data_start - 0x8000000))
367 - SECTION_bss (dataram, ALIGN (0x4), AT (bss - 0x4000000))
368 + SECTION_bss (datacacheram, ALIGN (0x4), AT (bss - 0x8000000))
369 CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
374 diff -Naur orig/hal/arm/netarm/current/src/netarm_misc.c new/hal/arm/netarm/current/src/netarm_misc.c
375 --- orig/hal/arm/netarm/current/src/netarm_misc.c 2004-11-29 17:35:48.000000000 +0100
376 +++ new/hal/arm/netarm/current/src/netarm_misc.c 2005-02-22 11:57:58.296703200 +0100
378 //==========================================================================
379 //==========================================================================
380 //#####DESCRIPTIONBEGIN####
383 // Author(s): Peter De Schrijver (p2@mind.be)
384 // Contributors: Peter De Schrijver (p2@mind.be)
386 // Purpose: HAL board support
387 // Description: Implementations of HAL board interfaces
390 //####DESCRIPTIONEND####
393 //========================================================================*/
395 #include <pkgconf/hal.h>
397 #include <cyg/hal/hal_io.h> // IO macros
398 #include <cyg/hal/hal_arch.h> // Register state info
399 #include <cyg/hal/hal_diag.h>
400 -#include <cyg/hal/hal_intr.h> // Interrupt names
401 +#include <cyg/hal/hal_intr.h> // Interrupt names
402 #include <cyg/hal/hal_cache.h>
403 #include <cyg/hal/hal_netarm.h> // Hardware definitions
404 #include <cyg/hal/hal_if.h> // calling interface API
406 void hal_clock_read(cyg_uint32 *pvalue) {
408 static cyg_uint32 clock_val;
410 - clock_val=*TIMERSTAT1 & 0x1ff;
411 - *pvalue = (cyg_uint32)(_period - clock_val);
413 + clock_val=*TIMERSTAT1 & 0x1ff;
414 + *pvalue = (cyg_uint32)(_period - clock_val);
420 void hal_hardware_init(void) {
422 +#if defined (CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP) || \
423 + defined (CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP)
426 - /* CS1 BSIZE = 4 */
430 - HAL_ICACHE_ENABLE();
431 -#endif /* ENABLECACHE */
432 + HAL_CACHE_ENABLE();
434 +#endif /* ENABLECACHE */
436 *INTENABLE_CLR=0xffffffff;
439 hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
443 -// HAL_ICACHE_DISABLE();
447 int hal_spurious_ints;
453 - for(i=0;i<CYGNUM_HAL_ISR_MAX;i++)
455 + for(i=0;i<CYGNUM_HAL_ISR_MAX;i++)
461 if((vector>=CYGNUM_HAL_INTERRUPT_C0) && (vector<=CYGNUM_HAL_INTERRUPT_C3)) {
462 *PORTC|=1<< (vector+23);
465 *PORTC|=1<< (vector+15);
467 *PORTC&=~(1<< (vector+15));