unified MX27, MX25, MX37 trees
[karo-tx-redboot.git] / packages / devs / eth / arm / netarm / v2_0 / doc / netarm_hal.patch
1 diff -Naur orig/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl new/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl
2 --- orig/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl  2004-11-29 17:35:46.000000000 +0100
3 +++ new/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl   2005-03-10 14:54:13.903367200 +0100
4 @@ -18,6 +18,26 @@
5                 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_netarm.h>"
6         }
7  
8 +       cdl_option CYGSEM_HAL_INSTRUCTION_CACHE_SETS {
9 +           display "Sets for Instruction Cache"
10 +           parent CYGPKG_HAL_CACHE_CONTROL
11 +           active_if CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
12 +               flavor data
13 +               legal_values 0 to 15
14 +               default_value 0xc
15 +           description "MSB: SET1 | SET2 | SET3 | SET4"
16 +       }
17 +       
18 +       cdl_option CYGSEM_HAL_DATA_CACHE_SETS {
19 +           display "Sets for Data Cache"
20 +           parent CYGPKG_HAL_CACHE_CONTROL
21 +           active_if CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
22 +               flavor data
23 +               legal_values 0 to 15
24 +               default_value 0x3
25 +           description "MSB: SET1 | SET2 | SET3 | SET4"
26 +       }
27 +
28         cdl_component CYG_HAL_STARTUP {
29         display "Startup type" 
30                 flavor data 
31 diff -Naur orig/hal/arm/netarm/current/include/hal_cache.h new/hal/arm/netarm/current/include/hal_cache.h
32 --- orig/hal/arm/netarm/current/include/hal_cache.h     2004-11-29 17:35:46.000000000 +0100
33 +++ new/hal/arm/netarm/current/include/hal_cache.h      2005-03-10 14:41:51.032173600 +0100
34 @@ -19,25 +19,57 @@
35  #define HAL_ICACHE_WAYS                 4        // Associativity of the cache
36  #define HAL_ICACHE_LINE_SIZE            4       // Size of a cache line
37  
38 -#define HAL_ICACHE_BASE                                        0x08000000
39 -#define HAL_ICACHE_MASK                                        0xfe000000
40 +#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_RAM)
41 +       #define HAL_ICACHE_BASE                                 0x04000000
42 +       #define HAL_DCACHE_BASE                                 0x08000000
43 +#else
44 +       #define HAL_ICACHE_BASE                                 0x02000000
45 +       #define HAL_DCACHE_BASE                                 0x04000000
46 +#endif
47 +
48 +#define HAL_ICACHE_MASK                                        0xff000000
49 +#define HAL_DCACHE_MASK                                        0xff000000
50 +
51 +
52 +#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
53 +       #define HAL_ICACHE_ENABLE()                                             \
54 +       {                                                                                               \
55 +               *(CCR0)=(HAL_ICACHE_BASE) |                                     \
56 +                               (HAL_ICACHE_MASK >> 8) |                        \
57 +                               (CCR_ENABLE) |                                          \
58 +                               (1 << 11)       |                                               \
59 +                               (CYGSEM_HAL_INSTRUCTION_CACHE_SETS);    \
60 +       }
61 +#else
62 +       #define HAL_ICACHE_ENABLE() (*(CCR0)=0)
63 +#endif
64  
65 -#define HAL_ICACHE_ENABLE()                     \
66 +#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
67 +       #define HAL_DCACHE_ENABLE()                                             \
68 +       {                                                                                               \
69 +               *(CCR1)=(HAL_DCACHE_BASE) |                                     \
70 +                               (HAL_DCACHE_MASK >> 8) |                        \
71 +                               (CCR_ENABLE) |                                          \
72 +                               (1 << 11)       |                                               \
73 +                               (CYGSEM_HAL_DATA_CACHE_SETS);   \
74 +       }
75 +#else
76 +       #define HAL_DCACHE_ENABLE() (*(CCR1)=0)
77 +#endif
78 +
79 +#define HAL_CACHE_ENABLE()                      \
80  {                                                                                              \
81         unsigned int *p;                                                        \
82         int i;                                                                      \
83                                                                                                 \
84         *(SYSCON)|=SYSCON_CINIT|SYSCON_CACHE;           \
85         p=(unsigned int *)0xfff00000;                           \
86 -       for(i=0;i<(0x2000/4);i++,p++)                           \
87 +       for(i=0;i<(0x4000/4);i++,p++)                           \
88                 *p=0;                                                                   \
89                                                                                                 \
90 -       *(SYSCON)&=~(SYSCON_CINIT);                                     \
91 -       *(CCR0)=(HAL_ICACHE_BASE) |                                     \
92 -                       (HAL_ICACHE_MASK >> 8) |                        \
93 -                       (CCR_ENABLE) |                                          \
94 -                       (CCR_SET1 | CCR_SET2 | CCR_SET3 | CCR_SET4);            \
95 -       *(CCR1)=0;                                                                      \
96 +       HAL_ICACHE_ENABLE();                                            \
97 +       HAL_DCACHE_ENABLE();                                            \
98 +                                                                                               \
99         *(SYSCON)|=SYSCON_CACHE;                                        \
100         *(SYSCON)&=~SYSCON_WB;                                          \
101  }
102 @@ -45,17 +77,25 @@
103  #define HAL_ICACHE_DISABLE()                    \
104  {                                                                                              \
105         *(CCR0)=0;                                                                      \
106 -       *(SYSCON)&=~SYSCON_CACHE;                                                       \
107 +       if (HAL_DCACHE_IS_ENABLED == 0)                         \
108 +               *(SYSCON)&=~SYSCON_CACHE;                               \
109  }
110  
111 -#define HAL_ICACHE_IS_ENABLED(_state_) _state_ = ((*(CCR0) & CCR_ENABLE) >> 15)
112 +#define HAL_DCACHE_DISABLE()                    \
113 +{                                                                                              \
114 +       *(CCR1)=0;                                                                      \
115 +       if (HAL_ICACHE_IS_ENABLED == 0)                         \
116 +               *(SYSCON)&=~SYSCON_CACHE;                               \
117 +}
118 +
119 +#define HAL_ICACHE_IS_ENABLED ((*(CCR0) & CCR_ENABLE) >> 15)
120  
121 -#define HAL_ICACHE_INVALIDATE_ALL()                            \
122 +#define HAL_CACHE_INVALIDATE_ALL()                             \
123  {                                                                                              \
124         unsigned *p;                                                            \
125         *(SYSCON)|=SYSCON_CINIT;                                                        \
126         for(p=(unsigned int*)0xfff00000;                        \
127 -               (unsigned int)p<0xfff02000;                             \
128 +               (unsigned int)p<0xfff04000;                             \
129                 p++)                                                                    \
130                 *p=0;                                                                   \
131                                                                                                 \
132 @@ -64,25 +104,13 @@
133  
134  #define HAL_ICACHE_SYNC()
135  
136 -#define HAL_ICACHE_PURGE_ALL()  HAL_ICACHE_INVALIDATE_ALL()
137 -
138 -#define HAL_DCACHE_LINE_SIZE 0
139 -#define HAL_DCACHE_WAYS 0
140 -#define HAL_DCACHE_SETS 0
141 -
142 -#define HAL_DCACHE_ENABLE()
143 +#define HAL_CACHE_PURGE_ALL()  HAL_ICACHE_INVALIDATE_ALL()
144  
145 -#define HAL_DCACHE_DISABLE()
146 -
147 -#define HAL_DCACHE_INVALIDATE_ALL()
148 +#define HAL_DCACHE_LINE_SIZE 4
149 +#define HAL_DCACHE_WAYS 4
150  
151  #define HAL_DCACHE_SYNC()
152  
153 -#define HAL_DCACHE_IS_ENABLED(_state_) 0
154 -
155 -#define HAL_DCACHE_FLUSH( _base_ , _size_ )
156 -
157 -#define HAL_DCACHE_STORE( _base_ , _size_ )
158 +#define HAL_DCACHE_IS_ENABLED ((*(CCR1) & CCR_ENABLE) >> 15)
159  
160  #endif
161 -
162 diff -Naur orig/hal/arm/netarm/current/include/hal_platform_setup.h new/hal/arm/netarm/current/include/hal_platform_setup.h
163 --- orig/hal/arm/netarm/current/include/hal_platform_setup.h    2004-11-29 17:35:46.000000000 +0100
164 +++ new/hal/arm/netarm/current/include/hal_platform_setup.h     2005-03-15 12:20:27.760534400 +0100
165 @@ -19,7 +19,7 @@
166  // Usage:       #include <cyg/hal/hal_platform_setup.h>
167  //
168  //####DESCRIPTIONEND####
169 -// 
170 +//
171  //===========================================================================*/
172  
173  #include <pkgconf/system.h>           // System-wide configuration info
174 @@ -34,15 +34,31 @@
175                                                         bic     r0,r0, #((\x & 3)<<1); \
176                                                         str r0,[r1]
177  
178 -#if defined(CYG_HAL_STARTUP_ROMRAM) 
179 +#if defined(CYG_HAL_STARTUP_ROMRAM)
180  #define HAL_FLASH_PHYS_ADDR            0x02000000
181 -#define UNMAPPED(x)                    ((x)-0x08000000)
182 +#define UNMAPPED(x)                    ((x)-0x04000000)
183  #elif  defined(CYG_HAL_STARTUP_ROM)
184  #define HAL_FLASH_PHYS_ADDR            0x02000000
185  #define UNMAPPED(x)                    ((x)-0x02000000)
186  #endif
187                 .macro  PLATFORM_SETUP1
188 -       
189 +
190 +               ldr             r1,=0xffb0000c          // software reset
191 +               ldr             r0,=0x00000123
192 +               str             r0,[r1]
193 +               ldr             r0,=0x00000321
194 +               str             r0,[r1]
195 +
196 +               mov             r0,#1000
197 +loop:
198 +               sub             r0,r0,#1
199 +               cmp             r0,#0
200 +               bne             loop
201 +
202 +               ldr             r0,=0x00000123
203 +               str             r0,[r1]
204 +               ldr             r0,=0x00000321
205 +               str             r0,[r1]
206  
207  #if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_ROM)
208                 mov             r1,#0xff000000
209 @@ -51,7 +67,11 @@
210                 ldr             r0,=0x4004a800          /* System control register */
211                 str             r0,[r1]
212  
213 -               mov             r0,#0                           /* PLL config */
214 +#ifdef CYG_HAL_STARTUP_ROM                     /* PLL config */
215 +               mov             r0,#0
216 +#else
217 +               ldr             r0,=0x09000e1e
218 +#endif
219                 str             r0,[r1,#8]
220  
221                 ldr             r0,=0xfff00000          /* PORT A mode & dir */
222 @@ -64,7 +84,7 @@
223                 str             r0,[r1,#0x28]
224  
225                 add             r1,r1,#0x100000         /* Setup MEM Module base addr */
226 -               
227 +
228                 ldr             r0,=0x148C0000          /* Memory Module Config register */
229                 str             r0,[r1]
230  
231 @@ -79,7 +99,7 @@
232                 ldr             r0,=0xf3f00304          /* CS0 Option register */
233                 str             r0,[r1,#0x14]
234  
235 -               ldr             r0,=0x02000001          /* CS0 Base Address register */ 
236 +               ldr             r0,=0x02000001          /* CS0 Base Address register */
237                 str             r0,[r1,#0x10]
238  
239                 mov             pc,r2                           /* Jump to new flash base */
240 @@ -92,7 +112,7 @@
241  
242                 /* Configure SDRAM */
243  
244 -               ldr             r0,=0xf38000b0          /* CS1 Option register, BLEN=11 */
245 +               ldr             r0,=0xf3000070          /* CS1 Option register, BLEN=11 */
246                 str             r0,[r1,#0x24]
247  
248                 ldr             r0,=0x0000022d          /* CS1 Base Address register */
249 @@ -110,7 +130,7 @@
250  #if defined(CYG_HAL_STARTUP_ROMRAM)
251                 mov             r1,#0
252                 mov             r2,#HAL_FLASH_PHYS_ADDR
253 -               ldr             r3,=(__heap1 - 0x04000000 + HAL_FLASH_PHYS_ADDR)
254 +               ldr             r3,=(__heap1 - 0x08000000 + HAL_FLASH_PHYS_ADDR)
255  
256                 mov             r4,#0
257                 mov             r6,#0
258 @@ -129,11 +149,11 @@
259                 nop
260                 nop
261                 nop
262 -30:    
263 +30:
264  #endif
265  
266  #endif
267                 .endm
268 -                       
269 +
270  #endif
271  
272 diff -Naur orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi
273 --- orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi  2004-11-29 17:35:46.000000000 +0100
274 +++ new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi   2005-03-10 14:56:07.137708600 +0100
275 @@ -3,34 +3,32 @@
276  MEMORY
277  {
278      noncacheram : ORIGIN = 0, LENGTH = 16*1024*1024
279 -    dataram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
280 -    codecacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
281 +    codecacheram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
282 +    datacacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
283  }
284  
285  SECTIONS
286  {
287      SECTIONS_BEGIN
288 -       _dataram = 0x4000000;
289 +       _dataram = 0x8000000;
290      SECTION_rom_vectors (nocacheram, 0x0, LMA_EQ_VMA)
291      SECTION_fixed_vectors (nocacheram, ALIGN (0x4), LMA_EQ_VMA)
292 -       code_start = . + 0x8000000; 
293 -    SECTION_text (codecacheram, code_start, AT (code_start - 0x8000000))
294 +       code_start = . + 0x4000000; 
295 +    SECTION_text (codecacheram, code_start, AT (code_start - 0x4000000))
296         fini = .;
297 -    SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x8000000))
298 +    SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x4000000))
299         rodata = .;
300 -    SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x8000000))
301 +    SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x4000000))
302         rodata1 = .;
303 -    SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x8000000))
304 +    SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x4000000))
305         fixup = .;
306 -    SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x8000000))
307 +    SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x4000000))
308         gcc_except_table =.;
309 -    SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x8000000))
310 -       data_start = ALIGN(0x4) - 0x4000000; 
311 -    SECTION_data (dataram, data_start, AT (data_start - 0x4000000))
312 +    SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x4000000))
313 +       data_start = ALIGN(0x4) + 0x4000000; 
314 +    SECTION_data (datacacheram, data_start, AT (data_start - 0x8000000))
315         bss = .;
316 -    SECTION_bss (dataram, ALIGN (0x4), AT (bss - 0x4000000))
317 +    SECTION_bss (datacacheram, ALIGN (0x4), AT (bss - 0x8000000))
318      CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
319      SECTIONS_END
320  }
321 -
322 -
323 diff -Naur orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi
324 --- orig/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi       2004-11-29 17:35:46.000000000 +0100
325 +++ new/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi        2005-03-10 14:56:18.184583600 +0100
326 @@ -3,34 +3,32 @@
327  MEMORY
328  {
329      noncacheram : ORIGIN = 0, LENGTH = 16*1024*1024
330 -    dataram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
331 -    codecacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
332 +    codecacheram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
333 +    datacacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
334  }
335  
336  SECTIONS
337  {
338      SECTIONS_BEGIN
339 -       _dataram = 0x4000000;
340 +       _dataram = 0x8000000;
341      SECTION_rom_vectors (nocacheram, 0x0, LMA_EQ_VMA)
342      SECTION_fixed_vectors (nocacheram, ALIGN (0x4), LMA_EQ_VMA)
343 -       code_start = . + 0x8000000; 
344 -    SECTION_text (codecacheram, code_start, AT (code_start -  0x8000000))
345 +       code_start = . + 0x4000000; 
346 +    SECTION_text (codecacheram, code_start, AT (code_start - 0x4000000))
347         fini = .;
348 -    SECTION_fini (codecacheram, ALIGN (0x4), AT (fini -  0x8000000))
349 +    SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x4000000))
350         rodata = .;
351 -    SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata -  0x8000000))
352 +    SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x4000000))
353         rodata1 = .;
354 -    SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 -  0x8000000))
355 +    SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x4000000))
356         fixup = .;
357 -    SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup -  0x8000000))
358 -       gcc_except_table = .;
359 -    SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table -  0x8000000))
360 -       data_start = . - 0x4000000; 
361 -    SECTION_data (dataram, data_start, AT (data_start -  0x4000000))
362 +    SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x4000000))
363 +       gcc_except_table =.;
364 +    SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x4000000))
365 +       data_start = ALIGN(0x4) + 0x4000000; 
366 +    SECTION_data (datacacheram, data_start, AT (data_start - 0x8000000))
367         bss = .;
368 -    SECTION_bss (dataram, ALIGN (0x4), AT (bss -  0x4000000))
369 +    SECTION_bss (datacacheram, ALIGN (0x4), AT (bss - 0x8000000))
370      CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
371      SECTIONS_END
372  }
373 -
374 -
375 diff -Naur orig/hal/arm/netarm/current/include/plf_mmap.h new/hal/arm/netarm/current/include/plf_mmap.h
376 --- orig/hal/arm/netarm/current/include/plf_mmap.h      1970-01-01 01:00:00.000000000 +0100
377 +++ new/hal/arm/netarm/current/include/plf_mmap.h       2005-04-01 11:13:23.378304500 +0200
378 @@ -0,0 +1,62 @@
379 +#ifndef CYGONCE_HAL_NETARM_PLATFORM_PLF_MMAP_H
380 +#define CYGONCE_HAL_NETARM_PLATFORM_PLF_MMAP_H
381 +//==========================================================================
382 +//
383 +//      plf_mmap.h
384 +//
385 +//      Platform specific memory map support
386 +//
387 +//==========================================================================
388 +//####ECOSGPLCOPYRIGHTBEGIN####
389 +// -------------------------------------------
390 +// This file is part of eCos, the Embedded Configurable Operating System
391 +// Copyright (C) 2005 eCosCentric Ltd.
392 +//
393 +// eCos is free software; you can redistribute it and/or modify it under
394 +// the terms of the GNU General Public License as published by the Free
395 +// Software Foundation; either version 2 or (at your option) any later version.
396 +//
397 +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
398 +// WARRANTY; without even the implied warranty of MERCHANTABILITY or
399 +// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
400 +// for more details.
401 +//
402 +// You should have received a copy of the GNU General Public License along
403 +// with eCos; if not, write to the Free Software Foundation, Inc.,
404 +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
405 +//
406 +// As a special exception, if other files instantiate templates or use macros
407 +// or inline functions from this file, or you compile this file and link it
408 +// with other works to produce a work based on this file, this file does not
409 +// by itself cause the resulting work to be covered by the GNU General Public
410 +// License. However the source code for this file must still be made available
411 +// in accordance with section (3) of the GNU General Public License.
412 +//
413 +// This exception does not invalidate any other reasons why a work based on
414 +// this file might be covered by the GNU General Public License.
415 +//
416 +// -------------------------------------------
417 +//####ECOSGPLCOPYRIGHTEND####
418 +//==========================================================================
419 +//#####DESCRIPTIONBEGIN####
420 +//
421 +// Author(s):           Harald Brandl (harald.brandl@fh-joanneum.at)
422 +// Contributors:        Harald Brandl
423 +// Date:                01.04.2005
424 +// Purpose:             NET+ARM memory map macro
425 +// Description:
426 +//
427 +//####DESCRIPTIONEND####
428 +//
429 +//==========================================================================
430 +
431 +
432 +extern unsigned int _dataram;
433 +
434 +
435 +#define HAL_CACHED_TO_UNCACHED_ADDRESS( caddr, uaddr, type ) CYG_MACRO_START       \
436 +    uaddr = (type)((cyg_uint32)caddr - (cyg_uint32)(&_dataram)); \
437 +CYG_MACRO_END
438 +
439 +//---------------------------------------------------------------------------
440 +#endif // CYGONCE_HAL_NETARM_PLATFORM_PLF_MMAP_H
441 diff -Naur orig/hal/arm/netarm/current/src/netarm_misc.c new/hal/arm/netarm/current/src/netarm_misc.c
442 --- orig/hal/arm/netarm/current/src/netarm_misc.c       2004-11-29 17:35:48.000000000 +0100
443 +++ new/hal/arm/netarm/current/src/netarm_misc.c        2005-02-22 11:57:58.296703200 +0100
444 @@ -7,15 +7,15 @@
445  //==========================================================================
446  //==========================================================================
447  //#####DESCRIPTIONBEGIN####
448 -// 
449 +//
450  // Author(s):    Peter De Schrijver (p2@mind.be)
451  // Contributors: Peter De Schrijver (p2@mind.be)
452  // Date:         2002-10-25
453  // Purpose:      HAL board support
454  // Description:  Implementations of HAL board interfaces
455 -// 
456 +//
457  //####DESCRIPTIONEND####
458 -// 
459 +//
460  //========================================================================*/
461  
462  #include <pkgconf/hal.h>
463 @@ -29,7 +29,7 @@
464  #include <cyg/hal/hal_io.h>             // IO macros
465  #include <cyg/hal/hal_arch.h>           // Register state info
466  #include <cyg/hal/hal_diag.h>
467 -#include <cyg/hal/hal_intr.h>           // Interrupt names 
468 +#include <cyg/hal/hal_intr.h>           // Interrupt names
469  #include <cyg/hal/hal_cache.h>
470  #include <cyg/hal/hal_netarm.h>         // Hardware definitions
471  #include <cyg/hal/hal_if.h>             // calling interface API
472 @@ -74,9 +74,9 @@
473  void hal_clock_read(cyg_uint32 *pvalue) {
474  
475         static cyg_uint32 clock_val;
476 -       
477 -       clock_val=*TIMERSTAT1 & 0x1ff; 
478 -       *pvalue = (cyg_uint32)(_period - clock_val); 
479 +
480 +       clock_val=*TIMERSTAT1 & 0x1ff;
481 +       *pvalue = (cyg_uint32)(_period - clock_val);
482  
483  }
484  
485 @@ -97,24 +97,19 @@
486  
487  void hal_hardware_init(void) {
488  
489 +#if defined (CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP) ||   \
490 +       defined (CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP)
491  
492 -#ifdef ENABLECACHE
493 -       /* CS1 BSIZE = 4 */
494 -       *OR1&=~(3 << 4);
495 -       *OR1|=1 << 4;
496 -       
497 -       HAL_ICACHE_ENABLE();
498 -#endif /* ENABLECACHE */
499 +       HAL_CACHE_ENABLE();
500  
501 +#endif /* ENABLECACHE */
502  
503         *INTENABLE_CLR=0xffffffff;
504 -                       
505 +
506         hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
507  
508         hal_if_init();
509  
510 -//     HAL_ICACHE_DISABLE();
511 -
512  }
513  
514  int hal_spurious_ints;
515 @@ -125,8 +120,8 @@
516         int i;
517  
518         stat=*INTSTATUS;
519 -       
520 -       for(i=0;i<CYGNUM_HAL_ISR_MAX;i++) 
521 +
522 +       for(i=0;i<CYGNUM_HAL_ISR_MAX;i++)
523                 if(stat & (1<<i))
524                         return i+1;
525  
526 @@ -154,7 +149,7 @@
527  
528         if((vector>=CYGNUM_HAL_INTERRUPT_C0) && (vector<=CYGNUM_HAL_INTERRUPT_C3)) {
529                 *PORTC|=1<< (vector+23);
530 -       if(up) 
531 +       if(up)
532                         *PORTC|=1<< (vector+15);
533                 else
534                         *PORTC&=~(1<< (vector+15));