1 //==========================================================================
5 // NetSilion NET+ARM PHY chip configuration
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 2005 eCosCentric Ltd.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // -------------------------------------------
37 //####ECOSGPLCOPYRIGHTEND####
38 //==========================================================================
39 //#####DESCRIPTIONBEGIN####
41 // Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
42 // Contributors: Harald Brandl
44 // Purpose: PHY chip configuration
47 //####DESCRIPTIONEND####
49 //==========================================================================
54 #define PHYS(_i_) (0x800 | _i_)
56 #define SysReg (unsigned *)0xffb00004 // System Status Register
58 /* Function: void cyg_netarm_mii_poll_busy (void)
61 * This routine is responsible for waiting for the current PHY
62 * operation to complete.
72 /* check to see if PHY is busy with read or write */
75 HAL_READ_UINT32(MIIIR, reg);
79 /* Function: void cyg_netarm_mii_reset (void)
83 * This routine resets the PHY.
90 cyg_netarm_mii_reset(void)
92 HAL_WRITE_UINT32(MIIAR, PHYS(0)); // select command register
93 HAL_WRITE_UINT32(MIIWDR, 0x8000); // reset
97 /* Function: cyg_bool cyg_netarm_mii_negotiate (void)
100 * This routine is responsible for causing the external Ethernet PHY
101 * to begin the negotatiation process.
112 cyg_netarm_mii_negotiate(void)
114 unsigned timeout = 100000, reg;
116 HAL_WRITE_UINT32(MIIAR, PHYS(4));
120 HAL_WRITE_UINT32(MIIAR, PHYS(0));
121 HAL_OR_UINT32(MIIWDR, 0x1200);
127 HAL_WRITE_UINT32(MIIAR, PHYS(1));
128 HAL_WRITE_UINT32(MIICR, 1);
132 HAL_READ_UINT32(MIIRDR, reg);
134 if(0x24 == (reg & 0x24))
144 /* Function: void cyg_netarm_mii_set_speed (cyg_bool speed, cyg_bool duplex)
148 * This routine will set the speed and duplex of the external PHY.
163 cyg_netarm_mii_set_speed(cyg_uint32 speed, cyg_bool duplex)
165 unsigned timeout = 1000000, reg;
167 HAL_WRITE_UINT32(MIIAR, PHYS(0)); // select command register
168 HAL_WRITE_UINT32(MIIWDR, (speed << 13) | (duplex << 8)); // set speed and duplex
173 HAL_WRITE_UINT32(MIIAR, PHYS(1)); // select status register
174 HAL_WRITE_UINT32(MIICR, 1);
176 HAL_READ_UINT32(MIIRDR, reg);
183 /* Function: cyg_bool cyg_netarm_mii_check_speed
187 * This routine will check the operating speed of the ethernet
199 cyg_netarm_mii_check_speed(void)
203 HAL_WRITE_UINT32(MIIAR, PHYS(17));
204 HAL_WRITE_UINT32(MIICR, 1);
206 HAL_READ_UINT32(MIIRDR, reg);
207 return (reg >> 14) & 1;
210 /* Function: void cyg_netarm_mii_check_duplex
214 * This routine will check the operating duplex of the ethernet
226 cyg_netarm_mii_check_duplex(void)
230 HAL_WRITE_UINT32(MIIAR, PHYS(17));
231 HAL_WRITE_UINT32(MIICR, 1);
233 HAL_READ_UINT32(MIIRDR, reg);
234 return (reg >> 9) & 1;