1 #ifndef _NETARM_ethregs_
2 #define _NETARM_ethregs_
3 // ====================================================================
7 // Address mappings for ethernet and DMA controller registers
9 // ====================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 2005 eCosCentric LTD
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
37 // ====================================================================
38 //#####DESCRIPTIONBEGIN####
40 // Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
41 // Contributors: Harald Brandl
43 // Purpose: Ethernet and DMA controller registers
46 //####DESCRIPTIONEND####
48 // ====================================================================
52 #define EthGenCR *(volatile unsigned *)0xff800000
53 #define EthGenSR *(volatile unsigned *)0xff800004
54 #define EthFIFODR *(volatile unsigned *)0xff800008
55 #define EthFIFODRkickoff *(volatile unsigned *)0xff80000c
56 #define EthTxSR *(volatile unsigned *)0xff800010
57 #define EthRxSR *(volatile unsigned *)0xff800014
58 #define MACCR *(volatile unsigned *)0xff800400
59 #define MACTR *(volatile unsigned *)0xff800404
60 #define PCSCR *(volatile unsigned *)0xff800408
61 #define PCSTR *(volatile unsigned *)0xff80040c
62 #define STLCR *(volatile unsigned *)0xff800410
63 #define STLTR *(volatile unsigned *)0xff800414
64 #define BtBIPGGapTimerR *(volatile unsigned *)0xff800440
65 #define NonBtBIPGGapTimerR *(volatile unsigned *)0xff800444
66 #define CollWinR *(volatile unsigned *)0xff800448
67 #define TxPNCR *(volatile unsigned *)0xff800460
68 #define TxBCR *(volatile unsigned *)0xff800464
69 #define ReTxBCR *(volatile unsigned *)0xff800468
70 #define TxRNG *(volatile unsigned *)0xff80046c
71 #define TxMRN *(volatile unsigned *)0xff800470
72 #define TxCDec *(volatile unsigned *)0xff800474
73 #define TOTxC *(volatile unsigned *)0xff800478
74 #define RxBC *(volatile unsigned *)0xff800480
75 #define RxCDec *(volatile unsigned *)0xff800484
76 #define TORxC *(volatile unsigned *)0xff800488
77 #define LnFC *(volatile unsigned *)0xff8004c0
78 #define JC10M *(volatile unsigned *)0xff800500
79 #define LoCC10M *(volatile unsigned *)0xff800504
80 #define MIICR *(volatile unsigned *)0xff800540
81 #define MIIAR *(volatile unsigned *)0xff800544
82 #define MIIWDR *(volatile unsigned *)0xff800548
83 #define MIIRDR *(volatile unsigned *)0xff80054c
84 #define MIIIR *(volatile unsigned *)0xff800550
85 #define CRCEC *(volatile unsigned *)0xff800580
86 #define AEC *(volatile unsigned *)0xff800584
87 #define CEC *(volatile unsigned *)0xff800588
88 #define LFC *(volatile unsigned *)0xff80058c
89 #define SFC *(volatile unsigned *)0xff800590
90 #define LCC *(volatile unsigned *)0xff800594
91 #define EDC *(volatile unsigned *)0xff800598
92 #define MCC *(volatile unsigned *)0xff80059c
93 #define SAFR *(volatile unsigned *)0xff8005c0
94 #define SAR1 *(volatile unsigned *)0xff8005c4
95 #define SAR2 *(volatile unsigned *)0xff8005c8
96 #define SAR3 *(volatile unsigned *)0xff8005cc
97 #define SAMHT1 *(volatile unsigned *)0xff8005d0
98 #define SAMHT2 *(volatile unsigned *)0xff8005d4
99 #define SAMHT3 *(volatile unsigned *)0xff8005d8
100 #define SAMHT4 *(volatile unsigned *)0xff8005dc
104 #define DMA1A_BDP *(volatile unsigned *)0xff900000
105 #define DMA1A_CR *(volatile unsigned *)0xff900010
106 #define DMA1A_SR *(volatile unsigned *)0xff900014
107 #define DMA1B_BDP *(volatile unsigned *)0xff900020
108 #define DMA1B_CR *(volatile unsigned *)0xff900030
109 #define DMA1B_SR *(volatile unsigned *)0xff900034
110 #define DMA1C_BDP *(volatile unsigned *)0xff900040
111 #define DMA1C_CR *(volatile unsigned *)0xff900050
112 #define DMA1C_SR *(volatile unsigned *)0xff900054
113 #define DMA1D_BDP *(volatile unsigned *)0xff900060
114 #define DMA1D_CR *(volatile unsigned *)0xff900070
115 #define DMA1D_SR *(volatile unsigned *)0xff900074
116 #define DMA2_BDP *(volatile unsigned *)0xff900080
117 #define DMA2_CR *(volatile unsigned *)0xff900090
118 #define DMA2_SR *(volatile unsigned *)0xff900094