packages/devs/eth/arm/tx51karo/v1_0/include/devs_eth_arm_tx51.inl

   1 //==========================================================================
   2 //
   3 //      devs_eth_arm_tx51.inl
   4 //
   5 //      Board ethernet I/O definitions.
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //===========================================================================
  41
  42 #include <cyg/hal/hal_intr.h>                   // CYGNUM_HAL_INTERRUPT_ETHR
  43 #include <cyg/hal/hal_if.h>
  44 #include <cyg/hal/mx51_iomux.h>
  45
  46 #ifdef CYGPKG_REDBOOT
  47 #include <pkgconf/redboot.h>
  48 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
  49 #include <redboot.h>
  50 #include <flash_config.h>
  51 #endif
  52 #endif
  53
  54
  55 #ifdef __WANT_DEVS
  56
  57 #ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
  58
  59 #ifdef CYGPKG_DEVS_ETH_PHY
  60
  61 static char  mxc_fec_name[] = "mxc_fec";
  62
  63 #define MX51_GPIO_ADDR(bank)                    (GPIO1_BASE_ADDR + (((bank) - 1) << 14))
  64 #define FEC_POWER_GPIO                                  1, 3
  65 #define FEC_RESET_GPIO                                  2, 14
  66
  67 #ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
  68 //
  69 // Verify that the given ESA is valid for this platform
  70 //
  71 static char oui[3] = CYGDAT_DEVS_ETH_ARM_TX51KARO_OUI;
  72
  73 bool
  74 cyg_plf_redboot_esa_validate(unsigned char *val)
  75 {
  76         return (val[0] == oui[0]) && (val[1] == oui[1]) && (val[2] == oui[2]);
  77 }
  78 #endif
  79
  80 extern int tx51_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN]);
  81
  82 static inline void tx51_write_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset, CYG_WORD32 val)
  83 {
  84         if (net_debug) {
  85                 diag_printf("Changing reg %08x from %08x to %08x\n",
  86                                         base_addr + offset, readl(base_addr + offset), val);
  87         }
  88         HAL_WRITE_UINT32(base_addr + offset, val);
  89 }
  90
  91 static inline CYG_WORD32 tx51_read_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset)
  92 {
  93         CYG_WORD32 val;
  94
  95         HAL_READ_UINT32(base_addr + offset, val);
  96         if (net_debug) diag_printf("Read %08x from reg %08x\n", val, base_addr + offset);
  97         return val;
  98 }
  99
 100 static inline void tx51_set_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset,
 101                                                                 CYG_WORD32 set_mask, CYG_WORD32 clr_mask)
 102 {
 103         CYG_WORD32 val;
 104
 105         HAL_READ_UINT32(base_addr + offset, val);
 106         if (net_debug) diag_printf("Changing reg %08x from %08x to %08x\n", base_addr + offset, val,
 107                                    (val & ~clr_mask) | set_mask);
 108         val = (val & ~clr_mask) | set_mask;
 109         HAL_WRITE_UINT32(base_addr + offset, val);
 110 }
 111
 112 static struct tx51_gpio_setup {
 113         cyg_uint32 iomux_addr;
 114         cyg_uint8 on_func;
 115         cyg_uint8 off_func;
 116         cyg_uint8 grp;
 117         cyg_uint8 shift;
 118 } tx51_fec_gpio_data[] = {
 119         /* iomux reg offset,                    func,       gpgrp, */
 120         /*                                                                    gpiofn,  gpshift, */
 121         { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3,              0x12, 0x13, 3, 19, },
 122         { IOMUXC_SW_MUX_CTL_PAD_EIM_EB2,                0x13, 0x11, 2, 22, },
 123         { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3,              0x11, 0x13, 3, 11, },
 124         { IOMUXC_SW_MUX_CTL_PAD_NANDF_D11,              0x12, 0x13, 3, 29, },
 125         { IOMUXC_SW_MUX_CTL_PAD_NANDF_D9,               0x12, 0x13, 3, 31, },
 126         { IOMUXC_SW_MUX_CTL_PAD_EIM_EB3,                0x13, 0x11, 2, 23, },
 127         { IOMUXC_SW_MUX_CTL_PAD_EIM_CS2,                0x13, 0x11, 2, 27, },
 128         { IOMUXC_SW_MUX_CTL_PAD_EIM_CS3,                0x13, 0x11, 2, 28, },
 129         { IOMUXC_SW_MUX_CTL_PAD_EIM_CS4,                0x13, 0x11, 2, 29, },
 130         { IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT,  0x11, 0x13, 3, 24, },
 131         { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7,              0x11, 0x13, 3, 23, },
 132         { IOMUXC_SW_MUX_CTL_PAD_NANDF_D8,               0x12, 0x13, 4,  0, },
 133         { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4,              0x12, 0x13, 3, 20, },
 134         { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5,              0x12, 0x13, 3, 21, },
 135         { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6,              0x12, 0x13, 3, 22, },
 136         { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2,              0x11, 0x13, 3, 10, },
 137         { IOMUXC_SW_MUX_CTL_PAD_EIM_CS5,                0x13, 0x11, 2, 30, },
 138         { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2,              0x13, 0x13, 3, 18, },
 139 };
 140
 141 static struct tx51_gpio_setup tx51_fec_pwr_pins[] = {
 142         { IOMUXC_SW_MUX_CTL_PAD_EIM_A20,                0x11, 0x11, 2, 14, }, /* PHY reset */
 143         { IOMUXC_SW_MUX_CTL_PAD_GPIO1_3,                0x10, 0x10, 1,  3, }, /* PHY power enable */
 144 };
 145
 146 static struct tx51_gpio_setup tx51_fec_strap_pins[] = {
 147         { IOMUXC_SW_MUX_CTL_PAD_GPIO1_3,                0x10, 0x10, 1,  3, }, /* PHY Power enable */
 148         { IOMUXC_SW_MUX_CTL_PAD_NANDF_D9,               0x12, 0x13, 3, 31, }, /* Mode[0] */
 149         { IOMUXC_SW_MUX_CTL_PAD_EIM_EB3,                0x13, 0x11, 2, 23, }, /* Mode[1] */
 150         { IOMUXC_SW_MUX_CTL_PAD_EIM_CS2,                0x13, 0x11, 2, 27, }, /* Mode[2] */
 151 #if 0
 152         { IOMUXC_SW_MUX_CTL_PAD_EIM_CS3,                0x13, 0x11, 2, 28, }, /* nINTSEL */
 153 #endif
 154 };
 155
 156 static inline void tx51_phy_power_off(void)
 157 {
 158         int i;
 159
 160         if (net_debug) diag_printf("Switching PHY POWER off\n");
 161 #if 1
 162         for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
 163                 struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
 164
 165                 if (net_debug) diag_printf("%s: GPIO%d_%d[%d] is %d\n", __FUNCTION__,
 166                                                                    gs->grp, gs->shift, i,
 167                                                                    gpio_tst_bit(gs->grp, gs->shift));
 168         }
 169 #endif
 170         /* deassert all pins attached to the PHY */
 171         for (i = 0; i < NUM_ELEMS(tx51_fec_pwr_pins); i++) {
 172                 struct tx51_gpio_setup *gs = &tx51_fec_pwr_pins[i];
 173
 174                 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
 175                                          GPIO_DR, 0, 1 << gs->shift);
 176                 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
 177                                          GPIO_GDIR, 1 << gs->shift, 0);
 178         }
 179         for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
 180                 struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
 181 #if 0
 182                 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
 183                                          GPIO_GDIR, 0, 1 << gs->shift);
 184 #else
 185                 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
 186                                          GPIO_DR, 0, 1 << gs->shift);
 187                 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
 188                                          GPIO_GDIR, 1 << gs->shift, 0);
 189 #endif
 190                 tx51_write_reg(0, gs->iomux_addr, gs->off_func);
 191         }
 192         for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
 193                 struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
 194
 195                 if (gpio_tst_bit(gs->grp, gs->shift)) {
 196                         diag_printf("%s: GPIO%d_%d[%d] is not low\n", __FUNCTION__,
 197                                                 gs->grp, gs->shift, i);
 198                 }
 199         }
 200         if (net_debug) diag_printf("PHY POWER off done\n");
 201 }
 202
 203 static bool mxc_fec_init(struct cyg_netdevtab_entry *tab);
 204 static bool tx51_fec_init(struct cyg_netdevtab_entry *tab)
 205 {
 206 #if 1
 207         cyg_bool esa_set;
 208         int ok;
 209
 210         /* Check, whether MAC address is enabled */
 211         ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
 212                                                                          "fec_esa", &esa_set, CONFIG_BOOL);
 213 #if 0
 214 ok |= 0;
 215 //esa_set |= ok;
 216 net_debug |= 1;
 217 #endif
 218         if (!(ok && esa_set)) {
 219                 diag_printf("FEC disabled; set fec_esa=true to enable networking\n");
 220                 return false;
 221         }
 222 #endif
 223         return mxc_fec_init(tab);
 224 }
 225
 226 static void tx51_fec_phy_init(void)
 227 {
 228         int i;
 229         int phy_reset_delay = 100;
 230         int dbg = net_debug;
 231
 232 #if 0
 233         net_debug |= 1;
 234 #endif
 235         /*
 236          * make sure the ETH PHY strap pins are pulled to the right voltage
 237          * before deasserting the PHY reset GPIO
 238          */
 239         /* assert FEC PHY Reset (GPIO2_14) and switch PHY power on (GPIO1_3) */
 240
 241 #if 0
 242         tx51_phy_power_off();
 243 #endif
 244
 245         if (!gpio_tst_bit(1, 3)) {
 246                 if (0 || net_debug) diag_printf("Switching PHY POWER on\n");
 247                 gpio_clr_bit(2, 14);
 248                 gpio_set_bit(1, 3);
 249                 /* wait for 22ms for LAN8700 to power up */
 250                 phy_reset_delay = 22000;
 251 #if 1
 252                 if (!gpio_tst_bit(1, 3)) {
 253                         diag_printf("**Failed to switch PHY power on: GPIO1_PSR[%08lx]=%08x\n",
 254                                                 MX51_GPIO_ADDR(1) + GPIO_PSR,
 255                                                 tx51_read_reg(MX51_GPIO_ADDR(1), GPIO_PSR));
 256                 }
 257 #endif
 258 #if 1
 259                 if (gpio_tst_bit(2, 14)) {
 260                         diag_printf("**Failed to assert PHY reset: GPIO2_PSR[%08lx]=%08x\n",
 261                                                 MX51_GPIO_ADDR(2) + GPIO_PSR,
 262                                                 tx51_read_reg(MX51_GPIO_ADDR(2), GPIO_PSR));
 263                 }
 264 #endif
 265         } else {
 266                 if (0 || net_debug) diag_printf("Asserting PHY RESET\n");
 267                 gpio_clr_bit(2, 14);
 268 #if 1
 269                 if (gpio_tst_bit(2, 14)) {
 270                         diag_printf("**Failed to assert PHY reset: GPIO2_PSR[%08lx]=%08x\n",
 271                                                 MX51_GPIO_ADDR(2) + GPIO_PSR,
 272                                                 tx51_read_reg(MX51_GPIO_ADDR(2), GPIO_PSR));
 273                 }
 274 #endif
 275         }
 276         for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
 277                 struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
 278                 int j;
 279                 int strap = 0;
 280
 281                 for (j = 0; j < NUM_ELEMS(tx51_fec_strap_pins); j++) {
 282                         struct tx51_gpio_setup *sp = &tx51_fec_strap_pins[j];
 283
 284                         if (gs->grp == sp->grp && gs->shift == sp->shift) {
 285                                 strap = 1;
 286                                 break;
 287                         }
 288                 }
 289                 if (strap) {
 290                         gpio_set_bit(gs->grp, gs->shift);
 291                         if (net_debug) diag_printf("Setting GPIO%d_%d[%d] high\n",
 292                                                                            gs->grp, gs->shift, i);
 293                 } else {
 294                         gpio_clr_bit(gs->grp, gs->shift);
 295                         if (net_debug) diag_printf("Setting GPIO%d_%d[%d] low\n",
 296                                                                            gs->grp, gs->shift, i);
 297                 }
 298                 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
 299                                          GPIO_GDIR, 1 << gs->shift, 0);
 300                 tx51_write_reg(0, gs->iomux_addr,
 301                                            gs->off_func);
 302         }
 303 #if 1
 304         /* configure FEC strap pins to their required values */
 305         for (i = 0; i < NUM_ELEMS(tx51_fec_strap_pins); i++) {
 306                 struct tx51_gpio_setup *gs = &tx51_fec_strap_pins[i];
 307
 308                 if (net_debug) diag_printf("Asserting GPIO%d_%d\n", gs->grp,
 309                                                                    gs->shift);
 310                 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
 311                                          GPIO_GDIR, 1 << gs->shift, 0);
 312                 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
 313                                          GPIO_DR, 1 << gs->shift, 0);
 314                 tx51_write_reg(0, gs->iomux_addr,
 315                                            gs->off_func);
 316                 gpio_set_bit(gs->grp, gs->shift);
 317                 if (!gpio_tst_bit(gs->grp, gs->shift)) {
 318                         diag_printf("**Failed to assert GPIO%d_%d: GPIO%d_PSR[%08lx]=%08x\n",
 319                                                 gs->grp, gs->shift, gs->grp,
 320                                                 MX51_GPIO_ADDR(gs->grp) + GPIO_PSR,
 321                                                 tx51_read_reg(MX51_GPIO_ADDR(gs->grp), GPIO_PSR));
 322                 }
 323         }
 324 #endif
 325         for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
 326                 struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
 327                 int j;
 328                 int strap = 0;
 329
 330                 for (j = 0; j < NUM_ELEMS(tx51_fec_strap_pins); j++) {
 331                         struct tx51_gpio_setup *sp = &tx51_fec_strap_pins[j];
 332
 333                         if (gs->grp == sp->grp && gs->shift == sp->shift) {
 334                                 strap = 1;
 335                                 break;
 336                         }
 337                 }
 338                 if (strap) {
 339                         if (!gpio_tst_bit(gs->grp, gs->shift)) {
 340                                 diag_printf("GPIO%d_%d[%d] is low instead of high\n",
 341                                                         gs->grp, gs->shift, i);
 342                         }
 343                 } else {
 344                         if (gpio_tst_bit(gs->grp, gs->shift)) {
 345                                 diag_printf("GPIO%d_%d[%d] is high instead of low\n",
 346                                                         gs->grp, gs->shift, i);
 347                         }
 348                 }
 349         }
 350         /* wait for 100us according to LAN8700 spec. before ... */
 351         HAL_DELAY_US(phy_reset_delay);
 352         /* ... deasserting FEC PHY reset */
 353         if (0 || net_debug) diag_printf("Releasing PHY RESET\n");
 354         gpio_set_bit(2, 14);
 355         if (!gpio_tst_bit(2, 14)) {
 356                 diag_printf("**Failed to release PHY reset\n");
 357         }
 358
 359         /* configure all FEC pins to their required functions */
 360         for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
 361                 struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
 362
 363                 tx51_write_reg(0, gs->iomux_addr, gs->on_func);
 364                 HAL_DELAY_US(10000);
 365         }
 366         net_debug = dbg;
 367 }
 368
 369 ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy,
 370                                                           tx51_fec_phy_init,
 371                                                           mxc_fec_phy_reset,
 372                                                           mxc_fec_phy_write,
 373                                                           mxc_fec_phy_read);
 374
 375 cyg_bool _tx51_provide_fec_esa(unsigned char *addr)
 376 {
 377         cyg_bool enabled;
 378         int ok;
 379
 380         ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
 381                                          "fec_esa", &enabled, CONFIG_BOOL);
 382         if (ok && enabled) {
 383 #ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
 384                 cyg_uint8 addr2[ETHER_ADDR_LEN];
 385
 386                 addr[0] = readl(SOC_FEC_MAC_BASE + 0x14);
 387                 addr[1] = readl(SOC_FEC_MAC_BASE + 0x10);
 388                 addr[2] = readl(SOC_FEC_MAC_BASE + 0xC);
 389                 addr[3] = readl(SOC_FEC_MAC_BASE + 0x8);
 390                 addr[4] = readl(SOC_FEC_MAC_BASE + 0x4);
 391                 addr[5] = readl(SOC_FEC_MAC_BASE + 0x0);
 392
 393                 if (cyg_plf_redboot_esa_validate(addr)) {
 394                         diag_printf("Ethernet FEC MAC address from fuse bank: ");
 395                         diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
 396                                                 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
 397                         CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
 398                                                                                 "fec_esa_data", addr2, CONFIG_ESA);
 399                         if (memcmp(addr, addr2, sizeof(addr)) != 0) {
 400                                 CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_SET,
 401                                                                                         "fec_esa_data", addr, CONFIG_ESA);
 402                         }
 403 #ifdef SOC_MAC_ADDR_LOCK_FUSE
 404                         if ((readl(IIM_BASE_ADDR + 0x800 + SOC_MAC_ADDR_FUSE_BANK * 0x400 +
 405                                            SOC_MAC_ADDR_LOCK_FUSE * 4) &
 406                                  SOC_MAC_ADDR_LOCK_BIT) == 0) {
 407                                 tx51_mac_addr_program(addr);
 408                         }
 409 #endif // SOC_MAC_ADDR_LOCK_FUSE
 410                         return true;
 411                 }
 412 #endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
 413
 414                 CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
 415                                                                         "fec_esa_data", addr, CONFIG_ESA);
 416
 417                 diag_printf("Ethernet FEC MAC address from fconfig: ");
 418                 diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
 419                                         addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
 420
 421 #ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
 422                 if (cyg_plf_redboot_esa_validate(addr)) {
 423                         tx51_mac_addr_program(addr);
 424                         return true;
 425                 }
 426
 427                 diag_printf("** Error: Invalid MAC address: ");
 428                 diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
 429                                         addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
 430
 431                 writel(addr[0], SOC_FEC_MAC_BASE + 0x14);
 432                 writel(addr[1], SOC_FEC_MAC_BASE + 0x10);
 433                 writel(addr[2], SOC_FEC_MAC_BASE + 0xC);
 434                 writel(addr[3], SOC_FEC_MAC_BASE + 0x8);
 435                 writel(addr[4], SOC_FEC_MAC_BASE + 0x4);
 436                 writel(addr[5], SOC_FEC_MAC_BASE + 0x0);
 437
 438 #ifdef SOC_MAC_ADDR_LOCK_FUSE
 439                 if ((readl(IIM_BASE_ADDR + 0x800 + SOC_MAC_ADDR_FUSE_BANK * 0x400 +
 440                                    SOC_MAC_ADDR_LOCK_FUSE * 4) &
 441                          SOC_MAC_ADDR_LOCK_BIT) == 0) {
 442                         diag_printf("Use 'fconfig fec_esa_data' to set the MAC address\n");
 443                         return false;
 444                 } else {
 445                         diag_printf("Using MAC address from fconfig\n");
 446                 }
 447 #else
 448                 diag_printf("Using MAC address from fconfig\n");
 449 #endif // SOC_MAC_ADDR_LOCK_FUSE
 450 #endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
 451                 return true;
 452         }
 453         return false;
 454 }
 455
 456 static mxc_fec_priv_t mxc_fec_private = {
 457         .phy = &eth0_phy,                                                         // PHY access routines
 458         .provide_esa = _tx51_provide_fec_esa,
 459 };
 460
 461 ETH_DRV_SC(mxc_fec_sc,
 462                    &mxc_fec_private, // Driver specific data
 463                    mxc_fec_name,
 464                    mxc_fec_start,
 465                    mxc_fec_stop,
 466                    mxc_fec_control,
 467                    mxc_fec_can_send,
 468                    mxc_fec_send,
 469                    mxc_fec_recv,
 470                    mxc_fec_deliver,             // "pseudoDSR" called from fast net thread
 471                    mxc_fec_poll,                // poll function, encapsulates ISR and DSR
 472                    mxc_fec_int_vector);
 473
 474 NETDEVTAB_ENTRY(mxc_fec_netdev,
 475                                 mxc_fec_name,
 476                                 tx51_fec_init,
 477                                 &mxc_fec_sc);
 478 #endif
 479
 480 #if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
 481 RedBoot_config_option("Set FEC network hardware address [MAC]",
 482                                           fec_esa,
 483                                           ALWAYS_ENABLED, true,
 484                                           CONFIG_BOOL, false
 485                                          );
 486 RedBoot_config_option("FEC network hardware address [MAC]",
 487                                           fec_esa_data,
 488                                           "fec_esa", true,
 489                                           CONFIG_ESA, 0
 490                                          );
 491 #endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
 492
 493 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
 494 // Note that this section *is* active in an application, outside RedBoot,
 495 // where the above section is not included.
 496
 497 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
 498 #endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
 499
 500 #endif // __WANT_DEVS