1 //==========================================================================
3 // devs_eth_arm_tx51.inl
5 // Board ethernet I/O definitions.
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //===========================================================================
42 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
43 #include <cyg/hal/hal_if.h>
44 #include <cyg/hal/mx51_iomux.h>
47 #include <pkgconf/redboot.h>
48 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
50 #include <flash_config.h>
57 #ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
59 #ifdef CYGPKG_DEVS_ETH_PHY
61 static bool mxc_fec_init(struct cyg_netdevtab_entry *tab);
63 static char mxc_fec_name[] = "mxc_fec";
65 #define MX51_GPIO_ADDR(bank) (GPIO1_BASE_ADDR + (((bank) - 1) << 14))
66 #define FEC_POWER_GPIO 1, 3
67 #define FEC_RESET_GPIO 2, 14
69 #ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
71 // Verify that the given ESA is valid for this platform
73 static char oui[3] = CYGDAT_DEVS_ETH_ARM_TX51KARO_OUI;
75 bool cyg_plf_redboot_esa_validate(unsigned char *val)
77 return (val[0] == oui[0]) && (val[1] == oui[1]) && (val[2] == oui[2]);
81 extern int tx51_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN]);
83 static inline void tx51_write_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset, CYG_WORD32 val)
86 diag_printf("Changing reg %08x from %08x to %08x\n",
87 base_addr + offset, readl(base_addr + offset), val);
89 HAL_WRITE_UINT32(base_addr + offset, val);
92 static inline CYG_WORD32 tx51_read_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset)
96 HAL_READ_UINT32(base_addr + offset, val);
97 if (net_debug) diag_printf("Read %08x from reg %08x\n", val, base_addr + offset);
101 static inline void tx51_set_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset,
102 CYG_WORD32 set_mask, CYG_WORD32 clr_mask)
106 HAL_READ_UINT32(base_addr + offset, val);
107 if (net_debug) diag_printf("Changing reg %08x from %08x to %08x\n",
108 base_addr + offset, val,
109 (val & ~clr_mask) | set_mask);
110 val = (val & ~clr_mask) | set_mask;
111 HAL_WRITE_UINT32(base_addr + offset, val);
114 static struct tx51_gpio_setup {
115 cyg_uint32 iomux_addr;
120 dir:1, /* 0: input; 1: output */
122 } tx51_fec_gpio_data[] = {
123 /* iomux reg offset, func, gpgrp, in/out */
124 /* gpiofn, gpshft,level */
125 { IOMUXC_SW_MUX_CTL_PAD_EIM_A20, 0x11, 0x11, 2, 14, 1, 0, }, /* PHY reset */
126 { IOMUXC_SW_MUX_CTL_PAD_GPIO1_3, 0x10, 0x10, 1, 3, 1, 1, }, /* PHY power enable */
127 { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3, 0x02, 0x13, 3, 19, 1, 0, }, /* MDC */
128 { IOMUXC_SW_MUX_CTL_PAD_EIM_EB2, 0x03, 0x11, 2, 22, 1, 0, }, /* MDIO */
129 { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3, 0x01, 0x13, 3, 11, 0, }, /* RX_CLK */
130 { IOMUXC_SW_MUX_CTL_PAD_NANDF_D11, 0x02, 0x13, 3, 29, 0, }, /* RX_DV */
131 { IOMUXC_SW_MUX_CTL_PAD_NANDF_D9, 0x02, 0x13, 3, 31, 1, 1, }, /* RXD0/Mode0 */
132 { IOMUXC_SW_MUX_CTL_PAD_EIM_EB3, 0x03, 0x11, 2, 23, 1, 1, }, /* RXD1/Mode1 */
133 { IOMUXC_SW_MUX_CTL_PAD_EIM_CS2, 0x03, 0x11, 2, 27, 1, 1, }, /* RXD2/Mode2 */
134 { IOMUXC_SW_MUX_CTL_PAD_EIM_CS3, 0x03, 0x11, 2, 28, 1, 1, }, /* RXD3/nINTSEL */
135 { IOMUXC_SW_MUX_CTL_PAD_EIM_CS4, 0x03, 0x11, 2, 29, 0, }, /* RX_ER/RXD4 */
136 { IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT, 0x01, 0x13, 3, 24, 0, }, /* TX_CLK */
137 { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7, 0x01, 0x13, 3, 23, 1, 0, }, /* TX_EN */
138 { IOMUXC_SW_MUX_CTL_PAD_NANDF_D8, 0x02, 0x13, 4, 0, 1, 0, }, /* TXD0 */
139 { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4, 0x02, 0x13, 3, 20, 1, 0, }, /* TXD1 */
140 { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5, 0x02, 0x13, 3, 21, 1, 0, }, /* TXD2 */
141 { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6, 0x02, 0x13, 3, 22, 1, 0, }, /* TXD3 */
142 { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2, 0x01, 0x13, 3, 10, 1, 0, }, /* COL/RMII/CRSDV */
143 { IOMUXC_SW_MUX_CTL_PAD_EIM_CS5, 0x03, 0x11, 2, 30, 1, 0, }, /* CRS */
144 { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2, 0x03, 0x13, 3, 18, 0, }, /* nINT/TX_ER/TXD4 */
147 static inline void tx51_phy_gpio_init(void)
151 if (net_debug) diag_printf("PHY GPIO init\n");
153 /* setup all pins attached to the PHY to required level */
154 for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
155 struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
157 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
158 GPIO_DR, gs->level << gs->shift, !gs->level << gs->shift);
159 tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
160 GPIO_GDIR, 1 << gs->shift, 0);
161 tx51_write_reg(gs->iomux_addr, 0, gs->off_func);
163 for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
164 struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
167 if (gs->level ^ gpio_tst_bit(gs->grp, gs->shift)) {
168 diag_printf("%s: GPIO%d_%d[%d] is not %s\n", __FUNCTION__,
169 gs->grp, gs->shift, i, gs->level ? "HIGH" : "LOW");
173 if (net_debug) diag_printf("PHY GPIO init done\n");
176 static bool tx51_fec_init(struct cyg_netdevtab_entry *tab)
181 /* Check, whether MAC address is enabled */
182 ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
183 "fec_esa", &esa_set, CONFIG_BOOL);
184 if (!(ok && esa_set)) {
185 diag_printf("FEC disabled; set fec_esa=true to enable networking\n");
188 return mxc_fec_init(tab);
191 static void tx51_fec_phy_init(void)
194 int phy_reset_delay = 100;
197 * make sure the ETH PHY strap pins are pulled to the right voltage
198 * before deasserting the PHY reset GPIO
200 tx51_phy_gpio_init();
202 /* LAN8700 requires 21ms to power up */
203 phy_reset_delay = 22000;
204 if (!gpio_tst_bit(1, 3)) {
205 diag_printf("**Failed to switch PHY power on: GPIO1_PSR[%08lx]=%08x\n",
206 MX51_GPIO_ADDR(1) + GPIO_PSR,
207 tx51_read_reg(MX51_GPIO_ADDR(1), GPIO_PSR));
209 if (gpio_tst_bit(2, 14)) {
210 diag_printf("**Failed to assert PHY reset: GPIO2_PSR[%08lx]=%08x\n",
211 MX51_GPIO_ADDR(2) + GPIO_PSR,
212 tx51_read_reg(MX51_GPIO_ADDR(2), GPIO_PSR));
215 /* wait the specified time according to LAN8700 spec. before ... */
216 HAL_DELAY_US(phy_reset_delay);
217 /* ... deasserting FEC PHY reset */
218 if (net_debug) diag_printf("Releasing PHY RESET\n");
220 if (!gpio_tst_bit(2, 14)) {
221 diag_printf("**Failed to release PHY reset\n");
225 /* configure all FEC pins to their required functions */
226 for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
227 struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
229 tx51_write_reg(gs->iomux_addr, 0, gs->on_func);
233 ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy,
239 cyg_bool _tx51_provide_fec_esa(unsigned char *addr)
244 ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
245 "fec_esa", &enabled, CONFIG_BOOL);
247 #ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
248 cyg_uint8 addr2[ETHER_ADDR_LEN];
250 addr[0] = readl(SOC_FEC_MAC_BASE + 0x14);
251 addr[1] = readl(SOC_FEC_MAC_BASE + 0x10);
252 addr[2] = readl(SOC_FEC_MAC_BASE + 0xC);
253 addr[3] = readl(SOC_FEC_MAC_BASE + 0x8);
254 addr[4] = readl(SOC_FEC_MAC_BASE + 0x4);
255 addr[5] = readl(SOC_FEC_MAC_BASE + 0x0);
257 if (cyg_plf_redboot_esa_validate(addr)) {
258 diag_printf("Ethernet FEC MAC address from fuse bank: ");
259 diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
260 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
261 CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
262 "fec_esa_data", addr2, CONFIG_ESA);
263 if (memcmp(addr, addr2, sizeof(addr)) != 0) {
264 CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_SET,
265 "fec_esa_data", addr, CONFIG_ESA);
267 #ifdef SOC_MAC_ADDR_LOCK_FUSE
268 if ((readl(IIM_BASE_ADDR + 0x800 + SOC_MAC_ADDR_FUSE_BANK * 0x400 +
269 SOC_MAC_ADDR_LOCK_FUSE * 4) &
270 SOC_MAC_ADDR_LOCK_BIT) == 0) {
271 tx51_mac_addr_program(addr);
273 #endif // SOC_MAC_ADDR_LOCK_FUSE
276 #endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
278 CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
279 "fec_esa_data", addr, CONFIG_ESA);
281 diag_printf("Ethernet FEC MAC address from fconfig: ");
282 diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
283 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
285 #ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
286 if (cyg_plf_redboot_esa_validate(addr)) {
287 tx51_mac_addr_program(addr);
291 diag_printf("** Error: Invalid MAC address: ");
292 diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
293 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
295 writel(addr[0], SOC_FEC_MAC_BASE + 0x14);
296 writel(addr[1], SOC_FEC_MAC_BASE + 0x10);
297 writel(addr[2], SOC_FEC_MAC_BASE + 0xC);
298 writel(addr[3], SOC_FEC_MAC_BASE + 0x8);
299 writel(addr[4], SOC_FEC_MAC_BASE + 0x4);
300 writel(addr[5], SOC_FEC_MAC_BASE + 0x0);
302 #ifdef SOC_MAC_ADDR_LOCK_FUSE
303 if ((readl(IIM_BASE_ADDR + 0x800 + SOC_MAC_ADDR_FUSE_BANK * 0x400 +
304 SOC_MAC_ADDR_LOCK_FUSE * 4) &
305 SOC_MAC_ADDR_LOCK_BIT) == 0) {
306 diag_printf("Use 'fconfig fec_esa_data' to set the MAC address\n");
309 diag_printf("Using MAC address from fconfig\n");
312 diag_printf("Using MAC address from fconfig\n");
313 #endif // SOC_MAC_ADDR_LOCK_FUSE
314 #endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
320 static mxc_fec_priv_t mxc_fec_private = {
321 .phy = ð0_phy, // PHY access routines
322 .provide_esa = _tx51_provide_fec_esa,
325 ETH_DRV_SC(mxc_fec_sc,
326 &mxc_fec_private, // Driver specific data
334 mxc_fec_deliver, // "pseudoDSR" called from fast net thread
335 mxc_fec_poll, // poll function, encapsulates ISR and DSR
338 NETDEVTAB_ENTRY(mxc_fec_netdev,
344 #if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
345 RedBoot_config_option("Set FEC network hardware address [MAC]",
347 ALWAYS_ENABLED, true,
350 RedBoot_config_option("FEC network hardware address [MAC]",
355 #endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
357 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
358 // Note that this section *is* active in an application, outside RedBoot,
359 // where the above section is not included.
361 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
362 #endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
364 #endif // __WANT_DEVS