1 #ifndef _CYGONCE_ETH_FEC_H_
2 #define _CYGONCE_ETH_FEC_H_
3 //==========================================================================
7 // Fast Ethernet MAC controller in i.MXx
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //####BSDCOPYRIGHTBEGIN####
45 //####BSDCOPYRIGHTEND####
46 //==========================================================================
47 //#####DESCRIPTIONBEGIN####
49 // Author(s): Fred Fan
55 //####DESCRIPTIONEND####
57 //==========================================================================
59 #include <cyg/infra/cyg_type.h>
61 #include <cyg/hal/hal_io.h>
63 #ifdef CYGPKG_DEVS_ETH_PHY
64 /* generic PHY device access functions */
65 void mxc_fec_phy_init(void);
66 void mxc_fec_phy_reset(void);
67 bool mxc_fec_phy_read(int reg, int unit, unsigned short *data);
68 void mxc_fec_phy_write(int reg, int unit, unsigned short data);
70 #include <cyg/io/eth_phy.h>
73 /* The defines of event bits */
74 #define FEC_EVENT_HBERR 0x80000000
75 #define FEC_EVENT_BABR 0x40000000
76 #define FEC_EVENT_BABT 0x20000000
77 #define FEC_EVENT_GRA 0x10000000
78 #define FEC_EVENT_TXF 0x08000000
79 #define FEC_EVENT_TXB 0x04000000
80 #define FEC_EVENT_RXF 0x02000000
81 #define FEC_EVENT_RXB 0x01000000
82 #define FEC_EVENT_MII 0x00800000
83 #define FEC_EVENT_EBERR 0x00400000
84 #define FEC_EVENT_LC 0x00200000
85 #define FEC_EVENT_RL 0x00100000
86 #define FEC_EVENT_UN 0x00080000
88 #define FEC_EVENT_TX FEC_EVENT_TXF
89 #define FEC_EVENT_TX_ERR (FEC_EVENT_BABT | FEC_EVENT_LC | FEC_EVENT_RL | FEC_EVENT_UN)
90 #define FEC_EVENT_RX FEC_EVENT_RXF
91 #define FEC_EVENT_ERR (FEC_EVENT_HBERR | FEC_EVENT_EBERR)
93 #define FEC_RX_FRAMES ((CYGNUM_IO_ETH_DRIVERS_NUM_PKT / 2) + 1)
94 #define FEC_FRAME_LEN (1540 + 4)
96 /* the defines to active transmit or receive frame */
97 #define FEC_RX_TX_ACTIVE 0x01000000
99 /* the defines of Ethernet Control register */
100 #define FEC_RESET 0x00000001
101 #define FEC_ETHER_EN 0x00000002
103 /* the defins of MII operation */
104 #define FEC_MII_ST 0x40000000
105 #define FEC_MII_OP_OFF 28
106 #define FEC_MII_OP_MASK 0x03
107 #define FEC_MII_OP_RD 0x02
108 #define FEC_MII_OP_WR 0x01
109 #define FEC_MII_PA_OFF 23
110 #define FEC_MII_PA_MASK 0xFF
111 #define FEC_MII_RA_OFF 18
112 #define FEC_MII_RA_MASK 0xFF
113 #define FEC_MII_TA 0x00020000
114 #define FEC_MII_DATA_OFF 0
115 #define FEC_MII_DATA_MASK 0x0000FFFF
117 #define FEC_MII_FRAME (FEC_MII_ST | FEC_MII_TA)
118 #define FEC_MII_OP(x) (((x) & FEC_MII_OP_MASK) << FEC_MII_OP_OFF)
119 #define FEC_MII_PA(pa) (((pa)& FEC_MII_PA_MASK) << FEC_MII_PA_OFF)
120 #define FEC_MII_RA(ra) (((ra)& FEC_MII_RA_MASK) << FEC_MII_RA_OFF)
121 #define FEC_MII_SET_DATA(v) (((v) & FEC_MII_DATA_MASK) << FEC_MII_DATA_OFF)
122 #define FEC_MII_GET_DATA(v) (((v) >> FEC_MII_DATA_OFF) & FEC_MII_DATA_MASK)
123 #define FEC_MII_READ(pa, ra) ((FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_RD)) | \
124 FEC_MII_PA(pa) | FEC_MII_RA(ra))
125 #define FEC_MII_WRITE(pa, ra, v) (FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_WR) | \
126 FEC_MII_PA(pa) | FEC_MII_RA(ra) | \
129 #define MII_SPEED_SHIFT 1
130 #define MII_SPEED_MASK 0x0000003F
131 #define MII_SPEED(x) ((((((x) + 499999) / 2500000) & MII_SPEED_MASK) >> 1) << MII_SPEED_SHIFT)
133 /* the defines of MIB control */
134 #define FEC_MIB_DISABLE 0x80000000
136 /* the defines of Receive Control*/
137 #define FEC_RCR_FCE 0x00000020
138 #define FEC_RCR_BC_REJ 0x00000010
139 #define FEC_RCR_PROM 0x00000008
140 #define FEC_RCR_MII_MODE 0x00000004
142 /* the defines of Transmit Control*/
143 #define FEC_TCR_RFC_PAUSE 0x00000010
144 #define FEC_TCR_FDEN 0x00000004
146 /* the defines of buffer description*/
147 #define FEC_BD_RX_NUM 256
148 #define FEC_BD_TX_NUM 2
150 #ifdef CYGOPT_HAL_ARM_MXC_FEC_MIIGSK
151 /* the defines for MIIGSK */
153 /* RMII frequency control: 0=50MHz, 1=5MHz */
154 #define MIIGSK_CFGR_FRCONT (1 << 6)
157 #define MIIGSK_CFGR_LBMODE (1 << 4)
160 #define MIIGSK_CFGR_EMODE (1 << 3)
162 /* MII gasket mode field */
163 #define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
165 /* MMI/7-Wire mode */
166 #define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
169 #define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
171 /* reflects MIIGSK Enable bit (RO) */
172 #define MIIGSK_ENR_READY (1 << 2)
174 /* enable MIGSK (set by default) */
175 #define MIIGSK_ENR_EN (1 << 1)
178 typedef volatile void mxc_fec_reg_t;
179 #define eir 0x004 /* Interrupt Event Register */
180 #define eimr 0x008 /* Interrupt Mask Register */
181 #define rdar 0x010 /* Receive Descriptor Active Register*/
182 #define tdar 0x014 /* Transmit Descriptor Active Register*/
183 #define ecr 0x024 /*Receive Descriptor Active Register*/
184 #define mmfr 0x040 /*MII Management Frame Register */
185 #define mscr 0x044 /*MII Speed Control Register */
186 #define mibc 0x064 /*MII Control/Status Register */
187 #define rcr 0x084 /*Receive Control Register */
188 #define tcr 0x0C4 /*Transmit Control register */
189 #define palr 0x0E4 /*Physical Address Low Register*/
190 #define paur 0x0E8 /*Physical Address High+Type Register*/
191 #define opd 0x0EC /*Opcode+Pause Duration */
192 #define iaur 0x118 /*Upper 32bits Individual Hash Table*/
193 #define ialr 0x11c /*lower 32bits Individual Hash Table*/
194 #define gaur 0x120 /*Upper 32bits Group Hash Table*/
195 #define galr 0x124 /*lower 32bits Group Hash Table*/
196 #define tfwr 0x144 /*Trasmit FIFO Watermark */
197 #define frbr 0x14c /*FIFO Receive Bound Register*/
198 #define frsr 0x150 /*FIFO Receive FIFO Start Registers*/
199 #define erdsr 0x180 /*Pointer to Receive Descriptor Ring*/
200 #define etdsr 0x184 /*Pointer to Transmit Descriptor Ring*/
201 #define emrbr 0x188 /*Maximum Receive Buffer size*/
202 #ifdef CYGOPT_HAL_ARM_MXC_FEC_MIIGSK
203 #define miigsk_cfgr 0x300 /* MIIGSK Configuration Register */
204 #define miigsk_enr 0x308 /* MIIGSK Enable Register */
207 #define BD_RX_ST_EMPTY 0x8000
208 #define BD_RX_ST_WRAP 0x2000
209 #define BD_RX_ST_LAST 0x0800
210 #define BD_RX_ST_ERRS 0x0037
212 #define BD_TX_ST_RDY 0x8000
213 #define BD_TX_ST_WRAP 0x2000
214 #define BD_TX_ST_LAST 0x0800
215 #define BD_TX_ST_TC 0x0400
216 #define BD_TX_ST_ABC 0x0200
218 typedef struct mxc_fec_bd_t
220 unsigned short int length; /*packet size*/
221 unsigned short int status; /*control & statue of this buffer description*/
222 unsigned char *data; /*frame buffer address*/
225 typedef struct mxc_fec_priv_s
227 mxc_fec_reg_t *hw_reg; /*the register base address of FEC*/
228 #ifdef CYGPKG_DEVS_ETH_PHY
229 eth_phy_access_t *phy;
231 unsigned char phy_addr; /*the address of PHY which associated with FEC controller*/
233 unsigned char tx_busy; /*0:free, 1:transmitting frame*/
234 unsigned char res[2];
235 unsigned long status; /*the status of FEC device:link-status etc.*/
236 unsigned long tx_key; /*save the key delivered from send function*/
237 mxc_fec_bd_t *rx_bd; /*the receive buffer description ring*/
238 mxc_fec_bd_t *rx_cur; /*the next recveive buffer description*/
239 mxc_fec_bd_t *tx_bd; /*the transmit buffer description rign*/
240 mxc_fec_bd_t *tx_cur; /*the next transmit buffer description*/
241 cyg_bool (*provide_esa)(unsigned char *);
244 #define MXC_FEC_PRIVATE(x) ((mxc_fec_priv_t *)(x)->driver_private)
246 /*The defines of the status field of mxc_fec_priv_t */
247 #define FEC_STATUS_LINK_ON 0x80000000
248 #define FEC_STATUS_FULL_DPLX 0x40000000
249 #define FEC_STATUS_AUTO_NEG 0x20000000
250 #define FEC_STATUS_100M 0x10000000
252 /*The defines about PHY */
254 #define PHY_PORT_ADDR 0x01
256 #define PHY_PORT_ADDR FEC_PHY_ADDR
259 #define PHY_CTRL_REG 0x00
260 #define PHY_CTRL_RESET 0x8000
261 #define PHY_CTRL_AUTO_NEG 0x1000
262 #define PHY_CTRL_FULL_DPLX 0x0100
264 #define PHY_STATUS_REG 0x01
265 #define PHY_STATUS_LINK_ST 0x0004
267 #define PHY_IDENTIFY_1 0x02
268 #define PHY_IDENTIFY_2 0x03
269 #define PHY_ID1_SHIFT 2
270 #define PHY_ID1_MASK 0xFFFF
271 #define PHY_ID2_SHIFT 8
272 #define PHY_ID2_MASK 0xFC00
273 #define PHY_MODE_NUM 0x03F0
274 #define PHY_REV_NUM 0x000F
276 #define PHY_DIAG_REG 0x12
277 #define PHY_DIAG_DPLX 0x0800
278 #define PHY_DIAG_RATE 0x0400
280 #define PHY_MODE_REG 0x15
281 #define PHY_LED_SEL 0x200
283 #define PHY_AUTO_NEG_REG 0x5
284 #define PHY_AUTO_10BASET 0x20
285 #define PHY_AUTO_10BASET_DPLX 0x40
286 #define PHY_AUTO_100BASET 0x80
287 #define PHY_AUTO_100BASET_DPLX 0x100
289 #define PHY_AUTO_NEG_EXP_REG 0x6
290 #define PHY_AUTO_NEG_NEW_PAGE 0x2
291 #define PHY_AUTO_NEG_CAP 0x1
293 #define PHY_INT_SRC_REG 29
294 #define PHY_INT_AUTO_NEG 0x40
295 #define FEC_COMMON_TICK 2
296 #define FEC_COMMON_TIMEOUT (1000 * 1000)
297 #define FEC_MII_TICK 2
298 #define FEC_MII_TIMEOUT (1000 * 1000)
299 #endif // _CYGONCE_ETH_FEC_H_