1 #ifndef CYGONCE_DEVS_ETH_INTEL_I82544_INFO_H
2 #define CYGONCE_DEVS_ETH_INTEL_I82544_INFO_H
3 /*==========================================================================
8 //==========================================================================
9 //####ECOSGPLCOPYRIGHTBEGIN####
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41 //==========================================================================
42 //#####DESCRIPTIONBEGIN####
49 //####DESCRIPTIONEND####
52 #include <pkgconf/devs_eth_intel_i82544.h>
54 #ifdef CYGDBG_DEVS_ETH_INTEL_I82544_KEEP_STATISTICS
55 # define KEEP_STATISTICS
56 # define nDISPLAY_STATISTICS
57 # define nDISPLAY_82544_STATISTICS
59 # define nKEEP_STATISTICS
60 # define nDISPLAY_STATISTICS
61 # define nDISPLAY_82544_STATISTICS
65 // ------------------------------------------------------------------------
67 // STATISTICAL COUNTER STRUCTURE
69 // ------------------------------------------------------------------------
70 #ifdef KEEP_STATISTICS
72 /* 0 */ cyg_uint32 tx_good;
73 /* 4 */ cyg_uint32 tx_max_collisions;
74 /* 8 */ cyg_uint32 tx_late_collisions;
75 /* 12 */ cyg_uint32 tx_underrun;
76 /* 16 */ cyg_uint32 tx_carrier_loss;
77 /* 20 */ cyg_uint32 tx_deferred;
78 /* 24 */ cyg_uint32 tx_single_collisions;
79 /* 28 */ cyg_uint32 tx_mult_collisions;
80 /* 32 */ cyg_uint32 tx_total_collisions;
81 /* 36 */ cyg_uint32 rx_good;
82 /* 40 */ cyg_uint32 rx_crc_errors;
83 /* 44 */ cyg_uint32 rx_align_errors;
84 /* 48 */ cyg_uint32 rx_resource_errors;
85 /* 52 */ cyg_uint32 rx_overrun_errors;
86 /* 56 */ cyg_uint32 rx_collisions; // Always 0
87 /* 60 */ cyg_uint32 rx_short_frames;
88 // In this setup; can also be flow-control counts after.
89 // If these are to be used, a config command (as in set promiscuous mode)
90 // must be issued at start, to let those stats escape. Params are in
91 // comments around the config command setup...
92 /* 64 */ cyg_uint32 done;
97 cyg_uint32 interrupts;
99 cyg_uint32 rx_deliver;
100 cyg_uint32 rx_resource;
101 cyg_uint32 rx_restart;
103 cyg_uint32 tx_complete;
104 cyg_uint32 tx_dropped;
108 extern STATISTICS statistics[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT];
109 #ifdef CYGDBG_DEVS_ETH_INTEL_I82544_KEEP_82544_STATISTICS
110 extern I82544_COUNTERS i82544_counters[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT];
113 #endif // KEEP_STATISTICS
115 // ------------------------------------------------------------------------
117 // DEVICES AND PACKET QUEUES
119 // ------------------------------------------------------------------------
120 // The system seems to work OK with as few as 8 of RX and TX descriptors.
121 // It limps very painfully with only 4.
122 // Performance is better with more than 8.
123 // But the size of non-cached (so useless for anything else)
124 // memory window is 1Mb, so we might as well use it all.
126 // 128 for these uses the whole 1Mb, near enough.
128 #ifndef MAX_RX_DESCRIPTORS
129 #define MAX_RX_DESCRIPTORS 128 // number of Rx descriptors
131 #ifndef MAX_TX_DESCRIPTORS
132 #define MAX_TX_DESCRIPTORS 128 // number of Tx descriptors
135 typedef struct i82544 {
136 cyg_uint8 // (split up for atomic byte access)
137 found:1, // was hardware discovered?
138 mac_addr_ok:1, // can we bring up?
139 active:1, // has this if been brung up?
140 hardwired_esa:1, // set if ESA is hardwired via CDL
141 link:1, // set if link is up
143 cyg_uint8 // Count nested sends to reject
144 within_send:8; // nested requests to send
146 tx_in_progress:1, // transmit in progress flag
147 tx_queue_full:1, // all Tx descriptors used flag
150 cyg_uint8 index; // 0 or 1 or whatever
151 cyg_uint32 devid; // PCI device id
152 cyg_uint32 device; // Device code from hardware
153 cyg_uint32 io_address; // memory mapped I/O address
154 cyg_uint8 mac_address[6]; // mac (hardware) address
155 void *ndp; // Network Device Pointer
157 cyg_int32 next_rx_descriptor; // descriptor index for callback
158 cyg_int32 rx_pointer; // descriptor index for ring head
159 CYG_ADDRESS rx_ring; // location of Rx descriptors
161 cyg_int32 tx_pointer; // next TXB to check for status.
162 CYG_ADDRESS tx_ring; // location of Tx descriptors
163 unsigned long tx_keys[MAX_TX_DESCRIPTORS]; // keys for tx q management
165 // Interrupt handling stuff
166 cyg_vector_t vector; // interrupt vector
167 cyg_handle_t interrupt_handle; // handle for int.handler
168 cyg_interrupt interrupt_object;
170 #ifdef KEEP_STATISTICS
171 void *p_statistics; // pointer to statistical counters
174 cyg_uint32 platform_timeout; // Some platforms use a timeout
175 int tx_descriptor_timeout; // Is it fixated on this tx?
180 // ------------------------------------------------------------------------
182 // 82544 GENERAL STATUS REGISTER
184 // ------------------------------------------------------------------------
185 #define GEN_STATUS_FDX 0x01 // 1 = full duplex, 0 = half
186 #define GEN_STATUS_BPS 0xC0 // 0 = 10M, 01 = 100M, 10&11 = 1000M
187 #define GEN_STATUS_BPS_SHIFT 6
188 #define GEN_STATUS_LINK 0x02 // 1 = link up, 0 = link down
190 extern int i82544_status( struct eth_drv_sc *sc );
192 // ------------------------------------------------------------------------
194 #ifdef KEEP_STATISTICS
195 void update_statistics(struct i82544* p_i82544);
199 #ifdef CYGDBG_DEVS_ETH_INTEL_I82544_KEEP_82544_STATISTICS
200 #define ETH_STATS_INIT( p ) \
201 update_statistics( (struct i82544 *)((p)->driver_private) )
203 #define ETH_STATS_INIT( p ) // otherwise do nothing
206 #define CYGDAT_DEVS_ETH_DESCRIPTION "Intel Gigabit Ethernet Controller (i82544)"
208 #define ETH_DEV_DOT3STATSETHERCHIPSET 1,3,6,1,2,1,10,7,8,2,5
210 #endif /* ifndef CYGONCE_DEVS_ETH_INTEL_I82544_INFO_H */
212 /* EOF i82544_info.h */