1 //==========================================================================
5 // Intel 82544 ethernet driver
7 //==========================================================================
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40 //####BSDCOPYRIGHTBEGIN####
42 // -------------------------------------------
44 // Portions of this software may have been derived from OpenBSD or
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50 //####BSDCOPYRIGHTEND####
51 //==========================================================================
52 //#####DESCRIPTIONBEGIN####
54 // Author(s): hmt, gthomas
55 // Contributors: Ron Spence, Pacific Softworks, jskov
58 // Description: hardware driver for 82544 Intel PRO/100+ ethernet
59 // Notes: CU commands such as dump and config should, according
60 // to the docs, set the CU active state while executing.
61 // That does not seem to be the case though, and the
62 // driver polls the completion bit in the packet status
65 // Platform code may provide this vector:
66 // CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT if it
67 // requires the interrupts to be handled via demuxers
68 // attached to a distinct interrupt.
70 // Platform code may alternatively define:
71 // CYGHWR_DEVS_ETH_INTEL_I82544_DEMUX_ALL if it is necessary
72 // to demux all interrupt sources - for example if they are
73 // wire-or'd together on some hardware but distinct on
74 // others. In this circumstance it is permitted for
75 // cyg_pci_translate_interrupt [HAL_PCI_TRANSLATE_INTERRUPT]
76 // to return invalid for 2nd and subsequent devices.
78 // Platform code can also define these three:
79 // CYGPRI_DEVS_ETH_INTEL_I82544_MASK_INTERRUPTS(p_i82544,old)
80 // CYGPRI_DEVS_ETH_INTEL_I82544_UNMASK_INTERRUPTS(p_i82544,old)
81 // CYGPRI_DEVS_ETH_INTEL_I82544_ACK_INTERRUPTS(p_i82544)
82 // which are particularly useful when nested interrupt
83 // management is needed (which is always IMHO).
85 // Platform code can define this:
86 // CYGHWR_DEVS_ETH_INTEL_I82544_MISSED_INTERRUPT(p_i82544)
87 // to detect a dropped interrupt and loop again or
88 // direct-call the DSR to reschedule the delivery routine.
89 // Only a problem on edge-triggered interrupt systems.
91 // Platform code can also provide this macro:
92 // CYGPRI_DEVS_ETH_INTEL_I82544_INTERRUPT_ACK_LOOP(p_i82544)
93 // to handle delaying for acks to register on the interrupt
94 // controller as necessary on the EBSA.
96 // Platform can define CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA()
97 // as an external means to get ESAs, possibly from RedBoot
98 // configuration info that's stored in flash memory.
100 // Platform def CYGHWR_DEVS_ETH_INTEL_I82544_HAS_NO_EEPROM
101 // removes all code for dealing with the EEPROM for those
102 // targets where there is none fitted. Either an external
103 // means to get ESAs should be used, or we must rely on
104 // hard-wiring the ESA's into each executable by means of the
105 // usual CDL configuration.
107 // Platform def CYGHWR_DEVS_ETH_INTEL_I82544_HAS_ONE_EEPROM
108 // is for hardware with multiple devices, but only one with a
109 // serial EEPROM installed. The 2nd device would get either
110 // the same ESA - because they are certain to be on different
111 // segment and internets - or the same ESA incremented by
112 // CYGHWR_DEVS_ETH_INTEL_I82544_HAS_ONE_EEPROM_MAC_ADJUST.
113 // CYGHWR_DEVS_ETH_INTEL_I82544_HAS_ONE_EEPROM should be the
114 // number (0 or 1) of the device that does have the EEPROM.
116 // CYGHWR_DEVS_ETH_INTEL_I82544_PCIMEM_DISCONTIGUOUS enables
117 // checking code for breaks in the physical address of PCI
118 // window memory. This can happen on some boards where a
119 // smaller SDRAM is fitted than the hardware allows, so some
120 // higher-order address bits are ignored. We make SDRAM
121 // contiguous in mapped memory, but what the i82544 sees
122 // might be discontiguous. The checking code skips any
123 // allocated chunk who appears to contain such a break, and
126 // CYGHWR_DEVS_ETH_INTEL_I82544_RESET_TIMEOUT( int32 )
127 // CYGHWR_DEVS_ETH_INTEL_I82544_TIMEOUT_FIRED( int32 ) if
128 // both defined give the driver a means to detect that we
129 // have been fixated on the same transmit operation for too
130 // long - we missed an interrupt or the device crashed. The
131 // int32 argument is used to hold a eg. the value of a
132 // fast-running hardware timer.
134 // Platform def CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD is
135 // used to select Auto Speed Detection for setting up the
138 // FIXME: replace -1/-2 return values with proper E-defines
139 // FIXME: For 82557/8 compatibility i82544_configure() function
140 // probably needs some tweaking - config bits differ
141 // slightly but crucially.
142 // FIXME: EEPROM code not tested on a BE system.
144 //####DESCRIPTIONEND####
146 //==========================================================================
148 #include <pkgconf/system.h>
149 #ifdef CYGPKG_IO_ETH_DRIVERS
150 #include <pkgconf/io_eth_drivers.h>
152 #include <pkgconf/devs_eth_intel_i82544.h>
154 #include <cyg/infra/cyg_type.h>
155 #include <cyg/infra/cyg_ass.h>
156 #include <cyg/hal/hal_arch.h>
157 #include <cyg/hal/hal_intr.h>
158 #include <cyg/infra/diag.h>
159 #include <cyg/hal/hal_if.h>
160 #include <cyg/hal/drv_api.h>
161 #include <cyg/io/eth/netdev.h>
162 #include <cyg/io/eth/eth_drv.h>
165 #include <pkgconf/net.h>
166 #include <net/if.h> /* Needed for struct ifnet */
170 #include <cyg/io/pci.h>
171 // So we can check the validity of the PCI window against the MLTs opinion,
172 // and thereby what the malloc heap consumes willy-nilly:
173 #include CYGHWR_MEMORY_LAYOUT_H
175 #error "Need PCI package here"
178 #include <cyg/devs/eth/i82544_info.h>
180 #include CYGDAT_DEVS_ETH_INTEL_I82544_INL
182 // ------------------------------------------------------------------------
184 #ifdef CYGDBG_DEVS_ETH_INTEL_I82544_CHATTER
185 #define DEBUG_82544 // This one prints stuff as packets come and go
186 #define DEBUG // Startup printing mainly
187 #define noDEBUG_EE // Some EEPROM specific retries &c
190 #ifdef CYGDBG_USE_ASSERTS
195 int waitcmd_timeouts;
196 int waitcmd_timeouts_cu;
199 } missed_interrupt = { 0,0,0, 0,0, 0, 0 };
202 #ifndef CYGPKG_REDBOOT
204 #define os_printf diag_printf
205 #define db_printf diag_printf
209 static void os_printf( char *fmt, ... )
211 extern int start_console(void);
212 extern void end_console(int);
216 old_console = start_console();
217 diag_vprintf( fmt, a );
218 end_console(old_console);
222 #define db_printf os_printf
226 // ------------------------------------------------------------------------
230 // ------------------------------------------------------------------------
231 // Macros for writing shared memory structures - no need for byte flipping
233 #define READMEM8( _reg_, _val_ ) ((CYG_BYTE)(_val_) = *((volatile CYG_BYTE *)(_reg_)))
234 #define WRITEMEM8( _reg_, _val_ ) (*((volatile CYG_BYTE *)(_reg_)) = (CYG_BYTE)(_val_))
235 #define READMEM16( _reg_, _val_ ) ((CYG_WORD16)(_val_) = *((volatile CYG_WORD16 *)(_reg_)))
236 #define WRITEMEM16( _reg_, _val_ ) (*((volatile CYG_WORD16 *)(_reg_)) = (CYG_WORD16)(_val_))
237 #define READMEM32( _reg_, _val_ ) ((CYG_WORD32)(_val_) = *((volatile CYG_WORD32 *)(_reg_)))
238 #define WRITEMEM32( _reg_, _val_ ) (*((volatile CYG_WORD32 *)(_reg_)) = (CYG_WORD32)(_val_))
239 #define READMEM64( _reg_, _val_ ) ((CYG_WORD64)(_val_) = *((volatile CYG_WORD64 *)(_reg_)))
240 #define WRITEMEM64( _reg_, _val_ ) (*((volatile CYG_WORD64 *)(_reg_)) = (CYG_WORD64)(_val_))
242 #define OUTL( _v_, _a_ ) WRITEMEM32( _a_, _v_ )
244 static inline cyg_uint32 INL(cyg_uint32 io_address)
245 { cyg_uint32 _t_; READMEM32( io_address, _t_ ); return _t_; }
248 // ------------------------------------------------------------------------
249 // Map from CPU-view addresses to PCI-bus master's view - however that is:
251 #ifdef CYGHWR_INTEL_I82544_PCI_VIRT_TO_BUS
253 #define VIRT_TO_BUS( _x_ ) CYGHWR_INTEL_I82544_PCI_VIRT_TO_BUS( _x_ )
254 #define BUS_TO_VIRT( _x_ ) CYGHWR_INTEL_I82544_PCI_BUS_TO_VIRT( _x_ )
256 #else // use default mappings: get a physical address to give to the device
258 #define VIRT_TO_BUS( _x_ ) virt_to_bus((cyg_uint32)(_x_))
259 static inline cyg_uint32 virt_to_bus(cyg_uint32 p_memory)
260 { return CYGARC_PHYSICAL_ADDRESS(p_memory); }
262 #define BUS_TO_VIRT( _x_ ) bus_to_virt((cyg_uint32)(_x_))
263 static inline cyg_uint32 bus_to_virt(cyg_uint32 p_bus)
264 { return CYGARC_UNCACHED_ADDRESS(p_bus); }
266 #endif // not defined CYGHWR_INTEL_I82544_PCI_VIRT_TO_BUS
268 // ------------------------------------------------------------------------
270 // 82544 REGISTER OFFSETS
272 // ------------------------------------------------------------------------
275 #define I82544_CTRL 0x00000
276 #define I82544_STATUS 0x00008
277 #define I82544_EECD 0x00010
278 #define I82544_CTRL_EXT 0x00018
279 #define I82544_MDIC 0x00020
280 #define I82544_FCAL 0x00028
281 #define I82544_FCAH 0x0002c
282 #define I82544_FCT 0x00030
283 #define I82544_VET 0x00038
284 #define I82544_FCTTV 0x00170
285 #define I82544_TXCW 0x00178
286 #define I82544_RXCW 0x00180
287 #define I82544_PBA 0x01000
289 // Interrupt control registers
290 #define I82544_ICR 0x000c0
291 #define I82544_ICS 0x000c8
292 #define I82544_IMS 0x000d0
293 #define I82544_IMC 0x000d8
296 #define I82544_RCTL 0x00100
297 #define I82544_FCRTL 0x02160
298 #define I82544_FCRTH 0x02168
299 #define I82544_RDBAL 0x02800
300 #define I82544_RDBAH 0x02804
301 #define I82544_RDLEN 0x02808
302 #define I82544_RDH 0x02810
303 #define I82544_RDT 0x02818
304 #define I82544_RDTR 0x02820
305 #define I82544_RXDCTL 0x02828
306 #define I82544_RXCSUM 0x05000
307 #define I82544_MTA 0x05200
308 #define I82544_RAT 0x05400
309 #define I82544_VFTA 0x05600
311 #define I82544_RCTL_EN (1<<1)
312 #define I82544_RCTL_BAM (1<<15)
314 // Transmit registers
315 #define I82544_TCTL 0x00400
316 #define I82544_TIPG 0x00410
317 #define I82544_TBT 0x00448
318 #define I82544_AIT 0x00458
319 #define I82544_TXDMAC 0x03000
320 #define I82544_TDBAL 0x03800
321 #define I82544_TDBAH 0x03804
322 #define I82544_TDLEN 0x03808
323 #define I82544_TDH 0x03810
324 #define I82544_TDT 0x03818
325 #define I82544_TIDV 0x03820
326 #define I82544_TXDCTL 0x03828
327 #define I82544_TSPMT 0x03830
330 #define I82544_TCTL_EN (1<<1)
331 #define I82544_TCTL_PSP (1<<3)
334 // ------------------------------------------------------------------------
336 // 82544 DEVICE CONTROL WORD DEFNITIONS
338 // ------------------------------------------------------------------------
340 #define I82544_CTRL_FD (1<<0)
341 #define I82544_CTRL_BEM (1<<1)
342 #define I82544_CTRL_LRST (1<<3)
343 #define I82544_CTRL_ASDE (1<<5)
344 #define I82544_CTRL_SLU (1<<6)
345 #define I82544_CTRL_ILOS (1<<7)
346 #define I82544_CTRL_SPEED (3<<8)
347 #define I82544_CTRL_FRCSPD (1<<11)
348 #define I82544_CTRL_FRCDPLX (1<<12)
349 #define I82544_CTRL_SWDPINSLO (15<<18)
350 #define I82544_CTRL_SWDPINSIO (15<<22)
351 #define I82544_CTRL_RST (1<<26)
352 #define I82544_CTRL_RFCE (1<<27)
353 #define I82544_CTRL_TFCE (1<<28)
354 #define I82544_CTRL_VME (1<<30)
355 #define I82544_CTRL_PHY_RST (1<<31)
357 #define I82544_CTRL_PHY_RESET (1<<18)
358 #define I82544_CTRL_PHY_RESET_DIR (1<<22)
359 #define I82544_CTRL_MDIO (1<<20)
360 #define I82544_CTRL_MDIO_DIR (1<<24)
361 #define I82544_CTRL_MDC (1<<21)
362 #define I82544_CTRL_MDC_DIR (1<<25)
364 #define I82544_CTRL_EXT_PHY_RESET4 (1<<4)
365 #define I82544_CTRL_EXT_PHY_RESET_DIR4 (1<<8)
367 #define PHY_ADDRESS 1
369 // ------------------------------------------------------------------------
371 // 82544 DEVICE STATUS WORD DEFNITIONS
373 // ------------------------------------------------------------------------
375 #define I82544_STATUS_FD 0x0001
376 #define I82544_STATUS_LU 0x0002
377 #define I82544_STATUS_TXOFF 0x0010
378 #define I82544_STATUS_TBIMODE 0x0020
379 #define I82544_STATUS_SPEED 0x00C0
380 #define I82544_STATUS_ASDV 0x0300
381 #define I82544_STATUS_PCI_SPD 0x0800
382 #define I82544_STATUS_BUS64 0x1000
383 #define I82544_STATUS_PCIX_MODE 0x2000
384 #define I82544_STATUS_PCIXSPD 0xC000
386 // ------------------------------------------------------------------------
388 // 82544 EEPROM INTERFACE
390 // ------------------------------------------------------------------------
393 #define EE_SHIFT_CLK 0x01 // EEPROM shift clock.
394 #define EE_CS 0x02 // EEPROM chip select.
395 #define EE_DATA_WRITE 0x04 // EEPROM chip data in.
396 #define EE_DATA_READ 0x08 // EEPROM chip data out.
397 #define EE_REQ 0x40 // EEPROM request (82546 only)
398 #define EE_GNT 0x80 // EEPROM grant (82546 only)
399 #define EE_PRES 0x100 // EEPROM present (82546 only)
400 #define EE_SIZE 0x200 // EEPROM size (82546 only)
401 #define EE_ENB (0x10|EE_CS)
404 // ------------------------------------------------------------------------
406 // RECEIVE DESCRIPTORS
408 // ------------------------------------------------------------------------
410 #define I82544_RD_BUFFER 0
411 #define I82544_RD_LENGTH 8
412 #define I82544_RD_CSUM 10
413 #define I82544_RD_STATUS 12
414 #define I82544_RD_ERRORS 13
415 #define I82544_RD_SPECIAL 14
416 #define I82544_RD_SIZE 16
418 #define I82544_RD_STATUS_DD (1<<0)
419 #define I82544_RD_STATUS_EOP (1<<1)
420 #define I82544_RD_STATUS_IXSM (1<<2)
421 #define I82544_RD_STATUS_VP (1<<3)
422 #define I82544_RD_STATUS_TCPCS (1<<5)
423 #define I82544_RD_STATUS_IPCS (1<<6)
424 #define I82544_RD_STATUS_PIF (1<<7)
426 // ------------------------------------------------------------------------
428 // TRANSMIT DESCRIPTORS
430 // ------------------------------------------------------------------------
432 // Currently we only use the legacy Tx descriptor
434 #define I82544_TD_BUFFER 0
435 #define I82544_TD_LENGTH 8
436 #define I82544_TD_CSO 10
437 #define I82544_TD_CMD 11
438 #define I82544_TD_STATUS 12
439 #define I82544_TD_CSS 13
440 #define I82544_TD_SPECIAL 14
441 #define I82544_TD_SIZE 16
443 #define I82544_TD_CMD_EOP (1<<0)
444 #define I82544_TD_CMD_IFCS (1<<1)
445 #define I82544_TD_CMD_IC (1<<2)
446 #define I82544_TD_CMD_RS (1<<3)
447 #define I82544_TD_CMD_RPS (1<<4)
448 #define I82544_TD_CMD_DEXT (1<<5)
449 #define I82544_TD_CMD_VLE (1<<6)
450 #define I82544_TD_CMD_IDE (1<<7)
452 #define I82544_TD_STATUS_DD (1<<0)
453 #define I82544_TD_STATUS_EC (1<<1)
454 #define I82544_TD_STATUS_LC (1<<2)
455 #define I82544_TD_STATUS_TU (1<<3)
457 // ------------------------------------------------------------------------
459 // DEVICES AND PACKET QUEUES
461 // ------------------------------------------------------------------------
463 #define MAX_RX_PACKET_SIZE 1536 // maximum Rx packet size
464 #define MAX_TX_PACKET_SIZE 1536 // maximum Tx packet size
467 // ------------------------------------------------------------------------
468 // Use arrays provided by platform header to verify pointers.
470 #ifdef CYGDBG_USE_ASSERTS
471 #define CHECK_NDP_SC_LINK() \
473 int i, valid_netdev = 0, valid_sc = 0; \
474 for(i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT; i++) { \
475 if (i82544_netdev_array[i] == ndp) valid_netdev = 1; \
476 if (i82544_sc_array[i] == sc) valid_sc = 1; \
477 if (valid_sc || valid_netdev) break; \
479 CYG_ASSERT( valid_netdev, "Bad ndp" ); \
480 CYG_ASSERT( valid_sc, "Bad sc" ); \
481 CYG_ASSERT( (void *)p_i82544 == i82544_sc_array[i]->driver_private, \
482 "sc pointer bad" ); \
485 #define CHECK_NDP_SC_LINK()
488 #define IF_BAD_82544( _p_ ) \
490 int i, valid_p = 0; \
491 for(i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT; i++) { \
492 if (i82544_priv_array[i] == (_p_)) { \
497 CYG_ASSERT(valid_p, "Bad pointer-to-i82544"); \
501 // ------------------------------------------------------------------------
503 // Managing the memory that is windowed onto the PCI bus
505 // ------------------------------------------------------------------------
507 static cyg_uint32 i82544_heap_size;
508 static cyg_uint8 *i82544_heap_base;
509 static cyg_uint8 *i82544_heap_free;
511 static void *mem_reserved_ioctl = (void*)0;
512 // uncacheable memory reserved for ioctl calls
514 // ------------------------------------------------------------------------
516 // FUNCTION PROTOTYPES
518 // ------------------------------------------------------------------------
520 static int pci_init_find_82544s(void);
522 static void i82544_reset(struct i82544* p_i82544);
523 static void i82544_setup(struct i82544* p_i82544);
524 static int eth_set_mac_address(struct i82544* p_i82544, cyg_uint8 *addr, int eeprom );
526 static void InitRxRing(struct i82544* p_i82544);
527 static void InitTxRing(struct i82544* p_i82544);
530 eth_isr(cyg_vector_t vector, cyg_addrword_t data);
532 static int i82544_configure(struct i82544* p_i82544, int promisc, int oversized);
534 // debugging/logging only:
535 //void dump_txcb(TxCB* p_txcb);
536 void DisplayStatistics(void);
537 void update_statistics(struct i82544* p_i82544);
538 //void dump_rfd(RFD* p_rfd, int anyway );
539 void dump_all_rfds( int intf );
540 void dump_packet(cyg_uint8 *p_buffer, int length);
542 static void i82544_stop( struct eth_drv_sc *sc );
544 // ------------------------------------------------------------------------
549 CYGACC_CALL_IF_DELAY_US(delay);
552 // ------------------------------------------------------------------------
553 // If we are demuxing for all interrupt sources, we must mask and unmask
554 // *all* interrupt sources together.
557 Mask82544Interrupt(struct i82544* p_i82544)
559 cyg_drv_interrupt_mask(p_i82544->vector);
565 UnMask82544Interrupt(struct i82544* p_i82544, int old)
568 cyg_drv_interrupt_unmask(p_i82544->vector);
573 Acknowledge82544Interrupt(struct i82544* p_i82544)
575 cyg_drv_interrupt_acknowledge(p_i82544->vector);
578 // ------------------------------------------------------------------------
581 // Simply carve off from the front of the PCI mapped window into real memory
584 pciwindow_mem_alloc(int size)
586 CYG_ADDRESS p_memory;
590 // db_printf("pciwindow_mem_alloc %d\n",size);
594 (CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE <= (int)i82544_heap_free)
596 ((CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE +
597 CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE) > (int)i82544_heap_free)
599 (0 < i82544_heap_size)
601 (CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE >= i82544_heap_size)
603 (CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE == (int)i82544_heap_base),
604 "Heap variables corrupted" );
607 size = (size + 3) & ~3;
608 if ( (i82544_heap_free+size) < (i82544_heap_base+i82544_heap_size) ) {
610 p_memory = (CYG_ADDRESS)i82544_heap_free;
611 i82544_heap_free += size;
612 for ( p = (cyg_uint32 *)p_memory; _size > 0; _size -= 4 )
618 VIRT_TO_BUS( p_memory ) + size == VIRT_TO_BUS( i82544_heap_free ),
619 "Discontiguous PCI memory in real addresses" );
625 // ------------------------------------------------------------------------
629 // Device-specific bit-twiddling and line driving side-effects
631 // CYGACC_CALL_IF_DELAY_US() drags in huge amounts of scheduler locking and
632 // the like 'cos it's a VV call! We only want a delay of 1uS tops, so:
634 #define MII_DELAY() do { int z; for ( z = 0; z < 100; z++ ) ; } while (0)
637 # define MII_PRINTF diag_printf
638 # define MII_STUFF "%4s | %4s | %4s | %4s [%08x]\n", \
639 (*_ctrl & (1<<20)) ? "MDIO" : "---", \
640 (*_ctrl & (1<<24)) ? "Wr" : "Rd", \
641 (*_ctrl & (1<<21)) ? "CLK" : "clk", \
644 # define MII_PRINTF( foo )
648 static inline cyg_uint32 mii_init( int ioaddr )
651 cyg_uint32 *_ctrl = &ctrl;
652 *_ctrl = INL( ioaddr + I82544_CTRL );
653 *_ctrl &=~ I82544_CTRL_MDC;
654 *_ctrl |= I82544_CTRL_MDC_DIR;
655 *_ctrl &= ~I82544_CTRL_MDIO_DIR;
656 *_ctrl &= ~I82544_CTRL_MDIO;
657 OUTL( *_ctrl, ioaddr + I82544_CTRL );
658 MII_PRINTF( "mii_init : " MII_STUFF );
663 static inline void mii_clock_up( int ioaddr, cyg_uint32 *_ctrl )
665 *_ctrl |= I82544_CTRL_MDC;
666 OUTL( *_ctrl, ioaddr + I82544_CTRL );
667 MII_PRINTF( "mii_clock_up : " MII_STUFF );
671 static inline void mii_clock_down( int ioaddr, cyg_uint32 *_ctrl )
673 *_ctrl &=~ I82544_CTRL_MDC;
674 OUTL( *_ctrl, ioaddr + I82544_CTRL );
675 MII_PRINTF( "mii_clock_down: " MII_STUFF );
679 static inline void mii_read_mode( int ioaddr, cyg_uint32 *_ctrl )
681 *_ctrl &= ~I82544_CTRL_MDIO_DIR;
682 *_ctrl &= ~I82544_CTRL_MDIO;
683 OUTL( *_ctrl, ioaddr + I82544_CTRL );
684 MII_PRINTF( "mii_read_mode : " MII_STUFF );
688 static inline int mii_read_data_bit( int ioaddr, cyg_uint32 *_ctrl )
690 *_ctrl = INL( ioaddr + I82544_CTRL );
691 MII_PRINTF( "mii_read_data : " MII_STUFF );
692 return I82544_CTRL_MDIO == (I82544_CTRL_MDIO & *_ctrl);
695 static inline void mii_write_data_bit( int ioaddr, int databit, cyg_uint32 *_ctrl )
698 *_ctrl |= I82544_CTRL_MDIO;
700 *_ctrl &= ~I82544_CTRL_MDIO;
701 *_ctrl |= I82544_CTRL_MDIO_DIR; // drive the mdio line
702 OUTL( *_ctrl, ioaddr + I82544_CTRL );
703 MII_PRINTF( "mii_write_data: " MII_STUFF );
707 // Pass ioaddr around "invisibly"
708 #define MII_INIT() cyg_uint32 _ctrl_val = mii_init(ioaddr); \
709 cyg_uint32 *_ctrl = &_ctrl_val;
711 #define MII_CLOCK_UP() mii_clock_up(ioaddr, _ctrl)
712 #define MII_CLOCK_DOWN() mii_clock_down(ioaddr, _ctrl)
713 #define MII_READ_MODE() mii_read_mode(ioaddr, _ctrl)
714 #define MII_READ_DATA_BIT() mii_read_data_bit(ioaddr, _ctrl)
715 #define MII_WRITE_DATA_BIT( _d_ ) mii_write_data_bit(ioaddr,(_d_),_ctrl)
717 // ------------------------------------------------------------------------
721 // Management data over the MII interface - nasty hand driven serial stuff
724 static void mii_write_bits( int ioaddr, int val, int bitcount, cyg_uint32 *_ctrl )
727 // These are deliberately signed ints so that we can send an overlong
728 // preamble if we want by saying "send -1 of width 40 bits" and relying
729 // on sign extension.
730 for ( i = bitcount - 1; i >= 0; i-- ) {
731 MII_WRITE_DATA_BIT( (val >> i) & 1 );
738 static int mii_read_bits( int ioaddr, int bitcount, cyg_uint32 *_ctrl )
742 for ( i = bitcount - 1; i >= 0; i-- ) {
745 val |= MII_READ_DATA_BIT();
751 #define MII_WRITE_BITS( val, bitcount ) mii_write_bits( ioaddr, val, bitcount, _ctrl )
752 #define MII_READ_BITS( bitcount ) mii_read_bits( ioaddr, bitcount, _ctrl )
754 // Now define subsections of the protocol in terms of the above
756 #define MII_WRITE_PREAMBLE() MII_WRITE_BITS( -1, 32 ) // >32 x 1s
757 #define MII_WRITE_START() MII_WRITE_BITS( 1, 2 ) // 01
758 #define MII_WRITE_WRITE_CMD() MII_WRITE_BITS( 1, 2 ) // 01
759 #define MII_WRITE_READ_CMD() MII_WRITE_BITS( 2, 2 ) // 10
761 #define MII_WRITE_PHY_ADDR(_p_) MII_WRITE_BITS( _p_, 5 )
762 #define MII_WRITE_REGNUM( _r_ ) MII_WRITE_BITS( (_r_), 5 )
764 #define MII_WRITE_TURNAROUND() MII_WRITE_BITS( 2, 2 )
766 #define MII_READ_TURNAROUND() CYG_MACRO_START \
767 MII_READ_MODE(); /* to turn off driving the line */ \
768 (void)(MII_READ_BITS( 2 )); /* discard TA "bits" */ \
771 #define MII_IDLE() CYG_MACRO_START \
772 MII_READ_MODE(); /* to turn off driving the line */ \
773 ((void)MII_READ_BITS( 5 )); /* extra clocks in Hi-Z mode */ \
777 #define MII_READ_REGVAL() MII_READ_BITS( 16 )
778 #define MII_WRITE_REGVAL( _v_ ) MII_WRITE_BITS( (_v_), 16 )
780 static int mii_read_register( struct i82544 *p_i82544, int phy, int regnum )
783 cyg_uint32 ioaddr = p_i82544->io_address;
785 if( p_i82544->device == 0x1004 )
787 // An 82543, read MII register via software defined pins in
791 MII_WRITE_PREAMBLE();
793 MII_WRITE_READ_CMD();
794 MII_WRITE_PHY_ADDR(phy);
795 MII_WRITE_REGNUM( regnum );
796 MII_READ_TURNAROUND();
797 value = MII_READ_REGVAL();
802 // Others, read MII register via MDIC register.
804 cyg_uint32 mdic = (2<<26) | (phy<<21) | (regnum<<16);
806 OUTL( mdic, ioaddr + I82544_MDIC );
811 mdic = INL( ioaddr + I82544_MDIC );
812 } while( (mdic & (1<<28)) == 0 );
814 value = mdic & 0xFFFF;
819 #ifndef CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
820 static void mii_write_register( struct i82544 *p_i82544, int phy, int regnum, int value )
822 cyg_uint32 ioaddr = p_i82544->io_address;
824 if( p_i82544->device == 0x1004 )
826 // An 82543, write MII register via software defined pins in
830 MII_WRITE_PREAMBLE();
832 MII_WRITE_WRITE_CMD();
833 MII_WRITE_PHY_ADDR(phy);
834 MII_WRITE_REGNUM( regnum );
835 MII_WRITE_TURNAROUND();
836 MII_WRITE_REGVAL( value );
841 // Others, write MII register via MDIC register.
843 cyg_uint32 mdic = (1<<26) | (phy<<21) | (regnum<<16) | (value&0xFFFF);
845 OUTL( mdic, ioaddr + I82544_MDIC );
850 mdic = INL( ioaddr + I82544_MDIC );
851 } while( (mdic & (1<<28)) == 0 );
857 // dump out the PHY registers
858 static void show_phy( struct i82544 *p_i82544, int phy )
862 os_printf("PHY %d regs:",phy);
863 for( i = 0; i < 32; i++ )
867 mdic = mii_read_register( p_i82544, phy, i );
869 if( (i%8)==0 ) os_printf("\n");
871 os_printf("%04x ",mdic);
877 // ------------------------------------------------------------------------
881 // ------------------------------------------------------------------------
883 // ------------------------------------------------------------------------
885 // Serial EEPROM access - much like the other Intel ethernet
888 // CYGACC_CALL_IF_DELAY_US() drags in huge amounts of scheduler locking and
889 // the like 'cos it's a VV call! Waste of time, mostly.
891 #define EE_DELAY() do { int z; for ( z = 0; z < 10000; z++ ) ; } while (0)
894 # define EE_PRINTF diag_printf
895 # define EE_STUFF "%4s | %4s | %4s | %4s [%08x]\n", \
896 (l & EE_SHIFT_CLK) ? "CLK" : "clk", \
897 (l & EE_CS) ? "eeCS" : "--", \
898 (l & EE_DATA_WRITE) ? "eeDW" : "---", \
899 (l & EE_DATA_READ) ? "eeDR" : "---", \
902 # define EE_PRINTF( foo )
907 static inline void ee_select( int ioaddr, struct i82544 *p_i82544 )
910 l = INL( ioaddr + I82544_EECD );
911 if (p_i82544->device == 0x1010 ||
912 p_i82544->device == 0x100e) {
913 // i82546 requires REQ/GNT before EEPROM access
915 OUTL( l, ioaddr + I82544_EECD );
917 while ((l & EE_GNT) == 0)
918 l = INL( ioaddr + I82544_EECD );
922 OUTL( l, ioaddr + I82544_EECD );
925 OUTL( l, ioaddr + I82544_EECD );
926 l = INL( ioaddr + I82544_EECD );
927 EE_PRINTF( "ee_select : " EE_STUFF );
931 static inline void ee_deselect( int ioaddr )
934 l = INL( ioaddr + I82544_EECD ) & ~0x3f;
936 OUTL( l, ioaddr + I82544_EECD );
937 EE_PRINTF( "ee_deselect 1 : " EE_STUFF );
942 OUTL( l, ioaddr + I82544_EECD );
943 l = INL( ioaddr + I82544_EECD );
944 EE_PRINTF( "ee_deselect 2 : " EE_STUFF );
950 OUTL( l, ioaddr + I82544_EECD );
955 static inline void ee_clock_up( int ioaddr )
958 l = INL( ioaddr + I82544_EECD );
960 OUTL( l, ioaddr + I82544_EECD );
962 l = INL( ioaddr + I82544_EECD );
963 EE_PRINTF( "ee_clock_up : " EE_STUFF );
967 static inline void ee_clock_down( int ioaddr )
970 l = INL( ioaddr + I82544_EECD );
972 OUTL( l, ioaddr + I82544_EECD );
974 l = INL( ioaddr + I82544_EECD );
975 EE_PRINTF( "ee_clock_down : " EE_STUFF );
979 static inline int ee_read_data_bit( int ioaddr )
982 l = INL( ioaddr + I82544_EECD );
983 EE_PRINTF( "ee_read_data : " EE_STUFF );
984 return EE_DATA_READ == (EE_DATA_READ & l);
987 static inline void ee_write_data_bit( int ioaddr, int databit )
990 l = INL( ioaddr + I82544_EECD );
995 OUTL( l, ioaddr + I82544_EECD );
996 l = INL( ioaddr + I82544_EECD );
997 EE_PRINTF( "ee_write_data : " EE_STUFF );
1001 // Pass ioaddr around "invisibly"
1002 #define EE_SELECT() ee_select(ioaddr, p_i82544)
1003 #define EE_DESELECT() ee_deselect(ioaddr)
1004 #define EE_CLOCK_UP() ee_clock_up(ioaddr)
1005 #define EE_CLOCK_DOWN() ee_clock_down(ioaddr)
1006 #define EE_READ_DATA_BIT() ee_read_data_bit(ioaddr)
1007 #define EE_WRITE_DATA_BIT( _d_ ) ee_write_data_bit(ioaddr,(_d_))
1009 // ------------------------------------------------------------------------
1012 get_eeprom_size( struct i82544 *p_i82544 )
1014 cyg_uint32 l, ioaddr = p_i82544->io_address;
1015 int i, tmp, addrbits;
1017 l = INL( ioaddr + I82544_EECD );
1020 diag_printf( "get_eeprom_size\n" );
1023 if (p_i82544->device == 0x1010 ||
1024 p_i82544->device == 0x100e) {
1027 OUTL( l, ioaddr + I82544_EECD );
1029 while ((l & EE_GNT) == 0)
1030 l = INL( ioaddr + I82544_EECD );
1033 OUTL( l, ioaddr + I82544_EECD );
1036 OUTL( l, ioaddr + I82544_EECD );
1037 l = INL( ioaddr + I82544_EECD );
1040 for (i = 3; i >= 0; i--) { // Doc says to shift out a zero then:
1041 tmp = (6 & (1 << i)) ? 1 : 0; // "6" is the "read" command.
1042 EE_WRITE_DATA_BIT(tmp);
1046 // Now clock out address zero, looking for the dummy 0 data bit
1047 for ( i = 1; i <= 10; i++ ) {
1048 EE_WRITE_DATA_BIT(0);
1051 if (EE_READ_DATA_BIT() == 0)
1052 break; // The dummy zero est arrive'
1055 if (6 != i && 8 != i)
1056 diag_printf("no EEPROM found\n");
1061 for (i = 15; i >= 0; i--) {
1063 if (EE_READ_DATA_BIT())
1068 l = INL( ioaddr + I82544_EECD ) & ~0x3f;
1070 OUTL( l, ioaddr + I82544_EECD );
1075 OUTL( l, ioaddr + I82544_EECD );
1076 l = INL( ioaddr + I82544_EECD );
1082 OUTL( l, ioaddr + I82544_EECD );
1092 read_eeprom_word( struct i82544 *p_i82544, int addrbits, int address )
1095 cyg_uint32 ioaddr = p_i82544->io_address;
1097 // Should already be not-selected, but anyway:
1100 // Shift the read command bits out.
1101 for (i = 3; i >= 0; i--) { // Doc says to shift out a zero then:
1102 tmp = (6 & (1 << i)) ? 1 : 0; // "6" is the "read" command.
1103 EE_WRITE_DATA_BIT(tmp);
1108 // Now clock out address
1109 for ( i = addrbits - 1; i >= 0 ; i-- ) {
1110 tmp = (address & (1<<i)) ? 1 : 0;
1111 EE_WRITE_DATA_BIT(tmp);
1113 tmp = EE_READ_DATA_BIT();
1116 // CYG_ASSERT( (0 == tmp) == (0 == i), "Looking for zero handshake bit" );
1121 for (i = 15; i >= 0; i--) {
1123 if ( EE_READ_DATA_BIT() )
1128 // Terminate the EEPROM access.
1132 // diag_printf( "eeprom address %4x: data %4x\n", address, tmp );
1138 // ------------------------------------------------------------------------
1140 // ------------------------------------------------------------------------
1142 // NETWORK INTERFACE INITIALIZATION
1144 // Function : Init82544
1147 // This routine resets, configures, and initializes the chip.
1148 // It also clears the ethernet statistics structure, and selects
1149 // which statistics are supported by this driver.
1151 // ------------------------------------------------------------------------
1154 i82544_init(struct cyg_netdevtab_entry * ndp)
1156 static int initialized = 0; // only probe PCI et al *once*
1158 struct eth_drv_sc *sc;
1161 struct i82544 *p_i82544;
1162 cyg_uint8 mac_address[ETHER_ADDR_LEN];
1165 db_printf("i82544_init\n");
1168 sc = (struct eth_drv_sc *)(ndp->device_instance);
1169 p_i82544 = (struct i82544 *)(sc->driver_private);
1171 IF_BAD_82544( p_i82544 ) {
1173 os_printf( "Bad device private pointer %x\n", sc->driver_private );
1178 CHECK_NDP_SC_LINK();
1180 if ( 0 == initialized++ ) {
1181 // then this is the first time ever:
1182 if ( ! pci_init_find_82544s() ) {
1184 os_printf( "pci_init_find_82544s failed\n" );
1190 // If this device is not present, exit
1191 if (0 == p_i82544->found)
1194 p_i82544->mac_addr_ok = 0;
1196 ioaddr = p_i82544->io_address; // get I/O address for 82544
1199 os_printf("Init82544 %d @ %x\n", p_i82544->index, (int)ndp);
1203 i82544_reset(p_i82544);
1205 i82544_setup(p_i82544);
1207 InitRxRing(p_i82544);
1208 InitTxRing(p_i82544);
1211 if (p_i82544->hardwired_esa) {
1212 // Hardwire the address without consulting the EEPROM.
1213 // When this flag is set, the p_i82544 will already contain
1214 // the ESA. Copy it to a mac_address for call to set_mac_addr
1215 mac_address[0] = p_i82544->mac_address[0];
1216 mac_address[1] = p_i82544->mac_address[1];
1217 mac_address[2] = p_i82544->mac_address[2];
1218 mac_address[3] = p_i82544->mac_address[3];
1219 mac_address[4] = p_i82544->mac_address[4];
1220 mac_address[5] = p_i82544->mac_address[5];
1222 eth_set_mac_address(p_i82544, mac_address, 0);
1226 // Acquire the ESA either from extenal means (probably RedBoot
1227 // variables) or from the attached EEPROM - if there is one.
1229 #ifdef CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA
1231 CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA( p_i82544, mac_address, ok );
1233 eth_set_mac_address(p_i82544, mac_address, 0);
1235 #else // ! CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA
1237 #ifndef CYGHWR_DEVS_ETH_INTEL_I82544_HAS_NO_EEPROM
1239 cyg_uint16 checksum;
1241 // read eeprom and get 82544's mac address
1242 addr_length = get_eeprom_size(p_i82544);
1243 // (this is the length of the *EEPROM*s address, not MAC address)
1245 // If length is 1, it _probably_ means there's no EEPROM
1246 // present. Couldn't find an explicit mention of this in the
1247 // docs, but length=1 appears to be the behaviour in that case.
1248 if (1 == addr_length) {
1250 os_printf("Error: No EEPROM present for device %d\n",
1254 for (checksum = 0, i = 0, count = 0; count < 64; count++) {
1256 // read word from eeprom
1257 value = read_eeprom_word(p_i82544, addr_length, count);
1259 os_printf( "%02x: %04x\n", count, value );
1263 mac_address[i++] = value & 0xFF;
1264 mac_address[i++] = (value >> 8) & 0xFF;
1268 #ifndef CYGHWR_DEVS_ETH_INTEL_I82544_HAS_ONE_EEPROM_WITHOUT_CRC
1269 // If the EEPROM checksum is wrong, the MAC address read
1270 // from the EEPROM is probably wrong as well. In that
1271 // case, we don't set mac_addr_ok, but continue the
1272 // initialization. If then somebody calls i82544_start
1273 // without calling eth_set_mac_address() first, we refuse
1274 // to bring up the interface, because running with an
1275 // invalid MAC address is not a very brilliant idea.
1277 if ((checksum & 0xFFFF) != 0xBABA) {
1278 // selftest verified checksum, verify again
1280 os_printf("Warning: Invalid EEPROM checksum %04X for device %d\n",
1281 checksum, p_i82544->index);
1283 } else // trailing block
1286 p_i82544->mac_addr_ok = 1;
1288 os_printf("Valid EEPROM checksum\n");
1290 // Second port of dual-port 82546 uses EEPROM ESA | 1
1291 if (p_i82544->device == 0x1010 ||
1292 p_i82544->device == 0x100e) {
1293 cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(p_i82544->devid);
1294 if (CYG_PCI_DEV_GET_FN(devfn) == 1)
1295 mac_address[5] |= 1;
1297 eth_set_mac_address(p_i82544, mac_address, 0);
1301 // record the MAC address in the device structure
1302 p_i82544->mac_address[0] = mac_address[0];
1303 p_i82544->mac_address[1] = mac_address[1];
1304 p_i82544->mac_address[2] = mac_address[2];
1305 p_i82544->mac_address[3] = mac_address[3];
1306 p_i82544->mac_address[4] = mac_address[4];
1307 p_i82544->mac_address[5] = mac_address[5];
1309 #endif // ! CYGHWR_DEVS_ETH_INTEL_I82544_HAS_NO_EEPROM
1310 #endif // ! CYGHWR_DEVS_ETH_INTEL_I82544_GET_ESA
1314 os_printf("i82544_init: MAC Address = %02X %02X %02X %02X %02X %02X\n",
1315 p_i82544->mac_address[0], p_i82544->mac_address[1],
1316 p_i82544->mac_address[2], p_i82544->mac_address[3],
1317 p_i82544->mac_address[4], p_i82544->mac_address[5]);
1320 // and record the net dev pointer
1321 p_i82544->ndp = (void *)ndp;
1323 p_i82544->within_send = 0; // init recursion level
1325 // Initialize upper level driver
1326 if ( p_i82544->mac_addr_ok )
1327 (sc->funs->eth_drv->init)(sc, &(p_i82544->mac_address[0]) );
1330 (sc->funs->eth_drv->init)(sc, NULL );
1336 os_printf("CTRL %08x\n",INL( ioaddr + I82544_CTRL ));
1337 os_printf("STATUS %08x\n",INL( ioaddr + I82544_STATUS ));
1344 // ------------------------------------------------------------------------
1346 // Function : i82544_setup
1348 // ------------------------------------------------------------------------
1351 i82544_setup( struct i82544 *p_i82544 )
1355 #ifndef CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
1356 cyg_uint32 ctrl_ext;
1359 ioaddr = p_i82544->io_address; // get 82544's I/O address
1361 #ifdef CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
1362 // Use Auto-negotiation
1364 ctrl = INL( ioaddr + I82544_CTRL );
1367 ctrl |= I82544_CTRL_SLU | I82544_CTRL_ASDE;
1368 ctrl &= ~(I82544_CTRL_ILOS | I82544_CTRL_FRCSPD | I82544_CTRL_FRCDPLX);
1369 OUTL( ctrl, ioaddr + I82544_CTRL );
1372 // we can assume link is up with autonegotiation
1375 // wait up to 5 seconds for link to come up
1377 int delay_cnt = 500;
1378 while ((mii_read_register( p_i82544, PHY_ADDRESS, 1 ) & 0x4) == 0) {
1380 if (--delay_cnt <= 0)
1386 // The following sequence of resets and bit twiddling seem to be
1387 // necessary to get the 82543 working. Not sure what is necessary
1390 ctrl = INL( ioaddr + I82544_CTRL );
1393 ctrl |= I82544_CTRL_SLU;
1394 ctrl &= ~I82544_CTRL_ILOS;
1395 OUTL( ctrl, ioaddr + I82544_CTRL );
1398 // Force PHY physical reset
1399 // We can only access the PHY after we have done this.
1401 ctrl_ext = INL( ioaddr + I82544_CTRL_EXT );
1402 ctrl_ext |= I82544_CTRL_EXT_PHY_RESET_DIR4;
1403 OUTL( ctrl_ext, ioaddr + I82544_CTRL_EXT );
1406 ctrl_ext = INL( ioaddr + I82544_CTRL_EXT );
1407 ctrl_ext &= ~I82544_CTRL_EXT_PHY_RESET4;
1408 OUTL( ctrl_ext, ioaddr + I82544_CTRL_EXT );
1411 ctrl_ext = INL( ioaddr + I82544_CTRL_EXT );
1412 ctrl_ext |= I82544_CTRL_EXT_PHY_RESET4;
1413 OUTL( ctrl_ext, ioaddr + I82544_CTRL_EXT );
1417 show_phy( p_i82544, PHY_ADDRESS );
1422 // Does not appear to be necessary.
1424 cyg_uint16 phy_ctrl;
1425 phy_ctrl = mii_read_register( p_i82544, PHY_ADDRESS, 0 );
1427 // os_printf("PHY ctrl %04x\n",phy_ctrl);
1428 mii_write_register( p_i82544, PHY_ADDRESS, 0, phy_ctrl );
1430 phy_ctrl = mii_read_register( p_i82544, PHY_ADDRESS, 0 );
1431 // os_printf("PHY ctrl %04x\n",phy_ctrl);
1432 } while( phy_ctrl & 0x8000 );
1434 show_phy( p_i82544, PHY_ADDRESS );
1438 // Tinker with PHY configuration.
1439 // Only on 82543? May not be necessary at all, since disabling
1440 // this does not see to make any difference.
1444 // Set CRS on Tx bit in PHY specific CR
1445 data = mii_read_register( p_i82544, PHY_ADDRESS, 16 );
1446 os_printf("PSCR %04x\n",data);
1448 mii_write_register( p_i82544, PHY_ADDRESS, 16, data );
1450 // Set TX clock to 25MHz in PHY extended CR
1451 data = mii_read_register( p_i82544, PHY_ADDRESS, 20 );
1452 os_printf("PSECR %04x\n",data);
1454 mii_write_register( p_i82544, PHY_ADDRESS, 20, data );
1456 show_phy( p_i82544, PHY_ADDRESS );
1460 // Force speed renegotiation.
1463 cyg_uint16 phy_ctrl;
1464 cyg_uint16 phy_stat;
1465 int delay_cnt = 100 * 5; // wait five seconds, then give up
1468 phy_ctrl = mii_read_register( p_i82544, PHY_ADDRESS, 0 );
1470 // os_printf("PHY ctrl %04x\n",phy_ctrl);
1471 mii_write_register( p_i82544, PHY_ADDRESS, 0, phy_ctrl );
1472 // Wait for it to complete
1475 phy_stat = mii_read_register( p_i82544, PHY_ADDRESS, 1 );
1476 phy_stat = mii_read_register( p_i82544, PHY_ADDRESS, 1 );
1477 } while( (phy_stat & 0x0020) == 0 && (delay_cnt-- > 0) );
1479 if (phy_stat & 0x0020)
1484 show_phy( p_i82544, PHY_ADDRESS );
1490 OUTL( ctrl | I82544_CTRL_LRST, ioaddr + I82544_CTRL );
1492 OUTL( ctrl, ioaddr + I82544_CTRL );
1494 show_phy( p_i82544, PHY_ADDRESS );
1499 // Transfer speed and duplicity settings from PHY to MAC
1501 // In theory the MAC is supposed to auto-configure from what the
1502 // PHY has autonegotiated. In practice this does not seem to work
1503 // (on the 82543 at least, it always thinks it is 1000MHz full
1504 // duplex) and we have to transfer the settings from the PHY by
1505 // hand. Additionally, the settings in the PHY ctrl register seem
1506 // bogus, so we read the values out of the PHY specific status
1507 // register instead.
1509 if (p_i82544->link) {
1510 cyg_uint16 phy_pssr;
1512 phy_pssr = mii_read_register( p_i82544, PHY_ADDRESS, 17 );
1514 ctrl = INL( ioaddr + I82544_CTRL );
1515 // os_printf("CTRL %08x\n",ctrl);
1516 ctrl &= ~(I82544_CTRL_SPEED | I82544_CTRL_FD);
1517 if( phy_pssr & (1<<13) )
1518 ctrl |= I82544_CTRL_FD;
1521 ctrl |= ((phy_pssr>>14)&3)<<8;
1523 ctrl |= I82544_CTRL_FRCDPLX | I82544_CTRL_FRCSPD;
1525 OUTL( ctrl, ioaddr + I82544_CTRL );
1526 // os_printf("CTRL %08x\n",ctrl);
1533 int status = i82544_status( sc );
1534 static int speed[4] = { 10, 100, 1000, 1000 };
1535 os_printf("i82544_start %d flg %x Link = %s, %d Mbps, %s Duplex\n",
1538 status & GEN_STATUS_LINK ? "Up" : "Down",
1539 speed[(status & GEN_STATUS_BPS)>>GEN_STATUS_BPS_SHIFT],
1540 status & GEN_STATUS_FDX ? "Full" : "Half");
1545 // Hang around here for a bit to let the device settle down. We
1546 // don't seem to get away without this.
1552 // Having done all that, the interface still does not work
1553 // properly, UNLESS I now wait >= 45 seconds here. After that it
1554 // seems happy. I cannot find any difference in the state of the
1555 // PHY or the 82543 to explain this.
1557 show_phy( p_i82544, PHY_ADDRESS );
1558 os_printf("CTRL %08x\n",INL( ioaddr + I82544_CTRL ));
1559 os_printf("STATUS %08x\n",INL( ioaddr + I82544_STATUS ));
1560 os_printf("ICR %08x\n",INL( ioaddr + I82544_ICR ));
1561 os_printf("RCTL %08x\n",INL( ioaddr + I82544_RCTL ));
1562 os_printf("TCTL %08x\n",INL( ioaddr + I82544_TCTL ));
1564 os_printf("Waiting 45 seconds\n");
1567 cyg_uint32 status = INL( ioaddr + I82544_STATUS );
1568 // for( i = 0; i < 60; i++ ) // works
1569 // for( i = 0; i < 45; i++ ) // works
1570 // for( i = 0; i < 40; i++ ) // fails
1571 // for( i = 0; i < 35; i++ ) // fails
1572 // for( i = 0; i < 30; i++ ) // fails
1575 PC_WRITE_SCREEN_32( 60, i );
1577 s = INL( ioaddr + I82544_STATUS );
1580 os_printf("%d STATUS change %08x\n",i,s);
1586 show_phy( p_i82544, PHY_ADDRESS );
1587 os_printf("CTRL %08x\n",INL( ioaddr + I82544_CTRL ));
1588 os_printf("STATUS %08x\n",INL( ioaddr + I82544_STATUS ));
1589 os_printf("ICR %08x\n",INL( ioaddr + I82544_ICR ));
1590 os_printf("RCTL %08x\n",INL( ioaddr + I82544_RCTL ));
1591 os_printf("TCTL %08x\n",INL( ioaddr + I82544_TCTL ));
1594 #endif // CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
1596 // Set up interrupts
1598 // Clear any pending interrupts
1599 ctrl = INL( ioaddr + I82544_ICR );
1601 // clear all mask bits
1602 OUTL( 0xFFFFFFFF, ioaddr + I82544_IMC );
1604 // Set interrupt bits for:
1605 // 1 = Transmit queue empty
1606 // 7 = Receiver timeout interrupt
1607 OUTL( (1<<1)|(1<<7), ioaddr + I82544_IMS );
1611 // ------------------------------------------------------------------------
1613 // Function : i82544_start
1615 // ------------------------------------------------------------------------
1618 i82544_start( struct eth_drv_sc *sc, unsigned char *enaddr, int flags )
1620 struct i82544 *p_i82544;
1622 cyg_uint32 txctl, rxctl;
1625 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1628 db_printf("i82544_start\n");
1631 p_i82544 = (struct i82544 *)sc->driver_private;
1632 ioaddr = p_i82544->io_address; // get 82544's I/O address
1634 IF_BAD_82544( p_i82544 ) {
1636 os_printf( "i82544_start: Bad device pointer %x\n", p_i82544 );
1641 if ( ! p_i82544->mac_addr_ok ) {
1643 os_printf("i82544_start %d: invalid MAC address, "
1644 "can't bring up interface\n",
1650 if ( p_i82544->active )
1654 p_i82544->active = 1;
1656 /* Enable promiscuous mode if requested, reception of oversized frames always.
1657 * The latter is needed for VLAN support and shouldn't hurt even if we're not
1660 i82544_configure(p_i82544, 0
1662 || !!(ifp->if_flags & IFF_PROMISC)
1664 #ifdef ETH_DRV_FLAGS_PROMISC_MODE
1665 || !!(flags & ETH_DRV_FLAGS_PROMISC_MODE)
1670 rxctl = INL( ioaddr + I82544_RCTL );
1671 rxctl |= I82544_RCTL_EN;
1672 OUTL( rxctl, ioaddr + I82544_RCTL );
1674 // Enable transmitter
1675 txctl = INL( ioaddr + I82544_TCTL );
1676 txctl |= I82544_TCTL_EN;
1677 OUTL( txctl, ioaddr + I82544_TCTL );
1681 // ------------------------------------------------------------------------
1683 // Function : i82544_status
1685 // ------------------------------------------------------------------------
1687 i82544_status( struct eth_drv_sc *sc )
1690 struct i82544 *p_i82544;
1693 db_printf("i82544_status\n");
1696 p_i82544 = (struct i82544 *)sc->driver_private;
1698 IF_BAD_82544( p_i82544 ) {
1700 os_printf( "i82544_status: Bad device pointer %x\n", p_i82544 );
1705 ioaddr = p_i82544->io_address; // get 82544's I/O address
1707 status = INL(ioaddr + I82544_STATUS);
1712 // ------------------------------------------------------------------------
1714 // Function : BringDown82544
1716 // ------------------------------------------------------------------------
1719 i82544_stop( struct eth_drv_sc *sc )
1721 struct i82544 *p_i82544;
1723 cyg_uint32 txctl, rxctl;
1726 db_printf("i82544_stop\n");
1729 p_i82544 = (struct i82544 *)sc->driver_private;
1731 IF_BAD_82544( p_i82544 ) {
1733 os_printf( "i82544_stop: Bad device pointer %x\n", p_i82544 );
1739 os_printf("i82544_stop %d flg %x\n", p_i82544->index, *(int *)p_i82544 );
1742 p_i82544->active = 0; // stop people tormenting it
1744 ioaddr = p_i82544->io_address;
1747 rxctl = INL( ioaddr + I82544_RCTL );
1748 rxctl &= ~I82544_RCTL_EN;
1749 OUTL( rxctl, ioaddr + I82544_RCTL );
1751 // Enable transmitter
1752 txctl = INL( ioaddr + I82544_TCTL );
1753 txctl &= ~I82544_TCTL_EN;
1754 OUTL( txctl, ioaddr + I82544_TCTL );
1759 // ------------------------------------------------------------------------
1761 // Function : InitRxRing
1763 // ------------------------------------------------------------------------
1766 InitRxRing(struct i82544* p_i82544)
1770 cyg_uint32 ioaddr = p_i82544->io_address;
1774 os_printf("InitRxRing %d\n", p_i82544->index);
1777 // Allocate array of Rx desriptors
1778 rxring = pciwindow_mem_alloc(
1779 MAX_RX_DESCRIPTORS * I82544_RD_SIZE + 32 );
1781 // assign ring structure, aligning it on a 16 byte boudary.
1782 p_i82544->rx_ring = (rxring + 15) & ~15;
1784 // Allocate and fill in buffer pointers
1785 for ( i = 0; i < MAX_RX_DESCRIPTORS; i++) {
1786 CYG_ADDRESS rd = p_i82544->rx_ring + (i*I82544_RD_SIZE);
1787 CYG_ADDRESS buf = pciwindow_mem_alloc(MAX_RX_PACKET_SIZE);
1788 WRITEMEM64( rd + I82544_RD_BUFFER, VIRT_TO_BUS(buf) );
1791 // Set the receiver queue registers
1793 OUTL( VIRT_TO_BUS(p_i82544->rx_ring), ioaddr + I82544_RDBAL );
1794 OUTL( 0, ioaddr + I82544_RDBAH );
1795 OUTL( MAX_RX_DESCRIPTORS * I82544_RD_SIZE, ioaddr + I82544_RDLEN );
1796 OUTL( 0, ioaddr + I82544_RDH );
1797 OUTL( MAX_RX_DESCRIPTORS - 5, ioaddr + I82544_RDT );
1801 for( i = 0; i < 32; i++ )
1802 OUTL( 0, ioaddr + I82544_RAT +(i*4) );
1805 for( i = 0; i < 128; i++ )
1806 OUTL( 0, ioaddr + I82544_MTA +(i*4) );
1808 // Set up receiver to accept broadcasts
1809 rxctl = INL( ioaddr + I82544_RCTL );
1810 rxctl |= I82544_RCTL_BAM;
1811 OUTL( rxctl, ioaddr + I82544_RCTL );
1814 os_printf("RCTL %08x\n",rxctl);
1817 p_i82544->next_rx_descriptor = 0;
1818 p_i82544->rx_pointer = 0;
1821 // ------------------------------------------------------------------------
1823 // Function : PacketRxReady (Called from delivery thread & foreground)
1825 // ------------------------------------------------------------------------
1828 PacketRxReady(struct i82544* p_i82544)
1830 struct cyg_netdevtab_entry *ndp;
1831 struct eth_drv_sc *sc;
1836 // db_printf("PacketRxReady\n");
1839 ndp = (struct cyg_netdevtab_entry *)(p_i82544->ndp);
1840 sc = (struct eth_drv_sc *)(ndp->device_instance);
1842 CHECK_NDP_SC_LINK();
1844 ioaddr = p_i82544->io_address;
1847 rxp = p_i82544->rx_pointer;
1855 rxh = INL( ioaddr + I82544_RDH );
1857 #if 0 //def DEBUG_82544
1858 os_printf("rxp %04d rxh %04x\n",rxp,rxh);
1861 // If the head pointer has not advanced, there have been no
1862 // packets received.
1866 // Form packet address
1867 dp = p_i82544->rx_ring + (rxp * I82544_RD_SIZE);
1870 READMEM8( dp + I82544_RD_STATUS, status );
1872 #if 0 //def DEBUG_82544
1875 READMEM16( dp + I82544_RD_LENGTH, length );
1876 os_printf("rxp %04d status %02x length %d\n",rxp,status,length);
1880 if( status & I82544_RD_STATUS_EOP )
1884 READMEM16( dp + I82544_RD_LENGTH, length );
1887 os_printf("rxp %04d length %d\n",rxp,length);
1889 CYG_ASSERT( MAX_RX_PACKET_SIZE >= length, "Oversize Rx" );
1891 // tell the callback the right packet
1892 p_i82544->next_rx_descriptor = rxp;
1895 if ( length > sizeof( struct ether_header ) )
1896 // then it is acceptable; offer the data to the network stack
1898 (sc->funs->eth_drv->recv)( sc, length );
1903 // Advance rxp pointer
1904 rxp = ( rxp + 1 ) % MAX_RX_DESCRIPTORS;
1906 // We can now also advance the tail pointer by 1
1907 rxt = INL( ioaddr + I82544_RDT );
1908 dp = p_i82544->rx_ring + (rxt * I82544_RD_SIZE);
1909 WRITEMEM8( dp + I82544_RD_STATUS, status );
1910 rxt = ( rxt + 1 ) % MAX_RX_DESCRIPTORS;
1911 OUTL( rxt, ioaddr + I82544_RDT );
1913 #ifdef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
1914 // Can't deliver more than one packet in polled standalone mode
1919 // Save next rx pointer for next time.
1920 p_i82544->rx_pointer = rxp;
1924 // and the callback function
1927 i82544_recv( struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len )
1929 struct i82544 *p_i82544;
1933 cyg_uint16 total_len;
1934 struct eth_drv_sg *last_sg;
1937 db_printf("i82544_recv\n");
1940 p_i82544 = (struct i82544 *)sc->driver_private;
1942 IF_BAD_82544( p_i82544 ) {
1944 os_printf( "i82544_recv: Bad device pointer %x\n", p_i82544 );
1949 rxp = p_i82544->next_rx_descriptor;
1950 // Form packet address
1951 dp = p_i82544->rx_ring + (rxp * I82544_RD_SIZE);
1953 #if 0 //def DEBUG_82544
1956 os_printf("RxD %08x",dp);
1957 for( i = 0; i < 16; i++ )
1960 if( (i%8) == 0 ) os_printf("\n");
1961 READMEM8( dp + i, b );
1962 os_printf("%02x ",b);
1967 // Copy the data to the network stack
1968 READMEM64( dp + I82544_RD_BUFFER, from_p );
1969 from_p = BUS_TO_VIRT(from_p);
1970 READMEM16( dp + I82544_RD_LENGTH, total_len );
1973 db_printf("RXP: %04x len %d\n",rxp,total_len);
1976 // check we have memory to copy into; we would be called even if
1977 // caller was out of memory in order to maintain our state.
1978 if ( 0 == sg_len || 0 == sg_list )
1979 return; // caller was out of mbufs
1981 CYG_ASSERT( 0 < sg_len, "sg_len underflow" );
1982 CYG_ASSERT( MAX_ETH_DRV_SG >= sg_len, "sg_len overflow" );
1984 for ( last_sg = &sg_list[sg_len]; sg_list < last_sg; sg_list++ ) {
1988 to_p = (cyg_uint8 *)(sg_list->buf);
1991 CYG_ASSERT( 0 <= l, "sg length -ve" );
1993 if ( 0 >= l || 0 == to_p )
1994 return; // caller was out of mbufs
1996 if ( l > total_len )
1999 #if 0 //def DEBUG_82544
2002 os_printf("Pkt len %d",l);
2003 if( ll > 32 ) ll = 32;
2004 for( i = 0; i < ll; i++ )
2007 if( (i%8) == 0 ) os_printf("\n %04x: ",i);
2008 b = ((cyg_uint8 *)from_p)[i];
2009 os_printf("%02x ",b);
2015 memcpy( to_p, (unsigned char *)from_p, l );
2020 CYG_ASSERT( 0 == total_len, "total_len mismatch in rx" );
2021 CYG_ASSERT( last_sg == sg_list, "sg count mismatch in rx" );
2026 // ------------------------------------------------------------------------
2028 // Function : InitTxRing
2030 // ------------------------------------------------------------------------
2033 InitTxRing(struct i82544* p_i82544)
2036 cyg_uint32 ioaddr = p_i82544->io_address;
2041 os_printf("InitTxRing %d\n", p_i82544->index);
2044 // Allocate array of Tx desriptors
2045 txring = pciwindow_mem_alloc(
2046 MAX_TX_DESCRIPTORS * I82544_TD_SIZE + 32 );
2048 // assign ring structure, aligning it on a 16 byte boudary.
2049 p_i82544->tx_ring = (txring + 15) & ~15;
2051 // Allocate and fill in buffer pointers
2052 for ( i = 0; i < MAX_TX_DESCRIPTORS; i++) {
2053 CYG_ADDRESS td = p_i82544->tx_ring + (i*I82544_TD_SIZE);
2054 WRITEMEM64( td + I82544_TD_BUFFER, 0 );
2057 // Set the transmitter queue registers
2059 OUTL( VIRT_TO_BUS(p_i82544->tx_ring), ioaddr + I82544_TDBAL );
2060 OUTL( 0, ioaddr + I82544_TDBAH );
2061 OUTL( MAX_TX_DESCRIPTORS * I82544_TD_SIZE, ioaddr + I82544_TDLEN );
2062 OUTL( 0, ioaddr + I82544_TDH );
2063 OUTL( 0, ioaddr + I82544_TDT );
2066 OUTL( 8 | (8<<10) | (6<<20), ioaddr + I82544_TIPG );
2068 // Program tx ctrl register
2069 txctl = INL( ioaddr + I82544_TCTL );
2070 txctl |= (15<<4); // collision threshold
2071 txctl |= (64<<12); // collision distance
2072 txctl |= I82544_TCTL_PSP;
2073 OUTL( txctl, ioaddr + I82544_TCTL );
2075 p_i82544->tx_in_progress = 0;
2076 p_i82544->tx_pointer = 0;
2080 // ------------------------------------------------------------------------
2082 // Function : TxDone (Called from delivery thread)
2084 // This returns Tx's from the Tx Machine to the stack (ie. reports
2085 // completion) - allowing for missed interrupts, and so on.
2086 // ------------------------------------------------------------------------
2089 TxDone(struct i82544* p_i82544)
2091 struct cyg_netdevtab_entry *ndp;
2092 struct eth_drv_sc *sc;
2094 cyg_int32 txp = p_i82544->tx_pointer;
2097 // db_printf("TxDone\n");
2100 ndp = (struct cyg_netdevtab_entry *)(p_i82544->ndp);
2101 sc = (struct eth_drv_sc *)(ndp->device_instance);
2103 CHECK_NDP_SC_LINK();
2105 ioaddr = p_i82544->io_address; // get device I/O address
2107 if( !p_i82544->active )
2117 txh = INL( ioaddr + I82544_TDH );
2119 // If there has been no advance on the transmit header,
2125 os_printf("TxDone: TxH %04d TxP %04d\n",txh,txp);
2128 // Get descriptor address
2129 dp = p_i82544->tx_ring + (txp * I82544_TD_SIZE);
2131 READMEM8( dp + I82544_TD_CMD, cmd );
2132 READMEM8( dp + I82544_TD_STATUS, status );
2134 os_printf("cmd %02x status %02x\n",cmd,status);
2137 // Zero out buffer and command
2138 WRITEMEM64( dp + I82544_TD_BUFFER, 0 );
2139 WRITEMEM8( dp + I82544_TD_CMD, 0 );
2141 if( cmd & I82544_TD_CMD_EOP )
2143 // A done end of packet descrptor
2145 if( p_i82544->tx_keys[txp] != 0 )
2147 // Call network stack with correct value of txp in structure.
2148 // There may be recursive calls in here, so we need to make sure
2149 // that txp is updated correctly.
2150 p_i82544->tx_pointer = ( txp + 1 ) % MAX_TX_DESCRIPTORS;
2151 (sc->funs->eth_drv->tx_done)( sc, p_i82544->tx_keys[txp], 0 );
2152 txp = p_i82544->tx_pointer;
2157 // Advance tx pointer
2158 txp = ( txp + 1 ) % MAX_TX_DESCRIPTORS;
2162 // restore txp to data structure.
2163 p_i82544->tx_pointer = txp;
2169 check_link(struct i82544 *p_i82544)
2171 if ( p_i82544->link == 0 )
2173 cyg_uint16 phy_pssr;
2174 cyg_uint16 phy_stat;
2176 phy_stat = mii_read_register( p_i82544, PHY_ADDRESS, 1 );
2177 if (phy_stat & 0x20)
2184 ioaddr = p_i82544->io_address; // get device I/O address
2186 phy_pssr = mii_read_register( p_i82544, PHY_ADDRESS, 17 );
2188 ctrl = INL( ioaddr + I82544_CTRL );
2189 ctrl &= ~(I82544_CTRL_SPEED | I82544_CTRL_FD);
2190 if( phy_pssr & (1<<13) )
2191 ctrl |= I82544_CTRL_FD;
2194 ctrl |= ((phy_pssr>>14)&3)<<8;
2195 ctrl |= I82544_CTRL_FRCDPLX | I82544_CTRL_FRCSPD;
2197 OUTL( ctrl, ioaddr + I82544_CTRL );
2201 return p_i82544->link == 1;
2205 // ------------------------------------------------------------------------
2207 // Function : i82544_can_send
2209 // ------------------------------------------------------------------------
2212 i82544_can_send(struct eth_drv_sc *sc)
2214 struct i82544 *p_i82544;
2218 // db_printf("i82544_can_send\n");
2221 p_i82544 = (struct i82544 *)sc->driver_private;
2223 IF_BAD_82544( p_i82544 ) {
2225 os_printf( "i82544_send: Bad device pointer %x\n", p_i82544 );
2230 ioaddr = p_i82544->io_address; // get device I/O address
2232 if ( p_i82544->active )
2234 cyg_int32 txh, txt, diff;
2237 if (!check_link(p_i82544))
2240 // Poll for Tx completion
2243 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2244 // We are not prepared to receive a packet now if we are in a polled
2245 // standalone configuration.
2247 // Poll for receptions
2248 PacketRxReady( p_i82544 );
2251 // Now see whether the Tx queue has space for another
2252 // transmit. We look at the difference between the head and
2253 // tail pointer, and if there is space for at least 5 more
2254 // descriptors, we allow a new transmission to go ahead.
2255 txh = INL( ioaddr + I82544_TDH );
2256 txt = INL( ioaddr + I82544_TDT );
2258 diff = (txh-1) - txt;
2259 if( diff < 0 ) diff += MAX_TX_DESCRIPTORS;
2261 // os_printf("TxH %04d TxT %04d diff %04d\n",txh,txt,diff);
2270 // ------------------------------------------------------------------------
2272 // Function : i82544_send
2274 // ------------------------------------------------------------------------
2277 i82544_send(struct eth_drv_sc *sc,
2278 struct eth_drv_sg *sg_list, int sg_len, int total_len,
2281 struct i82544 *p_i82544;
2283 struct eth_drv_sg *last_sg;
2288 db_printf("i82544_send\n");
2291 p_i82544 = (struct i82544 *)sc->driver_private;
2293 IF_BAD_82544( p_i82544 ) {
2295 os_printf( "i82544_send: Bad device pointer %x\n", p_i82544 );
2301 os_printf("Tx %d %x: %d sg's, %d bytes, KEY %x\n",
2302 p_i82544->index, (int)p_i82544, sg_len, total_len, key );
2305 if ( ! p_i82544->active )
2306 return; // device inactive, no return
2307 ioaddr = p_i82544->io_address; // get device I/O address
2309 // Get the tx tail pointer
2310 txt = INL( ioaddr + I82544_TDT );
2312 for ( last_sg = &sg_list[sg_len]; sg_list < last_sg; sg_list++ )
2319 from_p = (cyg_uint8 *)(sg_list->buf); // normal cached address
2322 if ( l > total_len )
2325 // Get the descriptor address from the tail pointer.
2326 dp = p_i82544->tx_ring + (txt * I82544_TD_SIZE);
2330 #ifdef HAL_DCACHE_STORE
2331 HAL_DCACHE_STORE( ((CYG_ADDRESS)from_p) &~(HAL_DCACHE_LINE_SIZE-1),
2332 l + (HAL_DCACHE_LINE_SIZE-1) );
2335 WRITEMEM64( dp + I82544_TD_BUFFER, VIRT_TO_BUS(from_p) );
2336 WRITEMEM16( dp + I82544_TD_LENGTH, l );
2338 // Set EOP bit on last packet
2339 if( total_len <= 0 )
2340 cmd |= I82544_TD_CMD_EOP;
2343 // cmd |= I82544_TD_CMD_RPS | I82544_TD_CMD_RS;
2345 cmd |= I82544_TD_CMD_IFCS;
2347 // Write command byte
2348 WRITEMEM8( dp + I82544_TD_CMD, cmd );
2350 // Zero out rest of fields
2351 WRITEMEM8( dp + I82544_TD_STATUS, 0 );
2352 WRITEMEM8( dp + I82544_TD_CSO, 0 );
2353 WRITEMEM8( dp + I82544_TD_CSS, 0 );
2354 WRITEMEM16( dp + I82544_TD_SPECIAL, 0 );
2356 // Store the key for this transmission in the matching slot
2357 // for the descriptor.
2358 p_i82544->tx_keys[txt] = key;
2360 // Increment tx tail pointer
2361 txt = (txt + 1) % MAX_TX_DESCRIPTORS;
2365 // And finally, cause the transmission to happen by setting the
2366 // tail pointer in the hardware.
2367 OUTL( txt, ioaddr + I82544_TDT );
2371 // ------------------------------------------------------------------------
2373 // Function : i82544_reset
2375 // ------------------------------------------------------------------------
2377 i82544_reset(struct i82544* p_i82544)
2379 cyg_uint32 ioaddr = p_i82544->io_address;
2383 db_printf("i82544_reset\n");
2386 ctrl = INL( ioaddr + I82544_CTRL );
2389 OUTL( ctrl | I82544_CTRL_RST, ioaddr + I82544_CTRL );
2391 ctrl = INL( ioaddr + I82544_CTRL );
2395 // ------------------------------------------------------------------------
2397 // INTERRUPT HANDLERS
2399 // ------------------------------------------------------------------------
2402 eth_isr(cyg_vector_t vector, cyg_addrword_t data)
2404 struct i82544* p_i82544 = (struct i82544 *)data;
2409 // db_printf("eth_isr\n");
2412 IF_BAD_82544( p_i82544 ) {
2414 os_printf( "i82544_isr: Bad device pointer %x\n", p_i82544 );
2419 ioaddr = p_i82544->io_address;
2421 status = INL( ioaddr + I82544_ICR );
2424 db_printf("eth_isr %04x\n",status);
2427 return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // schedule DSR
2431 // ------------------------------------------------------------------------
2433 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2435 eth_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
2437 struct i82544* p_i82544 = (struct i82544 *)data;
2438 struct cyg_netdevtab_entry *ndp =
2439 (struct cyg_netdevtab_entry *)(p_i82544->ndp);
2440 struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance);
2443 db_printf("eth_dsr\n");
2446 eth_drv_dsr( vector, count, (cyg_addrword_t)sc );
2448 cyg_drv_interrupt_acknowledge(p_i82544->vector);
2450 #endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2452 // ------------------------------------------------------------------------
2456 i82544_deliver(struct eth_drv_sc *sc)
2458 struct i82544* p_i82544 = (struct i82544 *)(sc->driver_private);
2461 db_printf("i82544_deliver\n");
2464 // First pass any rx data up the stack
2465 PacketRxReady(p_i82544);
2467 // Then scan for completed Tx and inform the stack
2471 // ------------------------------------------------------------------------
2472 // Device table entry to operate the chip in a polled mode.
2473 // Only diddle the interface we were asked to!
2476 i82544_poll(struct eth_drv_sc *sc)
2478 struct i82544 *p_i82544;
2479 p_i82544 = (struct i82544 *)sc->driver_private;
2482 db_printf("i82544_poll\n");
2485 IF_BAD_82544( p_i82544 ) {
2487 os_printf( "i82544_poll: Bad device pointer %x\n", p_i82544 );
2492 if (!check_link(p_i82544))
2495 // As it happens, this driver always requests the DSR to be called:
2496 (void)eth_isr( p_i82544->vector, (cyg_addrword_t)p_i82544 );
2498 // (no harm in calling this ints-off also, when polled)
2499 i82544_deliver( sc );
2502 // ------------------------------------------------------------------------
2503 // Determine interrupt vector used by a device - for attaching GDB stubs
2507 i82544_int_vector(struct eth_drv_sc *sc)
2509 struct i82544 *p_i82544;
2510 p_i82544 = (struct i82544 *)sc->driver_private;
2511 return (p_i82544->vector);
2515 // ------------------------------------------------------------------------
2517 // Function : pci_init_find_82544s
2519 // This is called exactly once at the start of time to:
2520 // o scan the PCI bus for objects
2521 // o record them in the device table
2522 // o acquire all the info needed for the driver to access them
2523 // o instantiate interrupts for them
2524 // o attach those interrupts appropriately
2525 // ------------------------------------------------------------------------
2527 static cyg_pci_match_func find_82544s_match_func;
2529 // Intel 82543 and 82544 are virtually identical, with different
2532 find_82544s_match_func( cyg_uint16 v, cyg_uint16 d, cyg_uint32 c, void *p )
2534 return ((0x8086 == v) &&
2535 ((0x1004 == d) || // 82543
2536 (0x100d == d) || // 82543
2537 (0x1008 == d) || // 82544
2538 (0x1010 == d) || // 82546
2539 (0x100e == d) // 82540EM
2545 pci_init_find_82544s( void )
2547 cyg_pci_device_id devid;
2548 cyg_pci_device dev_info;
2551 int found_devices = 0;
2554 db_printf("pci_init_find_82544s()\n");
2557 // allocate memory to be used in ioctls later
2558 if (mem_reserved_ioctl != (void*)0) {
2560 db_printf("pci_init_find_82544s() called > once\n");
2565 // First initialize the heap in PCI window'd memory
2566 i82544_heap_size = CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE;
2567 i82544_heap_base = (cyg_uint8 *)CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE;
2568 i82544_heap_free = i82544_heap_base;
2570 // mem_reserved_ioctl = pciwindow_mem_alloc(MAX_MEM_RESERVED_IOCTL);
2574 db_printf("Finished cyg_pci_init();\n");
2577 devid = CYG_PCI_NULL_DEVID;
2579 for (device_index = 0;
2580 device_index < CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT;
2582 struct i82544 *p_i82544 = i82544_priv_array[device_index];
2584 p_i82544->index = device_index;
2586 // See above for find_82544s_match_func
2587 if (cyg_pci_find_matching( &find_82544s_match_func, NULL, &devid )) {
2589 db_printf("eth%d = 8254x\n", device_index);
2591 cyg_pci_get_device_info(devid, &dev_info);
2593 p_i82544->interrupt_handle = 0; // Flag not attached.
2594 if (cyg_pci_translate_interrupt(&dev_info, &p_i82544->vector)) {
2596 db_printf(" Wired to HAL vector %d\n", p_i82544->vector);
2598 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2599 cyg_drv_interrupt_create(
2601 0, // Priority - unused
2602 (CYG_ADDRWORD)p_i82544, // Data item passed to ISR & DSR
2603 #ifdef CYGHWR_DEVS_ETH_INTEL_I82544_DEMUX_ALL
2609 &p_i82544->interrupt_handle, // handle to intr obj
2610 &p_i82544->interrupt_object ); // space for int obj
2612 cyg_drv_interrupt_attach(p_i82544->interrupt_handle);
2614 // Don't unmask the interrupt yet, that could get us into a
2616 #ifdef CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT
2617 // ALSO attach it to MUX interrupt for multiplexed
2618 // interrupts. This is for certain boards where the
2619 // PCI backplane is wired "straight through" instead of
2620 // with a rotation of interrupt lines in the different
2623 static cyg_handle_t mux_interrupt_handle = 0;
2624 static cyg_interrupt mux_interrupt_object;
2626 if ( ! mux_interrupt_handle ) {
2628 db_printf(" Also attaching to HAL vector %d\n",
2629 CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT);
2631 cyg_drv_interrupt_create(
2632 CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT,
2633 0, // Priority - unused
2634 (CYG_ADDRWORD)p_i82544,// Data item passed to ISR and DSR
2637 &mux_interrupt_handle,
2638 &mux_interrupt_object );
2640 cyg_drv_interrupt_attach(mux_interrupt_handle);
2643 #endif // CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT
2644 #endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2649 db_printf(" Does not generate interrupts.\n");
2653 if (cyg_pci_configure_device(&dev_info)) {
2656 db_printf("Found device on bus %d, devfn 0x%02x:\n",
2657 CYG_PCI_DEV_GET_BUS(devid),
2658 CYG_PCI_DEV_GET_DEVFN(devid));
2660 if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE) {
2661 db_printf(" Note that board is active. Probed"
2662 " sizes and CPU addresses invalid!\n");
2664 db_printf(" Vendor 0x%04x", dev_info.vendor);
2665 db_printf("\n Device 0x%04x", dev_info.device);
2666 db_printf("\n Command 0x%04x, Status 0x%04x\n",
2667 dev_info.command, dev_info.status);
2669 db_printf(" Class/Rev 0x%08x", dev_info.class_rev);
2670 db_printf("\n Header 0x%02x\n", dev_info.header_type);
2672 db_printf(" SubVendor 0x%04x, Sub ID 0x%04x\n",
2673 dev_info.header.normal.sub_vendor,
2674 dev_info.header.normal.sub_id);
2676 for(i = 0; i < CYG_PCI_MAX_BAR; i++) {
2677 db_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
2678 db_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
2679 dev_info.base_size[i], dev_info.base_map[i]);
2681 db_printf(" eth%d configured\n", device_index);
2684 p_i82544->found = 1;
2685 p_i82544->active = 0;
2686 p_i82544->devid = devid;
2687 p_i82544->device = dev_info.device;
2688 p_i82544->io_address = dev_info.base_map[0];
2690 db_printf(" I/O address = 0x%08x device = %04x\n", dev_info.base_map[0],
2694 // Don't use cyg_pci_set_device_info since it clears
2695 // some of the fields we want to print out below.
2696 cyg_pci_read_config_uint16(dev_info.devid,
2697 CYG_PCI_CFG_COMMAND, &cmd);
2698 cmd |= (CYG_PCI_CFG_COMMAND_IO // enable I/O space
2699 | CYG_PCI_CFG_COMMAND_MEMORY // enable memory space
2700 | CYG_PCI_CFG_COMMAND_MASTER); // enable bus master
2701 cyg_pci_write_config_uint16(dev_info.devid,
2702 CYG_PCI_CFG_COMMAND, cmd);
2704 // Now the PCI part of the device is configured, reset
2705 // it. This should make it safe to enable the
2707 i82544_reset(p_i82544);
2709 // This is the indicator for "uses an interrupt"
2710 if (p_i82544->interrupt_handle != 0) {
2711 cyg_drv_interrupt_acknowledge(p_i82544->vector);
2712 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2713 cyg_drv_interrupt_unmask(p_i82544->vector);
2714 #endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2717 db_printf(" **** Device enabled for I/O and Memory "
2718 "and Bus Master\n");
2722 p_i82544->found = 0;
2723 p_i82544->active = 0;
2725 db_printf("Failed to configure device %d\n",device_index);
2730 p_i82544->found = 0;
2731 p_i82544->active = 0;
2733 db_printf("eth%d not found\n", device_index);
2738 if (0 == found_devices)
2741 #ifdef CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT
2742 // Now enable the mux shared interrupt if it is in use
2743 if (mux_interrupt_handle) {
2744 cyg_drv_interrupt_acknowledge(CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT);
2745 cyg_drv_interrupt_unmask(CYGNUM_DEVS_ETH_INTEL_I82544_SEPARATE_MUX_INTERRUPT);
2749 // Now a delay to ensure the hardware has "come up" before you try to
2750 // use it. Yes, really, the full 2 seconds. It's only really
2751 // necessary if DEBUG is off - otherwise all that printout wastes
2752 // enough time. No kidding.
2757 // ------------------------------------------------------------------------
2759 // Function : i82544_configure
2761 // Return : 0 = It worked.
2762 // non0 = It failed.
2763 // ------------------------------------------------------------------------
2765 static int i82544_configure(struct i82544* p_i82544, int promisc, int oversized)
2768 // volatile CFG *ccs;
2769 // volatile cyg_uint8* config_bytes;
2770 // cyg_uint16 status;
2773 IF_BAD_82544( p_i82544 ) {
2775 os_printf( "eth_set_promiscuous_mode: Bad device pointer %x\n",
2781 ioaddr = p_i82544->io_address;
2783 // Not currently supported
2788 // ------------------------------------------------------------------------
2790 // Function : eth_set_mac_address
2792 // Return : 0 = It worked.
2793 // non0 = It failed.
2794 // ------------------------------------------------------------------------
2797 eth_set_mac_address(struct i82544* p_i82544, cyg_uint8 *addr, int eeprom)
2800 cyg_uint32 maclo, machi;
2803 db_printf("eth_set_mac_address\n");
2806 IF_BAD_82544( p_i82544 ) {
2808 os_printf( "eth_set_mac_address : Bad device pointer %x\n",
2814 ioaddr = p_i82544->io_address;
2816 // Write MAC address to RAT[0]
2818 maclo = addr[0] | (addr[1]<<8) | (addr[2]<<16) | (addr[3]<<24);
2819 machi = (1<<31) | (0<<16) | addr[4] | (addr[5]<<8);
2822 os_printf("setting: lo %08x hi %08x\n",maclo,machi);
2825 OUTL( maclo , ioaddr + I82544_RAT );
2826 OUTL( machi, ioaddr + I82544_RAT + 4 );
2829 // record the MAC address in the device structure
2830 p_i82544->mac_address[0] = addr[0];
2831 p_i82544->mac_address[1] = addr[1];
2832 p_i82544->mac_address[2] = addr[2];
2833 p_i82544->mac_address[3] = addr[3];
2834 p_i82544->mac_address[4] = addr[4];
2835 p_i82544->mac_address[5] = addr[5];
2836 p_i82544->mac_addr_ok = 1;
2839 os_printf( "Set MAC Address = %02X %02X %02X %02X %02X %02X (ok %d)\n",
2840 p_i82544->mac_address[0],
2841 p_i82544->mac_address[1],
2842 p_i82544->mac_address[2],
2843 p_i82544->mac_address[3],
2844 p_i82544->mac_address[4],
2845 p_i82544->mac_address[5],
2846 p_i82544->mac_addr_ok );
2849 return p_i82544->mac_addr_ok ? 0 : 1;
2852 // ------------------------------------------------------------------------
2854 // Function : eth_get_mac_address
2856 // ------------------------------------------------------------------------
2857 #ifdef ETH_DRV_GET_MAC_ADDRESS
2859 eth_get_mac_address(struct i82544* p_i82544, char *addr)
2862 db_printf("eth_get_mac_address\n");
2865 IF_BAD_82544( p_i82544 ) {
2867 os_printf( "eth_get_mac_address : Bad device pointer %x\n",
2873 memcpy( addr, (char *)(&p_i82544->mac_address[0]), 6 );
2877 // ------------------------------------------------------------------------
2879 // Function : i82544_ioctl
2881 // ------------------------------------------------------------------------
2883 i82544_ioctl(struct eth_drv_sc *sc, unsigned long key,
2884 void *data, int data_length)
2886 struct i82544 *p_i82544;
2889 db_printf("i82544_ioctl\n");
2892 p_i82544 = (struct i82544 *)sc->driver_private;
2894 IF_BAD_82544( p_i82544 ) {
2896 os_printf( "i82544_ioctl/control: Bad device pointer %x\n", p_i82544 );
2902 db_printf( "i82544_ioctl: device eth%d at %x; key is 0x%x, data at %x[%d]\n",
2903 p_i82544->index, p_i82544, key, data, data_length );
2908 #ifdef ETH_DRV_SET_MAC_ADDRESS
2909 case ETH_DRV_SET_MAC_ADDRESS:
2910 if ( 6 != data_length )
2912 return eth_set_mac_address( p_i82544, data, 1 /* do write eeprom */ );
2915 #ifdef ETH_DRV_GET_MAC_ADDRESS
2916 case ETH_DRV_GET_MAC_ADDRESS:
2917 return eth_get_mac_address( p_i82544, data );
2926 // ------------------------------------------------------------------------