1 #ifndef _IF_MCF5272_FEC
2 #define _IF_MCF5272_FEC
3 //==========================================================================
4 //####ECOSGPLCOPYRIGHTBEGIN####
5 // -------------------------------------------
6 // This file is part of eCos, the Embedded Configurable Operating System.
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15 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // or inline functions from this file, or you compile this file and link it
24 // with other works to produce a work based on this file, this file does not
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34 // -------------------------------------------
35 //####ECOSGPLCOPYRIGHTEND####
36 //==========================================================================
38 #include <cyg/hal/drv_api.h>
39 #include <cyg/io/eth/eth_drv_stats.h>
40 #include <cyg/devs/eth/nbuf.h>
42 /* Ethernet controller inetrrupt priority level. */
43 #define MCF5272_INT_LEVEL 4
45 /* Bit level definitions and macros */
46 #define MCF5272_FEC_ECR_RESET (0x00000001)
47 #define MCF5272_FEC_ECR_ETHER_EN (0x00000002)
48 #define MCF5272_FEC_EIR_GRA (0x10000000)
50 #define MCF5272_FEC_EIR_HBE (0x80000000)
51 #define MCF5272_FEC_EIR_BR (0x40000000)
52 #define MCF5272_FEC_EIR_BT (0x20000000)
53 #define MCF5272_FEC_EIR_GRA (0x10000000)
54 #define MCF5272_FEC_EIR_TXF (0x08000000)
55 #define MCF5272_FEC_EIR_TXB (0x04000000)
56 #define MCF5272_FEC_EIR_RXF (0x02000000)
57 #define MCF5272_FEC_EIR_RXB (0x01000000)
58 #define MCF5272_FEC_EIR_MII (0x00800000)
59 #define MCF5272_FEC_EIR_EBERR (0x00400000)
60 #define MCF5272_FEC_EIR_UMINT (1<<21)
62 #define MCF5272_FEC_IMR_HBEEN (0x80000000)
63 #define MCF5272_FEC_IMR_BREN (0x40000000)
64 #define MCF5272_FEC_IMR_BTEN (0x20000000)
65 #define MCF5272_FEC_IMR_GRAEN (0x10000000)
66 #define MCF5272_FEC_IMR_TXFEN (0x08000000)
67 #define MCF5272_FEC_IMR_TXBEN (0x04000000)
68 #define MCF5272_FEC_IMR_RXFEN (0x02000000)
69 #define MCF5272_FEC_IMR_RXBEN (0x01000000)
70 #define MCF5272_FEC_IMR_MIIEN (0x00800000)
71 #define MCF5272_FEC_IMR_EBERREN (0x00400000)
72 #define MCF5272_FEC_RCR_PROM (0x00000008)
73 #define MCF5272_FEC_RCR_MII_MODE (0x00000004)
74 #define MCF5272_FEC_RCR_DRT (0x00000002)
75 #define MCF5272_FEC_RCR_LOOP (0x00000001)
76 #define MCF5272_FEC_TCR_GTS (0x00000001)
77 #define MCF5272_FEC_TCR_HBC (0x00000002)
78 #define MCF5272_FEC_TCR_FDEN (0x00000004)
79 #define MCF5272_FEC_RDAR_DESTACT (0x01000000)
80 #define MCF5272_FEC_MFLR_BRDCAST (0x80000000)
81 #define MCF5272_FEC_MFLR_MLTCAST (0x40000000)
82 #define MCF5272_FEC_XWMRK_64 (0x00000000)
83 #define MCF5272_FEC_XWMRK_128 (0x00000002)
84 #define MCF5272_FEC_XWMRK_192 (0x00000003)
86 /* Define the PHY addresss. This address specifies which 32 attached */
89 //#define MCF5272_PHY_ADD (0)
90 #define MCF5272_PHY_ADD (0 << 23)
93 /* Start of frame delimter for valid MII management frame. */
95 #define MCF5272_FEC_MII_ST (0x40000000)
97 /* Operation code. This field bust be programmed to generate a valid */
98 /* MII management frame. */
100 #define MCF5272_FEC_MII_OP_READ (0x20000000)
101 #define MCF5272_FEC_MII_OP_WRITE (0x10000000)
103 /* Register address. Specifies one of the 32 attached PHY devices. */
105 #define MCF5272_FEC_MII_RA_POS (18)
106 #define MCF5272_FEC_MII_RA_MASK (0x1F)
108 /* Turn around. Must be programmed to 10 to generate a valid MII */
109 /* management frame. */
111 #define MCF5272_FEC_MII_TA (0x00020000)
114 /* The management frame data maske. Field for data to be written to */
115 /* or read from PHY register. */
117 #define MCF5272_FEC_MII_DATA_MASK (0x0000FFFF)
120 /* This define the MII unchanged MII frame management bits. */
122 #define MCF5272_FEC_MII_FIX_HDR (0 | \
123 MCF5272_FEC_MII_ST | \
128 /* The PHY address mask. */
130 #define MCF5272_FEC_MII_PA (0x1F << 23)
132 /* Define the interrupt mask. */
134 #define MCF5272_FEC_INTERRUPT_MASK (MCF5272_FEC_IMR_TXFEN | \
135 MCF5272_FEC_IMR_RXFEN )
138 /**************************************************
139 * FEC diagnostic counters
140 **************************************************/
141 typedef struct MCF5272_FEC_DIAG
144 /* We put all the receive statistics first. */
146 unsigned long rx_pk_cnt; /* The total number of */
147 /* received packets */
149 unsigned long rx_pk_cnt_sec;
151 unsigned long rx_bytes_cnt; /* The total number of */
154 unsigned long rx_bytes_cnt_sec;
156 unsigned long rx_err_cnt; /* The total number of bad */
157 /* packets received */
159 unsigned long rx_long_frm_err_cnt; /* The total number of long */
162 unsigned long rx_short_frm_err_cnt; /* The total number of short */
165 unsigned long rx_crc_err_cnt; /* The total number of CRC */
168 unsigned long rx_overrun_err_cnt; /* The total number of */
169 /* overrun errors. */
171 unsigned long rx_trunc_error_cnt; /* The total numbers of */
172 /* receieve truncated packet */
175 /* We put all the transmit statistics next. start_of_transmit */
176 /* doesn't take any space but only separates the receive statistics */
177 /* from the transmit statistics. */
179 char start_of_transmit[0];
181 unsigned long tx_pk_cnt; /* The total number of */
182 /* transmitted packet */
184 unsigned long tx_pk_cnt_sec;
186 unsigned long tx_bytes_cnt; /* The total number of */
187 /* transmitted bytes */
189 unsigned long tx_bytes_cnt_sec;
191 unsigned long tx_err_cnt; /* The total number of failed */
192 /* packet transmission */
194 unsigned long tx_def_cnt; /* The total number of tansmit */
197 unsigned long tx_hb_err_cnt; /* The total number of heart */
200 unsigned long tx_late_col_cnt; /* The total number of late */
203 unsigned long tx_exes_retry_cnt; /* Excessive rettry count. */
205 unsigned long tx_retry_cnt; /* The total number of transmit */
208 unsigned long tx_underrun_cnt; /* The total number of transmit */
211 unsigned long tx_carrrier_loss_cnt; /* The total number of */
212 /* trasnmit carrier losses. */
214 unsigned long tx_free_bd_cnt; /* The total number of freed */
215 /* buffer descriptor. */
217 unsigned long tx_free_min_bd_cnt; /* The minimum number of free */
218 /* buffer descriptor count. */
220 unsigned long tx_full_cnt; /* The number of times when */
221 /* there is no transmit buffer. */
223 unsigned long tx_not_complete_cnt; /* The number of times the */
224 /* device driver discovered */
225 /* that the BD is still in use */
228 unsigned long internal_bus_error_cnt; /* FEC bus error count. A */
229 /* bus error occurred when */
230 /* the FEC was accessing an */
233 }MCF5272_FEC_DIAG __attribute__ ((aligned, packed));
235 /* Ethernet driver status. */
236 enum eth_drv_status_t
243 /* Ethernet duplex mode. */
246 ETH_MODE_UNKNOWN = 1,
247 ETH_MODE_SIMPLEX = 2,
252 /* Ethernet speed values. */
255 ETH_SPEED_10MB = 10*1000*1000,
256 ETH_SPEED_100MB = 100*1000*1000
259 /* Ethernet driver statistics information structure. */
261 struct mcf5272_ether_drv_stats
263 struct ifreq ifreq; // tell ioctl() which interface.
265 char description[ DESC_LEN ]; // Textual description of hardware
266 unsigned char snmp_chipset[ SNMP_CHIPSET_LEN ];
267 // SNMP ID of chipset
268 enum eth_drv_mode_t duplex; // 1 = UNKNOWN, 2 = SIMPLEX, 3 = DUPLEX
269 enum eth_drv_status_t operational; // 1 = UNKNOWN, 2 = DOWN, 3 = UP
270 // These are general status information:
271 unsigned int speed; // 10,000,000 or 100,000,000
272 // to infinity and beyond?
274 MCF5272_FEC_DIAG stats;
276 }__attribute__ ((aligned, packed));
279 #define FIELD_OFFSET(type,field) (cyg_uint32)(&(((type*)0)->field)
280 #endif /* FIELD_OFFSET */
282 /* The value of 1 second in nanosecond. */
283 #define SEC_IN_NS 1000000000
285 /* 48-bit Ethernet Addresses */
286 typedef u8_t ETH_ADDR[6];
288 /* 16-bit Ethernet Frame Type, ie. Protocol */
289 typedef u16_t ETH_FTYPE;
291 /* Maximum and Minimum Ethernet Frame Size (Data Field) */
292 #define ETH_DATA_MAX_SIZE (1500)
293 #define ETH_DATA_MIN_SIZE (46)
295 /* Maximum and Minimum Ethernet Frame Size (Entire frame) */
296 #define ETH_MAX_SIZE (ETH_DATA_MAX_SIZE+14)
297 #define ETH_MIN_SIZE (ETH_DATA_MIN_SIZE+14)
299 /* Common Ethernet Frame definition */
305 u8_t data[ETH_DATA_MAX_SIZE];
307 } eth_frame_hdr __attribute__ ((aligned, packed));
309 /* 802.1Q Ethernet Frame definition */
316 u8_t data[ETH_DATA_MAX_SIZE];
318 } eth_802_1Q_frame_hdr __attribute__ ((aligned, packed));
320 /* Definition of macros that access the FEC registers */
321 #define put_reg(_addr_,_value_) \
322 *((volatile u32_t*)&(_addr_)) = (cyg_uint32)(_value_)
324 #define get_reg(_addr_) \
325 *(((volatile u32_t*)&(_addr_)))
328 #endif /* _IF_MCF5272_FEC */