1 #ifndef CYGONCE_HAL_UPD985XX_ETH_H
2 #define CYGONCE_HAL_UPD985XX_ETH_H
3 //==========================================================================
7 // Architecture specific abstractions for the on-chip ethernet
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
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41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): hmt, nickg
46 // Contributors: nickg
48 // Purpose: Define architecture abstractions
49 // Description: This file contains any extra or modified definitions for
50 // this variant of the architecture's ethernet controller.
51 // Usage: #include <cyg/io/upd985xx_eth.h>
53 //####DESCRIPTIONEND####
55 //==========================================================================
57 #include <cyg/hal/var_arch.h>
59 // --------------------------------------------------------------------------
60 // By default we use the definition of UPD985XX_SYSETH_REG( n ) from
61 // var_arch.h - if we port to a KORVA with multiple ethernet controllers we
62 // will have to vary this to account for the different base addresses.
64 // (the noise at the end of these lines is the default value)
66 // Table 5-2. MAC Control Register Map
68 #define ETH_MACC1 UPD985XX_SYSETH_REG( 0x000) // MAC configuration register 1 R/W 0000_0000H
69 #define ETH_MACC2 UPD985XX_SYSETH_REG( 0x004) // MAC configuration register 2 R/W 0000_0000H
70 #define ETH_IPGT UPD985XX_SYSETH_REG( 0x008) // Back-to-Back IPG register R/W 0000_0013H
71 #define ETH_IPGR UPD985XX_SYSETH_REG( 0x00C) // Non Back-to-Back IPG register R/W 0000_0E13H
72 #define ETH_CLRT UPD985XX_SYSETH_REG( 0x010) // Collision register R/W 0000_370FH
73 #define ETH_LMAX UPD985XX_SYSETH_REG( 0x014) // Max packet length register R/W 0000_0600H
74 // N/A UPD985XX_SYSETH_REG( 0x018) // Reserved for future use - -
75 #define ETH_RETX UPD985XX_SYSETH_REG( 0x020) // Retry count register R/W 0000_0000H
76 // N/A UPD985XX_SYSETH_REG( 0x024) // Reserved for future use - -
77 #define ETH_LSA2 UPD985XX_SYSETH_REG( 0x054) // Station Address register 2 R/W 0000_0000H
78 #define ETH_LSA1 UPD985XX_SYSETH_REG( 0x058) // Station Address register 1 R/W 0000_0000H
79 #define ETH_PTVR UPD985XX_SYSETH_REG( 0x05C) // Pause timer value read register R 0000_0000H
80 // N/A UPD985XX_SYSETH_REG( 0x060) // Reserved for future use - -
81 #define ETH_VLTP UPD985XX_SYSETH_REG( 0x064) // VLAN type register R/W 0000_0000H
82 #define ETH_MIIC UPD985XX_SYSETH_REG( 0x080) // MII configuration register R/W 0000_0000H
83 // N/A UPD985XX_SYSETH_REG( 0x084) // Reserved for future use - -
84 #define ETH_MCMD UPD985XX_SYSETH_REG( 0x094) // MII command register W 0000_0000H
85 #define ETH_MADR UPD985XX_SYSETH_REG( 0x098) // MII address register R/W 0000_0000H
86 #define ETH_MWTD UPD985XX_SYSETH_REG( 0x09C) // MII write data register R/W 0000_0000H
87 #define ETH_MRDD UPD985XX_SYSETH_REG( 0x0A0) // MII read data register R 0000_0000H
88 #define ETH_MIND UPD985XX_SYSETH_REG( 0x0A4) // MII indicator register R 0000_0000H
89 // N/A UPD985XX_SYSETH_REG( 0x0A8) // Reserved for future use - -
90 #define ETH_AFR UPD985XX_SYSETH_REG( 0x0C8) // Address Filtering register R/W 0000_0000H
91 #define ETH_HT1 UPD985XX_SYSETH_REG( 0x0CC) // Hash table register 1 R/W 0000_0000H
92 #define ETH_HT2 UPD985XX_SYSETH_REG( 0x0D0) // Hash table register 2 R/W 0000_0000H
93 // N/A UPD985XX_SYSETH_REG( 0x0D4) // Reserved for future use - -
94 #define ETH_CAR1 UPD985XX_SYSETH_REG( 0x0DC) // Carry register 1 R/W 0000_0000H
95 #define ETH_CAR2 UPD985XX_SYSETH_REG( 0x0E0) // Carry register 2 R/W 0000_0000H
96 // N/A UPD985XX_SYSETH_REG( 0x0E4) // Reserved for future use - -
97 #define ETH_CAM1 UPD985XX_SYSETH_REG( 0x130) // Carry mask register 1 R/W 0000_0000H
98 #define ETH_CAM2 UPD985XX_SYSETH_REG( 0x134) // Carry mask register 2 R/W 0000_0000H
99 // N/A UPD985XX_SYSETH_REG( 0x138) // Reserved for future use - -
101 // Table 5-3. Statistics Counter Register Map
103 #define ETH_RBYT UPD985XX_SYSETH_REG( 0x140) // Receive Byte Counter R/W
104 #define ETH_RPKT UPD985XX_SYSETH_REG( 0x144) // Receive Packet Counter R/W
105 #define ETH_RFCS UPD985XX_SYSETH_REG( 0x148) // Receive FCS Error Counter R/W
106 #define ETH_RMCA UPD985XX_SYSETH_REG( 0x14C) // Receive Multicast Packet Counter R/W
107 #define ETH_RBCA UPD985XX_SYSETH_REG( 0x150) // Receive Broadcast Packet Counter R/W
108 #define ETH_RXCF UPD985XX_SYSETH_REG( 0x154) // Receive Control Frame Packet Counter R/W
109 #define ETH_RXPF UPD985XX_SYSETH_REG( 0x158) // Receive PAUSE Frame Packet Counter R/W
110 #define ETH_RXUO UPD985XX_SYSETH_REG( 0x15C) // Receive Unknown OP code Counter R/W
111 #define ETH_RALN UPD985XX_SYSETH_REG( 0x160) // Receive Alignment Error Counter R/W
112 #define ETH_RFLR UPD985XX_SYSETH_REG( 0x164) // Receive Frame Length Out of Range Counter R/W
113 #define ETH_RCDE UPD985XX_SYSETH_REG( 0x168) // Receive Code Error Counter R/W
114 #define ETH_RFCR UPD985XX_SYSETH_REG( 0x16C) // Receive False Carrier Counter R/W
115 #define ETH_RUND UPD985XX_SYSETH_REG( 0x170) // Receive Undersize Packet Counter R/W
116 #define ETH_ROVR UPD985XX_SYSETH_REG( 0x174) // Receive Oversize Packet Counter R/W
117 #define ETH_RFRG UPD985XX_SYSETH_REG( 0x178) // Receive Error Undersize Packet Counter R/W
118 #define ETH_RJBR UPD985XX_SYSETH_REG( 0x17C) // Receive Error Oversize Packet Counter R/W
119 #define ETH_R64 UPD985XX_SYSETH_REG( 0x180) // Receive 64 Byte Frame Counter R/W
120 #define ETH_R127 UPD985XX_SYSETH_REG( 0x184) // Receive 65 to 127 Byte Frame Counter R/W
121 #define ETH_R255 UPD985XX_SYSETH_REG( 0x188) // Receive 128 to 255 Byte Frame Counter R/W
122 #define ETH_R511 UPD985XX_SYSETH_REG( 0x18C) // Receive 256 to 511 Byte Frame Counter R/W
123 #define ETH_R1K UPD985XX_SYSETH_REG( 0x190) // Receive 512 to 1023 Byte Frame Counter R/W
124 #define ETH_RMAX UPD985XX_SYSETH_REG( 0x194) // Receive Over 1023 Byte Frame Counter R/W
125 #define ETH_RVBT UPD985XX_SYSETH_REG( 0x198) // Receive Valid Byte Counter R/W
126 #define ETH_TBYT UPD985XX_SYSETH_REG( 0x1C0) // Transmit Byte Counter R/W
127 #define ETH_TPCT UPD985XX_SYSETH_REG( 0x1C4) // Transmit Packet Counter R/W
128 #define ETH_TFCS UPD985XX_SYSETH_REG( 0x1C8) // Transmit CRC Error Packet Counter R/W
129 #define ETH_TMCA UPD985XX_SYSETH_REG( 0x1CC) // Transmit Multicast Packet Counter R/W
130 #define ETH_TBCA UPD985XX_SYSETH_REG( 0x1D0) // Transmit Broadcast Packet Counter R/W
131 #define ETH_TUCA UPD985XX_SYSETH_REG( 0x1D4) // Transmit Unicast Packet Counter R/W
132 #define ETH_TXPF UPD985XX_SYSETH_REG( 0x1D8) // Transmit PAUSE control Frame Counter R/W
133 #define ETH_TDFR UPD985XX_SYSETH_REG( 0x1DC) // Transmit Single Deferral Packet Counter R/W
134 #define ETH_TXDF UPD985XX_SYSETH_REG( 0x1E0) // Transmit Excessive Deferral Packet Counter R/W
135 #define ETH_TSCL UPD985XX_SYSETH_REG( 0x1E4) // Transmit Single Collision Packet Counter R/W
136 #define ETH_TMCL UPD985XX_SYSETH_REG( 0x1E8) // Transmit Multiple collision Packet Counter R/W
137 #define ETH_TLCL UPD985XX_SYSETH_REG( 0x1EC) // Transmit Late Collision Packet Counter R/W
138 #define ETH_TXCL UPD985XX_SYSETH_REG( 0x1F0) // Transmit Excessive Collision Packet Counter R/W
139 #define ETH_TNCL UPD985XX_SYSETH_REG( 0x1F4) // Transmit Total Collision Counter R/W
140 #define ETH_TCSE UPD985XX_SYSETH_REG( 0x1F8) // Transmit Carrier Sense Error Counter R/W
141 #define ETH_TIME UPD985XX_SYSETH_REG( 0x1FC) // Transmit Internal MAC Error Counter R/W
143 // Table 5-4. DMA and FIFO Management Registers Map
145 #define ETH_TXCR UPD985XX_SYSETH_REG( 0x200) // Transmit Configuration Register R/W 0000_0000H
146 #define ETH_TXFCR UPD985XX_SYSETH_REG( 0x204) // Transmit FIFO Control Register R/W FFFF_40C0H
147 #define ETH_TXDTR UPD985XX_SYSETH_REG( 0x208) // Transmit Data Register W 0000_0000H
148 #define ETH_TXSR UPD985XX_SYSETH_REG( 0x20C) // Transmit Status Register R 0000_0000H
149 // N/A UPD985XX_SYSETH_REG( 0x210) // Reserved for future use - -
150 #define ETH_TXDPR UPD985XX_SYSETH_REG( 0x214) // Transmit Descriptor Pointer R/W 0000_0000H
151 #define ETH_RXCR UPD985XX_SYSETH_REG( 0x218) // Receive Configuration Register R/W 0000_0000H
152 #define ETH_RXFCR UPD985XX_SYSETH_REG( 0x21C) // Receive FIFO Control Register R/W C040_0040H
153 #define ETH_RXDTR UPD985XX_SYSETH_REG( 0x220) // Receive Data Register R 0000_0000H
154 #define ETH_RXSR UPD985XX_SYSETH_REG( 0x224) // Receive Status Register R 0000_0000H
155 // N/A UPD985XX_SYSETH_REG( 0x228) // Reserved for future use - -
156 #define ETH_RXDPR UPD985XX_SYSETH_REG( 0x22C) // Receive Descriptor Pointer R/W 0000_0000H
157 #define ETH_RXPDR UPD985XX_SYSETH_REG( 0x230) // Receive Pool Descriptor Register R/W 0000_0000H
159 // Table 5-5. Interrupt and Configuration Registers Map
161 #define ETH_CCR UPD985XX_SYSETH_REG( 0x234) // Configuration Register R/W 0000_0000H
162 #define ETH_ISR UPD985XX_SYSETH_REG( 0x238) // Interrupt Service Register R 0000_0000H
163 #define ETH_MSR UPD985XX_SYSETH_REG( 0x23C) // Mask Serves Register R/W 0000_0000H
165 // --------------------------------------------------------------------------
166 // Now the fields within all those registers...
168 // Table 5-2. MAC Control Register Map
170 // ETH_MACC1 0x000 MAC configuration register 1 R/W 0000_0000H
171 #define ETH_MACC1_MACLB (1<<14) // MAC loopback: 0
172 #define ETH_MACC1_TXFC (1<<11) // Transmit flow control enable: 0
173 #define ETH_MACC1_RXFC (1<<10) // Receive flow control enable: 0
174 #define ETH_MACC1_SRXEN (1<< 9) // Receive enable: 0
175 #define ETH_MACC1_PARF (1<< 8) // Control packet pass: 0
176 #define ETH_MACC1_PUREP (1<< 7) // Pure preamble: 0
177 #define ETH_MACC1_FLCHT (1<< 6) // Length field check: 0
178 #define ETH_MACC1_NOBO (1<< 5) // No Back Off: 0
179 #define ETH_MACC1_CRCEN (1<< 3) // CRC append enable: 0
180 #define ETH_MACC1_PADEN (1<< 2) // PAD append enable: 0
181 #define ETH_MACC1_FDX (1<< 1) // Full duplex enable: 0
182 #define ETH_MACC1_HUGEN (1<< 0) // Large packet enable: 0
183 // ETH_MACC2 0x004 MAC configuration register 2 R/W 0000_0000H
184 #define ETH_MACC2_MCRST (1<<10) // MAC Control Block software reset: 0
185 #define ETH_MACC2_RFRST (1<< 9) // Receive Function Block software reset: 0
186 #define ETH_MACC2_TFRST (1<< 8) // Transmit Function Block software reset: 0
187 #define ETH_MACC2_BPNB (1<< 6) // Back Pressure No Back Off: 0
188 #define ETH_MACC2_APD (1<< 5) // Auto VLAN PAD: 0
189 #define ETH_MACC2_VPD (1<< 4) // VLAN PAD mode: 0
191 // ETH_IPGT 0x008 Back-to-Back IPG register R/W 0000_0013H
192 // ETH_IPGR 0x00C Non Back-to-Back IPG register R/W 0000_0E13H
193 // ETH_CLRT 0x010 Collision register R/W 0000_370FH
194 // ETH_LMAX 0x014 Max packet length register R/W 0000_0600H
195 // N/A 0x018 Reserved for future use - -
196 // ETH_RETX 0x020 Retry count register R/W 0000_0000H
197 // N/A 0x024 Reserved for future use - -
198 // ETH_LSA2 0x054 Station Address register 2 R/W 0000_0000H
199 // ETH_LSA1 0x058 Station Address register 1 R/W 0000_0000H
200 // ETH_PTVR 0x05C Pause timer value read register R 0000_0000H
201 // N/A 0x060 Reserved for future use - -
202 // ETH_VLTP 0x064 VLAN type register R/W 0000_0000H
203 #define ETH_VLTP_VLTP (0x00008100) // magic number from example
204 // ETH_MIIC 0x080 MII configuration register R/W 0000_0000H
205 #define ETH_MIIC_MIRST (1<<15) // MII Management Interface Block software reset
206 #define ETH_MIIC_CLKS (0x0C) // 3:2 CLKS Select frequency range:
207 #define ETH_MIIC_25 (0x00) // 00: HCLK is equal to 25 MHz
208 #define ETH_MIIC_33 (0x04) // 01: HCLK is less than or equal to 33 MHz
209 #define ETH_MIIC_50 (0x08) // 10: HCLK is less than or equal to 50 MHz
210 #define ETH_MIIC_66 (0x0C) // 11: HCLK is less than or equal to 66 MHz
211 // ETH_MCMD 0x094 MII command register W 0000_0000H
212 #define ETH_MCMD_SCANC (1<< 1) // SCAN command: 0
213 #define ETH_MCMD_RSTAT (1<< 0) // MII management read: 0
214 // ETH_MADR 0x098 MII address register R/W 0000_0000H
215 #define ETH_MADR_PHY_ADDR_SHIFT (8)
216 // ETH_MWTD 0x09C MII write data register R/W 0000_0000H
217 // ETH_MRDD 0x0A0 MII read data register R 0000_0000H
218 // ETH_MIND 0x0A4 MII indicator register R 0000_0000H
219 #define ETH_MIND_NVALID (1<< 2) // SCAN command start status: 0
220 #define ETH_MIND_SCANA (1<< 1) // SCAN command active: 0
221 #define ETH_MIND_BUSY (1<< 0) // BUSY: 0
222 // ETH_AFR 0x0C8 Address Filtering register R/W 0000_0000H
223 #define ETH_AFR_PRO (1<< 3) // Promiscuous mode: 0
224 #define ETH_AFR_PRM (1<< 2) // Accept Multicast: 0
225 #define ETH_AFR_AMC (1<< 1) // Accept Multicast ( qualified ): 0
226 #define ETH_AFR_ABC (1<< 0) // Accept Broadcast: 0
227 // ETH_HT1 0x0CC Hash table register 1 R/W 0000_0000H
228 // ETH_HT2 0x0D0 Hash table register 2 R/W 0000_0000H
229 // ETH_CAR1 0x0DC Carry register 1 R/W 0000_0000H
230 // ETH_CAR2 0x0E0 Carry register 2 R/W 0000_0000H
231 // ETH_CAM1 0x130 Carry mask register 1 R/W 0000_0000H
232 // ETH_CAM2 0x134 Carry mask register 2 R/W 0000_0000H
234 // Table 5-3. Statistics Counter Register Map
237 // Table 5-4. DMA and FIFO Management Registers Map
239 // ETH_TXCR 0x200 Transmit Configuration Register R/W 0000_0000H
240 #define ETH_TXCR_TXE (1<<31) // Transmit Enable:
241 #define ETH_TXCR_DTBS_SHIFT (16) // 18:16 DMA Transmit Burst Size:
242 #define ETH_TXCR_DTBS (0x70000) // 18:16 DMA Transmit Burst Size:
243 #define ETH_TXCR_DTBS_1 (0x00000) // 000: 1 Word (4 bytes)
244 #define ETH_TXCR_DTBS_2 (0x10000) // 001: 2 Word (8 bytes)
245 #define ETH_TXCR_DTBS_4 (0x20000) // 010: 4 Word (16 bytes)
246 #define ETH_TXCR_DTBS_8 (0x30000) // 011: 8 Word (32 bytes)
247 #define ETH_TXCR_DTBS_16 (0x40000) // 100: 16 Word (64 bytes)
248 #define ETH_TXCR_DTBS_32 (0x50000) // 101: 32 Word (128 bytes)
249 #define ETH_TXCR_DTBS_64 (0x60000) // 110: 64 Word (256 bytes)
250 #define ETH_TXCR_AFCE (1<< 0) // Auto Flow Control Enable:
251 // ETH_TXFCR 0x204 Transmit FIFO Control Register R/W FFFF_40C0H
252 #define ETH_TXFCR_TPTV_SHIFT (16) // 31:16 Transmit Pause Timer Value: FFFFH
253 #define ETH_TXFCR_TPTV (0xffff0000) // 31:16 Transmit Pause Timer Value: FFFFH
254 #define ETH_TXFCR_TX_DRTH_SHIFT (10) // 15:10 Transmit Drain Threshold Level: 10H
255 #define ETH_TXFCR_TX_DRTH (0x0000fc00) // 15:10 Transmit Drain Threshold Level: 10H
256 #define ETH_TXFCR_TX_FLTH_SHIFT (2) // 7:2 Transmit Fill Threshold Level: 03H
257 #define ETH_TXFCR_TX_FLTH (0x000000fc) // 7:2 Transmit Fill Threshold Level: 03H
258 #define ETH_TXFCR_TPTV_DEFAULT (0x10000000) // default 0x1000 slot time (1slot:512bit)
259 #define ETH_TXFCR_TX_DRTH_DEFAULT (0x00002000) // 001000b (8long, 32byte)
260 #define ETH_TXFCR_TX_FLTH_DEFAULT (0x000000c0) // default 110000b (48word, 192byte)
261 // ETH_TXDTR 0x208 Transmit Data Register W 0000_0000H
262 // ETH_TXSR 0x20C Transmit Status Register R 0000_0000H
263 #define ETH_TXSR_CSE (1<<31) // Carrier lost was detected during the transmission 0
264 #define ETH_TXSR_TBP (1<<30) // Back pressure occurred when the packet was received 0
265 #define ETH_TXSR_TPP (1<<29) // A packet request during the PAUSE operation was transmitted 0
266 #define ETH_TXSR_TPCF (1<<28) // A PAUSE control frame was transmitted 0
267 #define ETH_TXSR_TCFR (1<<27) // A control frame was transmitted 0
268 #define ETH_TXSR_TUDR (1<<26) // The TPUR pin was set high and aborted. Note 2 0
269 #define ETH_TXSR_TGNT (1<<25) // A huge packet was transmitted and aborted. 0
270 #define ETH_TXSR_LCOL (1<<24) // Collision occurred
271 #define ETH_TXSR_ECOL (1<<23) // Excess collisions
272 #define ETH_TXSR_TEDFR (1<<22) // Excess deferred
273 #define ETH_TXSR_TDFR (1<<21) // Transmission deferral occurred
274 #define ETH_TXSR_TBRO (1<<20) // A broadcast packet was transmitted. 0
275 #define ETH_TXSR_TMUL (1<<19) // A multicast packet was transmitted. 0
276 #define ETH_TXSR_TDONE (1<<18) // Transmission was completed. 0
277 #define ETH_TXSR_TFLOR (1<<17) // Value of the length field was huge
278 #define ETH_TXSR_TFLER (1<<16) // Value of the length field didn~t match the actual data count
279 #define ETH_TXSR_TCRCE (1<<15) // Attached CRC didn~t match the internal generated CRC
281 #define ETH_TXSR_TCBC_SHIFT (11) // 14:11 collisions for the previous transmission
282 #define ETH_TXSR_TCBC (0x7800) // 14:11 collisions for the previous transmission
283 #define ETH_TXSR_TBYT_SHIFT (0) // 10:0 transmitted bytes not including collided bytes
284 #define ETH_TXSR_TBYT (0x07FF) // 10:0 transmitted bytes not including collided bytes
286 // ETH_RXCR UPD985XX_SYSETH_REG( 0x218) // Receive Configuration Register R/W 0000_0000H
287 #define ETH_RXCR_RXE (1<<31) // Receive Enable:
288 #define ETH_RXCR_DRBS_SHIFT (16) // 18:16 DRBS DMA Transmit Burst Size: 0
289 #define ETH_RXCR_DRBS (0x70000) //
290 #define ETH_RXCR_DRBS_1 (0x00000) // 000: 1 Word (4 bytes)
291 #define ETH_RXCR_DRBS_2 (0x10000) // 001: 2 Word (8 bytes)
292 #define ETH_RXCR_DRBS_4 (0x20000) // 010: 4 Word (16 bytes)
293 #define ETH_RXCR_DRBS_8 (0x30000) // 011: 8 Word (32 bytes)
294 #define ETH_RXCR_DRBS_16 (0x40000) // 100: 16 Word (64 bytes)
295 #define ETH_RXCR_DRBS_32 (0x50000) // 101: 32 Word (128 bytes)
296 #define ETH_RXCR_DRBS_64 (0x60000) // 110: 64 Word (256 bytes)
298 // ETH_RXFCR 0x21C Receive FIFO Control Register R/W C040_0040H
299 #define ETH_RXFCR_UWM (0xfc000000) // 31:26 Upper Water Mark: 30H
300 #define ETH_RXFCR_UWM_SHIFT (26) // 31:26 Upper Water Mark: 30H
301 #define ETH_RXFCR_LWM (0x00fc0000) // 23:18 Lower Water Mark: 10H
302 #define ETH_RXFCR_LWM_SHIFT (18) // 23:18 Lower Water Mark: 10H
303 #define ETH_RXFCR_RX_DRTH (0x000000fc) // 7: 2 Receive Drain Threshold Level 10H
304 #define ETH_RXFCR_RX_DRTH_SHIFT (2) // 7: 2 Receive Drain Threshold Level 10H
305 #define ETH_RXFCR_UWM_DEFAULT (0xE0000000) // default 110000b ( 48word, 192byte )
306 #define ETH_RXFCR_LWM_DEFAULT (0x00400000) // default 010000b (16word, 64byte)
307 #define ETH_RXFCR_DRTH16W (0x00000040) // default 010000b (16word, 64byte)
309 // ETH_RXDTR 0x220 Receive Data Register R 0000_0000H
310 // ETH_RXSR 0x224 Receive Status Register R 0000_0000H
311 #define ETH_RXSR_RLENE (1<<31) // A toosmall or toolarge packet was received.
312 #define ETH_RXSR_VLAN (1<<30) // A VLAN was received.
313 #define ETH_RXSR_USOP (1<<29) // A control frame containing an unknown OP code was received.
314 #define ETH_RXSR_PRCF (1<<28) // A control frame containing the PAUSE OP code was received.
315 #define ETH_RXSR_RCFR (1<<27) // A control frame was received.
316 #define ETH_RXSR_DBNB (1<<26) // An alignment error occurred.
317 #define ETH_RXSR_RBRO (1<<25) // A broadcast packet was received. 0
318 #define ETH_RXSR_RMUL (1<<24) // A multicast packet was received. 0
319 #define ETH_RXSR_RXOK (1<<23) // A good packet was received.
320 #define ETH_RXSR_RLOR (1<<22) // The value of the length field was huge
321 #define ETH_RXSR_RLER (1<<21) // The value of the length field didn~t match
322 #define ETH_RXSR_RCRCE (1<<20) // A CRC error occurred. 0
323 #define ETH_RXSR_RCV (1<<19) // RXER was detected. 0
324 #define ETH_RXSR_CEPS (1<<18) // A False Carrier was detected. 0
325 #define ETH_RXSR_REPS (1<<17) // A packet which had a preamble and SFD only or one data nibble
326 #define ETH_RXSR_PAIG (1<<16) //
327 #define ETH_RXSR_RBYT (0xffff) // 15:0 The received byte count 0
328 #define ETH_RXSR_RBYT_SHIFT (0) // 15:0 The received byte count 0
329 // ETH_RXDPR 0x22C Receive Descriptor Register R/W 0000_0000H
330 // ETH_RXPDR 0x230 Receive Pool Descriptor Register R/W 0000_0000H
331 #define ETH_RXPDR_AL (0x70000000) // 30:28 AL[2:0] Alert Level 0H
332 #define ETH_RXPDR_AL_SHIFT (28)
333 #define ETH_RXPDR_RNOD (0xffff) // 15:0 Remaining Number of Descriptor 0H
334 #define ETH_RXPDR_RNOD_SHIFT (0)
336 // Table 5-5. Interrupt and Configuration Registers Map
338 // ETH_CCR 0x234 Configuration Register R/W 0000_0000H
339 #define ETH_CCR_SRT (1) // Software Reset (cleared automatically to '0')
340 // ETH_ISR 0x238 Interrupt Service Register R 0000_0000H
341 #define ETH_ISR_XMTDN (1<<15) // Transmit Done
342 #define ETH_ISR_TBDR (1<<14) // Transmit Buffer Descriptor Request at Null
343 #define ETH_ISR_TFLE (1<<13) // Transmit Frame Length Exceed
344 #define ETH_ISR_UR (1<<12) // Underrun
345 #define ETH_ISR_TABR (1<<11) // Transmit Aborted
346 #define ETH_ISR_TCFRI (1<<10) // Control Frame Transmit
347 #define ETH_ISR_RCVDN (1<<7 ) // Receive Done
348 #define ETH_ISR_RBDRS (1<<6 ) // Receive Buffer Descriptor Request at alert level
349 #define ETH_ISR_RBDRU (1<<5 ) // Receive Buffer Descriptor Request at zero
350 #define ETH_ISR_OF (1<<4 ) // Overflow
351 #define ETH_ISR_LFAL (1<<3 ) // Link Failed
352 #define ETH_ISR_CARRY (1<<0 ) // Carry Flag:
353 // ETH_MSR 0x23C Mask Serves Register R/W 0000_0000H
356 // --------------------------------------------------------------------------
357 // And the "buffer descriptor" control structures in RAM...
360 #define ETH_BUF_LAST (1<<31) // Last Descriptor
361 #define ETH_BUF_D_L (1<<30) // Data Buffer / Link Pointer
362 #define ETH_BUF_D_L_DATA (1<<30) // Data Buffer / Link Pointer
363 #define ETH_BUF_D_L_LINK (0<<30) // Data Buffer / Link Pointer
364 #define ETH_BUF_OWN (1<<29) // Owner 1:Ethernet Controller 0: VR4120A
365 #define ETH_BUF_OWN_ETH (1<<29)
366 #define ETH_BUF_OWN_CPU (0<<29)
368 #define ETH_BUF_DBRWE (1<<28) // Buffer Access Error
369 #define ETH_BUF_OK (1<<16) // Tx or Rx OK
370 #define ETH_BUF_SIZE (0xffff) // Byte Count
372 #define ETH_BUF_TX_TUDR (1<<27) // Transmit Underrun Error
373 #define ETH_BUF_TX_CSE (1<<26) // Carrier Sense Lost Error
374 #define ETH_BUF_TX_LCOL (1<<25) // Late Collision
375 #define ETH_BUF_TX_ECOL (1<<24) // Excessive Collision
376 #define ETH_BUF_TX_EDFR (1<<23) // Excessive Deferral
377 #define ETH_BUF_TX_TGNT (1<<18) // Transmit Giant Frame
378 #define ETH_BUF_TX_HBF (1<<17) // Heart Beat Fail for ENDEC mode
380 #define ETH_BUF_RX_OVRN (1<<24) // Overrun Error
381 #define ETH_BUF_RX_RUNT (1<<23) // Runt packet
382 #define ETH_BUF_RX_FRGE (1<<22) // Fragment Error
383 #define ETH_BUF_RX_RCV (1<<21) // Detects RXER
384 #define ETH_BUF_RX_FC (1<<20) // False Carrier
385 #define ETH_BUF_RX_CRCE (1<<19) // CRC Error
386 #define ETH_BUF_RX_FAE (1<<18) // Frame Alignment Error
387 #define ETH_BUF_RX_RFLE (1<<17) // Receive Frame Length Error
389 #define ETH_BUF_RX_FTYP (0x0e000000) // 27:25 Frame Type[2:0]
390 #define ETH_BUF_RX_FTYP_SHIFT (25) // 27:25 Frame Type[2:0]
391 // I don't think we need to know these...
392 // 000 Broadcast Frame
393 // 001 Multicast Frame
396 // 100 PAUSE control frame
397 // 101 Control Frame (except pause)
398 // 11x Reserved for future use
401 // --------------------------------------------------------------------------
402 // MII stuff for talking to the separate PHY
403 // Initially this was a SEEQ NQ80225 but now it is a LU3X31T-T64.
405 //#define SEEQ_DEVICE_PHYS_ADDRESS (1) // this from the board documentation
406 #define LU3X31T_DEVICE_PHYS_ADDRESS (2)
408 #define ETH_MADR_PHY_DEVICE_PHYS_ADDRESS \
409 (LU3X31T_DEVICE_PHYS_ADDRESS << ETH_MADR_PHY_ADDR_SHIFT)
411 // I don't know how much they have in common, but I think MII is pretty
412 // standard, and the "mandated" registers ought to be common.
414 #define PHY_CONTROL_REG (0)
415 #define PHY_STATUS_REG (1)
416 #define PHY_ID_ONE (2)
417 #define PHY_ID_TWO (3)
418 #define PHY_AUTONEG_ADVERT (4)
419 #define PHY_AUTONEG_REMOTE (5)
420 #define PHY_STATUS_DETECT_REG (18)
422 #define PHY_CONTROL_RESET (1<<15)
423 #define PHY_CONTROL_LOOPBACK (1<<14)
424 #define PHY_CONTROL_SPEED100 (1<<13)
425 #define PHY_CONTROL_AUTONEG_EN (1<<12)
426 #define PHY_CONTROL_POWERDOWN (1<<11)
427 #define PHY_CONTROL_MII_DIS (1<<10)
428 #define PHY_CONTROL_AUTONEG_RST (1<< 9)
429 #define PHY_CONTROL_DPLX_FULL (1<< 8)
430 #define PHY_CONTROL_COLLTEST (1<< 7)
432 #define PHY_STATUS_CAP_T4 (1<<15)
433 #define PHY_STATUS_CAP_100TXF (1<<14)
434 #define PHY_STATUS_CAP_100TXH (1<<13)
435 #define PHY_STATUS_CAP_10TF (1<<12)
436 #define PHY_STATUS_CAP_10TH (1<<11)
437 #define PHY_STATUS_CAP_SUPR (1<< 6)
438 #define PHY_STATUS_AUTONEG_ACK (1<< 5)
439 #define PHY_STATUS_REMOTEFAULT (1<< 4)
440 #define PHY_STATUS_CAP_AUTONEG (1<< 3)
441 #define PHY_STATUS_LINK_OK (1<< 2)
442 #define PHY_STATUS_JABBER (1<< 1)
443 #define PHY_STATUS_EXTREGS (1<< 0)
445 // These are the same for both AUTONEG registers
446 #define PHY_AUTONEG_NEXT (1<<15)
447 #define PHY_AUTONEG_ACK (1<<14)
448 #define PHY_AUTONEG_REMOTEFAULT (1<<13)
449 #define PHY_AUTONEG_100BASET4 (1<< 9)
450 #define PHY_AUTONEG_100BASETX_FDX (1<< 8)
451 #define PHY_AUTONEG_100BASETX_HDX (1<< 7)
452 #define PHY_AUTONEG_10BASET_FDX (1<< 6)
453 #define PHY_AUTONEG_10BASET_HDX (1<< 5)
454 #define PHY_AUTONEG_CSMA_802_3 (1<< 0)
457 // Others are undocumented
458 #define PHY_STATUS_DETECT_SPEED100 (1<< 7)
459 #define PHY_STATUS_DETECT_DPLX_FULL (1<< 6)
463 // --------------------------------------------------------------------------
464 #endif // CYGONCE_HAL_UPD985XX_ETH_H
465 // End of upd985xx_eth.h
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