1 //==========================================================================
5 // Ethernet transceiver (PHY) support
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 2003 Gary Thomas
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 // or inline functions from this file, or you compile this file and link it
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30 // License. However the source code for this file must still be made available
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): John Eigelaar
44 // Contributors: Gary Thomas
47 // Description: Support for Davicom DM9161A PHY
50 //####DESCRIPTIONEND####
52 //==========================================================================
54 #include <pkgconf/system.h>
55 #include <pkgconf/devs_eth_phy.h>
57 #include <cyg/infra/cyg_type.h>
59 #include <cyg/hal/hal_arch.h>
60 #include <cyg/hal/drv_api.h>
61 #include <cyg/hal/hal_if.h>
62 #include <cyg/hal/hal_tables.h>
64 #include <cyg/io/eth_phy.h>
65 #include <cyg/io/eth_phy_dev.h>
67 #define DM9161A_BMSR 0x01
68 #define DM9161A_BMSR_ANEG_COMP (1<<5)
69 #define DM9161A_BMSR_LINK (1<<2)
71 #define DM9161A_BMCR 0x00
73 #define DM9161A_DSCSR 17
74 #define DM9161A_DSCSR_100FDX (1<<15)
75 #define DM9161A_DSCSR_100HDX (1<<14)
76 #define DM9161A_DSCSR_10FDX (1<<13)
77 #define DM9161A_DSCSR_10HDX (1<<12)
79 static bool dm9161a_stat(eth_phy_access_t *f, int *state)
81 unsigned short phy_state;
85 // Read negotiated state
87 if (_eth_phy_read(f, DM9161A_BMSR, f->phy_addr, &phy_state))
89 if ((phy_state & DM9161A_BMSR_ANEG_COMP) == 0)
91 eth_phy_printf("... waiting for auto-negotiation");
92 for (tries = 0; tries < CYGINT_DEVS_ETH_PHY_AUTO_NEGOTIATION_TIME;
95 if (_eth_phy_read(f, DM9161A_BMSR, f->phy_addr, &phy_state))
97 if ((phy_state & DM9161A_BMSR_ANEG_COMP) != 0)
102 CYGACC_CALL_IF_DELAY_US(1000000); // 1 second
105 eth_phy_printf("\n");
107 if ((phy_state & DM9161A_BMSR_ANEG_COMP) != 0)
110 if (!_eth_phy_read(f, DM9161A_DSCSR, f->phy_addr, &phy_state))
113 if (phy_state & 0xF000)
115 *state |= ETH_PHY_STAT_LINK;
117 if ((phy_state & DM9161A_DSCSR_100FDX) ||
118 (phy_state & DM9161A_DSCSR_100HDX))
120 *state |= ETH_PHY_STAT_100MB;
122 if ((phy_state & DM9161A_DSCSR_100FDX) ||
123 (phy_state & DM9161A_DSCSR_10FDX))
125 *state |= ETH_PHY_STAT_FDX;
134 _eth_phy_dev("Davicom DM9161A", 0x0181B8A0, dm9161a_stat)