1 //==========================================================================
5 // RealTek 8139 ethernet driver
7 //==========================================================================
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39 //####ECOSGPLCOPYRIGHTEND####
40 //####BSDCOPYRIGHTBEGIN####
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50 //####BSDCOPYRIGHTEND####
51 //==========================================================================
52 //#####DESCRIPTIONBEGIN####
54 // Author(s): Eric Doenges
55 // Contributors: Chris Nimmers, Gary Thomas, Andy Dyer
58 // Description: hardware driver for RealTek 8139 ethernet
59 // Notes: This is a very basic driver that will send and receive
60 // packets and not much else. A lot of features of the 8139
61 // are not supported (power management, MII interface,
62 // access to the serial eeprom, 'twister tuning', etc.).
64 // Many of the configuration options (like media type and
65 // speed) the 8139 has are taken directly from the serial
66 // eeprom and are not currently configurable from this driver.
68 // I've tentatively added some code to handle cache coherency
69 // issues for platforms that do not have a separate address
70 // space for uncached memory access and do not do cache
71 // snooping for PCI bus masters. This code can be activated by
72 // defining CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
73 // in the platform specific .inl file. Note that if
74 // CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY is
75 // defined, the .inl file is also responsible for making sure
76 // the receive and transmit buffers are located in memory in
77 // such a way that flushing or invalidating cache lines for
78 // these buffers will not affect any other buffers. See the
79 // README in the doc directory for some suggestions on how
82 // Since the official data sheet for this chip is a bit
83 // vague, I had to look at the Linux and OpenBSD drivers to
84 // understand the basic workings of the chip; however, I have
85 // not copied any code from those drivers to avoid tainting
90 //####DESCRIPTIONEND####
92 //==========================================================================
93 #include <pkgconf/system.h>
94 #ifdef CYGPKG_IO_ETH_DRIVERS
95 #include <pkgconf/io_eth_drivers.h>
97 #include <pkgconf/devs_eth_rltk_8139.h>
99 #include <cyg/infra/cyg_type.h>
100 #include <cyg/infra/cyg_ass.h>
101 #include <cyg/infra/diag.h>
102 #include <cyg/hal/hal_arch.h>
103 #include <cyg/hal/drv_api.h>
104 #include <cyg/hal/hal_cache.h>
105 #include <cyg/io/eth/netdev.h>
106 #include <cyg/io/eth/eth_drv.h>
108 #include <string.h> /* for memset */
111 #include <cyg/io/pci.h>
113 #error "This driver requires the PCI package (CYGPKG_IO_PCI)"
116 #include <cyg/io/pci.h>
118 /* Necessary for memory mapping macros */
119 #include CYGHWR_MEMORY_LAYOUT_H
121 /* Check if we should be dumping debug information or not */
122 #if defined CYGDBG_DEVS_ETH_RLTK_8139_CHATTER \
123 && (CYGDBG_DEVS_ETH_RLTK_8139_CHATTER > 0)
124 #define DEBUG_RLTK8139_DRIVER
129 /* Which interrupts we will handle */
130 #define RLTK8139_IRQ (IR_SERR|IR_FOVW|IR_RXOVW|IR_TER|IR_TOK|IR_RER|IR_ROK)
132 /* Allow platform-specific configuration of the driver */
133 #ifndef CYGDAT_DEVS_ETH_RLTK_8139_INL
134 #error "CYGDAT_DEVS_ETH_RLTK_8139_INL not defined"
136 #include CYGDAT_DEVS_ETH_RLTK_8139_INL
139 #ifndef CYGHWR_RLTK_8139_PLF_INIT
140 #define CYGHWR_RLTK_8139_PLF_INIT(sc) do {} while(0)
144 * If software cache coherency is required, the HAL_DCACHE_INVALIDATE
145 * hal macro must be defined as well.
147 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
148 #if !defined HAL_DCACHE_INVALIDATE || !defined HAL_DCACHE_FLUSH
149 #error "HAL_DCACHE_INVALIDATE/HAL_DCACHE_FLUSH not defined for this platform but CYGPKG_DEVS_ETH_RLTK_8139_CACHE_COHERENCY was defined."
153 /* Local driver function declarations */
154 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
155 static cyg_uint32 rltk8139_isr(cyg_vector_t vector, cyg_addrword_t data);
158 #ifdef ETH_DRV_SET_MC_LIST
159 static cyg_uint32 ether_crc(cyg_uint8 *data, int length);
160 static void rltk8139_set_multicast_list(Rltk8139_t *rltk8139_info,
161 struct eth_drv_mc_list *mc_list);
164 static void rltk8139_reset(struct eth_drv_sc *sc);
165 static bool rltk8139_init(struct cyg_netdevtab_entry *tab);
166 static void rltk8139_start(struct eth_drv_sc *sc, unsigned char *enaddr,
168 static void rltk8139_stop(struct eth_drv_sc *sc);
169 static int rltk8139_control(struct eth_drv_sc *sc, unsigned long key,
170 void *data, int data_length);
171 static int rltk8139_can_send(struct eth_drv_sc *sc);
172 static void rltk8139_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
173 int sg_len, int total_len, unsigned long key);
174 static void rltk8139_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
176 static void rltk8139_deliver(struct eth_drv_sc *sc);
177 static void rltk8139_poll(struct eth_drv_sc *sc);
178 static int rltk8139_int_vector(struct eth_drv_sc *sc);
180 #ifdef DEBUG_RLTK8139_DRIVER
181 void rltk8139_print_state(struct eth_drv_sc *sc);
185 * Define inline functions to access the card. This will also handle
186 * endianess issues in one place. This code was lifted from the eCos
189 #if (CYG_BYTEORDER == CYG_MSBFIRST)
190 #define HAL_CTOLE32(x) ((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | (((x) >> 24) & 0xff))
191 #define HAL_LE32TOC(x) ((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | (((x) >> 24) & 0xff))
193 #define HAL_CTOLE16(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
194 #define HAL_LE16TOC(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
197 OUTB(cyg_uint8 value,
198 cyg_uint32 io_address)
200 HAL_WRITE_UINT8( io_address, value);
204 OUTW(cyg_uint16 value, cyg_uint32 io_address)
206 HAL_WRITE_UINT16(io_address,
207 (((value & 0xff) << 8) | ((value & 0xff00) >> 8)) );
211 OUTL(cyg_uint32 value, cyg_uint32 io_address)
213 HAL_WRITE_UINT32(io_address,
214 ((((value) & 0xff) << 24) | (((value) & 0xff00) << 8)
215 | (((value) & 0xff0000) >> 8)
216 | (((value) >> 24) & 0xff)) );
219 static inline cyg_uint8
220 INB(cyg_uint32 io_address)
223 HAL_READ_UINT8(io_address, d);
227 static inline cyg_uint16
228 INW(cyg_uint32 io_address)
231 HAL_READ_UINT16( io_address, d );
232 return (((d & 0xff) << 8) | ((d & 0xff00) >> 8));
235 static inline cyg_uint32
236 INL(cyg_uint32 io_address)
239 HAL_READ_UINT32(io_address, d);
240 return ((((d) & 0xff) << 24) | (((d) & 0xff00) << 8)
241 | (((d) & 0xff0000) >> 8) | (((d) >> 24) & 0xff));
245 // Maintaining the same styleee as above...
246 #define HAL_CTOLE32(x) ((((x))))
247 #define HAL_LE32TOC(x) ((((x))))
249 #define HAL_CTOLE16(x) ((((x))))
250 #define HAL_LE16TOC(x) ((((x))))
252 static inline void OUTB(cyg_uint8 value, cyg_uint32 io_address)
253 { HAL_WRITE_UINT8( io_address, value ); }
255 static inline void OUTW(cyg_uint16 value, cyg_uint32 io_address)
256 { HAL_WRITE_UINT16( io_address, value ); }
258 static inline void OUTL(cyg_uint32 value, cyg_uint32 io_address)
259 { HAL_WRITE_UINT32( io_address, value ); }
261 static inline cyg_uint8 INB(cyg_uint32 io_address)
262 { cyg_uint8 _t_; HAL_READ_UINT8( io_address, _t_ ); return _t_; }
264 static inline cyg_uint16 INW(cyg_uint32 io_address)
265 { cyg_uint16 _t_; HAL_READ_UINT16( io_address, _t_ ); return _t_; }
267 static inline cyg_uint32 INL(cyg_uint32 io_address)
268 { cyg_uint32 _t_; HAL_READ_UINT32( io_address, _t_ ); return _t_; }
274 * Table of all known PCI device/vendor ID combinations for the RealTek 8139.
275 * Add them as you get to know them.
277 #define CYGNUM_DEVS_ETH_RLTK_8139_KNOWN_ALIASES 2
278 static pci_identifier_t
279 known_8139_aliases[CYGNUM_DEVS_ETH_RLTK_8139_KNOWN_ALIASES] = {
280 { 0x10ec, 0x8139, NULL }, /* This is the offical RealTek vendor/device code */
281 { 0x11db, 0x1234, NULL} /* SEGA DreamCast BroadBandAdapter */
286 * Check if the device description matches a known 8139 alias.
289 rltk8139_find_match_func(cyg_uint16 vendor_id, cyg_uint16 device_id,
290 cyg_uint32 class_id, void *p)
295 for (i = 0; i < CYGNUM_DEVS_ETH_RLTK_8139_KNOWN_ALIASES; ++i) {
296 if (((known_8139_aliases[i].vendor_id == PCI_ANY_ID) ||
297 (known_8139_aliases[i].vendor_id == vendor_id)) &&
298 ((known_8139_aliases[i].device_id == PCI_ANY_ID) ||
299 (known_8139_aliases[i].device_id == device_id)))
308 * Find the Nth 8139 device on all attached PCI busses and do some initial
309 * PCI-type initialization. Also setup the interrupt for use in eCos.
312 rltk8139_find(int n_th, struct eth_drv_sc *sc)
314 Rltk8139_t *rltk8139_info;
315 cyg_pci_device_id pci_device_id;
316 cyg_pci_device pci_device_info;
321 /* Go through all PCI devices until we find the Nth 8139 chip */
322 pci_device_id = CYG_PCI_NULL_DEVID;
324 if (!cyg_pci_find_matching(&rltk8139_find_match_func, NULL,
329 } while (found != n_th);
331 /* Save device ID in driver private data in case we ever need it again */
332 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
333 rltk8139_info->pci_device_id = pci_device_id;
335 /* Now that we have found the device, we can extract some data about it */
336 cyg_pci_get_device_info(pci_device_id, &pci_device_info);
338 /* Get the assigned interrupt and set up ISR and DSR for it. */
339 if (cyg_pci_translate_interrupt(&pci_device_info, &rltk8139_info->vector)) {
340 #ifdef DEBUG_RLTK8139_DRIVER
341 diag_printf(" Wired to HAL interrupt vector %d\n", rltk8139_info->vector);
344 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
346 * Note that we use the generic eth_drv_dsr routine instead of
349 cyg_drv_interrupt_create(rltk8139_info->vector, 0,
353 &rltk8139_info->interrupt_handle,
354 &rltk8139_info->interrupt);
355 cyg_drv_interrupt_attach(rltk8139_info->interrupt_handle);
359 #ifdef DEBUG_RLTK8139_DRIVER
360 diag_printf(" Does not generate interrupts.\n");
365 * Call 'cyg_pci_configure_device' for those platforms that do not
366 * configure the PCI bus during HAL initialization. According to Nick
367 * Garnett, there are good reasons to not configure PCI devices during HAL
368 * initialization. Also according to Nick, calling
369 * 'cyg_pci_configure_device' for devices already configured should have no
370 * effect and thus is safe to do.
372 if (cyg_pci_configure_device(&pci_device_info)) {
373 #ifdef DEBUG_RLTK8139_DRIVER
375 diag_printf("Found device #%d on bus %d, devfn 0x%02x:\n", n_th,
376 CYG_PCI_DEV_GET_BUS(pci_device_id),
377 CYG_PCI_DEV_GET_DEVFN(pci_device_id));
379 if (pci_device_info.command & CYG_PCI_CFG_COMMAND_ACTIVE)
380 diag_printf(" Note that board is active. Probed"
381 " sizes and CPU addresses are invalid!\n");
383 diag_printf(" Vendor 0x%04x", pci_device_info.vendor);
384 diag_printf("\n Device 0x%04x", pci_device_info.device);
385 diag_printf("\n Command 0x%04x, Status 0x%04x\n",
386 pci_device_info.command, pci_device_info.status)
389 diag_printf(" Class/Rev 0x%08x", pci_device_info.class_rev);
390 diag_printf("\n Header 0x%02x\n", pci_device_info.header_type);
392 diag_printf(" SubVendor 0x%04x, Sub ID 0x%04x\n",
393 pci_device_info.header.normal.sub_vendor,
394 pci_device_info.header.normal.sub_id);
396 for(i = 0; i < CYG_PCI_MAX_BAR; i++) {
397 diag_printf(" BAR[%d] 0x%08x /", i, pci_device_info.base_address[i]);
398 diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
399 pci_device_info.base_size[i], pci_device_info.base_map[i]);
404 #ifdef DEBUG_RLTK8139_DRIVER
405 diag_printf("Failed to configure 8139 device #%d\n", n_th);
411 * Enable memory mapped and port based I/O and busmastering. We currently
412 * only support IO space accesses; memory mapping is enabled so that bit
413 * DVRLOAD in CONFIG1 is cleared automatically.
415 * NOTE: it seems that for some configurations/HALs, the device is already
416 * activated at this point, even though eCos' documentation suggests
417 * it shouldn't be. At least in my case, this is not a problem.
419 cyg_pci_read_config_uint16(pci_device_info.devid, CYG_PCI_CFG_COMMAND,
421 command |= (CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MEMORY
422 | CYG_PCI_CFG_COMMAND_MASTER);
423 cyg_pci_write_config_uint16(pci_device_info.devid, CYG_PCI_CFG_COMMAND,
427 * This is the base address used to talk to the device. The 8139's IOAR
428 * and MEMAR registers are BAR0 and BAR1, respectively.
430 rltk8139_info->base_address = pci_device_info.base_map[0];
433 * Read the MAC address. The RealTek data sheet seems to claim this should
434 * only be read in 4 byte accesses, but the code below works just fine.
436 for (found = 0; found < 6; ++found)
437 rltk8139_info->mac[found] = INB(rltk8139_info->base_address + IDR0 + found);
440 * This is the indicator for "uses an interrupt". The code was lifted
441 * from the eCos Intel 82559 driver.
443 if (rltk8139_info->interrupt_handle != 0) {
444 cyg_drv_interrupt_acknowledge(rltk8139_info->vector);
446 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
447 cyg_drv_interrupt_unmask(rltk8139_info->vector);
454 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
456 * Interrupt service routine. We do not clear the interrupt status bits
457 * (since this should really only be done after handling whatever caused
458 * the interrupt, and that is done in the '_deliver' routine), but instead
459 * clear the interrupt mask.
461 * If we are sharing interrupts with other devices, we have two options
464 * 1. Mask the interrupt vector completly. Personally I think this is a bad
465 * idea because the other devices sharing this interrupt are also masked
466 * until the network thread gets around to calling the '_deliver' routine.
468 * 2. Use the interrupt mask register in the 8139 to mask just the interrupt
469 * request coming from the 8139. This way, the other devices' requests
470 * can still be serviced.
473 rltk8139_isr(cyg_vector_t vector, cyg_addrword_t data)
475 Rltk8139_t *rltk8139_info;
476 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SHARE_INTERRUPTS
480 rltk8139_info = (Rltk8139_t *)(((struct eth_drv_sc *)data)->driver_private);
482 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SHARE_INTERRUPTS
484 * If interrupt sharing is enabled, check if the interrupt is really
485 * intended for us. Note that while the RealTek data sheet claims that
486 * reading the interrupt status register will clear all it's bits,
487 * this is not true, so we can read it without problems.
489 if (!(isr = INW(rltk8139_info->base_address + ISR)))
493 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_MASK_INTERRUPTS_IN_8139
494 /* Clear the interrupt mask to stop the current request. */
495 OUTW(0, rltk8139_info->base_address + IMR);
497 /* Mask the interrupt */
498 cyg_interrupt_mask(vector);
501 /* Acknowledge the interrupt for those platforms were this is necessary */
502 cyg_interrupt_acknowledge(vector);
504 return (CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
506 #endif /* ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE */
509 * Reset the chip. This function is not exported to higher level software.
512 rltk8139_reset(struct eth_drv_sc *sc)
515 rltk8139_start(sc, NULL, 0);
518 #ifdef ETH_DRV_SET_MC_LIST
520 * I assume (hope !) that this is identical to Ethernet's CRC algorithm
521 * specified in IEEE 802.3. It does seem to calculate the same CRC that
522 * the 8139 itself does, so I think it is correct.
523 * Note that while Ethernet's polynomial is usually specified as 04C11DB7,
524 * we must use EDB88320 because we shift the bits to the left, not the right.
525 * (See ftp://ftp.rocksoft.com/papers/crc_v3.txt for a good description of
529 ether_crc(cyg_uint8 *data, int length)
532 cyg_uint32 crc = 0xFFFFFFFFU;
534 while (length-- > 0) {
536 for (bit = 0; bit < 8; ++bit) {
538 crc = (crc >> 1) ^ 0xEDB88320U;
544 return crc ^ 0xFFFFFFFFU;
549 * Set up multicast filtering. The way I understand existing driver code
550 * (Linux and OpenBSD), the 8139 calculates the ethernet CRC of
551 * incoming addresses and uses the top 6 bits as an index into a hash
552 * table. If the corresponding bit is set in MAR0..7, the address is
556 rltk8139_set_multicast_list(Rltk8139_t *rltk8139_info,
557 struct eth_drv_mc_list *mc_list)
559 cyg_uint32 mar[2], hash;
562 /* If 'mc_list' is NULL, accept all multicast packets. */
564 mar[0] = 0xFFFFFFFFU;
565 mar[1] = 0xFFFFFFFFU;
571 for (i = 0; i < mc_list->len; ++i) {
572 hash = ether_crc(&mc_list->addrs[i][0], ETHER_ADDR_LEN) >> 26;
573 mar[hash >> 5] |= (1 << (hash & 0x1F));
577 /* Program the new filter values */
578 OUTL(mar[0], rltk8139_info->base_address + MAR0);
579 OUTL(mar[1], rltk8139_info->base_address + MAR4);
581 #endif /* ifdef ETH_DRV_SET_MC_LIST */
585 * Initialize the network interface. Since the chips is reset by calling
586 * _stop() and _start(), any code that will never need to be executed more
587 * than once after system startup should go here.
590 rltk8139_init(struct cyg_netdevtab_entry *tab)
592 struct eth_drv_sc *sc;
593 Rltk8139_t *rltk8139_info;
596 sc = (struct eth_drv_sc *)(tab->device_instance);
597 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
600 * Initialize the eCos PCI library. According to the documentation, it
601 * is safe to call this function multiple times, so we call it just to
602 * be sure it has been done.
607 * Scan the PCI bus for the specified chip. The '_find' function will also
608 * do some basic PCI initialization.
610 if (!rltk8139_find(rltk8139_info->device_num, sc)) {
611 #ifdef DEBUG_RLTK8139_DRIVER
612 diag_printf("rltk8139_init: could not find RealTek 8139 chip #%d.\n",
613 rltk8139_info->device_num);
618 /* platform depends initialize */
619 CYGHWR_RLTK_8139_PLF_INIT(sc);
622 * The initial tx threshold is set here to prevent it from being reset
623 * with every _start().
625 rltk8139_info->tx_threshold = 3;
627 /* Initialize upper level driver */
628 (sc->funs->eth_drv->init)(sc, rltk8139_info->mac);
635 * (Re)Start the chip, initializing data structures and enabling the
636 * transmitter and receiver. Currently, 'flags' is unused by eCos.
639 rltk8139_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
641 Rltk8139_t *rltk8139_info;
645 #ifdef DEBUG_RLTK8139_DRIVER
646 diag_printf("rltk8139_start(%s)\n", sc->dev_name);
649 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
652 * Reset the chip. Existing driver code implies that this may take up
653 * to 10ms; since I don't know under what exact circumstances this code may
654 * be called I busy wait here regardless.
656 OUTB(RST, rltk8139_info->base_address + CR);
657 while (INB(rltk8139_info->base_address + CR) & RST);
659 #ifdef DEBUG_RLTK8139_DRIVER
660 diag_printf("rltk8139_start(%s): 8139 was successfully reset.\n",
665 * Clear the key storage area. These keys are used by the eCos networking
666 * support code to keep track of individual packets.
668 for (i = 0; i < NUM_TX_DESC; ++i)
669 rltk8139_info->tx_desc_key[i] = 0;
671 /* Initialize transmission buffer control */
672 rltk8139_info->tx_free_desc = 0;
673 rltk8139_info->tx_num_free_desc = NUM_TX_DESC;
676 * Set the requested MAC address if enaddr != NULL. This is a special
677 * feature of my '_start' function since it's used to reset the chip after
680 if (enaddr != NULL) {
681 for (i = 0; i < 6; ++i) {
682 rltk8139_info->mac[i] = enaddr[i];
683 OUTB(enaddr[i], rltk8139_info->base_address + IDR0 + i);
688 * Now setup the transmission and reception buffers. These could be done
689 * in _init() and kept around, but putting them here fits better logically.
691 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)(rltk8139_info->tx_buffer
693 rltk8139_info->base_address + TSAD0);
694 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)(rltk8139_info->tx_buffer
696 rltk8139_info->base_address + TSAD1);
697 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)(rltk8139_info->tx_buffer
699 rltk8139_info->base_address + TSAD2);
700 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)(rltk8139_info->tx_buffer
702 rltk8139_info->base_address + TSAD3);
703 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)rltk8139_info->rx_ring),
704 rltk8139_info->base_address + RBSTART);
707 * Enable the transmitter and receiver, then clear the missed packet
710 OUTB(INB(rltk8139_info->base_address + CR) | (TE|RE),
711 rltk8139_info->base_address + CR);
712 OUTL(0, rltk8139_info->base_address + MPC);
715 * It seems the receiver and transmitter configuration can only
716 * be set after the transmitter/receiver have been enabled.
718 OUTL(TXCFG, rltk8139_info->base_address + TCR);
719 OUTL(RXCFG | AM, rltk8139_info->base_address + RCR);
722 * Enable the transmitter and receiver again. I'm not sure why this is
723 * necessary; the Linux driver does it so we do it here just to be on
726 OUTB(INB(rltk8139_info->base_address + CR) | (TE|RE),
727 rltk8139_info->base_address + CR);
729 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
731 * If this driver was not compiled in stand alone (without interrupts)
732 * mode, enable interrupts.
734 OUTW(RLTK8139_IRQ, rltk8139_info->base_address + IMR);
737 #ifdef DEBUG_RLTK8139_DRIVER
738 rltk8139_print_state(sc);
744 * Stop the chip, disabling the transmitter and receiver.
747 rltk8139_stop(struct eth_drv_sc *sc)
749 Rltk8139_t *rltk8139_info;
752 #ifdef DEBUG_RLTK8139_DRIVER
753 diag_printf("rltk8139_stop(%s)\n", sc->dev_name);
756 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
758 /* Disable receiver and transmitter */
759 OUTB(INB(rltk8139_info->base_address + CR) & ~(TE|RE),
760 rltk8139_info->base_address + CR);
762 /* Mask all interrupts */
763 OUTW(0, rltk8139_info->base_address + IMR);
768 * 8139 control function. Unlike a 'real' ioctl function, this function is
769 * not required to tell the caller why a request failed, only that it did
770 * (see the eCos documentation).
773 rltk8139_control(struct eth_drv_sc *sc, unsigned long key, void *data,
777 Rltk8139_t *rltk8139_info;
780 #ifdef DEBUG_RLTK8139_DRIVER
781 diag_printf("rltk8139_control(%08x, %lx)\n", sc, key);
784 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
787 #ifdef ETH_DRV_SET_MAC_ADDRESS
788 case ETH_DRV_SET_MAC_ADDRESS:
789 if ( 6 != data_length )
792 /* Set the mac address */
793 for (i = 0; i < 6; ++i) {
794 rltk8139_info->mac[i] = *(((cyg_uint8 *)data) + i);
795 OUTB(rltk8139_info->mac[i], rltk8139_info->base_address + IDR0 + i);
800 #ifdef ETH_DRV_GET_MAC_ADDRESS
801 case ETH_DRV_GET_MAC_ADDRESS:
802 if (6 != data_length)
805 memcpy(data, rltk8139_info->mac, 6);
809 #ifdef ETH_DRV_GET_IF_STATS_UD
810 case ETH_DRV_GET_IF_STATS_UD: // UD == UPDATE
811 //ETH_STATS_INIT( sc ); // so UPDATE the statistics structure
814 #ifdef ETH_DRV_GET_IF_STATS
815 case ETH_DRV_GET_IF_STATS:
817 #if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
821 #ifdef ETH_DRV_SET_MC_LIST
822 case ETH_DRV_SET_MC_LIST:
824 * Program the 8139's multicast filter register. If the eth_drv_mc_list
825 * contains at least one element, set the accept multicast bit in the
826 * receive config register.
828 rltk8139_set_multicast_list(rltk8139_info, (struct eth_drv_mc_list *)data);
829 if (((struct eth_drv_mc_list *)data)->len > 0)
830 OUTL(INL(rltk8139_info->base_address + RCR) | AM,
831 rltk8139_info->base_address + RCR);
833 OUTL(INL(rltk8139_info->base_address + RCR) & ~AM,
834 rltk8139_info->base_address + RCR);
837 #endif // ETH_DRV_SET_MC_LIST
839 #ifdef ETH_DRV_SET_MC_ALL
840 case ETH_DRV_SET_MC_ALL:
842 * Set the accept multicast bit in the receive config register and
843 * program the multicast filter to accept all addresses.
845 rltk8139_set_multicast_list(rltk8139_info, NULL);
846 OUTL(INL(rltk8139_info->base_address + RCR) | AM,
847 rltk8139_info->base_address + RCR);
849 #endif // ETH_DRV_SET_MC_ALL
860 * Check if a new packet can be sent.
863 rltk8139_can_send(struct eth_drv_sc *sc)
865 return ((Rltk8139_t *)(sc->driver_private))->tx_num_free_desc;
870 * Send a packet over the wire.
873 rltk8139_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
874 int total_len, unsigned long key)
876 Rltk8139_t *rltk8139_info;
877 cyg_uint8 *tx_buffer;
878 struct eth_drv_sg *last_sg;
881 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
883 #ifdef DEBUG_RLTK8139_DRIVER
884 diag_printf("rltk8139_send(%s, %08x, %d, %d, %08lx)\n",
885 sc->dev_name, sg_list, sg_len, total_len, key);
888 CYG_ASSERT(total_len <= TX_BUF_SIZE, "packet too long");
891 * Get the next free descriptor to send. We lock out all interrupts
892 * and scheduling because we really, really do not want to be interrupted
895 * IMPORTANT NOTE: the RealTek data sheet does not really make this clear,
896 * but when they talk about a 'ring' of transmit descriptors, they
897 * _really_ mean it, i.e. you _must_ use descriptor #1 after descriptor
898 * #0 even if transmission of descriptor #0 has already completed.
903 * Sanity check to see if '_send' was called even though there is no free
904 * descriptor. This is probably unnecessary.
906 if (rltk8139_info->tx_num_free_desc == 0) {
907 cyg_drv_isr_unlock();
908 #ifdef DEBUG_RLTK8139_DRIVER
909 diag_printf("rltk8139_send(%s): no free descriptor available\n",
916 * Get the free descriptor and advance the descriptor counter modulo
917 * TX_NUM_DESC. We assume that TX_NUM_DESC will always be a power of 2.
919 desc = rltk8139_info->tx_free_desc;
920 rltk8139_info->tx_free_desc = (rltk8139_info->tx_free_desc + 1)
923 /* Decrement the number of free descriptors */
924 rltk8139_info->tx_num_free_desc -= 1;
926 /* Reenable interrupts at this point */
927 cyg_drv_isr_unlock();
930 * Determine the buffer memory to use and tell the hardware about it.
931 * Since we use fixed buffer addresses, we do not need to set up TSADx.
932 * Memorize the key so we can call the tx_done callback correctly.
934 * While it would be possible to set TSADx to the packet directly if
935 * it is stored in a linear memory area with 32 bit alignment, it seems
936 * this happens so seldomly that it's simply not worth the extra
939 tx_buffer = CYGARC_UNCACHED_ADDRESS(rltk8139_info->tx_buffer
940 + TX_BUF_SIZE * desc);
941 rltk8139_info->tx_desc_key[desc] = key;
944 * Copy the data to the designated position. Note that unlike the eCos
945 * Intel 82559 driver, we simply assume that all the scatter/gather list
946 * elements' lengths will add up to total_len exactly, and don't check
949 for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
950 memcpy(tx_buffer, (void *)(sg_list->buf), sg_list->len);
951 tx_buffer += sg_list->len;
955 * Make sure the packet has the minimum ethernet packet size, padding
956 * with zeros if necessary.
958 if (total_len < MIN_ETH_FRAME_SIZE) {
959 memset(tx_buffer, 0, MIN_ETH_FRAME_SIZE - total_len);
960 total_len = MIN_ETH_FRAME_SIZE;
964 * Flush the data cache here if necessary. This ensures the 8139 can
965 * read the correct data from the transmit buffer.
967 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
968 HAL_DCACHE_FLUSH(rltk8139_info->tx_buffer + TX_BUF_SIZE * desc, total_len);
972 * Now setup the correct transmit descriptor to actually send the data.
973 * The early TX threshold is incremented by the driver until we reach a
974 * size that prevents transmit underruns. (An earlier attempt to calculate
975 * this parameter from the packet size didn't work).
977 OUTL((rltk8139_info->tx_threshold << ERTXTH_SHIFT) | (total_len & SIZE),
978 rltk8139_info->base_address + TSD0 + (desc<<2));
983 * This routine actually retrieves data from the receive ring by
984 * copying it into the specified scatter/gather buffers. Again,
985 * we assume the scatter/gather list is OK and don't check against
989 rltk8139_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
992 Rltk8139_t *rltk8139_info;
993 struct eth_drv_sg *last_sg;
994 cyg_uint8 *rx_buffer;
997 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
998 rx_buffer = rltk8139_info->rx_current;
1001 * Invalidate the cache line(s) mapped to the receive buffer
1004 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
1005 HAL_DCACHE_INVALIDATE(rx_buffer, rltk8139_info->rx_size);
1008 for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
1009 if (sg_list->buf != (CYG_ADDRESS)0) {
1010 memcpy((void *)(sg_list->buf), rx_buffer, sg_list->len);
1011 rx_buffer += sg_list->len;
1018 * This function does all the heavy lifting associated with interrupts.
1021 rltk8139_deliver(struct eth_drv_sc *sc)
1023 Rltk8139_t *rltk8139_info;
1024 cyg_uint16 status, pci_status;
1029 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
1032 * The RealTek data sheet claims that reading the ISR will clear
1033 * it. This is incorrect; to clear a bit in the ISR, a '1' must be
1034 * written to the ISR instead. We immediately clear the interrupt
1035 * bits at this point.
1037 status = INW(rltk8139_info->base_address + ISR);
1038 OUTW(status, rltk8139_info->base_address + ISR);
1040 #ifdef DEBUG_RLTK8139_DRIVER
1041 diag_printf("rltk8139_deliver(%s): %04x\n", sc->dev_name, status);
1045 * Check for a PCI error. This seems like a very serious error to
1046 * me, so we will reset the chip and hope for the best.
1048 if (status & IR_SERR) {
1049 cyg_pci_read_config_uint16(rltk8139_info->pci_device_id,
1050 CYG_PCI_CFG_STATUS, &pci_status);
1051 cyg_pci_write_config_uint16(rltk8139_info->pci_device_id,
1052 CYG_PCI_CFG_STATUS, pci_status);
1053 #ifdef DEBUG_RLTK8139_DRIVER
1054 diag_printf("rltk8139_deliver(%s): PCI error %04x\n",
1055 sc->dev_name, pci_status);
1062 /* Check for transmission complete (with errors or not) */
1063 if ((status & IR_TER) || (status & IR_TOK)) {
1065 * Figure out which descriptors' status must be checked. We lock out
1066 * interrupts while manipulating the descriptor list because we do not
1067 * want to be interrupted at this point.
1072 /* Check if all descriptors are ready, in which case we are done. */
1073 if (rltk8139_info->tx_num_free_desc >= NUM_TX_DESC) {
1074 cyg_drv_isr_unlock();
1078 desc = (rltk8139_info->tx_free_desc
1079 - (NUM_TX_DESC - rltk8139_info->tx_num_free_desc))
1080 & (NUM_TX_DESC - 1);
1081 cyg_drv_isr_unlock();
1083 /* Get the current status of the descriptor */
1084 tsd = INL(rltk8139_info->base_address + TSD0 + (desc<<2));
1087 * If a transmit FIFO underrun occurred, increment the threshold
1090 if ((tsd & TUN) && (rltk8139_info->tx_threshold < 64))
1091 rltk8139_info->tx_threshold += 1;
1094 * Check if a transmission completed OK. RealTek's data sheet implies
1095 * that a successful transmission that experiences underrun will only
1096 * set TUN. This is not true; TOK is set for all successful
1100 (sc->funs->eth_drv->tx_done)(sc, rltk8139_info->tx_desc_key[desc], 0);
1102 else if (tsd & TABT) {
1104 * Set the CLRABT bit in TCR. Since I haven't encountered any
1105 * transmission aborts so far, I don't really know if this code
1108 OUTL(INL(rltk8139_info->base_address + TCR) & CLRABT,
1109 rltk8139_info->base_address + TCR);
1110 (sc->funs->eth_drv->tx_done)(sc, rltk8139_info->tx_desc_key[desc], -1);
1114 * This descriptor is not ready. Since the descriptors are used
1115 * in a ring, this means that no more descriptors are ready.
1121 * Clear the saved key value. This is not really necessary, since
1122 * the key value is never used to determine if a descriptor is
1123 * valid or not. However, clearing it is a tidier IMO.
1125 rltk8139_info->tx_desc_key[desc] = 0;
1128 * Increment the free descriptor count and go through the loop again
1129 * to see if more descriptors are ready.
1132 rltk8139_info->tx_num_free_desc += 1;
1133 cyg_drv_isr_unlock();
1137 if (status & IR_ROK) {
1139 * Received a frame. Note that '_deliver' does not actually copy any
1140 * data; it just determines how many bytes are available and tells
1141 * the generic ethernet driver about it, which then calls into
1142 * the '_recv' function to copy the data.
1145 cyg_uint32 header, length;
1148 * CAPR contains the index into the receive buffer. It is controlled
1149 * completely in software. For some reason, CAPR points 16 bytes
1150 * before the actual start of the packet.
1152 rx_pos = (INW(rltk8139_info->base_address + CAPR) + 16) % RX_BUF_LEN;
1155 * Loop until the rx buffer is empty. I have no idea how the 8139
1156 * determines if the buffer still contains a packet; it may check
1157 * that CAPR points 16 bytes before CBR.
1159 while (!(INB(rltk8139_info->base_address + CR) & BUFE)) {
1161 * Invalidate the data cache for the cache line containing the header
1164 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
1165 HAL_DCACHE_INVALIDATE(&rltk8139_info->rx_ring[rx_pos],
1166 sizeof(cyg_uint32));
1170 * The 8139 prepends each packet with a 32 bit packet header that
1171 * contains a 16 bit length and 16 bit status field, in little-endian
1174 header = HAL_LE32TOC(*((volatile cyg_uint32 *)CYGARC_UNCACHED_ADDRESS(&rltk8139_info->rx_ring[rx_pos])));
1177 * If the 8139 is still copying data for this packet into the
1178 * receive ring, it will set packet length to 0xfff0. This shouldn't
1179 * ever happen because we do not use early receive.
1181 if ((header >> 16) == 0xFFF0)
1185 * Since the 8139 appends the ethernet CRC to every packet, we
1186 * must subtract 4 from the length to get the true packet length.
1188 length = (header >> 16) - 4;
1191 * Check if the packet was received correctly. The OpenBSD driver
1192 * resets the chip if this is not the case; we attempt to salvage
1193 * following packets by doing nothing.
1195 if (!(header & HDR_ROK)) {
1199 * Packet was received OK. Determine from where to start copying
1200 * bytes. This is saved in the driver private area so rlt8139_recv
1201 * doesn't have to redetermine this information. Then, inform
1202 * the generic ethernet driver about the packet.
1204 rltk8139_info->rx_current = CYGARC_UNCACHED_ADDRESS(rltk8139_info->rx_ring + rx_pos + 4);
1205 rltk8139_info->rx_size = length;
1207 /* Tell eCos about the packet */
1208 (sc->funs->eth_drv->recv)(sc, length);
1212 * Update CAPR. CAPR must be aligned to a 32 bit boundary, and should
1213 * point 16 bytes before it's actual position.
1215 rx_pos = ((rx_pos + length + 8 + 3) & ~3) % RX_BUF_LEN;
1216 OUTW((rx_pos - 16) % RX_BUF_LEN, rltk8139_info->base_address + CAPR);
1220 if (status & IR_RXOVW) {
1222 * In case of a receive buffer overflow, the RealTek data sheet claims we
1223 * should update CAPR and then write a '1' to ROK in ISR. However, none of
1224 * the other 8139 drivers I have looked at do this, so we will just reset
1227 #ifdef DEBUG_RLTK8139_DRIVER
1228 diag_printf("rltk8139_deliver(%s): receive buffer overflow\n",
1235 if (status & IR_FOVW) {
1237 * Rx FIFO overflow. According to RealTek's data sheet, this is cleared
1238 * by writing a '1' to RXOVW. Again, none of the 8139 drivers I have
1239 * seen actually do this, so we reset the chip instead.
1241 #ifdef DEBUG_RLTK8139_DRIVER
1242 diag_printf("rltk8139_deliver(%s): receive FIFO overflow\n",
1249 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
1250 /* Finally, reenable interrupts */
1251 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_MASK_INTERRUPTS_IN_8139
1252 OUTW(RLTK8139_IRQ, rltk8139_info->base_address + IMR);
1254 cyg_interrupt_unmask(rltk8139_info->vector);
1261 * '_poll' does the same thing as '_deliver'. It is called periodically when
1262 * the ethernet driver is operated in non-interrupt mode, for instance by
1266 rltk8139_poll(struct eth_drv_sc *sc)
1268 Rltk8139_t *rltk8139_info;
1272 #ifdef DEBUG_RLTK8139_DRIVER
1273 diag_printf("rltk8139_poll(%s)\n", sc->dev_name);
1276 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
1279 * Get the current interrupt status. If anything changed, call
1282 if ((isr = INW(rltk8139_info->base_address + ISR)))
1283 rltk8139_deliver(sc);
1288 * Return the interrupt vector used by this device.
1291 rltk8139_int_vector(struct eth_drv_sc *sc)
1293 return ((Rltk8139_t *)(sc->driver_private))->vector;
1298 * Quick and dirty register dump. This is somewhat dangerous, since
1299 * we read the register space 32 bits at a time, regardless of actual
1302 #ifdef DEBUG_RLTK8139_DRIVER
1304 rltk8139_print_state(struct eth_drv_sc *sc) {
1306 Rltk8139_t *rltk8139_info;
1309 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
1311 for (i = IDR0; i < FFER; i += 16) {
1312 diag_printf("8139 reg address 0x%02x = 0x%08x", i,
1313 INL(rltk8139_info->base_address + i));
1314 diag_printf(" 0x%08x", INL(rltk8139_info->base_address + i + 4));
1315 diag_printf(" 0x%08x", INL(rltk8139_info->base_address + i + 8));
1316 diag_printf(" 0x%08x\n", INL(rltk8139_info->base_address + i + 12));