1 #ifndef CYGONCE_DEVS_ETH_SMSC_LAN91C111_LAN91C111_H
2 #define CYGONCE_DEVS_ETH_SMSC_LAN91C111_LAN91C111_H
3 //==========================================================================
7 // SMCS LAN91C111 (LAN91C111 compatible) Ethernet chip
9 //==========================================================================
10 //#####ECOSGPLCOPYRIGHTBEGIN####
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41 //#####ECOSGPLCOPYRIGHTEND####
42 //####BSDCOPYRIGHTBEGIN####
44 // -------------------------------------------
46 // Portions of this software may have been derived from OpenBSD or other sources,
47 // and are covered by the appropriate copyright disclaimers included herein.
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51 //####BSDCOPYRIGHTEND####
52 //==========================================================================
53 //#####DESCRIPTIONBEGIN####
55 // Author(s): jskov, usteinkohl
56 // Contributors: jskov, hmt, jco, usteinkohl
58 // Purpose: Hardware description of LAN9000 series, LAN91C96/110.
59 // modified by usteinkohl for LAN91C111 chip
62 //####DESCRIPTIONEND####
64 //==========================================================================
66 #include <cyg/hal/hal_io.h>
71 // 0 disables all debug output
72 // 1 for process debug output
73 // 2 for added data IO output: get_reg, put_reg
74 // 4 for packet allocation/free output
75 // 8 for only startup status, so we can tell we're installed OK
78 #define DEBUG_SMSC (0x00)
80 #define PHY_LAN83C183 0x0016f840
81 #define PHY_LAN83C180 0x02821c50
83 #define LAN91C111_TCR 0x00
84 #define LAN91C111_EPH_STATUS 0x01
85 #define LAN91C111_RCR 0x02
86 #define LAN91C111_COUNTER 0x03
87 #define LAN91C111_MIR 0x04
88 #define LAN91C111_RPCR 0x05 // for 91C110 this was MCR
89 #define LAN91C111_RESERVED_0 0x06
90 #define LAN91C111_BS 0x07
94 #define LAN91C111_CONFIG 0x08
95 #define LAN91C111_BASE_REG 0x09
96 #define LAN91C111_IA01 0x0a
97 #define LAN91C111_IA23 0x0b
98 #define LAN91C111_IA45 0x0c
99 #define LAN91C111_GENERAL 0x0d // 91C96 - was "RESERVED_1" for others
100 #define LAN91C111_CONTROL 0x0e
101 #define LAN91C111_BS2 0x0f
105 #define LAN91C111_MMU_COMMAND 0x10
106 #define LAN91C111_PNR 0x11
107 #define LAN91C111_FIFO_PORTS 0x12
108 #define LAN91C111_POINTER 0x13
109 #define LAN91C111_DATA 0x15
110 #define LAN91C111_DATA_HIGH 0x14
111 #define LAN91C111_INTERRUPT 0x16
112 #define LAN91C111_BS3 0x17
116 #define LAN91C111_MT01 0x18
117 #define LAN91C111_MT23 0x19
118 #define LAN91C111_MT45 0x1a
119 #define LAN91C111_MT67 0x1b
120 #define LAN91C111_MGMT 0x1c
121 #define LAN91C111_REVISION 0x1d
122 #define LAN91C111_ERCV 0x1e
123 #define LAN91C111_BS4 0x1f
125 #define LAN91C111_RCR_SOFT_RST 0x8000 // soft reset
126 #define LAN91C111_RCR_FILT_CAR 0x4000 // filter carrier
127 #define LAN91C111_RCR_ABORT_ENB 0x2000 // abort on collision
128 #define LAN91C111_RCR_STRIP_CRC 0x0200 // strip CRC
129 #define LAN91C111_RCR_RXEN 0x0100 // enable RX
130 #define LAN91C111_RCR_ALMUL 0x0004 // receive all muticasts
131 #define LAN91C111_RCR_PRMS 0x0002 // promiscuous
132 #define LAN91C111_RCR_RX_ABORT 0x0001 // set when abort due to long frame
136 #define LAN91C111_RPCR_SPEED 0x2000 // Speed select
137 #define LAN91C111_RPCR_DPLX 0x1000 // Speed select
138 #define LAN91C111_RPCR_ANEG 0x0800 // Speed select
141 #define LAN91C111_MGMT__MDOE 0x0008
142 #define LAN91C111_MGMT__MCLK 0x0004
143 #define LAN91C111_MGMT__MDI 0x0002
144 #define LAN91C111_MGMT__MDO 0x0001
147 #define LAN91C111_CONFIG_EXT_PHY 0x0200
148 #define LAN91C111_CONFIG_POW_EN 0x8000
149 #define LAN91C111_CONFIG_NO_WAIT 0x1000
153 #define LAN91C111_TCR_SWFDUP 0x8000 // Switched Full Duplex mode
154 //#define LAN91CXX_TCR_ETEN_TYPE 0x4000 // ETEN type (91C96) 0 <=> like a 91C94
155 #define LAN91C111_TCR_EPH_LOOP 0x2000 // loopback mode
156 #define LAN91C111_TCR_STP_SQET 0x1000 // Stop transmission on SQET error
157 #define LAN91C111_TCR_FDUPLX 0x0800 // full duplex
158 #define LAN91C111_TCR_MON_CSN 0x0400 // monitor carrier during tx (91C96)
159 #define LAN91C111_TCR_NOCRC 0x0100 // does not append CRC to frames
160 #define LAN91C111_TCR_PAD_EN 0x0080 // pads frames with 00 to min length
161 #define LAN91C111_TCR_FORCOL 0x0004 // force collision
162 #define LAN91C111_TCR_LLOOP 0x0002 // local loopback (91C96)
163 #define LAN91C111_TCR_TXENA 0x0001 // enable
168 #define LAN91C111_POINTER_RCV 0x8000
169 #define LAN91C111_POINTER_AUTO_INCR 0x4000
170 #define LAN91C111_POINTER_READ 0x2000
171 #define LAN91C111_POINTER_ETEN 0x1000
172 #define LAN91C111_POINTER_NOT_EMPTY 0x0800
175 #define LAN91C111_INTERRUPT_MD_INT_M 0x8000 // (91C111)
176 #define LAN91C111_INTERRUPT_ERCV_INT_M 0x4000
177 #define LAN91C111_INTERRUPT_EPH_INT_M 0x2000
178 #define LAN91C111_INTERRUPT_RX_OVRN_INT_M 0x1000
179 #define LAN91C111_INTERRUPT_ALLOC_INT_M 0x0800
180 #define LAN91C111_INTERRUPT_TX_EMPTY_INT_M 0x0400
181 #define LAN91C111_INTERRUPT_TX_INT_M 0x0200
182 #define LAN91C111_INTERRUPT_RCV_INT_M 0x0100
186 #define LAN91C111_INTERRUPT_MD_INT 0x0080 // (91C111) also ack
187 #define LAN91C111_INTERRUPT_ERCV_INT 0x0040 // also ack
188 #define LAN91C111_INTERRUPT_EPH_INT 0x0020
189 #define LAN91C111_INTERRUPT_RX_OVRN_INT 0x0010 // also ack
190 #define LAN91C111_INTERRUPT_ALLOC_INT 0x0008
191 #define LAN91C111_INTERRUPT_TX_EMPTY_INT 0x0004 // also ack
192 #define LAN91C111_INTERRUPT_TX_INT 0x0002 // also ack
193 #define LAN91C111_INTERRUPT_RCV_INT 0x0001
199 #if 0 // Whichever we choose, the behaviour is the same.
200 #define LAN91CXX_INTERRUPT_TX_SET 0x0002 // TX
201 #define LAN91CXX_INTERRUPT_TX_SET_ACK 0x0000 // -none-
202 #define LAN91CXX_INTERRUPT_TX_FIFO_ACK 0x0002 // TX alone
203 #define LAN91CXX_INTERRUPT_TX_SET_M 0x0200 // TX alone
205 #define LAN91C111_INTERRUPT_TX_SET 0x0006 // TX_EMPTY + TX
206 #define LAN91C111_INTERRUPT_TX_SET_ACK 0x0004 // TX_EMPTY and not plain TX
207 #define LAN91C111_INTERRUPT_TX_FIFO_ACK 0x0002 // TX alone
208 #define LAN91C111_INTERRUPT_TX_SET_M 0x0600 // TX_EMPTY + TX
216 #define LAN91C111_CONTROL_RCV_BAD 0x4000
217 #define LAN91C111_CONTROL_AUTO_RELEASE 0x0800
218 #define LAN91C111_CONTROL_LE_ENABLE 0x0080
219 #define LAN91C111_CONTROL_CR_ENABLE 0x0040
220 #define LAN91C111_CONTROL_TE_ENABLE 0x0020
222 // These are for setting the MAC address in the 91C96 serial EEPROM
223 #define LAN91C111_CONTROL_EEPROM_SELECT 0x0004
224 #define LAN91C111_CONTROL_RELOAD 0x0002
225 #define LAN91C111_CONTROL_STORE 0x0001
228 //#define LAN91CXX_CONTROL_EEPROM_BUSY 0x0003
229 //#define LAN91CXX_ESA_EEPROM_OFFSET 0x0020
233 #define LAN91C111_STATUS_TX_UNRN 0x8000
234 #define LAN91C111_STATUS_LINK_OK 0x4000 // do not use this to check Link status, its just a general purpose input pin
235 #define LAN91C111_STATUS_CTR_ROL 0x1000
236 #define LAN91C111_STATUS_EXC_DEF 0x0800
237 #define LAN91C111_STATUS_LOST_CARR 0x0400
238 #define LAN91C111_STATUS_LATCOL 0x0200
239 //#define LAN91CXX_STATUS_WAKEUP 0x0100
240 #define LAN91C111_STATUS_TX_DEFR 0x0080
241 #define LAN91C111_STATUS_LTX_BRD 0x0040
242 #define LAN91C111_STATUS_SQET 0x0020
243 #define LAN91C111_STATUS_16COL 0x0010
244 #define LAN91C111_STATUS_LTX_MULT 0x0008
245 #define LAN91C111_STATUS_MUL_COL 0x0004
246 #define LAN91C111_STATUS_SNGL_COL 0x0002
247 #define LAN91C111_STATUS_TX_SUC 0x0001
252 #define LAN91C111_MMU_noop 0x0000
253 #define LAN91C111_MMU_alloc_for_tx 0x0020
254 #define LAN91C111_MMU_reset_mmu 0x0040
255 #define LAN91C111_MMU_rem_rx_frame 0x0060
256 //#define LAN91CXX_MMU_rem_tx_frame 0x0070 // (91C96) only when TX stopped
257 #define LAN91C111_MMU_remrel_rx_frame 0x0080
258 #define LAN91C111_MMU_rel_packet 0x00a0
259 #define LAN91C111_MMU_enq_packet 0x00c0
260 #define LAN91C111_MMU_reset_tx_fifo 0x00e0
268 #define LAN91C111_CONTROLBYTE_CRC 0x1000
269 #define LAN91C111_CONTROLBYTE_ODD 0x2000
270 #define LAN91C111_CONTROLBYTE_RX 0x4000
276 #define LAN91C111_RX_STATUS_ALIGNERR 0x8000
277 #define LAN91C111_RX_STATUS_BCAST 0x4000
278 #define LAN91C111_RX_STATUS_BADCRC 0x2000
279 #define LAN91C111_RX_STATUS_ODDFRM 0x1000
280 #define LAN91C111_RX_STATUS_TOOLONG 0x0800
281 #define LAN91C111_RX_STATUS_TOOSHORT 0x0400
282 #define LAN91C111_RX_STATUS_HASHVALMASK 0x007e // MASK
283 #define LAN91C111_RX_STATUS_MCAST 0x0001
287 // PHY Register Addresses (LAN91C111 Internal PHY)
289 // PHY Control Register
290 #define PHY_CNTL_REG 0x00
291 #define PHY_CNTL_RST 0x8000 // 1=PHY Reset
292 #define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
293 #define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
294 #define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
295 #define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
296 #define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
297 #define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
298 #define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
299 #define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
301 // PHY Status Register
302 #define PHY_STAT_REG 0x01
303 #define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
304 #define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
305 #define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
306 #define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
307 #define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
308 #define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
309 #define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
310 #define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
311 #define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
312 #define PHY_STAT_LINK 0x0004 // 1=valid link
313 #define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
314 #define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
316 // PHY Identifier Registers
317 #define PHY_ID1_REG 0x02 // PHY Identifier 1
318 #define PHY_ID2_REG 0x03 // PHY Identifier 2
320 // PHY Auto-Negotiation Advertisement Register
321 #define PHY_AD_REG 0x04
322 #define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
323 #define PHY_AD_ACK 0x4000 // 1=got link code word from remote
324 #define PHY_AD_RF 0x2000 // 1=advertise remote fault
325 #define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
326 #define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
327 #define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
328 #define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
329 #define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
330 #define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
332 // PHY Auto-negotiation Remote End Capability Register
333 #define PHY_RMT_REG 0x05
334 // Uses same bit definitions as PHY_AD_REG
336 // PHY Configuration Register 1
337 #define PHY_CFG1_REG 0x10
338 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
339 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
340 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
341 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
342 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
343 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
344 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
345 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
346 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
347 #define PHY_CFG1_TLVL_MASK 0x003C
348 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
351 // PHY Configuration Register 2
352 #define PHY_CFG2_REG 0x11
353 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
354 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
355 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
356 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
358 // PHY Status Output (and Interrupt status) Register
359 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
360 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
361 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
362 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
363 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
364 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
365 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
366 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
367 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
368 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
369 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
371 // PHY Interrupt/Status Mask Register
372 #define PHY_MASK_REG 0x13 // Interrupt Mask
373 // Uses the same bit definitions as PHY_INT_REG
380 // ------------------------------------------------------------------------
382 #ifdef KEEP_STATISTICS
383 struct smsc_lan91c111_stats {
384 unsigned int tx_good ;
385 unsigned int tx_max_collisions ;
386 unsigned int tx_late_collisions ;
387 unsigned int tx_underrun ;
388 unsigned int tx_carrier_loss ;
389 unsigned int tx_deferred ;
390 unsigned int tx_sqetesterrors ;
391 unsigned int tx_single_collisions;
392 unsigned int tx_mult_collisions ;
393 unsigned int tx_total_collisions ;
394 unsigned int rx_good ;
395 unsigned int rx_crc_errors ;
396 unsigned int rx_align_errors ;
397 unsigned int rx_resource_errors ;
398 unsigned int rx_overrun_errors ;
399 unsigned int rx_collisions ;
400 unsigned int rx_short_frames ;
401 unsigned int rx_too_long_frames ;
402 unsigned int rx_symbol_errors ;
403 unsigned int interrupts ;
404 unsigned int rx_count ;
405 unsigned int rx_deliver ;
406 unsigned int rx_resource ;
407 unsigned int rx_restart ;
408 unsigned int tx_count ;
409 unsigned int tx_complete ;
410 unsigned int tx_dropped ;
414 typedef struct lan91c111_priv_data {
415 int txbusy; // A packet has been sent
416 unsigned long txkey; // Used to ack when packet sent
417 volatile unsigned short* base; // Base I/O address of controller
418 // (as it comes out of reset)
420 int interrupt; // Interrupt vector used by controller
421 unsigned char enaddr[6]; // Controller ESA
422 // Function to configure the ESA - may fetch ESA from EPROM or
423 // RedBoot config option.
424 cyg_bool (*config_enaddr)(struct lan91c111_priv_data* cpd);
428 int addrsh; // Address bits to shift
429 #ifdef KEEP_STATISTICS
430 struct smsc_lan91c111_stats stats;
434 } lan91c111_priv_data;
436 // ------------------------------------------------------------------------
438 static __inline__ unsigned short
439 get_reg(struct eth_drv_sc *sc, int regno)
441 struct lan91c111_priv_data *cpd =
442 (struct lan91c111_priv_data *)sc->driver_private;
445 HAL_WRITE_UINT16(cpd->base+(LAN91C111_BS << cpd->addrsh), regno>>3);
446 HAL_READ_UINT16(cpd->base+((regno&0x7) << cpd->addrsh), val);
448 diag_printf("read reg %02X val 0x%04x\n", regno, val);
453 static __inline__ void
454 put_reg(struct eth_drv_sc *sc, int regno, unsigned short val)
456 struct lan91c111_priv_data *cpd =
457 (struct lan91c111_priv_data *)sc->driver_private;
459 HAL_WRITE_UINT16(cpd->base+(LAN91C111_BS << cpd->addrsh), regno>>3);
460 HAL_WRITE_UINT16(cpd->base+((regno&0x7) << cpd->addrsh), val);
463 diag_printf("write reg %02X val 0x%04x\n", regno, val);
467 // ------------------------------------------------------------------------
468 // Assumes bank2 has been selected
469 static __inline__ void
470 put_data(struct eth_drv_sc *sc, unsigned short val)
472 struct lan91c111_priv_data *cpd =
473 (struct lan91c111_priv_data *)sc->driver_private;
475 HAL_WRITE_UINT16(cpd->base+((LAN91C111_DATA & 0x7) << cpd->addrsh), val);
478 diag_printf("write data 0x%04x\n", val);
482 // Assumes bank2 has been selected
483 static __inline__ unsigned short
484 get_data(struct eth_drv_sc *sc)
487 struct lan91c111_priv_data *cpd =
488 (struct lan91c111_priv_data *)sc->driver_private;
490 HAL_READ_UINT16(cpd->base+((LAN91C111_DATA & 0x7) << cpd->addrsh), val);
493 diag_printf("read data 0x%04x\n", val);
499 // Assumes bank2 has been selected
500 static __inline__ unsigned long
501 get_data32(struct eth_drv_sc *sc)
504 //unsigned long ret_val = 0;
505 struct lan91c111_priv_data *cpd =
506 (struct lan91c111_priv_data *)sc->driver_private;
508 HAL_READ_UINT32(cpd->base+((0x04) << cpd->addrsh), val);
509 //ret_val =((val&0xffff0000)>>16) | ((val&0xffff)<<16);
510 //diag_printf("val: %08X ret_val: %08X \n", val, ret_val);
513 diag_printf("read data 0x%08x\n", val);
525 // ------------------------------------------------------------------------
526 // Read the bank register (this one is bank-independent)
527 static __inline__ unsigned short
528 get_banksel(struct eth_drv_sc *sc)
532 struct lan91c111_priv_data *cpd =
533 (struct lan91c111_priv_data *)sc->driver_private;
537 HAL_READ_UINT16(cpd->base+(LAN91C111_BS << cpd->addrsh), val);
539 diag_printf("read bank val 0x%04x\n", val);
548 // ------------------------------------------------------------------------
549 #endif // CYGONCE_DEVS_ETH_SMSC_LAN91C111_LAN91C111_H
550 // EOF smsc_lan91c111.h