1 #ifndef CYGONCE_DEVS_ETH_SMSC_LAN92XX_LAN92XX_H
2 #define CYGONCE_DEVS_ETH_SMSC_LAN92XX_LAN92XX_H
3 //==========================================================================
7 // SMCS LAN9217 (LAN92XX compatible) Ethernet chip
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2003 Nick Garnett
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //####BSDCOPYRIGHTBEGIN####
45 // -------------------------------------------
47 // Portions of this software may have been derived from OpenBSD or other sources,
48 // and are covered by the appropriate copyright disclaimers included herein.
50 // -------------------------------------------
52 //####BSDCOPYRIGHTEND####
54 #include <cyg/hal/hal_io.h>
55 #include <cyg/hal/hal_endian.h>
58 #include CYGDAT_DEVS_ETH_SMSC_LAN92XX_CFG
68 // LAN92xx register offset
69 #define LAN92XX_RX_DATA 0x00
70 #define LAN92XX_TX_DATA 0x20
71 #define LAN92XX_RX_STATUS1 0x40
72 #define LAN92XX_RX_STATUS2 0x44
73 #define LAN92XX_TX_STATUS1 0x48
74 #define LAN92XX_TX_STATUS2 0x4C
75 #define LAN92XX_ID_REV 0x50
76 #define LAN92XX_IRQ_CFG 0x54
77 #define LAN92XX_INT_STS 0x58
78 #define LAN92XX_INT_EN 0x5C
79 #define LAN92XX_RESERVED1 0x60
80 #define LAN92XX_BYTE_TEST 0x64
81 #define LAN92XX_FIFO_INT 0x68
82 #define LAN92XX_RX_CFG 0x6C
83 #define LAN92XX_TX_CFG 0x70
84 #define LAN92XX_HW_CFG 0x74
85 #define LAN92XX_RX_DP_CTRL 0x78
86 #define LAN92XX_RX_FIFO_INF 0x7C
87 #define LAN92XX_TX_FIFO_INF 0x80
88 #define LAN92XX_PMT_CTRL 0x84
89 #define LAN92XX_GPIO_CFG 0x88
90 #define LAN92XX_GPT_CFG 0x8C
91 #define LAN92XX_GPT_CNT 0x90
92 #define LAN92XX_RESERVED2 0x94
93 #define LAN92XX_WORD_SWAP 0x98
94 #define LAN92XX_FREE_RUN 0x9C
95 #define LAN92XX_RX_DROP 0xA0
96 #define LAN92XX_MAC_CMD 0xA4
97 #define LAN92XX_MAC_DATA 0xA8
98 #define LAN92XX_AFC_CFG 0xAC
99 #define LAN92XX_E2P_CMD 0xB0
100 #define LAN92XX_E2P_DATA 0xB4
102 // Access these MAC registers indirectly through MAC_CMD and MAC_DATA
109 #define MAC_MII_ACC 6
110 #define MAC_MII_DATA 7
117 // These PHY registers are accessed indirectly through the MAC via the
118 // MII interface using the MII_ACC and MII_DATA registers. PHY controls
119 // the 802.3 physical layer such as 10/100Mbps, full/half mode.
134 #define PHY_100TX_FD 0x4000
135 #define PHY_100TX_HD 0x2000
136 #define PHY_10T_RD 0x1000
137 #define PHY_10T_HD 0x0800
138 #define PHY_LINK_ON 0x0004
140 #define IS_DUPLEX(x) ((x) & (PHY_100TX_FD | PHY_10T_RD))
142 #define MAC_TIMEOUT (1000 * 100)
145 #define E2P_CMD_SHIFT 28
146 #define E2P_CMD_BUSY 0x80000000
147 #define E2P_CMD_TIMEOUT 0x00000200
148 #define E2P_CMD_LOADED 0x00000100
151 E2P_CMD_READ = 0 << E2P_CMD_SHIFT,
152 E2P_CMD_EWDS = 1 << E2P_CMD_SHIFT,
153 E2P_CMD_EWEN = 2 << E2P_CMD_SHIFT,
154 E2P_CMD_WRITE = 3 << E2P_CMD_SHIFT,
155 E2P_CMD_WRAL = 4 << E2P_CMD_SHIFT,
156 E2P_CMD_ERASE = 5 << E2P_CMD_SHIFT,
157 E2P_CMD_ERAL = 6 << E2P_CMD_SHIFT,
158 E2P_CMD_Reload = 7 << E2P_CMD_SHIFT,
160 #define E2P_CMD(cmd, addr) (E2P_CMD_BUSY | (cmd) | (addr))
162 #define E2P_CONTEXT_ID 0xA5
170 unsigned char mac_addr[6];
173 #ifndef LAN92XX_REG_BASE
174 #define LAN92XX_REG_BASE PBC_BASE
177 #ifndef LAN92XX_REG_READ
178 #define LAN92XX_REG_READ(reg_offset) \
179 (*(volatile unsigned int *)(LAN92XX_REG_BASE + reg_offset))
182 #ifndef LAN92XX_REG_WRITE
183 #define LAN92XX_REG_WRITE(reg_offset, val) \
184 (*(volatile unsigned int *)(LAN92XX_REG_BASE + reg_offset) = (val))
187 #endif // CYGONCE_DEVS_ETH_SMSC_MAC_MAC_H