1 #ifndef CYGONCE_DEVS_FLASH_BOARD_STRATAFLASH_INL
2 #define CYGONCE_DEVS_FLASH_BOARD_STRATAFLASH_INL
3 //==========================================================================
5 // board_strataflash.inl
7 // Flash programming - device constants, etc.
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
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41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): gthomas, hmt
46 // Contributors: gthomas
51 //####DESCRIPTIONEND####
53 //==========================================================================
55 // Intel Flash configuration: Buffered Read Block
56 // write query locking
57 // 28FxxxB3 - Bootblock - no no no
58 // 28FxxxC3 - StrataFlash - no yes yes
59 // 28FxxxJ3 - Advanced StrataFlash - yes yes yes
60 // 28FxxxK3 - Synchronous StrataFlash - yes yes yes
62 // These options are controlled by defining or not, in that include file,
63 // these symbols (not CDL options, just symbols - though they could be CDL
65 // CYGOPT_FLASH_IS_BOOTBLOCK - for xxxB3 devices.
66 // CYGOPT_FLASH_IS_NOT_ADVANCED - for xxxC3 devices.
67 // CYGOPT_FLASH_IS_SYNCHRONOUS - for xxxK3 devices.
68 // none of the above - for xxxJ3 devices.
69 // (Advanced seems to be usual these days hence the sense of that opt)
71 // Other properties are controlled by these symbols:
72 // CYGNUM_FLASH_DEVICES number of devices across the databus
73 // CYGNUM_FLASH_WIDTH number of bits in each device
74 // CYGNUM_FLASH_BLANK 1 if blank is allones, 0 if 0
75 // CYGNUM_FLASH_BASE base address
76 // CYGNUM_FLASH_BASE_MASK a mask to get base address from any
78 // for example, a 32-bit memory could be made from 1x32bit, 2x16bit or
79 // 4x8bit devices; usually 16bit ones are chosen in practice, so we would
80 // have CYGNUM_FLASH_DEVICES = 2, and CYGNUM_FLASH_WIDTH = 16. Both
81 // devices would be handled simulataneously, via 32bit bus operations.
82 // Some CPUs can handle a single 16bit device as 32bit memory "by magic".
83 // In that case, CYGNUM_FLASH_DEVICES = 1 and CYGNUM_FLASH_WIDTH = 16, and
84 // the device is managed using only 16bit bus operations.
87 // The NOR flash type of the i.300-30 ADS board is a StrataFlash 28F256L18B.
88 // The 256 means 256Mbit, so 16M x 16bit. 16bits width.
89 // but There are 2 chips and there conf depends on Three resistors:
91 #define I30030ADS_FLASH_DEF_CONF
93 #ifdef I30030ADS_FLASH_DEF_CONF
94 //by default the two 28F256L18B are configured in parallel so 32 bits width: 16Mx32bits
96 #define CYGNUM_FLASH_DEVICES (1)
97 #define CYGNUM_FLASH_BASE (0xA0000000u)
98 #define CYGNUM_FLASH_BASE_MASK (0xFF000000u) // 16MB devices (size=0x01000000 -> mask=0xFF000000)
99 #define CYGNUM_FLASH_WIDTH (16) // width of one device
100 #define CYGNUM_FLASH_BLANK (1)
102 #define CYGOPT_FLASH_IS_SYNCHRONOUS
103 #define CYGOPT_FLASH_IS_BOOTBLOCK 1
105 #endif //I30030ADS_FLASH_DEF_CONF
107 #endif // CYGONCE_DEVS_FLASH_BOARD_STRATAFLASH_INL
108 // ------------------------------------------------------------------------