packages/devs/flash/arm/mxc/v2_0/include/card_mx32.h

   1 #ifndef CARD_MX32_H
   2 #define CARD_MX32_H
   3
   4 #include <cyg/infra/cyg_type.h>
   5
   6 /*sdhc memory map*/
   7 typedef struct _sdhc
   8 {
   9     cyg_uint32 sdhc_clk;
  10     cyg_uint32 sdhc_status;
  11     cyg_uint32 sdhc_clk_rate;
  12     cyg_uint32 sdhc_dat_cont;
  13     cyg_uint32 sdhc_response_to;
  14     cyg_uint32 sdhc_read_to;
  15     cyg_uint32 sdhc_blk_len;
  16     cyg_uint32 sdhc_nob;
  17     cyg_uint32 sdhc_rev_no;
  18     cyg_uint32 sdhc_int_cntr;
  19     cyg_uint32 sdhc_cmd;
  20     cyg_uint32 sdhc_arg;
  21     cyg_uint32 sdhc_reserved;
  22     cyg_uint32 sdhc_res_fifo;
  23     cyg_uint32 sdhc_buffer_access;
  24 }sdhc_t, *psdhc_t;
  25
  26 /* Defines for card types */
  27 typedef enum
  28 {
  29         TYPE_NONE,
  30         SD_CSD_1_0,
  31         SD_CSD_2_0,
  32         MMC_CSD_1_0,
  33         MMC_CSD_1_1,
  34         MMC_CSD_1_2,
  35         MMC_UNKNOWN
  36 }card_type;
  37
  38 typedef struct _card_specific_data
  39 {
  40         cyg_uint32 csd0;
  41         cyg_uint32 csd1;
  42         cyg_uint32 csd2;
  43         cyg_uint32 csd3;
  44 }CARD_SPECIFIC_DATA;
  45
  46 /* Defines for card types */
  47 typedef struct _card_id
  48 {
  49         cyg_uint32 cid0;
  50         cyg_uint32 cid1;
  51         cyg_uint32 cid2;
  52         cyg_uint32 cid3;
  53 }CARD_ID;
  54
  55 enum sdhc_clk_val
  56 {
  57     SDHC_CLK_START = 0x2,
  58     SDHC_CLK_STOP = 0x1,
  59     SDHC_CLK_RESET = 0x8
  60 };
  61
  62 typedef enum frequency_mode
  63 {
  64         iden_mode = 0x1,
  65         trans_mode = 0x2
  66 } frequency_mode_t;
  67
  68 typedef struct command
  69 {
  70         cyg_uint32 index;
  71         cyg_uint32 data_control;
  72         cyg_uint32 arg;
  73 }command_t;
  74
  75
  76 #define NO_ARG 0
  77 #define ENABLE 1
  78 #define DISABLE 0
  79 #define PASS 0
  80 #define SUCCESS 0
  81 #define FAIL 1
  82
  83 #define CARD_STATE 0x1E00
  84 #define CARD_STATE_SHIFT 9
  85
  86 /*Defines of CSD data*/
  87 #define CSD_STRUCT_MSK 0x00C00000
  88 #define CSD_STRUCT_SHIFT        22
  89
  90
  91 /* Define the states of the card*/
  92 enum states
  93 {
  94         IDLE,
  95         READY,
  96         IDENT,
  97         STBY,
  98         TRAN,
  99         DATA,
 100         RCV,
 101         PRG,
 102         DIS
 103 };
 104
 105
 106 /* SDHC Response */
 107 typedef struct _response
 108 {
 109     cyg_uint32 rsp0;
 110     cyg_uint32 rsp1;
 111     cyg_uint32 rsp2;
 112     cyg_uint32 rsp3;
 113 }response_t;
 114
 115
 116 typedef enum card_mode
 117 {
 118         NONE = 0,
 119         SD = 1,
 120         MMC = 2
 121 }card_mode_t;
 122
 123 enum RW
 124 {
 125         READ = 0,
 126         WRITE = 1
 127 };
 128
 129 enum cmd_response
 130 {
 131         RESPONSE_NO = 0x0,
 132         RESPONSE_48_CRC = 0x1,
 133         RESPONSE_136 = 0x2,
 134         RESPONSE_48_WITHOUT_CRC = 0x3
 135 };
 136
 137 enum status_bus_width
 138 {
 139         ONE = 0x0,
 140         FOUR = 0x2
 141 };
 142
 143
 144 #define SDHC_INT                  0xc015
 145
 146 #define OCR_VALUE 0x80ff8000
 147 #define OCR_VALUE_MASK 0x00ff8000
 148 #define CARD_BUSY 0x80000000
 149 #define SD_R1_APP_CMD_MSK 0x20
 150
 151 #define BLOCK_LEN 0x200
 152
 153
 154
 155 /* Status regsiter Masks */
 156 #define SDHC_STATUS_END_CMD_RESP_MSK          0x2000
 157 #define SDHC_STATUS_WRITE_OP_DONE_MSK         0x1000
 158 #define SDHC_STATUS_READ_OP_DONE_MSK          0x800
 159 #define SDHC_STATUS_WR_CRC_ERR_CODE_MSK       0x600
 160 #define SDHC_STATUS_CARD_BUS_CLK_RUN_MSK               0x100
 161 #define SDHC_STATUS_RESP_CRC_ERR_MSK          0x20
 162 #define SDHC_STATUS_BUF_READ_RDY_MSK          0x80
 163 #define SDHC_STATUS_BUF_WRITE_RDY_MSK         0x40
 164 #define SDHC_STATUS_READ_CRC_ERR_MSK          0x8
 165 #define SDHC_STATUS_WRITE_CRC_ERR_MSK         0x4
 166 #define SDHC_STATUS_TIME_OUT_RESP_MSK         0x2
 167 #define SDHC_STATUS_TIME_OUT_READ             0x1
 168
 169 #define SDHC_STATUS_CLEAR                     ((cyg_uint32)(0xC0007E2F))
 170
 171
 172
 173 /* Command (data control) masks */
 174 #define SDHC_CMD_FROMAT_OF_RESP      0x00000007
 175 #define SDHC_CMD_DATA_ENABLE         0x00000008
 176 #define SDHC_CMD_WRITE_READ          0x00000010
 177 #define SDHC_CMD_INIT                0x00000080
 178 #define SDHC_CMD_BUS_WIDTH           0x00000300
 179 #define SDHC_CMD_START_READWAIT     0x00000400
 180 #define SDHC_CMD_STOP_READWAIT      0x00000800
 181 #define SDHC_CMD_DATA_CTRL_CMD_RESP_LONG_OFF   0x00001000
 182
 183 /* Command (data control) shift */
 184 #define SDHC_CMD_FROMAT_OF_RESP_SHIFT     0x0
 185 #define SDHC_CMD_DATA_ENABLE_SHIFT        0x3
 186 #define SDHC_CMD_BUS_WIDTH_SHIFT          0x8
 187 #define SDHC_CMD_WRITE_READ_SHIFT         0x4
 188 #define SDHC_CMD_INIT_SHIFT               0x7
 189
 190 //#define SDHC_CMD_FROMAT_OF_RESP_NONE      0x0
 191 //#define SDHC_CMD_DATA_CTRL_FROMAT_OF_RESP_48        0x1
 192 //#define SDHC_CMD_DATA_CTRL_FROMAT_OF_RESP_136       0x2
 193 //#define SDHC_CMD_DATA_CTRL_FROMAT_OF_RESP_48_N0_CRC 0x3
 194 //#define SDHC_CMD_DATA_CTRL_BUS_WIDTH_1_BIT          0x0
 195 //#define SDHC_CMD_DATA_CTRL_BUS_WIDTH_4_BIT          0x2
 196
 197 /* Define  each command */
 198 enum commands
 199 {
 200         CMD0= 0,
 201         CMD1= 1,
 202         CMD2= 2,
 203         CMD3= 3,
 204         CMD5= 5,
 205         CMD6=6,
 206         ACMD6= 6,
 207         CMD7= 7,
 208         CMD8 = 8,
 209         CMD9=9,
 210         CMD12   = 12,
 211         CMD13   = 13,
 212         CMD16   = 16,
 213         CMD17   = 17,
 214         CMD18   = 18,
 215         CMD24   = 24,
 216         CMD25   = 25,
 217         CMD26   = 26,
 218         CMD32   = 32,
 219         CMD33   = 33,
 220         CMD35   = 35,
 221         CMD36   = 36,
 222         CMD38   = 38,
 223         ACMD41  = 41,
 224         ACMD51  = 51,
 225         CMD55   = 55
 226 };
 227
 228 extern cyg_uint32 CCC; /* Card Command Class */
 229
 230 extern cyg_uint32 mxcmci_init (cyg_uint32 bus_width, cyg_uint32 base_address);
 231 extern cyg_uint32 mmc_data_write (cyg_uint32 *src_ptr,cyg_uint32 length,cyg_uint32 offset);
 232 extern cyg_uint32 mmc_data_erase (cyg_uint32 offset, cyg_uint32 size);
 233 extern cyg_uint32 mmc_data_read (cyg_uint32 *,cyg_uint32 ,cyg_uint32);
 234 extern cyg_uint32 card_flash_query(void* data);
 235 extern cyg_uint32 card_get_capacity_size (void);
 236
 237 struct csd_v1_0 {
 238         cyg_uint32 rsv3:1,
 239         crc:7,
 240         rsv2:2,
 241         file_format:2,
 242         tmp_write_protect:1,
 243         perm_write_protect:1,
 244         copy:1,
 245         file_format_grp:1,
 246         rsv1:5,
 247         write_bl_partial:1,
 248         write_bl_len:4,
 249         r2w_factor:3,
 250         rsv0:2,
 251         wp_grp_enable:1;
 252         cyg_uint32 wp_grp_size:7,
 253         sector_size:7,
 254         erase_blk_en:1,
 255         c_size_mult:3,
 256         vdd_w_curr_max:3,
 257         vdd_w_curr_min:3,
 258         vdd_r_curr_max:3,
 259         vdd_r_curr_min:3,
 260         c_size_lo:2;
 261     cyg_uint32 c_size_up:10,
 262         rsv4:2,
 263         dsr_imp:1,
 264         read_blk_misalign:1,
 265         write_blk_misalign:1,
 266         read_bl_partial:1,
 267         read_bl_len:4,
 268         ccc:12;
 269     cyg_uint32 tran_speed:8,
 270         nsac:8,
 271         taac:8,
 272         rsv5:6,
 273         csd_structure:2;
 274 } __attribute__ ((packed));
 275
 276 struct csd_v2_0 {
 277         cyg_uint32
 278         rsv3:1,
 279         crc:7,
 280         rsv2:2,
 281         file_format:2,
 282         tmp_write_protect:1,
 283         perm_write_protect:1,
 284         copy:1,
 285         file_format_grp:1,
 286         rsv1:5,
 287         write_bl_partial:1,
 288         write_bl_len:4,
 289         r2w_factor:3,
 290         rsv0:2,
 291         wp_grp_enable:1;
 292         cyg_uint32
 293         wp_grp_size:7,
 294         sector_size:7,
 295         erase_blk_en:1,
 296         rsv9:1,
 297         c_size_lo:16;
 298     cyg_uint32
 299         c_size_up:6,
 300         rsv4:6,
 301         dsr_imp:1,
 302         read_blk_misalign:1,
 303         write_blk_misalign:1,
 304         read_bl_partial:1,
 305         read_bl_len:4,
 306         ccc:12;
 307     cyg_uint32 tran_speed:8,
 308         nsac:8,
 309         taac:8,
 310         rsv5:6,
 311         csd_structure:2;
 312 } __attribute__ ((packed));
 313
 314 #endif