1 #ifndef CYGONCE_DEVS_FLASH_INTEL_28FXXX_INL
2 #define CYGONCE_DEVS_FLASH_INTEL_28FXXX_INL
3 //==========================================================================
7 // Intel 28Fxxx series flash driver
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2002 Gary Thomas
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //==========================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: jskov
52 // Notes: Device table could use unions of flags to save some space
54 //####DESCRIPTIONEND####
56 //==========================================================================
58 #include <pkgconf/hal.h>
59 #include <pkgconf/io_flash.h>
60 #include <pkgconf/devs_flash_intel_28fxxx.h>
62 #include <cyg/hal/hal_arch.h>
63 #include <cyg/hal/hal_cache.h>
64 #include CYGHWR_MEMORY_LAYOUT_H
66 #include <cyg/hal/hal_io.h>
68 #define _FLASH_PRIVATE_
69 #include <cyg/io/flash.h>
75 typedef void (*call_t)(char* str, ...);
76 extern void diag_printf(char* str, ...);
77 call_t d_print = &diag_printf;
79 //----------------------------------------------------------------------------
80 // Common device details.
82 #define FLASH_BOOTBLOCKS_PER_BLOCK 4
84 #define FLASH_Read_ID FLASHWORD( 0x90 )
85 #define FLASH_Reset FLASHWORD( 0xFF )
86 #define FLASH_Program FLASHWORD( 0x40 )
87 #define FLASH_Write_Buffer FLASHWORD( 0xe8 )
88 #define FLASH_Block_Erase FLASHWORD( 0x20 )
89 #define FLASH_Confirm FLASHWORD( 0xD0 )
90 #define FLASH_Resume FLASHWORD( 0xD0 )
92 #define FLASH_Set_Lock FLASHWORD( 0x60 )
93 #define FLASH_Set_Lock_Confirm FLASHWORD( 0x01 )
94 #define FLASH_Clear_Lock FLASHWORD( 0x60 )
95 #define FLASH_Clear_Lock_Confirm FLASHWORD( 0xd0 )
96 #define FLASH_Lock_State_Mask FLASHWORD( 0x03 )
97 #define FLASH_Status_Locked FLASHWORD( 0x01 )
99 #define FLASH_Read_Status FLASHWORD( 0x70 )
100 #define FLASH_Clear_Status FLASHWORD( 0x50 )
101 #define FLASH_Status_Ready FLASHWORD( 0x80 )
103 // Status that we read back:
104 #define FLASH_ErrorMask FLASHWORD( 0x7E )
105 #define FLASH_ErrorProgram FLASHWORD( 0x10 )
106 #define FLASH_ErrorErase FLASHWORD( 0x20 )
107 #define FLASH_ErrorLock FLASHWORD( 0x30 )
108 #define FLASH_ErrorLowVoltage FLASHWORD( 0x08 )
109 #define FLASH_ErrorLocked FLASHWORD( 0x02 )
111 // Platform code must define the below
112 // #define CYGNUM_FLASH_INTERLEAVE : Number of interleaved devices (in parallel)
113 // #define CYGNUM_FLASH_SERIES : Number of devices in series
114 // #define CYGNUM_FLASH_WIDTH : Width of devices on platform
115 // #define CYGNUM_FLASH_BASE : Address of first device
117 #define CYGNUM_FLASH_BLANK (1)
118 #define CYGNUM_FLASH_DEVICES (CYGNUM_FLASH_INTERLEAVE*CYGNUM_FLASH_SERIES)
121 # define FLASH_P2V( _a_ ) ((volatile flash_data_t *)((CYG_ADDRWORD)(_a_)))
123 #ifndef CYGHWR_FLASH_28FXXX_PLF_INIT
124 # define CYGHWR_FLASH_28FXXX_PLF_INIT()
126 #ifndef CYGHWR_FLASH_WRITE_ENABLE
127 #define CYGHWR_FLASH_WRITE_ENABLE()
129 #ifndef CYGHWR_FLASH_WRITE_DISABLE
130 #define CYGHWR_FLASH_WRITE_DISABLE()
133 //----------------------------------------------------------------------------
134 // Now that device properties are defined, include magic for defining
135 // accessor type and constants.
136 #include <cyg/io/flash_dev.h>
138 //----------------------------------------------------------------------------
139 // Information about supported devices
140 typedef struct flash_dev_info {
141 flash_data_t device_id;
142 cyg_uint32 block_size;
143 cyg_int32 block_count;
144 cyg_uint32 base_mask;
145 cyg_uint32 device_size;
146 cyg_bool locking; // supports locking
147 cyg_bool buffered_w; // supports buffered writes
149 cyg_uint32 bootblocks[12]; // 0 is bootblock offset, 1-11 sub-sector sizes (or 0)
151 cyg_uint32 banks[2]; // bank offets, highest to lowest (lowest should be 0)
152 // (only one entry for now, increase to support devices
156 // Information about stacked die devices
157 typedef struct flash_stacked_die_dev_info {
158 flash_data_t device_id;
159 cyg_uint32 num_blocks_1;
160 cyg_uint32 num_blocks_2;
161 cyg_uint32 num_bytes_1;
162 cyg_uint32 num_bytes_2;
164 cyg_uint32 dev_start;
165 } flash_stacked_die_dev_info_t;
167 static const flash_dev_info_t* flash_dev_info;
168 static const flash_dev_info_t supported_devices[] = {
169 #include <cyg/io/flash_28fxxx_parts.inl>
172 static flash_stacked_die_dev_info_t sdi[CYGNUM_FLASH_SERIES];
174 #define NUM_DEVICES (sizeof(supported_devices)/sizeof(flash_dev_info_t))
177 //----------------------------------------------------------------------------
178 // Functions that put the flash device into non-read mode must reside
181 void flash_query(void* data) __attribute__ ((section (".2ram.flash_query")));
183 int flash_erase_block(void* block, unsigned int size)
184 __attribute__ ((section (".2ram.flash_erase_block")));
185 int flash_program_buf(void* addr, void* data, int len,
186 unsigned long block_mask, int buffer_size)
187 __attribute__ ((section (".2ram.flash_program_buf")));
188 int flash_lock_block(void* addr)
189 __attribute__ ((section (".2ram.flash_lock_block")));
190 int flash_unlock_block(void* block, int block_size, int blocks, void *)
191 __attribute__ ((section (".2ram.flash_unlock_block")));
192 //----------------------------------------------------------------------------
195 // Initialize driver details
202 CYGHWR_FLASH_28FXXX_PLF_INIT();
206 // Look through table for device data
207 flash_dev_info = supported_devices;
208 for (i = 0; i < NUM_DEVICES; i++) {
210 if (flash_dev_info->device_id == id[1])
215 // Did we find the device? If not, return error.
216 if (NUM_DEVICES == i){
217 return FLASH_ERR_DRV_WRONG_PART;
220 // Hard wired for now
221 flash_info.block_size = flash_dev_info->block_size;
222 flash_info.blocks = flash_dev_info->block_count * CYGNUM_FLASH_SERIES;
223 flash_info.start = (void *)CYGNUM_FLASH_BASE;
224 flash_info.end = (void *)(CYGNUM_FLASH_BASE+ (flash_dev_info->device_size * CYGNUM_FLASH_SERIES));
229 //----------------------------------------------------------------------------
230 // Map a hardware status to a package error
232 flash_hwr_map_error(int e)
237 //----------------------------------------------------------------------------
238 // See if a range of FLASH addresses overlaps currently running code
240 flash_code_overlaps(void *start, void *end)
242 extern unsigned char _stext[], _etext[];
244 return ((((unsigned long)&_stext >= (unsigned long)start) &&
245 ((unsigned long)&_stext < (unsigned long)end)) ||
246 (((unsigned long)&_etext >= (unsigned long)start) &&
247 ((unsigned long)&_etext < (unsigned long)end)));
250 //----------------------------------------------------------------------------
253 // Only reads the manufacturer and part number codes for the first
254 // device(s) in series. It is assumed that any devices in series
255 // will be of the same type.
258 flash_query(void* data)
260 volatile flash_data_t *ROM;
261 flash_data_t* id = (flash_data_t*) data;
263 unsigned long flash_base;
264 unsigned long max_erase_time;
266 unsigned long max_write_buffer;
267 unsigned long block_size;
268 unsigned short val1, val2;
269 unsigned long nblocks1; // number of blocks in 1st section
270 unsigned long nblocks2; // number of blocks in 2nd section
271 unsigned long bsize1; // blocksize in 1st section
272 unsigned long bsize2; // blocksize in 2nd section
275 ROM = FLASH_P2V(CYGNUM_FLASH_BASE);
279 CYGHWR_FLASH_WRITE_ENABLE();
281 ROM[0] = FLASH_Read_ID;
283 // Manufacturers' code
288 ROM[0] = FLASH_Reset;
289 //Stall, waiting for flash to return to read mode.
292 flash_base = CYGNUM_FLASH_BASE;
293 for (j = 0; j < CYGNUM_FLASH_SERIES; j++) {
294 ROM = FLASH_P2V(flash_base);
295 ROM[0] = 0x0050; // clear status register
296 ROM[0] = 0x0098; // read query
297 ROM = FLASH_P2V(flash_base + (0x10 << 1));
298 if (ROM[0] != 0x0051) { //Q
300 d_print("error reading flash attribute space Q\n");
302 ROM = FLASH_P2V(flash_base);
303 ROM[0] = 0x00ff; // read array / reset
304 //return FLASH_ERR_DRV_WRONG_PART;
307 d_print("read flash attribute space Q ok\n");
310 ROM = FLASH_P2V(flash_base + (0x11 << 1));
311 if (ROM[0] != 0x0052) { //R
313 d_print("error reading flash attribute space R\n");
315 ROM = FLASH_P2V(flash_base);
316 ROM[0] = 0x00ff; // read array / reset
317 //return FLASH_ERR_DRV_WRONG_PART;
320 d_print("read flash attribute space R ok\n");
323 ROM = FLASH_P2V(flash_base + (0x12 << 1));
324 if (ROM[0] != 0x0059) { //Y
326 d_print("error reading flash attribute space Y\n");
328 ROM = FLASH_P2V(flash_base);
329 ROM[0] = 0x00ff; // read array / reset
330 //return FLASH_ERR_DRV_WRONG_PART;
333 d_print("read flash attribute space Y ok\n");
336 ROM = FLASH_P2V(flash_base + (0x25 << 1));
337 max_erase_time = ROM[0]; // "n" such that the max block erase time = 2^n
338 max_erase_time = 1 << (max_erase_time & 0xffff); // convert erase time 2^n to the number of seconds
340 ROM = FLASH_P2V(flash_base + (0x27 << 1));
341 dsize = ROM[0]; // "n" such that the device size = 2^n in number of bytes
342 dsize = 1 << (dsize & 0xffff); // convert data size from 2^n to the number of bytes
344 ROM = FLASH_P2V(flash_base + (0x2a << 1));
345 max_write_buffer = ROM[0]; // "n" such that the max num of bytes in write buffer = 2^n
346 max_write_buffer = (1 << (max_write_buffer & 0xffff)) / 2; // convert from 2^n bytes to the number of words
348 ROM = FLASH_P2V(flash_base + (0x2d << 1));
350 ROM = FLASH_P2V(flash_base + (0x2e << 1));
352 nblocks1 = (val1 + (val2 << 8)) + 1;
354 ROM = FLASH_P2V(flash_base + (0x31 << 1));
356 ROM = FLASH_P2V(flash_base + (0x32 << 1));
358 nblocks2 = (val1 + (val2 << 8)) + 1;
360 ROM = FLASH_P2V(flash_base + (0x2f << 1));
362 ROM = FLASH_P2V(flash_base + (0x30 << 1));
364 bsize1 = (val1 + (val2 << 8)) * 256;
366 ROM = FLASH_P2V(flash_base + (0x33 << 1));
368 ROM = FLASH_P2V(flash_base + (0x34 << 1));
370 bsize2 = (val1 + (val2 << 8)) * 256;
372 block_size = bsize1/2;
374 ROM = FLASH_P2V(flash_base);
375 ROM[0] = 0x00ff; // read array / reset
377 sdi[j].device_id = 0;
378 sdi[j].num_blocks_1 = nblocks1;
379 sdi[j].num_blocks_2 = nblocks2;
380 sdi[j].num_bytes_1 = bsize1;
381 sdi[j].num_bytes_2 = bsize2;
382 sdi[j].dev_size = dsize;
383 sdi[j].dev_start = flash_base;
385 d_print("number of blocks in region 1: %d\n", sdi[j].num_blocks_1);
386 d_print("number of blocks in region 2: %d\n", sdi[j].num_blocks_2);
387 d_print("number of bytes in region 1: %lu (0x%04X)\n", sdi[j].num_bytes_1, sdi[j].num_bytes_1);
388 d_print("number of bytes in region 2: %lu (0x%04X)\n", sdi[j].num_bytes_2, sdi[j].num_bytes_2);
389 d_print("Device size = %ld Mbytes (0x%lx)\n",sdi[j].dev_size/1024/1024 ,sdi[j].dev_size);
390 d_print("max. erase time is %d nseconds\n", max_erase_time);
391 d_print("number of words for write buffer are %d\n\n\n\n", max_write_buffer);
393 flash_info.buffer_size = max_write_buffer;
396 CYGHWR_FLASH_WRITE_DISABLE();
399 //----------------------------------------------------------------------------
402 flash_erase_block(void* block, unsigned int block_size)
404 int res = FLASH_ERR_OK;
408 volatile flash_data_t *ROM;
409 int j, die_number, blocks_to_do;
410 unsigned long phys_block_length;
411 volatile flash_data_t *b_p = (flash_data_t*) block;
412 volatile flash_data_t *b_v;
415 ROM = FLASH_P2V((unsigned long)block & flash_dev_info->base_mask);
417 // check out which die we have to handle
419 for (j = 0; j < CYGNUM_FLASH_SERIES; j++) {
420 if (((unsigned long)block >= sdi[j].dev_start) &&
421 ((unsigned long)block < (sdi[j].dev_start + sdi[j].dev_size))) {
426 if (die_number == 0) {
428 d_print("\n\ndid not found a valid die number \n\n");
430 return FLASH_ERR_DRV_WRONG_PART;
433 // check out which area we have to handle inside the die
434 if ((unsigned long)block < sdi[die_number - 1].dev_start +
435 sdi[die_number - 1].num_blocks_1 *
436 sdi[die_number - 1].num_bytes_1) {
437 // we stay in flash region 1
438 phys_block_length = sdi[die_number - 1].num_bytes_1;
439 if (sdi[die_number - 1].num_bytes_1 > sdi[die_number - 1].num_bytes_2) {
440 blocks_to_do = 1; // this is no boot block area
443 blocks_to_do = FLASH_BOOTBLOCKS_PER_BLOCK; //sdi[die_number - 1].num_bytes_2 / sdi[die_number - 1].num_bytes_1; // this is a bootblock area
447 // we stay in flash region 2
448 phys_block_length = sdi[die_number - 1].num_bytes_2;
449 if (sdi[die_number - 1].num_bytes_2 > sdi[die_number - 1].num_bytes_1) {
450 blocks_to_do = 1; // this is no boot block area
453 blocks_to_do = FLASH_BOOTBLOCKS_PER_BLOCK; //sdi[die_number - 1].num_bytes_1 / sdi[die_number - 1].num_bytes_2; // this is a bootblock area
458 len = phys_block_length;
460 CYGHWR_FLASH_WRITE_ENABLE();
462 b_v = FLASH_P2V(b_p);
464 // Clear any error conditions
465 *b_v = FLASH_Clear_Status;
468 *b_v = FLASH_Block_Erase;
469 *b_v = FLASH_Confirm;
472 while (((stat = *b_v) & FLASH_Status_Ready) != FLASH_Status_Ready) {
473 if (--timeout == 0) break;
476 // Restore ROM to "normal" mode
479 if (stat & FLASH_ErrorMask) {
480 if (!(stat & FLASH_ErrorErase)) {
481 res = FLASH_ERR_HWR; // Unknown error
483 if (stat & FLASH_ErrorLowVoltage)
484 res = FLASH_ERR_LOW_VOLTAGE;
485 else if (stat & FLASH_ErrorLocked)
486 res = FLASH_ERR_PROTECT;
488 res = FLASH_ERR_ERASE;
492 // Check if block got erased
495 b_v = FLASH_P2V(b_p);
497 if (*b_v != FLASH_BlankValue ) {
498 // Only update return value if erase operation was OK
499 if (FLASH_ERR_OK == res) res = FLASH_ERR_DRV_VERIFY;
507 len = phys_block_length;
513 CYGHWR_FLASH_WRITE_DISABLE();
518 //----------------------------------------------------------------------------
521 flash_program_buf(void* addr, void* data, int len,
522 unsigned long block_mask, int buffer_size)
524 flash_data_t stat = 0;
527 volatile flash_data_t* ROM;
529 volatile flash_data_t* addr_v;
530 volatile flash_data_t* addr_p = (flash_data_t*) addr;
531 volatile flash_data_t* data_p = (flash_data_t*) data;
532 int res = FLASH_ERR_OK;
535 d_print("programming at address: 0x%08X length: 0x%08X buffer_size: 0x%08X\n",
536 (unsigned long)addr, (unsigned long)len, (unsigned long)buffer_size);
538 // Base address of device(s) being programmed.
539 ROM = FLASH_P2V((unsigned long)addr & flash_dev_info->base_mask);
541 CYGHWR_FLASH_WRITE_ENABLE();
543 // Clear any error conditions
544 ROM[0] = FLASH_Clear_Status;
546 if (len/sizeof( flash_data_t ) >= buffer_size){
547 words_to_write = buffer_size; //full buffer
549 words_to_write = len / sizeof( flash_data_t );
554 addr_v = FLASH_P2V(addr_p);
555 addr_p += words_to_write;
558 while (--timeout>0) {
559 *addr_v = FLASH_Write_Buffer;
561 //d_print("\nstatus after FLASH_WRITE_BUFFER command is 0x%08X\n", stat);
562 if (stat & FLASH_Status_Ready)
566 res = FLASH_ERR_DRV_TIMEOUT;
570 *addr_v = words_to_write - 1; // write word count
572 for (i = 0; i < words_to_write; i++) {
573 *(addr_v+i) = *(data_p+i);
576 *addr_v = FLASH_Confirm;
579 while (((stat = *addr_v) & FLASH_Status_Ready) != FLASH_Status_Ready) {
580 if (--timeout == 0) {
582 d_print("status is 0x%08X \n", stat);
584 res = FLASH_ERR_DRV_TIMEOUT;
589 d_print("address pointer : 0x%08X\n", (unsigned long)addr_v);
590 d_print("status register is: 0x%08X\n", stat);
592 if (stat & FLASH_ErrorMask) {
593 if (!(stat & FLASH_ErrorProgram))
594 res = FLASH_ERR_HWR; // Unknown error
596 if (stat & FLASH_ErrorLowVoltage)
597 res = FLASH_ERR_LOW_VOLTAGE;
598 else if (stat & FLASH_ErrorLocked)
599 res = FLASH_ERR_PROTECT;
601 res = FLASH_ERR_PROGRAM;
605 *addr_v = FLASH_Clear_Status;
606 *addr_v = FLASH_Reset;
607 for (i = 0; i < words_to_write; i++) {
608 if (*(addr_v+i) != *(data_p+i)) {
609 res = FLASH_ERR_DRV_VERIFY;
613 data_p += words_to_write;
614 if (words_to_write == buffer_size) {
615 len -= (buffer_size*sizeof(flash_data_t));
621 // Restore ROM to "normal" mode
623 ROM[0] = FLASH_Reset;
625 CYGHWR_FLASH_WRITE_DISABLE();
627 // Ideally, we'd want to return not only the failure code, but also
628 // the address/device that reported the error.
632 #ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
633 //----------------------------------------------------------------------------
636 flash_lock_block(void* block)
638 volatile flash_data_t *ROM;
639 int res = FLASH_ERR_OK;
641 int timeout = 5000000;
642 volatile flash_data_t* b_p = (flash_data_t*) block;
643 volatile flash_data_t *b_v;
646 int j, die_number, blocks_to_do;
647 unsigned long phys_block_length;
649 if (!flash_dev_info->locking)
653 d_print("flash_lock_block %08x\n", block);
655 ROM = FLASH_P2V((unsigned long)block & flash_dev_info->base_mask);
657 // check out which die we have to handle
659 for (j = 0; j < CYGNUM_FLASH_SERIES; j++) {
660 if (((unsigned long)block >= sdi[j].dev_start)&&((unsigned long)block < (sdi[j].dev_start + sdi[j].dev_size))) {
665 if (die_number == 0) {
667 d_print("\n\ndid not found a valid die number \n\n");
669 return FLASH_ERR_DRV_WRONG_PART;
672 // check out which area we have to handle inside the die
673 if ((unsigned long)block < sdi[die_number - 1].dev_start + sdi[die_number - 1].num_blocks_1 * sdi[die_number - 1].num_bytes_1) {
674 // we stay in flash region 1
675 phys_block_length = sdi[die_number - 1].num_bytes_1;
676 if (sdi[die_number - 1].num_bytes_1 > sdi[die_number - 1].num_bytes_2) {
677 blocks_to_do = 1; // this is no boot block area
680 blocks_to_do = FLASH_BOOTBLOCKS_PER_BLOCK; //sdi[die_number - 1].num_bytes_2 / sdi[die_number - 1].num_bytes_1; // this is a bootblock area
684 // we stay in flash region 2
685 phys_block_length = sdi[die_number - 1].num_bytes_2;
686 if (sdi[die_number - 1].num_bytes_2 > sdi[die_number - 1].num_bytes_1) {
687 blocks_to_do = 1; // this is no boot block area
690 blocks_to_do = FLASH_BOOTBLOCKS_PER_BLOCK; //sdi[die_number - 1].num_bytes_1 / sdi[die_number - 1].num_bytes_2; // this is a bootblock area
694 len = phys_block_length;
696 CYGHWR_FLASH_WRITE_ENABLE();
700 d_print("locking block at address 0x%08X\n", (unsigned long)b_p);
702 b_v = FLASH_P2V(b_p);
704 // Clear any error conditions
705 *b_v = FLASH_Clear_Status;
708 *b_v = FLASH_Set_Lock;
709 *b_v = FLASH_Set_Lock_Confirm; // Confirmation
710 *(b_v + 2) = FLASH_Read_ID ;
711 while (((state = *(b_v + 2)) & FLASH_Lock_State_Mask) != FLASH_Status_Locked) {
712 if (--timeout == 0) {
713 res = FLASH_ERR_DRV_TIMEOUT;
718 // Restore ROM to "normal" mode
722 b_p += len / sizeof( flash_data_t );
724 if (FLASH_ErrorLock == (state & FLASH_ErrorLock))
725 res = FLASH_ERR_LOCK;
727 if (res != FLASH_ERR_OK)
732 len = phys_block_length;
738 CYGHWR_FLASH_WRITE_DISABLE();
743 //----------------------------------------------------------------------------
747 flash_unlock_block(void* block, int block_size, int blocks, void *myprint)
749 volatile flash_data_t *ROM;
750 int res = FLASH_ERR_OK;
752 int timeout = 5000000;
753 volatile flash_data_t* b_p = (flash_data_t*) block;
754 volatile flash_data_t *b_v;
755 int j, die_number, blocks_to_do;
756 unsigned long phys_block_length;
760 void (*func_ptr)(void) = myprint;
764 d_print("flash_unlock_block function entered ....\n");
766 if (!flash_dev_info->locking)
769 ROM = FLASH_P2V((unsigned long)block & flash_dev_info->base_mask);
771 d_print("flash_unlock_block dev %08x block %08x size %08x count %08x\n", ROM, block, block_size, blocks);
773 // check out which die we have to handle
775 for (j = 0; j < CYGNUM_FLASH_SERIES; j++) {
776 if (((unsigned long)block >= sdi[j].dev_start)&&((unsigned long)block < (sdi[j].dev_start + sdi[j].dev_size))) {
781 if (die_number == 0) {
783 d_print("\n\ndid not found a valid die number \n\n");
785 return FLASH_ERR_DRV_WRONG_PART;
788 // check out which area we have to handle inside the die
789 if ((unsigned long)block < sdi[die_number - 1].dev_start + sdi[die_number - 1].num_blocks_1 * sdi[die_number - 1].num_bytes_1) {
790 // we stay in flash region 1
791 phys_block_length = sdi[die_number - 1].num_bytes_1;
792 if (sdi[die_number - 1].num_bytes_1 > sdi[die_number - 1].num_bytes_2) {
793 blocks_to_do = 1; // this is no boot block area
796 blocks_to_do = FLASH_BOOTBLOCKS_PER_BLOCK; //sdi[die_number - 1].num_bytes_2 / sdi[die_number - 1].num_bytes_1; // this is a bootblock area
800 // we stay in flash region 2
801 phys_block_length = sdi[die_number - 1].num_bytes_2;
802 if (sdi[die_number - 1].num_bytes_2 > sdi[die_number - 1].num_bytes_1) {
803 blocks_to_do = 1; // this is no boot block area
806 blocks_to_do = FLASH_BOOTBLOCKS_PER_BLOCK; //sdi[die_number - 1].num_bytes_1 / sdi[die_number - 1].num_bytes_2; // this is a bootblock area
812 d_print("unlocking block: ....... 0x%08X\n", (unsigned long)block);
813 d_print("block size: ............ 0x%08X\n", (unsigned long)block_size);
814 d_print("die number: ............ %d\n", die_number);
815 d_print("physical block length: . 0x%08X\n", phys_block_length);
816 d_print("blocks to do: .......... 0x%08X\n", blocks_to_do);
818 len = phys_block_length;
820 CYGHWR_FLASH_WRITE_ENABLE();
824 d_print("unlocking block at address 0x%08X\n", (unsigned long)b_p);
826 b_v = FLASH_P2V(b_p);
828 // Clear any error conditions
829 *b_v = FLASH_Clear_Status;
832 *b_v = FLASH_Clear_Lock;
833 *b_v = FLASH_Clear_Lock_Confirm; // Confirmation
835 *(b_v+2) = FLASH_Read_ID;
837 while ((state = *(b_v+2)) & FLASH_Lock_State_Mask) {
838 if (--timeout == 0) {
839 res = FLASH_ERR_DRV_TIMEOUT;
844 // Restore ROM to "normal" mode
848 b_p += len / sizeof( flash_data_t );
850 if (FLASH_ErrorLock == (state & FLASH_ErrorLock))
851 res = FLASH_ERR_LOCK;
853 if (res != FLASH_ERR_OK)
858 len = phys_block_length;
864 CYGHWR_FLASH_WRITE_DISABLE();
868 #endif // CYGHWR_IO_FLASH_BLOCK_LOCKING
869 #endif // CYGONCE_DEVS_FLASH_INTEL_28FXXX_INL