TX51 pre-release

[karo-tx-redboot.git] / packages / devs / ipu / arm / imx / v1_0 / include / ipuv3ex_reg_def.h

//==========================================================================
//
//      IPUV3ex_REG_DEF.h
//
//      regs definitions of IPUv3ex
//
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):       Ray Sun <Yanfei.Sun@freescale.com>
// Create Date: 2008-07-31
//
//####DESCRIPTIONEND####
//
//==========================================================================

#ifndef _IPUV3E_REGS_DEF_H_
#define _IPUV3E_REGS_DEF_H_

// ================= Start of IPUV3EX Common Registers =====================

#define IPU_IPU_CONF__ADDR             0x1E000000
#define IPU_IPU_CONF__EMPTY            0x1E000000,0x00000000
#define IPU_IPU_CONF__FULL             0x1E000000,0xffffffff
#define IPU_IPU_CONF__CSI_SEL          0x1E000000,0x80000000
#define IPU_IPU_CONF__IC_INPUT         0x1E000000,0x40000000
#define IPU_IPU_CONF__CSI1_DATA_SOURCE 0x1E000000,0x20000000
#define IPU_IPU_CONF__CSI0_DATA_SOURCE 0x1E000000,0x10000000
#define IPU_IPU_CONF__IC_DMFC_SYNC     0x1E000000,0x04000000
#define IPU_IPU_CONF__IC_DMFC_SEL      0x1E000000,0x02000000
#define IPU_IPU_CONF__ISP_DOUBLE_FLOW  0x1E000000,0x01000000
#define IPU_IPU_CONF__IDMAC_DISABLE    0x1E000000,0x00400000
#define IPU_IPU_CONF__IPU_DIAGBUS_ON   0x1E000000,0x00200000
#define IPU_IPU_CONF__IPU_DIAGBUS_MODE 0x1E000000,0x001F0000
#define IPU_IPU_CONF__IPU_HSP_CLK_EN   0x1E000000,0x00008000
#define IPU_IPU_CONF__SISG_EN          0x1E000000,0x00000800
#define IPU_IPU_CONF__DMFC_EN          0x1E000000,0x00000400
#define IPU_IPU_CONF__DC_EN            0x1E000000,0x00000200
#define IPU_IPU_CONF__SMFC_EN          0x1E000000,0x00000100
#define IPU_IPU_CONF__DI1_EN           0x1E000000,0x00000080
#define IPU_IPU_CONF__DI0_EN           0x1E000000,0x00000040
#define IPU_IPU_CONF__DP_EN            0x1E000000,0x00000020
#define IPU_IPU_CONF__ISP_EN           0x1E000000,0x00000010
#define IPU_IPU_CONF__IRT_EN           0x1E000000,0x00000008
#define IPU_IPU_CONF__IC_EN            0x1E000000,0x00000004
#define IPU_IPU_CONF__CSI1_EN          0x1E000000,0x00000002
#define IPU_IPU_CONF__CSI0_EN          0x1E000000,0x00000001

#define IPU_SISG_CTRL0__ADDR                  0x1E000004
#define IPU_SISG_CTRL0__EMPTY                 0x1E000004,0x00000000
#define IPU_SISG_CTRL0__FULL                  0x1E000004,0xffffffff
#define IPU_SISG_CTRL0__EXT_ACTV              0x1E000004,0x40000000
#define IPU_SISG_CTRL0__MCU_ACTV_TRIG         0x1E000004,0x20000000
#define IPU_SISG_CTRL0__VAL_STOP_SISG_COUNTER 0x1E000004,0x1FFFFFF0
#define IPU_SISG_CTRL0__NO_OF_VSYNC           0x1E000004,0x0000000E
#define IPU_SISG_CTRL0__VSYNC_RESET_COUNTER   0x1E000004,0x00000001

#define IPU_SISG_CTRL1__ADDR            0x1E000008
#define IPU_SISG_CTRL1__EMPTY           0x1E000008,0x00000000
#define IPU_SISG_CTRL1__FULL            0x1E000008,0xffffffff
#define IPU_SISG_CTRL1__SISG_OUT_POL    0x1E000008,0x00003F00
#define IPU_SISG_CTRL1__SISG_STROBE_CNT 0x1E000008,0x0000001F

#define IPU_SISG_SET_1__ADDR       0x1E00000C
#define IPU_SISG_SET_1__EMPTY      0x1E00000C,0x00000000
#define IPU_SISG_SET_1__FULL       0x1E00000C,0xffffffff
#define IPU_SISG_SET_1__SISG_SET_1 0x1E00000C,0x01FFFFFF

#define IPU_SISG_SET_2__ADDR       0x1E000010
#define IPU_SISG_SET_2__EMPTY      0x1E000010,0x00000000
#define IPU_SISG_SET_2__FULL       0x1E000010,0xffffffff
#define IPU_SISG_SET_2__SISG_SET_2 0x1E000010,0x01FFFFFF

#define IPU_SISG_SET_3__ADDR       0x1E000014
#define IPU_SISG_SET_3__EMPTY      0x1E000014,0x00000000
#define IPU_SISG_SET_3__FULL       0x1E000014,0xffffffff
#define IPU_SISG_SET_3__SISG_SET_3 0x1E000014,0x01FFFFFF

#define IPU_SISG_SET_4__ADDR       0x1E000018
#define IPU_SISG_SET_4__EMPTY      0x1E000018,0x00000000
#define IPU_SISG_SET_4__FULL       0x1E000018,0xffffffff
#define IPU_SISG_SET_4__SISG_SET_4 0x1E000018,0x01FFFFFF

#define IPU_SISG_SET_5__ADDR       0x1E00001C
#define IPU_SISG_SET_5__EMPTY      0x1E00001C,0x00000000
#define IPU_SISG_SET_5__FULL       0x1E00001C,0xffffffff
#define IPU_SISG_SET_5__SISG_SET_5 0x1E00001C,0x01FFFFFF

#define IPU_SISG_SET_6__ADDR       0x1E000020
#define IPU_SISG_SET_6__EMPTY      0x1E000020,0x00000000
#define IPU_SISG_SET_6__FULL       0x1E000020,0xffffffff
#define IPU_SISG_SET_6__SISG_SET_6 0x1E000020,0x01FFFFFF

#define IPU_SISG_CLR_1__ADDR         0x1E000024
#define IPU_SISG_CLR_1__EMPTY        0x1E000024,0x00000000
#define IPU_SISG_CLR_1__FULL         0x1E000024,0xffffffff
#define IPU_SISG_CLR_1__SISG_CLEAR_1 0x1E000024,0x01FFFFFF

#define IPU_SISG_CLR_2__ADDR         0x1E000028
#define IPU_SISG_CLR_2__EMPTY        0x1E000028,0x00000000
#define IPU_SISG_CLR_2__FULL         0x1E000028,0xffffffff
#define IPU_SISG_CLR_2__SISG_CLEAR_2 0x1E000028,0x01FFFFFF

#define IPU_SISG_CLR_3__ADDR         0x1E00002C
#define IPU_SISG_CLR_3__EMPTY        0x1E00002C,0x00000000
#define IPU_SISG_CLR_3__FULL         0x1E00002C,0xffffffff
#define IPU_SISG_CLR_3__SISG_CLEAR_3 0x1E00002C,0x01FFFFFF

#define IPU_SISG_CLR_4__ADDR         0x1E000030
#define IPU_SISG_CLR_4__EMPTY        0x1E000030,0x00000000
#define IPU_SISG_CLR_4__FULL         0x1E000030,0xffffffff
#define IPU_SISG_CLR_4__SISG_CLEAR_4 0x1E000030,0x01FFFFFF

#define IPU_SISG_CLR_5__ADDR         0x1E000034
#define IPU_SISG_CLR_5__EMPTY        0x1E000034,0x00000000
#define IPU_SISG_CLR_5__FULL         0x1E000034,0xffffffff
#define IPU_SISG_CLR_5__SISG_CLEAR_5 0x1E000034,0x01FFFFFF

#define IPU_SISG_CLR_6__ADDR         0x1E000038
#define IPU_SISG_CLR_6__EMPTY        0x1E000038,0x00000000
#define IPU_SISG_CLR_6__FULL         0x1E000038,0xffffffff
#define IPU_SISG_CLR_6__SISG_CLEAR_6 0x1E000038,0x01FFFFFF

#define IPU_IPU_INT_CTRL_1__ADDR            0x1E00003C
#define IPU_IPU_INT_CTRL_1__EMPTY           0x1E00003C,0x00000000
#define IPU_IPU_INT_CTRL_1__FULL            0x1E00003C,0xffffffff
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_31 0x1E00003C,0x80000000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_29 0x1E00003C,0x20000000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_28 0x1E00003C,0x10000000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_27 0x1E00003C,0x08000000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_24 0x1E00003C,0x01000000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_23 0x1E00003C,0x00800000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_22 0x1E00003C,0x00400000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_21 0x1E00003C,0x00200000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_20 0x1E00003C,0x00100000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_18 0x1E00003C,0x00040000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_17 0x1E00003C,0x00020000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_15 0x1E00003C,0x00008000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_14 0x1E00003C,0x00004000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_12 0x1E00003C,0x00001000
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_11 0x1E00003C,0x00000800
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_7  0x1E00003C,0x00000080
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_6  0x1E00003C,0x00000040
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_5  0x1E00003C,0x00000020
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_4  0x1E00003C,0x00000010
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_3  0x1E00003C,0x00000008
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_2  0x1E00003C,0x00000004
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_1  0x1E00003C,0x00000002
#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_0  0x1E00003C,0x00000001

#define IPU_IPU_INT_CTRL_2__ADDR            0x1E000040
#define IPU_IPU_INT_CTRL_2__EMPTY           0x1E000040,0x00000000
#define IPU_IPU_INT_CTRL_2__FULL            0x1E000040,0xffffffff
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_52 0x1E000040,0x00100000
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_51 0x1E000040,0x00080000
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_50 0x1E000040,0x00040000
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_49 0x1E000040,0x00020000
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_48 0x1E000040,0x00010000
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_47 0x1E000040,0x00008000
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_46 0x1E000040,0x00004000
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_45 0x1E000040,0x00002000
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_44 0x1E000040,0x00001000
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_43 0x1E000040,0x00000800
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_42 0x1E000040,0x00000400
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_41 0x1E000040,0x00000200
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_40 0x1E000040,0x00000100
#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_33 0x1E000040,0x00000002

#define IPU_IPU_INT_CTRL_3__ADDR              0x1E000044
#define IPU_IPU_INT_CTRL_3__EMPTY             0x1E000044,0x00000000
#define IPU_IPU_INT_CTRL_3__FULL              0x1E000044,0xffffffff
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31 0x1E000044,0x80000000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29 0x1E000044,0x20000000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28 0x1E000044,0x10000000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27 0x1E000044,0x08000000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24 0x1E000044,0x01000000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23 0x1E000044,0x00800000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22 0x1E000044,0x00400000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21 0x1E000044,0x00200000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20 0x1E000044,0x00100000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18 0x1E000044,0x00040000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17 0x1E000044,0x00020000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15 0x1E000044,0x00008000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14 0x1E000044,0x00004000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12 0x1E000044,0x00001000
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11 0x1E000044,0x00000800
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_7  0x1E000044,0x00000080
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_6  0x1E000044,0x00000040
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_5  0x1E000044,0x00000020
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_4  0x1E000044,0x00000010
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_3  0x1E000044,0x00000008
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_2  0x1E000044,0x00000004
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_1  0x1E000044,0x00000002
#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_0  0x1E000044,0x00000001

#define IPU_IPU_INT_CTRL_4__ADDR              0x1E000048
#define IPU_IPU_INT_CTRL_4__EMPTY             0x1E000048,0x00000000
#define IPU_IPU_INT_CTRL_4__FULL              0x1E000048,0xffffffff
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52 0x1E000048,0x00100000
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51 0x1E000048,0x00080000
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50 0x1E000048,0x00040000
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49 0x1E000048,0x00020000
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48 0x1E000048,0x00010000
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47 0x1E000048,0x00008000
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46 0x1E000048,0x00004000
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45 0x1E000048,0x00002000
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44 0x1E000048,0x00001000
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43 0x1E000048,0x00000800
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42 0x1E000048,0x00000400
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41 0x1E000048,0x00000200
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40 0x1E000048,0x00000100
#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33 0x1E000048,0x00000002

#define IPU_IPU_INT_CTRL_5__ADDR                0x1E00004C
#define IPU_IPU_INT_CTRL_5__EMPTY               0x1E00004C,0x00000000
#define IPU_IPU_INT_CTRL_5__FULL                0x1E00004C,0xffffffff
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31 0x1E00004C,0x80000000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29 0x1E00004C,0x20000000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28 0x1E00004C,0x10000000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27 0x1E00004C,0x08000000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24 0x1E00004C,0x01000000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23 0x1E00004C,0x00800000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22 0x1E00004C,0x00400000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21 0x1E00004C,0x00200000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20 0x1E00004C,0x00100000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18 0x1E00004C,0x00040000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17 0x1E00004C,0x00020000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15 0x1E00004C,0x00008000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14 0x1E00004C,0x00004000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12 0x1E00004C,0x00001000
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11 0x1E00004C,0x00000800
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_7  0x1E00004C,0x00000080
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_6  0x1E00004C,0x00000040
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_5  0x1E00004C,0x00000020
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_4  0x1E00004C,0x00000010
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_3  0x1E00004C,0x00000008
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_2  0x1E00004C,0x00000004
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_1  0x1E00004C,0x00000002
#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_0  0x1E00004C,0x00000001

#define IPU_IPU_INT_CTRL_6__ADDR                0x1E000050
#define IPU_IPU_INT_CTRL_6__EMPTY               0x1E000050,0x00000000
#define IPU_IPU_INT_CTRL_6__FULL                0x1E000050,0xffffffff
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52 0x1E000050,0x00100000
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51 0x1E000050,0x00080000
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50 0x1E000050,0x00040000
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49 0x1E000050,0x00020000
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48 0x1E000050,0x00010000
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47 0x1E000050,0x00008000
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46 0x1E000050,0x00004000
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45 0x1E000050,0x00002000
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44 0x1E000050,0x00001000
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43 0x1E000050,0x00000800
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42 0x1E000050,0x00000400
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41 0x1E000050,0x00000200
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40 0x1E000050,0x00000100
#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33 0x1E000050,0x00000002

#define IPU_IPU_INT_CTRL_7__ADDR            0x1E000054
#define IPU_IPU_INT_CTRL_7__EMPTY           0x1E000054,0x00000000
#define IPU_IPU_INT_CTRL_7__FULL            0x1E000054,0xffffffff
#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_31 0x1E000054,0x80000000
#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_29 0x1E000054,0x20000000
#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_28 0x1E000054,0x10000000
#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_27 0x1E000054,0x08000000
#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_24 0x1E000054,0x01000000
#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_23 0x1E000054,0x00800000

#define IPU_IPU_INT_CTRL_8__ADDR            0x1E000058
#define IPU_IPU_INT_CTRL_8__EMPTY           0x1E000058,0x00000000
#define IPU_IPU_INT_CTRL_8__FULL            0x1E000058,0xffffffff
#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_52 0x1E000058,0x00100000
#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_51 0x1E000058,0x00080000
#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_44 0x1E000058,0x00001000
#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_43 0x1E000058,0x00000800
#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_42 0x1E000058,0x00000400
#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_41 0x1E000058,0x00000200
#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_33 0x1E000058,0x00000002

#define IPU_IPU_INT_CTRL_9__ADDR                0x1E00005C
#define IPU_IPU_INT_CTRL_9__EMPTY               0x1E00005C,0x00000000
#define IPU_IPU_INT_CTRL_9__FULL                0x1E00005C,0xffffffff
#define IPU_IPU_INT_CTRL_9__CSI1_PUPE_EN        0x1E00005C,0x80000000
#define IPU_IPU_INT_CTRL_9__CSI0_PUPE_EN        0x1E00005C,0x40000000
#define IPU_IPU_INT_CTRL_9__ISP_PUPE_EN         0x1E00005C,0x20000000
#define IPU_IPU_INT_CTRL_9__IC_VF_BUF_OVF_EN    0x1E00005C,0x10000000
#define IPU_IPU_INT_CTRL_9__IC_ENC_BUF_OVF_EN   0x1E00005C,0x08000000
#define IPU_IPU_INT_CTRL_9__IC_BAYER_BUF_OVF_EN 0x1E00005C,0x04000000

#define IPU_IPU_INT_CTRL_10__ADDR                      0x1E000060
#define IPU_IPU_INT_CTRL_10__EMPTY                     0x1E000060,0x00000000
#define IPU_IPU_INT_CTRL_10__FULL                      0x1E000060,0xffffffff
#define IPU_IPU_INT_CTRL_10__AXIR_ERR_EN               0x1E000060,0x40000000
#define IPU_IPU_INT_CTRL_10__AXIW_ERR_EN               0x1E000060,0x20000000
#define IPU_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN 0x1E000060,0x10000000
#define IPU_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN  0x1E000060,0x04000000
#define IPU_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN    0x1E000060,0x02000000
#define IPU_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN     0x1E000060,0x01000000
#define IPU_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN       0x1E000060,0x00400000
#define IPU_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN       0x1E000060,0x00200000
#define IPU_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN      0x1E000060,0x00100000
#define IPU_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN      0x1E000060,0x00080000
#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN       0x1E000060,0x00040000
#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN       0x1E000060,0x00020000
#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN       0x1E000060,0x00010000
#define IPU_IPU_INT_CTRL_10__ISP_RAM_HIST_OF_EN        0x1E000060,0x00000020
#define IPU_IPU_INT_CTRL_10__ISP_RAM_ST_OF_EN          0x1E000060,0x00000010
#define IPU_IPU_INT_CTRL_10__SMFC3_FRM_LOST_EN         0x1E000060,0x00000008
#define IPU_IPU_INT_CTRL_10__SMFC2_FRM_LOST_EN         0x1E000060,0x00000004
#define IPU_IPU_INT_CTRL_10__SMFC1_FRM_LOST_EN         0x1E000060,0x00000002
#define IPU_IPU_INT_CTRL_10__SMFC0_FRM_LOST_EN         0x1E000060,0x00000001

#define IPU_IPU_INT_CTRL_11__ADDR              0x1E000064
#define IPU_IPU_INT_CTRL_11__EMPTY             0x1E000064,0x00000000
#define IPU_IPU_INT_CTRL_11__FULL              0x1E000064,0xffffffff
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22 0x1E000064,0x00400000
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21 0x1E000064,0x00200000
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20 0x1E000064,0x00100000
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12 0x1E000064,0x00001000
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11 0x1E000064,0x00000800
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_5  0x1E000064,0x00000020
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_3  0x1E000064,0x00000008
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_2  0x1E000064,0x00000004
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_1  0x1E000064,0x00000002
#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_0  0x1E000064,0x00000001

#define IPU_IPU_INT_CTRL_12__ADDR              0x1E000068
#define IPU_IPU_INT_CTRL_12__EMPTY             0x1E000068,0x00000000
#define IPU_IPU_INT_CTRL_12__FULL              0x1E000068,0xffffffff
#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50 0x1E000068,0x00040000
#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49 0x1E000068,0x00020000
#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48 0x1E000068,0x00010000
#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47 0x1E000068,0x00008000
#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46 0x1E000068,0x00004000
#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45 0x1E000068,0x00002000

#define IPU_IPU_INT_CTRL_13__ADDR           0x1E00006C
#define IPU_IPU_INT_CTRL_13__EMPTY          0x1E00006C,0x00000000
#define IPU_IPU_INT_CTRL_13__FULL           0x1E00006C,0xffffffff
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_31 0x1E00006C,0x80000000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_29 0x1E00006C,0x20000000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_28 0x1E00006C,0x10000000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_27 0x1E00006C,0x08000000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_24 0x1E00006C,0x01000000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_23 0x1E00006C,0x00800000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_22 0x1E00006C,0x00400000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_21 0x1E00006C,0x00200000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_20 0x1E00006C,0x00100000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_18 0x1E00006C,0x00040000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_17 0x1E00006C,0x00020000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_15 0x1E00006C,0x00008000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_14 0x1E00006C,0x00004000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_12 0x1E00006C,0x00001000
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_11 0x1E00006C,0x00000800
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_7  0x1E00006C,0x00000080
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_6  0x1E00006C,0x00000040
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_5  0x1E00006C,0x00000020
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_4  0x1E00006C,0x00000010
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_3  0x1E00006C,0x00000008
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_2  0x1E00006C,0x00000004
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_1  0x1E00006C,0x00000002
#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_0  0x1E00006C,0x00000001

#define IPU_IPU_INT_CTRL_14__ADDR           0x1E000070
#define IPU_IPU_INT_CTRL_14__EMPTY          0x1E000070,0x00000000
#define IPU_IPU_INT_CTRL_14__FULL           0x1E000070,0xffffffff
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_52 0x1E000070,0x00100000
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_51 0x1E000070,0x00080000
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_50 0x1E000070,0x00040000
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_49 0x1E000070,0x00020000
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_48 0x1E000070,0x00010000
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_47 0x1E000070,0x00008000
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_46 0x1E000070,0x00004000
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_45 0x1E000070,0x00002000
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_44 0x1E000070,0x00001000
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_43 0x1E000070,0x00000800
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_42 0x1E000070,0x00000400
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_41 0x1E000070,0x00000200
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_40 0x1E000070,0x00000100
#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_33 0x1E000070,0x00000002

#define IPU_IPU_INT_CTRL_15__ADDR                   0x1E000074
#define IPU_IPU_INT_CTRL_15__EMPTY                  0x1E000074,0x00000000
#define IPU_IPU_INT_CTRL_15__FULL                   0x1E000074,0xffffffff
#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN    0x1E000074,0x80000000
#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN    0x1E000074,0x40000000
#define IPU_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN 0x1E000074,0x20000000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN   0x1E000074,0x10000000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN    0x1E000074,0x08000000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN    0x1E000074,0x04000000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN    0x1E000074,0x02000000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN    0x1E000074,0x01000000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN    0x1E000074,0x00800000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN    0x1E000074,0x00400000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN    0x1E000074,0x00200000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN    0x1E000074,0x00100000
#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN    0x1E000074,0x00080000
#define IPU_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN 0x1E000074,0x00040000
#define IPU_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN       0x1E000074,0x00020000
#define IPU_IPU_INT_CTRL_15__DC_DP_START_EN         0x1E000074,0x00010000
#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN      0x1E000074,0x00008000
#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN      0x1E000074,0x00004000
#define IPU_IPU_INT_CTRL_15__DC_FC_6_EN             0x1E000074,0x00002000
#define IPU_IPU_INT_CTRL_15__DC_FC_4_EN             0x1E000074,0x00001000
#define IPU_IPU_INT_CTRL_15__DC_FC_3_EN             0x1E000074,0x00000800
#define IPU_IPU_INT_CTRL_15__DC_FC_2_EN             0x1E000074,0x00000400
#define IPU_IPU_INT_CTRL_15__DC_FC_1_EN             0x1E000074,0x00000200
#define IPU_IPU_INT_CTRL_15__DC_FC_0_EN             0x1E000074,0x00000100
#define IPU_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN        0x1E000074,0x00000080
#define IPU_IPU_INT_CTRL_15__DP_SF_BRAKE_EN         0x1E000074,0x00000040
#define IPU_IPU_INT_CTRL_15__DP_ASF_END_EN          0x1E000074,0x00000020
#define IPU_IPU_INT_CTRL_15__DP_ASF_START_EN        0x1E000074,0x00000010
#define IPU_IPU_INT_CTRL_15__DP_SF_END_EN           0x1E000074,0x00000008
#define IPU_IPU_INT_CTRL_15__DP_SF_START_EN         0x1E000074,0x00000004
#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN   0x1E000074,0x00000002
#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN   0x1E000074,0x00000001

#define IPU_IPU_SDMA_EVENT_1__ADDR                 0x1E000078
#define IPU_IPU_SDMA_EVENT_1__EMPTY                0x1E000078,0x00000000
#define IPU_IPU_SDMA_EVENT_1__FULL                 0x1E000078,0xffffffff
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31 0x1E000078,0x80000000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29 0x1E000078,0x20000000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28 0x1E000078,0x10000000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27 0x1E000078,0x08000000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24 0x1E000078,0x01000000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23 0x1E000078,0x00800000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22 0x1E000078,0x00400000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21 0x1E000078,0x00200000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20 0x1E000078,0x00100000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18 0x1E000078,0x00040000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17 0x1E000078,0x00020000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15 0x1E000078,0x00008000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14 0x1E000078,0x00004000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12 0x1E000078,0x00001000
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11 0x1E000078,0x00000800
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_7  0x1E000078,0x00000080
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_6  0x1E000078,0x00000040
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_5  0x1E000078,0x00000020
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_4  0x1E000078,0x00000010
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_3  0x1E000078,0x00000008
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_2  0x1E000078,0x00000004
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_1  0x1E000078,0x00000002
#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_0  0x1E000078,0x00000001

#define IPU_IPU_SDMA_EVENT_2__ADDR                 0x1E00007C
#define IPU_IPU_SDMA_EVENT_2__EMPTY                0x1E00007C,0x00000000
#define IPU_IPU_SDMA_EVENT_2__FULL                 0x1E00007C,0xffffffff
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52 0x1E00007C,0x00100000
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51 0x1E00007C,0x00080000
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50 0x1E00007C,0x00040000
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49 0x1E00007C,0x00020000
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48 0x1E00007C,0x00010000
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47 0x1E00007C,0x00008000
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46 0x1E00007C,0x00004000
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45 0x1E00007C,0x00002000
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44 0x1E00007C,0x00001000
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43 0x1E00007C,0x00000800
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42 0x1E00007C,0x00000400
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41 0x1E00007C,0x00000200
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40 0x1E00007C,0x00000100
#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33 0x1E00007C,0x00000002

#define IPU_IPU_SDMA_EVENT_3__ADDR                   0x1E000080
#define IPU_IPU_SDMA_EVENT_3__EMPTY                  0x1E000080,0x00000000
#define IPU_IPU_SDMA_EVENT_3__FULL                   0x1E000080,0xffffffff
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31 0x1E000080,0x80000000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29 0x1E000080,0x20000000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28 0x1E000080,0x10000000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27 0x1E000080,0x08000000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24 0x1E000080,0x01000000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23 0x1E000080,0x00800000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22 0x1E000080,0x00400000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21 0x1E000080,0x00200000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20 0x1E000080,0x00100000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18 0x1E000080,0x00040000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17 0x1E000080,0x00020000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15 0x1E000080,0x00008000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14 0x1E000080,0x00004000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12 0x1E000080,0x00001000
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11 0x1E000080,0x00000800
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_7  0x1E000080,0x00000080
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_6  0x1E000080,0x00000040
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_5  0x1E000080,0x00000020
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_4  0x1E000080,0x00000010
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_3  0x1E000080,0x00000008
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_2  0x1E000080,0x00000004
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_1  0x1E000080,0x00000002
#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_0  0x1E000080,0x00000001

#define IPU_IPU_SDMA_EVENT_4__ADDR                   0x1E000084
#define IPU_IPU_SDMA_EVENT_4__EMPTY                  0x1E000084,0x00000000
#define IPU_IPU_SDMA_EVENT_4__FULL                   0x1E000084,0xffffffff
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52 0x1E000084,0x00100000
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51 0x1E000084,0x00080000
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50 0x1E000084,0x00040000
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49 0x1E000084,0x00020000
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48 0x1E000084,0x00010000
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47 0x1E000084,0x00008000
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46 0x1E000084,0x00004000
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45 0x1E000084,0x00002000
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44 0x1E000084,0x00001000
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43 0x1E000084,0x00000800
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42 0x1E000084,0x00000400
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41 0x1E000084,0x00000200
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40 0x1E000084,0x00000100
#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33 0x1E000084,0x00000002

#define IPU_IPU_SDMA_EVENT_7__ADDR                 0x1E000088
#define IPU_IPU_SDMA_EVENT_7__EMPTY                0x1E000088,0x00000000
#define IPU_IPU_SDMA_EVENT_7__FULL                 0x1E000088,0xffffffff
#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31 0x1E000088,0x80000000
#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29 0x1E000088,0x20000000
#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28 0x1E000088,0x10000000
#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27 0x1E000088,0x08000000
#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24 0x1E000088,0x01000000
#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23 0x1E000088,0x00800000

#define IPU_IPU_SDMA_EVENT_8__ADDR                 0x1E00008C
#define IPU_IPU_SDMA_EVENT_8__EMPTY                0x1E00008C,0x00000000
#define IPU_IPU_SDMA_EVENT_8__FULL                 0x1E00008C,0xffffffff
#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52 0x1E00008C,0x00100000
#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51 0x1E00008C,0x00080000
#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44 0x1E00008C,0x00001000
#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43 0x1E00008C,0x00000800
#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42 0x1E00008C,0x00000400
#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41 0x1E00008C,0x00000200
#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32 0x1E00008C,0x00000002

#define IPU_IPU_SDMA_EVENT_11__ADDR                   0x1E000090
#define IPU_IPU_SDMA_EVENT_11__EMPTY                  0x1E000090,0x00000000
#define IPU_IPU_SDMA_EVENT_11__FULL                   0x1E000090,0xffffffff
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22 0x1E000090,0x00400000
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21 0x1E000090,0x00200000
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20 0x1E000090,0x00100000
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12 0x1E000090,0x00001000
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11 0x1E000090,0x00000800
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_5  0x1E000090,0x00000020
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_3  0x1E000090,0x00000008
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_2  0x1E000090,0x00000004
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_1  0x1E000090,0x00000002
#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_0  0x1E000090,0x00000001

#define IPU_IPU_SDMA_EVENT_12__ADDR                   0x1E000094
#define IPU_IPU_SDMA_EVENT_12__EMPTY                  0x1E000094,0x00000000
#define IPU_IPU_SDMA_EVENT_12__FULL                   0x1E000094,0xffffffff
#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50 0x1E000094,0x00040000
#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49 0x1E000094,0x00020000
#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48 0x1E000094,0x00010000
#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47 0x1E000094,0x00008000
#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46 0x1E000094,0x00004000
#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45 0x1E000094,0x00002000

#define IPU_IPU_SDMA_EVENT_13__ADDR                0x1E000098
#define IPU_IPU_SDMA_EVENT_13__EMPTY               0x1E000098,0x00000000
#define IPU_IPU_SDMA_EVENT_13__FULL                0x1E000098,0xffffffff
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31 0x1E000098,0x80000000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29 0x1E000098,0x20000000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28 0x1E000098,0x10000000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27 0x1E000098,0x08000000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24 0x1E000098,0x01000000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23 0x1E000098,0x00800000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22 0x1E000098,0x00400000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21 0x1E000098,0x00200000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20 0x1E000098,0x00100000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18 0x1E000098,0x00040000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17 0x1E000098,0x00020000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15 0x1E000098,0x00008000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14 0x1E000098,0x00004000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12 0x1E000098,0x00001000
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11 0x1E000098,0x00000800
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_7  0x1E000098,0x00000080
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_6  0x1E000098,0x00000040
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_5  0x1E000098,0x00000020
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_4  0x1E000098,0x00000010
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_3  0x1E000098,0x00000008
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_2  0x1E000098,0x00000004
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_1  0x1E000098,0x00000002
#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_0  0x1E000098,0x00000001

#define IPU_IPU_SDMA_EVENT_14__ADDR                0x1E00009C
#define IPU_IPU_SDMA_EVENT_14__EMPTY               0x1E00009C,0x00000000
#define IPU_IPU_SDMA_EVENT_14__FULL                0x1E00009C,0xffffffff
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52 0x1E00009C,0x00100000
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51 0x1E00009C,0x00080000
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50 0x1E00009C,0x00040000
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49 0x1E00009C,0x00020000
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48 0x1E00009C,0x00010000
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47 0x1E00009C,0x00008000
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46 0x1E00009C,0x00004000
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45 0x1E00009C,0x00002000
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44 0x1E00009C,0x00001000
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43 0x1E00009C,0x00000800
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42 0x1E00009C,0x00000400
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41 0x1E00009C,0x00000200
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40 0x1E00009C,0x00000100
#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33 0x1E00009C,0x00000002

#define IPU_IPU_SRM_PRI1__ADDR          0x1E0000A0
#define IPU_IPU_SRM_PRI1__EMPTY         0x1E0000A0,0x00000000
#define IPU_IPU_SRM_PRI1__FULL          0x1E0000A0,0xffffffff
#define IPU_IPU_SRM_PRI1__ISP_SRM_MODE  0x1E0000A0,0x00180000
#define IPU_IPU_SRM_PRI1__ISP_SRM_PRI   0x1E0000A0,0x00070000
#define IPU_IPU_SRM_PRI1__CSI0_SRM_MODE 0x1E0000A0,0x00001800
#define IPU_IPU_SRM_PRI1__CSI0_SRM_PRI  0x1E0000A0,0x00000700
#define IPU_IPU_SRM_PRI1__CSI1_SRM_MODE 0x1E0000A0,0x00000018
#define IPU_IPU_SRM_PRI1__CSI1_SRM_PRI  0x1E0000A0,0x00000007

#define IPU_IPU_SRM_PRI2__ADDR           0x1E0000A4
#define IPU_IPU_SRM_PRI2__EMPTY          0x1E0000A4,0x00000000
#define IPU_IPU_SRM_PRI2__FULL           0x1E0000A4,0xffffffff
#define IPU_IPU_SRM_PRI2__DI1_SRM_MODE   0x1E0000A4,0x18000000
#define IPU_IPU_SRM_PRI2__DI1_SRM_PRI    0x1E0000A4,0x07000000
#define IPU_IPU_SRM_PRI2__DI0_SRM_MODE   0x1E0000A4,0x00180000
#define IPU_IPU_SRM_PRI2__DI0_SRM_PRI    0x1E0000A4,0x00070000
#define IPU_IPU_SRM_PRI2__DC_6_SRM_MODE  0x1E0000A4,0x0000C000
#define IPU_IPU_SRM_PRI2__DC_2_SRM_MODE  0x1E0000A4,0x00003000
#define IPU_IPU_SRM_PRI2__DC_SRM_PRI     0x1E0000A4,0x00000E00
#define IPU_IPU_SRM_PRI2__DP_A1_SRM_MODE 0x1E0000A4,0x00000180
#define IPU_IPU_SRM_PRI2__DP_A0_SRM_MODE 0x1E0000A4,0x00000060
#define IPU_IPU_SRM_PRI2__DP_S_SRM_MODE  0x1E0000A4,0x00000018
#define IPU_IPU_SRM_PRI2__DP_SRM_PRI     0x1E0000A4,0x00000007

#define IPU_IPU_FS_PROC_FLOW1__ADDR               0x1E0000A8
#define IPU_IPU_FS_PROC_FLOW1__EMPTY              0x1E0000A8,0x00000000
#define IPU_IPU_FS_PROC_FLOW1__FULL               0x1E0000A8,0xffffffff
#define IPU_IPU_FS_PROC_FLOW1__VF_IN_VALID        0x1E0000A8,0x80000000
#define IPU_IPU_FS_PROC_FLOW1__ENC_IN_VALID       0x1E0000A8,0x40000000
#define IPU_IPU_FS_PROC_FLOW1__PRP_SRC_SEL        0x1E0000A8,0x0F000000
#define IPU_IPU_FS_PROC_FLOW1__ISP_SRC_SEL        0x1E0000A8,0x00F00000
#define IPU_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL     0x1E0000A8,0x000F0000
#define IPU_IPU_FS_PROC_FLOW1__PP_SRC_SEL         0x1E0000A8,0x0000F000
#define IPU_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL  0x1E0000A8,0x00000F00
#define IPU_IPU_FS_PROC_FLOW1__ALT_ISP_SRC_SEL    0x1E0000A8,0x000000F0
#define IPU_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL 0x1E0000A8,0x0000000F

#define IPU_IPU_FS_PROC_FLOW2__ADDR                0x1E0000AC
#define IPU_IPU_FS_PROC_FLOW2__EMPTY               0x1E0000AC,0x00000000
#define IPU_IPU_FS_PROC_FLOW2__FULL                0x1E0000AC,0xffffffff
#define IPU_IPU_FS_PROC_FLOW2__PRP_ALT_DEST_SEL    0x1E0000AC,0xF0000000
#define IPU_IPU_FS_PROC_FLOW2__PRP_DEST_SEL        0x1E0000AC,0x0F000000
#define IPU_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL 0x1E0000AC,0x00F00000
#define IPU_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL     0x1E0000AC,0x000F0000
#define IPU_IPU_FS_PROC_FLOW2__PP_DEST_SEL         0x1E0000AC,0x0000F000
#define IPU_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL  0x1E0000AC,0x00000F00
#define IPU_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL      0x1E0000AC,0x000000F0
#define IPU_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL    0x1E0000AC,0x0000000F

#define IPU_IPU_FS_PROC_FLOW3__ADDR           0x1E0000B0
#define IPU_IPU_FS_PROC_FLOW3__EMPTY          0x1E0000B0,0x00000000
#define IPU_IPU_FS_PROC_FLOW3__FULL           0x1E0000B0,0xffffffff
#define IPU_IPU_FS_PROC_FLOW3__SMFC3_DEST_SEL 0x1E0000B0,0x00003800
#define IPU_IPU_FS_PROC_FLOW3__SMFC2_DEST_SEL 0x1E0000B0,0x00000780
#define IPU_IPU_FS_PROC_FLOW3__SMFC1_DEST_SEL 0x1E0000B0,0x00000070
#define IPU_IPU_FS_PROC_FLOW3__SMFC0_DEST_SEL 0x1E0000B0,0x0000000F

#define IPU_IPU_FS_DISP_FLOW1__ADDR              0x1E0000B4
#define IPU_IPU_FS_DISP_FLOW1__EMPTY             0x1E0000B4,0x00000000
#define IPU_IPU_FS_DISP_FLOW1__FULL              0x1E0000B4,0xffffffff
#define IPU_IPU_FS_DISP_FLOW1__DC1_SRC_SEL       0x1E0000B4,0x00F00000
#define IPU_IPU_FS_DISP_FLOW1__DC2_SRC_SEL       0x1E0000B4,0x000F0000
#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL 0x1E0000B4,0x0000F000
#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL 0x1E0000B4,0x00000F00
#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL  0x1E0000B4,0x000000F0
#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL  0x1E0000B4,0x0000000F

#define IPU_IPU_FS_DISP_FLOW2__ADDR                  0x1E0000B8
#define IPU_IPU_FS_DISP_FLOW2__EMPTY                 0x1E0000B8,0x00000000
#define IPU_IPU_FS_DISP_FLOW2__FULL                  0x1E0000B8,0xffffffff
#define IPU_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL       0x1E0000B8,0x000F0000
#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL 0x1E0000B8,0x000000F0
#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL 0x1E0000B8,0x0000000F

#define IPU_IPU_SKIP__ADDR                      0x1E0000BC
#define IPU_IPU_SKIP__EMPTY                     0x1E0000BC,0x00000000
#define IPU_IPU_SKIP__FULL                      0x1E0000BC,0xffffffff
#define IPU_IPU_SKIP__CSI_SKIP_IC_VF            0x1E0000BC,0x0000F800
#define IPU_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_VF  0x1E0000BC,0x00000700
#define IPU_IPU_SKIP__CSI_SKIP_IC_ENC           0x1E0000BC,0x000000F8
#define IPU_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_ENC 0x1E0000BC,0x00000007

#define IPU_IPU_DISP_ALT_CONF__ADDR  0x1E0000C0
#define IPU_IPU_DISP_ALT_CONF__EMPTY 0x1E0000C0,0x00000000
#define IPU_IPU_DISP_ALT_CONF__FULL  0x1E0000C0,0xffffffff

#define IPU_IPU_DISP_GEN__ADDR                 0x1E0000C4
#define IPU_IPU_DISP_GEN__EMPTY                0x1E0000C4,0x00000000
#define IPU_IPU_DISP_GEN__FULL                 0x1E0000C4,0xffffffff
#define IPU_IPU_DISP_GEN__DI1_COUNTER_RELEASE  0x1E0000C4,0x02000000
#define IPU_IPU_DISP_GEN__DI0_COUNTER_RELEASE  0x1E0000C4,0x01000000
#define IPU_IPU_DISP_GEN__CSI_VSYNC_DEST       0x1E0000C4,0x00800000
#define IPU_IPU_DISP_GEN__MCU_MAX_BURST_STOP   0x1E0000C4,0x00400000
#define IPU_IPU_DISP_GEN__MCU_T                0x1E0000C4,0x003C0000
#define IPU_IPU_DISP_GEN__MCU_DI_ID_9          0x1E0000C4,0x00020000
#define IPU_IPU_DISP_GEN__MCU_DI_ID_8          0x1E0000C4,0x00010000
#define IPU_IPU_DISP_GEN__DP_PIPE_CLR          0x1E0000C4,0x00000040
#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC1      0x1E0000C4,0x00000020
#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC0      0x1E0000C4,0x00000010
#define IPU_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW 0x1E0000C4,0x00000008
#define IPU_IPU_DISP_GEN__DC2_DOUBLE_FLOW      0x1E0000C4,0x00000004
#define IPU_IPU_DISP_GEN__DI1_DUAL_MODE        0x1E0000C4,0x00000002
#define IPU_IPU_DISP_GEN__DI0_DUAL_MODE        0x1E0000C4,0x00000001

#define IPU_IPU_DISP_ALT1__ADDR                  0x1E0000C8
#define IPU_IPU_DISP_ALT1__EMPTY                 0x1E0000C8,0x00000000
#define IPU_IPU_DISP_ALT1__FULL                  0x1E0000C8,0xffffffff
#define IPU_IPU_DISP_ALT1__SEL_ALT_0             0x1E0000C8,0xF0000000
#define IPU_IPU_DISP_ALT1__STEP_REPEAT_ALT_0     0x1E0000C8,0x0FFF0000
#define IPU_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0 0x1E0000C8,0x00008000
#define IPU_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0     0x1E0000C8,0x00007000
#define IPU_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0    0x1E0000C8,0x00000FFF

#define IPU_IPU_DISP_ALT2__ADDR                    0x1E0000CC
#define IPU_IPU_DISP_ALT2__EMPTY                   0x1E0000CC,0x00000000
#define IPU_IPU_DISP_ALT2__FULL                    0x1E0000CC,0xffffffff
#define IPU_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0    0x1E0000CC,0x00070000
#define IPU_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0 0x1E0000CC,0x00007000
#define IPU_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0      0x1E0000CC,0x00000FFF

#define IPU_IPU_DISP_ALT3__ADDR                  0x1E0000D0
#define IPU_IPU_DISP_ALT3__EMPTY                 0x1E0000D0,0x00000000
#define IPU_IPU_DISP_ALT3__FULL                  0x1E0000D0,0xffffffff
#define IPU_IPU_DISP_ALT3__SEL_ALT_1             0x1E0000D0,0xF0000000
#define IPU_IPU_DISP_ALT3__STEP_REPEAT_ALT_1     0x1E0000D0,0x0FFF0000
#define IPU_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1 0x1E0000D0,0x00008000
#define IPU_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1     0x1E0000D0,0x00007000
#define IPU_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1    0x1E0000D0,0x00000FFF

#define IPU_IPU_DISP_ALT4__ADDR                    0x1E0000D4
#define IPU_IPU_DISP_ALT4__EMPTY                   0x1E0000D4,0x00000000
#define IPU_IPU_DISP_ALT4__FULL                    0x1E0000D4,0xffffffff
#define IPU_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1    0x1E0000D4,0x00070000
#define IPU_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1 0x1E0000D4,0x00007000
#define IPU_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1      0x1E0000D4,0x00000FFF

#define IPU_IPU_SNOOP__ADDR            0x1E0000D8
#define IPU_IPU_SNOOP__EMPTY           0x1E0000D8,0x00000000
#define IPU_IPU_SNOOP__FULL            0x1E0000D8,0xffffffff
#define IPU_IPU_SNOOP__SNOOP2_SYNC_BYP 0x1E0000D8,0x00010000
#define IPU_IPU_SNOOP__AUTOREF_PER     0x1E0000D8,0x000003FF

#define IPU_IPU_MEM_RST__ADDR          0x1E0000DC
#define IPU_IPU_MEM_RST__EMPTY         0x1E0000DC,0x00000000
#define IPU_IPU_MEM_RST__FULL          0x1E0000DC,0xffffffff
#define IPU_IPU_MEM_RST__RST_MEM_START 0x1E0000DC,0x80000000
#define IPU_IPU_MEM_RST__RST_MEM_EN    0x1E0000DC,0x007FFFFF

#define IPU_IPU_PM__ADDR                      0x1E0000E0
#define IPU_IPU_PM__EMPTY                     0x1E0000E0,0x00000000
#define IPU_IPU_PM__FULL                      0x1E0000E0,0xffffffff
#define IPU_IPU_PM__LPSR_MODE                 0x1E0000E0,0x80000000
#define IPU_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x40000000
#define IPU_IPU_PM__DI1_CLK_PERIOD_1          0x1E0000E0,0x3F800000
#define IPU_IPU_PM__DI1_CLK_PERIOD_0          0x1E0000E0,0x007F0000
#define IPU_IPU_PM__CLOCK_MODE_STAT           0x1E0000E0,0x00008000
#define IPU_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x00004000
#define IPU_IPU_PM__DI0_CLK_PERIOD_1          0x1E0000E0,0x00003F80
#define IPU_IPU_PM__DI0_CLK_PERIOD_0          0x1E0000E0,0x0000007F

#define IPU_IPU_GPR__ADDR                       0x1E0000E4
#define IPU_IPU_GPR__EMPTY                      0x1E0000E4,0x00000000
#define IPU_IPU_GPR__FULL                       0x1E0000E4,0xffffffff
#define IPU_IPU_GPR__IPU_CH_BUF1_RDY1_CLR       0x1E0000E4,0x80000000
#define IPU_IPU_GPR__IPU_CH_BUF1_RDY0_CLR       0x1E0000E4,0x40000000
#define IPU_IPU_GPR__IPU_CH_BUF0_RDY1_CLR       0x1E0000E4,0x20000000
#define IPU_IPU_GPR__IPU_CH_BUF0_RDY0_CLR       0x1E0000E4,0x10000000
#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR   0x1E0000E4,0x08000000
#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR   0x1E0000E4,0x04000000
#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR   0x1E0000E4,0x02000000
#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR   0x1E0000E4,0x01000000
#define IPU_IPU_GPR__IPU_DI1_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00800000
#define IPU_IPU_GPR__IPU_DI0_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00400000
#define IPU_IPU_GPR__IPU_GP21                   0x1E0000E4,0x00200000
#define IPU_IPU_GPR__IPU_GP20                   0x1E0000E4,0x00100000
#define IPU_IPU_GPR__IPU_GP19                   0x1E0000E4,0x00080000
#define IPU_IPU_GPR__IPU_GP18                   0x1E0000E4,0x00040000
#define IPU_IPU_GPR__IPU_GP17                   0x1E0000E4,0x00020000
#define IPU_IPU_GPR__IPU_GP16                   0x1E0000E4,0x00010000
#define IPU_IPU_GPR__IPU_GP15                   0x1E0000E4,0x00008000
#define IPU_IPU_GPR__IPU_GP14                   0x1E0000E4,0x00004000
#define IPU_IPU_GPR__IPU_GP13                   0x1E0000E4,0x00002000
#define IPU_IPU_GPR__IPU_GP12                   0x1E0000E4,0x00001000
#define IPU_IPU_GPR__IPU_GP11                   0x1E0000E4,0x00000800
#define IPU_IPU_GPR__IPU_GP10                   0x1E0000E4,0x00000400
#define IPU_IPU_GPR__IPU_GP9                    0x1E0000E4,0x00000200
#define IPU_IPU_GPR__IPU_GP8                    0x1E0000E4,0x00000100
#define IPU_IPU_GPR__IPU_GP7                    0x1E0000E4,0x00000080
#define IPU_IPU_GPR__IPU_GP6                    0x1E0000E4,0x00000040
#define IPU_IPU_GPR__IPU_GP5                    0x1E0000E4,0x00000020
#define IPU_IPU_GPR__IPU_GP4                    0x1E0000E4,0x00000010
#define IPU_IPU_GPR__IPU_GP3                    0x1E0000E4,0x00000008
#define IPU_IPU_GPR__IPU_GP2                    0x1E0000E4,0x00000004
#define IPU_IPU_GPR__IPU_GP1                    0x1E0000E4,0x00000002
#define IPU_IPU_GPR__IPU_GP0                    0x1E0000E4,0x00000001

#define IPU_IPU_CH_DB_MODE_SEL_0__ADDR                  0x1E000150
#define IPU_IPU_CH_DB_MODE_SEL_0__EMPTY                 0x1E000150,0x00000000
#define IPU_IPU_CH_DB_MODE_SEL_0__FULL                  0x1E000150,0xffffffff
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_31 0x1E000150,0x80000000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_29 0x1E000150,0x20000000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_28 0x1E000150,0x10000000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_27 0x1E000150,0x08000000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_24 0x1E000150,0x01000000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_23 0x1E000150,0x00800000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_22 0x1E000150,0x00400000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_21 0x1E000150,0x00200000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_20 0x1E000150,0x00100000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_18 0x1E000150,0x00040000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_17 0x1E000150,0x00020000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_15 0x1E000150,0x00008000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_14 0x1E000150,0x00004000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_12 0x1E000150,0x00001000
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_11 0x1E000150,0x00000800
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_7  0x1E000150,0x00000080
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_6  0x1E000150,0x00000040
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_5  0x1E000150,0x00000020
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_4  0x1E000150,0x00000010
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_3  0x1E000150,0x00000008
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_2  0x1E000150,0x00000004
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_1  0x1E000150,0x00000002
#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_0  0x1E000150,0x00000001

#define IPU_IPU_CH_DB_MODE_SEL_1__ADDR                  0x1E000154
#define IPU_IPU_CH_DB_MODE_SEL_1__EMPTY                 0x1E000154,0x00000000
#define IPU_IPU_CH_DB_MODE_SEL_1__FULL                  0x1E000154,0xffffffff
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_52 0x1E000154,0x00100000
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_51 0x1E000154,0x00080000
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_50 0x1E000154,0x00040000
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_49 0x1E000154,0x00020000
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_48 0x1E000154,0x00010000
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_47 0x1E000154,0x00008000
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_46 0x1E000154,0x00004000
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_45 0x1E000154,0x00002000
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_44 0x1E000154,0x00001000
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_43 0x1E000154,0x00000800
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_42 0x1E000154,0x00000400
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_41 0x1E000154,0x00000200
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_40 0x1E000154,0x00000100
#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_33 0x1E000154,0x00000002

#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__ADDR                      0x1E000168
#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__EMPTY                     0x1E000168,0x00000000
#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__FULL                      0x1E000168,0xffffffff
#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_29 0x1E000168,0x20000000
#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_24 0x1E000168,0x01000000
#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_7  0x1E000168,0x00000080
#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_6  0x1E000168,0x00000040
#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_5  0x1E000168,0x00000020
#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_4  0x1E000168,0x00000010

#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__ADDR                      0x1E00016C
#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__EMPTY                     0x1E00016C,0x00000000
#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__FULL                      0x1E00016C,0xffffffff
#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_52 0x1E00016C,0x00100000
#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_41 0x1E00016C,0x00000200
#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_33 0x1E00016C,0x00000002

#define IPU_IPU_CH_TRB_MODE_SEL_0__ADDR                      0x1E000178
#define IPU_IPU_CH_TRB_MODE_SEL_1__ADDR                      0x1E00017C

// ================== End of IPUV3EX Common Registers ======================

// ================= Start of IPUV3EX Status Registers =====================

#define IPU_IPU_INT_STAT_1__ADDR         0x1E000200
#define IPU_IPU_INT_STAT_1__EMPTY        0x1E000200,0x00000000
#define IPU_IPU_INT_STAT_1__FULL         0x1E000200,0xffffffff
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_31 0x1E000200,0x80000000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_29 0x1E000200,0x20000000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_28 0x1E000200,0x10000000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_27 0x1E000200,0x08000000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_24 0x1E000200,0x01000000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_23 0x1E000200,0x00800000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_22 0x1E000200,0x00400000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_21 0x1E000200,0x00200000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_20 0x1E000200,0x00100000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_18 0x1E000200,0x00040000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_17 0x1E000200,0x00020000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_15 0x1E000200,0x00008000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_14 0x1E000200,0x00004000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_12 0x1E000200,0x00001000
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_11 0x1E000200,0x00000800
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_7  0x1E000200,0x00000080
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_6  0x1E000200,0x00000040
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_5  0x1E000200,0x00000020
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_4  0x1E000200,0x00000010
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_3  0x1E000200,0x00000008
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_2  0x1E000200,0x00000004
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_1  0x1E000200,0x00000002
#define IPU_IPU_INT_STAT_1__IDMAC_EOF_0  0x1E000200,0x00000001

#define IPU_IPU_INT_STAT_2__ADDR         0x1E000204
#define IPU_IPU_INT_STAT_2__EMPTY        0x1E000204,0x00000000
#define IPU_IPU_INT_STAT_2__FULL         0x1E000204,0xffffffff
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_52 0x1E000204,0x00100000
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_51 0x1E000204,0x00080000
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_50 0x1E000204,0x00040000
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_49 0x1E000204,0x00020000
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_48 0x1E000204,0x00010000
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_47 0x1E000204,0x00008000
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_46 0x1E000204,0x00004000
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_45 0x1E000204,0x00002000
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_44 0x1E000204,0x00001000
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_43 0x1E000204,0x00000800
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_42 0x1E000204,0x00000400
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_41 0x1E000204,0x00000200
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_40 0x1E000204,0x00000100
#define IPU_IPU_INT_STAT_2__IDMAC_EOF_33 0x1E000204,0x00000002

#define IPU_IPU_INT_STAT_3__ADDR           0x1E000208
#define IPU_IPU_INT_STAT_3__EMPTY          0x1E000208,0x00000000
#define IPU_IPU_INT_STAT_3__FULL           0x1E000208,0xffffffff
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_31 0x1E000208,0x80000000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_29 0x1E000208,0x20000000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_28 0x1E000208,0x10000000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_27 0x1E000208,0x08000000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_24 0x1E000208,0x01000000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_23 0x1E000208,0x00800000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_22 0x1E000208,0x00400000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_21 0x1E000208,0x00200000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_20 0x1E000208,0x00100000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_18 0x1E000208,0x00040000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_17 0x1E000208,0x00020000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_15 0x1E000208,0x00008000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_14 0x1E000208,0x00004000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_12 0x1E000208,0x00001000
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_11 0x1E000208,0x00000800
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_7  0x1E000208,0x00000080
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_6  0x1E000208,0x00000040
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_5  0x1E000208,0x00000020
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_4  0x1E000208,0x00000010
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_3  0x1E000208,0x00000008
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_2  0x1E000208,0x00000004
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_1  0x1E000208,0x00000002
#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_0  0x1E000208,0x00000001

#define IPU_IPU_INT_STAT_4__ADDR           0x1E00020C
#define IPU_IPU_INT_STAT_4__EMPTY          0x1E00020C,0x00000000
#define IPU_IPU_INT_STAT_4__FULL           0x1E00020C,0xffffffff
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_52 0x1E00020C,0x00100000
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_51 0x1E00020C,0x00080000
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_50 0x1E00020C,0x00040000
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_49 0x1E00020C,0x00020000
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_48 0x1E00020C,0x00010000
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_47 0x1E00020C,0x00008000
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_46 0x1E00020C,0x00004000
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_45 0x1E00020C,0x00002000
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_44 0x1E00020C,0x00001000
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_43 0x1E00020C,0x00000800
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_42 0x1E00020C,0x00000400
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_41 0x1E00020C,0x00000200
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_40 0x1E00020C,0x00000100
#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_33 0x1E00020C,0x00000002

#define IPU_IPU_INT_STAT_5__ADDR                 0x1E000210
#define IPU_IPU_INT_STAT_5__EMPTY                0x1E000210,0x00000000
#define IPU_IPU_INT_STAT_5__FULL                 0x1E000210,0xffffffff
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_31 0x1E000210,0x80000000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_29 0x1E000210,0x20000000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_28 0x1E000210,0x10000000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_27 0x1E000210,0x08000000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_24 0x1E000210,0x01000000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_23 0x1E000210,0x00800000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_22 0x1E000210,0x00400000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_21 0x1E000210,0x00200000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_20 0x1E000210,0x00100000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_18 0x1E000210,0x00040000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_17 0x1E000210,0x00020000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_15 0x1E000210,0x00008000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_14 0x1E000210,0x00004000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_12 0x1E000210,0x00001000
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_11 0x1E000210,0x00000800
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_7  0x1E000210,0x00000080
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_6  0x1E000210,0x00000040
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_5  0x1E000210,0x00000020
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_4  0x1E000210,0x00000010
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_3  0x1E000210,0x00000008
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_2  0x1E000210,0x00000004
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_1  0x1E000210,0x00000002
#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_0  0x1E000210,0x00000001

#define IPU_IPU_INT_STAT_6__ADDR                 0x1E000214
#define IPU_IPU_INT_STAT_6__EMPTY                0x1E000214,0x00000000
#define IPU_IPU_INT_STAT_6__FULL                 0x1E000214,0xffffffff
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_52 0x1E000214,0x00100000
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_51 0x1E000214,0x00080000
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_50 0x1E000214,0x00040000
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_49 0x1E000214,0x00020000
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_48 0x1E000214,0x00010000
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_47 0x1E000214,0x00008000
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_46 0x1E000214,0x00004000
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_45 0x1E000214,0x00002000
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_44 0x1E000214,0x00001000
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_43 0x1E000214,0x00000800
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_42 0x1E000214,0x00000400
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_41 0x1E000214,0x00000200
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_40 0x1E000214,0x00000100
#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_33 0x1E000214,0x00000002

#define IPU_IPU_INT_STAT_7__ADDR         0x1E000218
#define IPU_IPU_INT_STAT_7__EMPTY        0x1E000218,0x00000000
#define IPU_IPU_INT_STAT_7__FULL         0x1E000218,0xffffffff
#define IPU_IPU_INT_STAT_7__IDMAC_EOS_31 0x1E000218,0x80000000
#define IPU_IPU_INT_STAT_7__IDMAC_EOS_29 0x1E000218,0x20000000
#define IPU_IPU_INT_STAT_7__IDMAC_EOS_28 0x1E000218,0x10000000
#define IPU_IPU_INT_STAT_7__IDMAC_EOS_27 0x1E000218,0x08000000
#define IPU_IPU_INT_STAT_7__IDMAC_EOS_24 0x1E000218,0x01000000
#define IPU_IPU_INT_STAT_7__IDMAC_EOS_23 0x1E000218,0x00800000

#define IPU_IPU_INT_STAT_8__ADDR         0x1E00021C
#define IPU_IPU_INT_STAT_8__EMPTY        0x1E00021C,0x00000000
#define IPU_IPU_INT_STAT_8__FULL         0x1E00021C,0xffffffff
#define IPU_IPU_INT_STAT_8__IDMAC_EOS_52 0x1E00021C,0x00100000
#define IPU_IPU_INT_STAT_8__IDMAC_EOS_51 0x1E00021C,0x00080000
#define IPU_IPU_INT_STAT_8__IDMAC_EOS_44 0x1E00021C,0x00001000
#define IPU_IPU_INT_STAT_8__IDMAC_EOS_43 0x1E00021C,0x00000800
#define IPU_IPU_INT_STAT_8__IDMAC_EOS_42 0x1E00021C,0x00000400
#define IPU_IPU_INT_STAT_8__IDMAC_EOS_41 0x1E00021C,0x00000200
#define IPU_IPU_INT_STAT_8__IDMAC_EOS_32 0x1E00021C,0x00000002

#define IPU_IPU_INT_STAT_9__ADDR             0x1E000220
#define IPU_IPU_INT_STAT_9__EMPTY            0x1E000220,0x00000000
#define IPU_IPU_INT_STAT_9__FULL             0x1E000220,0xffffffff
#define IPU_IPU_INT_STAT_9__CSI1_PUPE        0x1E000220,0x80000000
#define IPU_IPU_INT_STAT_9__CSI0_PUPE        0x1E000220,0x40000000
#define IPU_IPU_INT_STAT_9__ISP_PUPE         0x1E000220,0x20000000
#define IPU_IPU_INT_STAT_9__IC_VF_BUF_OVF    0x1E000220,0x10000000
#define IPU_IPU_INT_STAT_9__IC_ENC_BUF_OVF   0x1E000220,0x08000000
#define IPU_IPU_INT_STAT_9__IC_BAYER_BUF_OVF 0x1E000220,0x04000000

#define IPU_IPU_INT_STAT_10__ADDR                   0x1E000224
#define IPU_IPU_INT_STAT_10__EMPTY                  0x1E000224,0x00000000
#define IPU_IPU_INT_STAT_10__FULL                   0x1E000224,0xffffffff
#define IPU_IPU_INT_STAT_10__AXIR_ERR               0x1E000224,0x40000000
#define IPU_IPU_INT_STAT_10__AXIW_ERR               0x1E000224,0x20000000
#define IPU_IPU_INT_STAT_10__NON_PRIVILEGED_ACC_ERR 0x1E000224,0x10000000
#define IPU_IPU_INT_STAT_10__IC_BAYER_FRM_LOST_ERR  0x1E000224,0x04000000
#define IPU_IPU_INT_STAT_10__IC_ENC_FRM_LOST_ERR    0x1E000224,0x02000000
#define IPU_IPU_INT_STAT_10__IC_VF_FRM_LOST_ERR     0x1E000224,0x01000000
#define IPU_IPU_INT_STAT_10__DI1_TIME_OUT_ERR       0x1E000224,0x00400000
#define IPU_IPU_INT_STAT_10__DI0_TIME_OUT_ERR       0x1E000224,0x00200000
#define IPU_IPU_INT_STAT_10__DI1_SYNC_DISP_ERR      0x1E000224,0x00100000
#define IPU_IPU_INT_STAT_10__DI0_SYNC_DISP_ERR      0x1E000224,0x00080000
#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_6       0x1E000224,0x00040000
#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_2       0x1E000224,0x00020000
#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_1       0x1E000224,0x00010000
#define IPU_IPU_INT_STAT_10__ISP_RAM_HIST_OF        0x1E000224,0x00000020
#define IPU_IPU_INT_STAT_10__ISP_RAM_ST_OF          0x1E000224,0x00000010
#define IPU_IPU_INT_STAT_10__SMFC3_FRM_LOST         0x1E000224,0x00000008
#define IPU_IPU_INT_STAT_10__SMFC2_FRM_LOST         0x1E000224,0x00000004
#define IPU_IPU_INT_STAT_10__SMFC1_FRM_LOST         0x1E000224,0x00000002
#define IPU_IPU_INT_STAT_10__SMFC0_FRM_LOST         0x1E000224,0x00000001

#define IPU_IPU_INT_STAT_11__ADDR           0x1E000228
#define IPU_IPU_INT_STAT_11__EMPTY          0x1E000228,0x00000000
#define IPU_IPU_INT_STAT_11__FULL           0x1E000228,0xffffffff
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_22 0x1E000228,0x00400000
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_21 0x1E000228,0x00200000
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_20 0x1E000228,0x00100000
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_12 0x1E000228,0x00001000
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_11 0x1E000228,0x00000800
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_5  0x1E000228,0x00000020
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_3  0x1E000228,0x00000008
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_2  0x1E000228,0x00000004
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_1  0x1E000228,0x00000002
#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_0  0x1E000228,0x00000001

#define IPU_IPU_INT_STAT_12__ADDR           0x1E00022C
#define IPU_IPU_INT_STAT_12__EMPTY          0x1E00022C,0x00000000
#define IPU_IPU_INT_STAT_12__FULL           0x1E00022C,0xffffffff
#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_50 0x1E00022C,0x00040000
#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_49 0x1E00022C,0x00020000
#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_48 0x1E00022C,0x00010000
#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_47 0x1E00022C,0x00008000
#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_46 0x1E00022C,0x00004000
#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_45 0x1E00022C,0x00002000

#define IPU_IPU_INT_STAT_13__ADDR        0x1E000230
#define IPU_IPU_INT_STAT_13__EMPTY       0x1E000230,0x00000000
#define IPU_IPU_INT_STAT_13__FULL        0x1E000230,0xffffffff
#define IPU_IPU_INT_STAT_13__IDMAC_TH_31 0x1E000230,0x80000000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_29 0x1E000230,0x20000000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_28 0x1E000230,0x10000000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_27 0x1E000230,0x08000000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_24 0x1E000230,0x01000000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_23 0x1E000230,0x00800000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_22 0x1E000230,0x00400000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_21 0x1E000230,0x00200000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_20 0x1E000230,0x00100000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_18 0x1E000230,0x00040000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_17 0x1E000230,0x00020000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_15 0x1E000230,0x00008000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_14 0x1E000230,0x00004000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_12 0x1E000230,0x00001000
#define IPU_IPU_INT_STAT_13__IDMAC_TH_11 0x1E000230,0x00000800
#define IPU_IPU_INT_STAT_13__IDMAC_TH_7  0x1E000230,0x00000080
#define IPU_IPU_INT_STAT_13__IDMAC_TH_6  0x1E000230,0x00000040
#define IPU_IPU_INT_STAT_13__IDMAC_TH_5  0x1E000230,0x00000020
#define IPU_IPU_INT_STAT_13__IDMAC_TH_4  0x1E000230,0x00000010
#define IPU_IPU_INT_STAT_13__IDMAC_TH_3  0x1E000230,0x00000008
#define IPU_IPU_INT_STAT_13__IDMAC_TH_2  0x1E000230,0x00000004
#define IPU_IPU_INT_STAT_13__IDMAC_TH_1  0x1E000230,0x00000002
#define IPU_IPU_INT_STAT_13__IDMAC_TH_0  0x1E000230,0x00000001

#define IPU_IPU_INT_STAT_14__ADDR        0x1E000234
#define IPU_IPU_INT_STAT_14__EMPTY       0x1E000234,0x00000000
#define IPU_IPU_INT_STAT_14__FULL        0x1E000234,0xffffffff
#define IPU_IPU_INT_STAT_14__IDMAC_TH_52 0x1E000234,0x00100000
#define IPU_IPU_INT_STAT_14__IDMAC_TH_51 0x1E000234,0x00080000
#define IPU_IPU_INT_STAT_14__IDMAC_TH_50 0x1E000234,0x00040000
#define IPU_IPU_INT_STAT_14__IDMAC_TH_49 0x1E000234,0x00020000
#define IPU_IPU_INT_STAT_14__IDMAC_TH_48 0x1E000234,0x00010000
#define IPU_IPU_INT_STAT_14__IDMAC_TH_47 0x1E000234,0x00008000
#define IPU_IPU_INT_STAT_14__IDMAC_TH_46 0x1E000234,0x00004000
#define IPU_IPU_INT_STAT_14__IDMAC_TH_45 0x1E000234,0x00002000
#define IPU_IPU_INT_STAT_14__IDMAC_TH_44 0x1E000234,0x00001000
#define IPU_IPU_INT_STAT_14__IDMAC_TH_43 0x1E000234,0x00000800
#define IPU_IPU_INT_STAT_14__IDMAC_TH_42 0x1E000234,0x00000400
#define IPU_IPU_INT_STAT_14__IDMAC_TH_41 0x1E000234,0x00000200
#define IPU_IPU_INT_STAT_14__IDMAC_TH_40 0x1E000234,0x00000100
#define IPU_IPU_INT_STAT_14__IDMAC_TH_33 0x1E000234,0x00000002

#define IPU_IPU_INT_STAT_15__ADDR                0x1E000238
#define IPU_IPU_INT_STAT_15__EMPTY               0x1E000238,0x00000000
#define IPU_IPU_INT_STAT_15__FULL                0x1E000238,0xffffffff
#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_8    0x1E000238,0x80000000
#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_3    0x1E000238,0x40000000
#define IPU_IPU_INT_STAT_15__DI1_DISP_CLK_EN_PRE 0x1E000238,0x20000000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_10   0x1E000238,0x10000000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_9    0x1E000238,0x08000000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_8    0x1E000238,0x04000000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_7    0x1E000238,0x02000000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_6    0x1E000238,0x01000000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_5    0x1E000238,0x00800000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_4    0x1E000238,0x00400000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_3    0x1E000238,0x00200000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_2    0x1E000238,0x00100000
#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_1    0x1E000238,0x00080000
#define IPU_IPU_INT_STAT_15__DI0_DISP_CLK_EN_PRE 0x1E000238,0x00040000
#define IPU_IPU_INT_STAT_15__DC_ASYNC_STOP       0x1E000238,0x00020000
#define IPU_IPU_INT_STAT_15__DC_DP_START         0x1E000238,0x00010000
#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_1      0x1E000238,0x00008000
#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_0      0x1E000238,0x00004000
#define IPU_IPU_INT_STAT_15__DC_FC_6             0x1E000238,0x00002000
#define IPU_IPU_INT_STAT_15__DC_FC_4             0x1E000238,0x00001000
#define IPU_IPU_INT_STAT_15__DC_FC_3             0x1E000238,0x00000800
#define IPU_IPU_INT_STAT_15__DC_FC_2             0x1E000238,0x00000400
#define IPU_IPU_INT_STAT_15__DC_FC_1             0x1E000238,0x00000200
#define IPU_IPU_INT_STAT_15__DC_FC_0             0x1E000238,0x00000100
#define IPU_IPU_INT_STAT_15__DP_ASF_BRAKE        0x1E000238,0x00000080
#define IPU_IPU_INT_STAT_15__DP_SF_BRAKE         0x1E000238,0x00000040
#define IPU_IPU_INT_STAT_15__DP_ASF_END          0x1E000238,0x00000020
#define IPU_IPU_INT_STAT_15__DP_ASF_START        0x1E000238,0x00000010
#define IPU_IPU_INT_STAT_15__DP_SF_END           0x1E000238,0x00000008
#define IPU_IPU_INT_STAT_15__DP_SF_START         0x1E000238,0x00000004
#define IPU_IPU_INT_STAT_15__IPU_SNOOPING2_INT   0x1E000238,0x00000002
#define IPU_IPU_INT_STAT_15__IPU_SNOOPING1_INT   0x1E000238,0x00000001

#define IPU_IPU_CUR_BUF_0__ADDR              0x1E00023C
#define IPU_IPU_CUR_BUF_0__EMPTY             0x1E00023C,0x00000000
#define IPU_IPU_CUR_BUF_0__FULL              0x1E00023C,0xffffffff
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_31 0x1E00023C,0x80000000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_29 0x1E00023C,0x20000000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_28 0x1E00023C,0x10000000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_27 0x1E00023C,0x08000000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_24 0x1E00023C,0x01000000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_23 0x1E00023C,0x00800000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_22 0x1E00023C,0x00400000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_21 0x1E00023C,0x00200000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_20 0x1E00023C,0x00100000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_18 0x1E00023C,0x00040000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_17 0x1E00023C,0x00020000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_15 0x1E00023C,0x00008000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_14 0x1E00023C,0x00004000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_12 0x1E00023C,0x00001000
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_11 0x1E00023C,0x00000800
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_7  0x1E00023C,0x00000080
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_6  0x1E00023C,0x00000040
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_5  0x1E00023C,0x00000020
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_4  0x1E00023C,0x00000010
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_3  0x1E00023C,0x00000008
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_2  0x1E00023C,0x00000004
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_1  0x1E00023C,0x00000002
#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_0  0x1E00023C,0x00000001

#define IPU_IPU_CUR_BUF_1__ADDR              0x1E000240
#define IPU_IPU_CUR_BUF_1__EMPTY             0x1E000240,0x00000000
#define IPU_IPU_CUR_BUF_1__FULL              0x1E000240,0xffffffff
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_52 0x1E000240,0x00100000
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_51 0x1E000240,0x00080000
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_50 0x1E000240,0x00040000
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_49 0x1E000240,0x00020000
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_48 0x1E000240,0x00010000
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_47 0x1E000240,0x00008000
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_46 0x1E000240,0x00004000
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_45 0x1E000240,0x00002000
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_44 0x1E000240,0x00001000
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_43 0x1E000240,0x00000800
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_42 0x1E000240,0x00000400
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_41 0x1E000240,0x00000200
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_40 0x1E000240,0x00000100
#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_33 0x1E000240,0x00000002

#define IPU_IPU_ALT_CUR_BUF_0__ADDR                  0x1E000244
#define IPU_IPU_ALT_CUR_BUF_0__EMPTY                 0x1E000244,0x00000000
#define IPU_IPU_ALT_CUR_BUF_0__FULL                  0x1E000244,0xffffffff
#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_29 0x1E000244,0x20000000
#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_24 0x1E000244,0x01000000
#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_7  0x1E000244,0x00000080
#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_6  0x1E000244,0x00000040
#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_5  0x1E000244,0x00000020
#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_4  0x1E000244,0x00000010

#define IPU_IPU_ALT_CUR_BUF_1__ADDR                  0x1E000248
#define IPU_IPU_ALT_CUR_BUF_1__EMPTY                 0x1E000248,0x00000000
#define IPU_IPU_ALT_CUR_BUF_1__FULL                  0x1E000248,0xffffffff
#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_52 0x1E000248,0x00100000
#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_41 0x1E000248,0x00000200
#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_33 0x1E000248,0x00000002

#define IPU_IPU_SRM_STAT__ADDR           0x1E00024C
#define IPU_IPU_SRM_STAT__EMPTY          0x1E00024C,0x00000000
#define IPU_IPU_SRM_STAT__FULL           0x1E00024C,0xffffffff
#define IPU_IPU_SRM_STAT__DI1_SRM_STAT   0x1E00024C,0x00000200
#define IPU_IPU_SRM_STAT__DI0_SRM_STAT   0x1E00024C,0x00000100
#define IPU_IPU_SRM_STAT__CSI1_SRM_STAT  0x1E00024C,0x00000080
#define IPU_IPU_SRM_STAT__CSI0_SRM_STAT  0x1E00024C,0x00000040
#define IPU_IPU_SRM_STAT__DC_6_SRM_STAT  0x1E00024C,0x00000020
#define IPU_IPU_SRM_STAT__DC_2_SRM_STAT  0x1E00024C,0x00000010
#define IPU_IPU_SRM_STAT__ISP_SRM_STAT   0x1E00024C,0x00000008
#define IPU_IPU_SRM_STAT__DP_A1_SRM_STAT 0x1E00024C,0x00000004
#define IPU_IPU_SRM_STAT__DP_A0_SRM_STAT 0x1E00024C,0x00000002
#define IPU_IPU_SRM_STAT__DP_S_SRM_STAT  0x1E00024C,0x00000001

#define IPU_IPU_PROC_TASKS_STAT__ADDR                0x1E000250
#define IPU_IPU_PROC_TASKS_STAT__EMPTY               0x1E000250,0x00000000
#define IPU_IPU_PROC_TASKS_STAT__FULL                0x1E000250,0xffffffff
#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC3_TSTAT 0x1E000250,0x00C00000
#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC2_TSTAT 0x1E000250,0x00300000
#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC1_TSTAT 0x1E000250,0x000C0000
#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC0_TSTAT 0x1E000250,0x00030000
#define IPU_IPU_PROC_TASKS_STAT__MEM2PRP_TSTAT       0x1E000250,0x00007000
#define IPU_IPU_PROC_TASKS_STAT__PP_ROT_TSTAT        0x1E000250,0x00000C00
#define IPU_IPU_PROC_TASKS_STAT__VF_ROT_TSTAT        0x1E000250,0x00000300
#define IPU_IPU_PROC_TASKS_STAT__ENC_ROT_TSTAT       0x1E000250,0x000000C0
#define IPU_IPU_PROC_TASKS_STAT__PP_TSTAT            0x1E000250,0x00000030
#define IPU_IPU_PROC_TASKS_STAT__VF_TSTAT            0x1E000250,0x0000000C
#define IPU_IPU_PROC_TASKS_STAT__ENC_TSTAT           0x1E000250,0x00000003

#define IPU_IPU_DISP_TASKS_STAT__ADDR               0x1E000254
#define IPU_IPU_DISP_TASKS_STAT__EMPTY              0x1E000254,0x00000000
#define IPU_IPU_DISP_TASKS_STAT__FULL               0x1E000254,0xffffffff
#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC2_CUR_FLOW 0x1E000254,0x00000800
#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC2_STAT     0x1E000254,0x00000700
#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC1_STAT     0x1E000254,0x00000030
#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_CUR_FLOW  0x1E000254,0x00000008
#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_STAT      0x1E000254,0x00000007

#define IPU_IPU_TRB_CUR_BUF_REG0__ADDR                  0x0E000258
#define IPU_IPU_TRB_CUR_BUF_REG1__ADDR                  0x0E00025C
#define IPU_IPU_TRB_CUR_BUF_REG2__ADDR                  0x0E000260
#define IPU_IPU_TRB_CUR_BUF_REG3__ADDR                  0x0E000264

#define IPU_IPU_CH_BUF0_RDY0__ADDR               0x1E000268
#define IPU_IPU_CH_BUF0_RDY0__EMPTY              0x1E000268,0x00000000
#define IPU_IPU_CH_BUF0_RDY0__FULL               0x1E000268,0xffffffff
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_31 0x1E000268,0x80000000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_29 0x1E000268,0x20000000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_28 0x1E000268,0x10000000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_27 0x1E000268,0x08000000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_24 0x1E000268,0x01000000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_23 0x1E000268,0x00800000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_22 0x1E000268,0x00400000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_21 0x1E000268,0x00200000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_20 0x1E000268,0x00100000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_18 0x1E000268,0x00040000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_17 0x1E000268,0x00020000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_15 0x1E000268,0x00008000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_14 0x1E000268,0x00004000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_12 0x1E000268,0x00001000
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_11 0x1E000268,0x00000800
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_7  0x1E000268,0x00000080
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_6  0x1E000268,0x00000040
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_5  0x1E000268,0x00000020
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_4  0x1E000268,0x00000010
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_3  0x1E000268,0x00000008
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_2  0x1E000268,0x00000004
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_1  0x1E000268,0x00000002
#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_0  0x1E000268,0x00000001

#define IPU_IPU_CH_BUF0_RDY1__ADDR               0x1E00026C
#define IPU_IPU_CH_BUF0_RDY1__EMPTY              0x1E00026C,0x00000000
#define IPU_IPU_CH_BUF0_RDY1__FULL               0x1E00026C,0xffffffff
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_52 0x1E00026C,0x00100000
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_51 0x1E00026C,0x00080000
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_50 0x1E00026C,0x00040000
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_49 0x1E00026C,0x00020000
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_48 0x1E00026C,0x00010000
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_47 0x1E00026C,0x00008000
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_46 0x1E00026C,0x00004000
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_45 0x1E00026C,0x00002000
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_44 0x1E00026C,0x00001000
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_43 0x1E00026C,0x00000800
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_42 0x1E00026C,0x00000400
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_41 0x1E00026C,0x00000200
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_40 0x1E00026C,0x00000100
#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_33 0x1E00026C,0x00000002

#define IPU_IPU_CH_BUF1_RDY0__ADDR               0x1E000270
#define IPU_IPU_CH_BUF1_RDY0__EMPTY              0x1E000270,0x00000000
#define IPU_IPU_CH_BUF1_RDY0__FULL               0x1E000270,0xffffffff
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_31 0x1E000270,0x80000000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_29 0x1E000270,0x20000000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_28 0x1E000270,0x10000000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_27 0x1E000270,0x08000000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_24 0x1E000270,0x01000000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_23 0x1E000270,0x00800000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_22 0x1E000270,0x00400000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_21 0x1E000270,0x00200000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_20 0x1E000270,0x00100000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_18 0x1E000270,0x00040000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_17 0x1E000270,0x00020000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_15 0x1E000270,0x00008000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_14 0x1E000270,0x00004000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_12 0x1E000270,0x00001000
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_11 0x1E000270,0x00000800
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_7  0x1E000270,0x00000080
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_6  0x1E000270,0x00000040
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_5  0x1E000270,0x00000020
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_4  0x1E000270,0x00000010
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_3  0x1E000270,0x00000008
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_2  0x1E000270,0x00000004
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_1  0x1E000270,0x00000002
#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_0  0x1E000270,0x00000001

#define IPU_IPU_CH_BUF1_RDY1__ADDR               0x1E000274
#define IPU_IPU_CH_BUF1_RDY1__EMPTY              0x1E000274,0x00000000
#define IPU_IPU_CH_BUF1_RDY1__FULL               0x1E000274,0xffffffff
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_52 0x1E000274,0x00100000
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_51 0x1E000274,0x00080000
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_50 0x1E000274,0x00040000
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_49 0x1E000274,0x00020000
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_48 0x1E000274,0x00010000
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_47 0x1E000274,0x00008000
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_46 0x1E000274,0x00004000
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_45 0x1E000274,0x00002000
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_44 0x1E000274,0x00001000
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_43 0x1E000274,0x00000800
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_42 0x1E000274,0x00000400
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_41 0x1E000274,0x00000200
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_40 0x1E000274,0x00000100
#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_33 0x1E000274,0x00000002

#define IPU_IPU_ALT_CH_BUF0_RDY0__ADDR                   0x1E000278
#define IPU_IPU_ALT_CH_BUF0_RDY0__EMPTY                  0x1E000278,0x00000000
#define IPU_IPU_ALT_CH_BUF0_RDY0__FULL                   0x1E000278,0xffffffff
#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_29 0x1E000278,0x20000000
#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_24 0x1E000278,0x01000000
#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_7  0x1E000278,0x00000080
#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_6  0x1E000278,0x00000040
#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_5  0x1E000278,0x00000020
#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_4  0x1E000278,0x00000010

#define IPU_IPU_ALT_CH_BUF0_RDY1__ADDR                   0x1E00027C
#define IPU_IPU_ALT_CH_BUF0_RDY1__EMPTY                  0x1E00027C,0x00000000
#define IPU_IPU_ALT_CH_BUF0_RDY1__FULL                   0x1E00027C,0xffffffff
#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_52 0x1E00027C,0x00100000
#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_41 0x1E00027C,0x00000200
#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_33 0x1E00027C,0x00000002

#define IPU_IPU_ALT_CH_BUF1_RDY0__ADDR                   0x1E000280
#define IPU_IPU_ALT_CH_BUF1_RDY0__EMPTY                  0x1E000280,0x00000000
#define IPU_IPU_ALT_CH_BUF1_RDY0__FULL                   0x1E000280,0xffffffff
#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_29 0x1E000280,0x20000000
#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_24 0x1E000280,0x01000000
#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_7  0x1E000280,0x00000080
#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_6  0x1E000280,0x00000040
#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_5  0x1E000280,0x00000020
#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_4  0x1E000280,0x00000010

#define IPU_IPU_ALT_CH_BUF1_RDY1__ADDR                   0x1E000284
#define IPU_IPU_ALT_CH_BUF1_RDY1__EMPTY                  0x1E000284,0x00000000
#define IPU_IPU_ALT_CH_BUF1_RDY1__FULL                   0x1E000284,0xffffffff
#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_52 0x1E000284,0x00100000
#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_41 0x1E000284,0x00000200
#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_33 0x1E000284,0x00000002

#define IPU_IPU_CH_BUF2_RDY0__ADDR               0x1E000288
#define IPU_IPU_CH_BUF2_RDY1__ADDR               0x1E00028C

// ================== End of IPUV3EX Status Registers ======================

// ================= Start of IPUV3EX IDMAC Registers =====================
#define IPU_IDMAC_CONF__ADDR         0x1E008000
#define IPU_IDMAC_CONF__EMPTY        0x1E008000,0x00000000
#define IPU_IDMAC_CONF__FULL         0x1E008000,0xffffffff
#define IPU_IDMAC_CONF__P_ENDIAN     0x1E008000,0x00010000
#define IPU_IDMAC_CONF__RDI          0x1E008000,0x00000020
#define IPU_IDMAC_CONF__WIDPT        0x1E008000,0x00000018
#define IPU_IDMAC_CONF__MAX_REQ_READ 0x1E008000,0x00000007

#define IPU_IDMAC_CH_EN_1__ADDR           0x1E008004
#define IPU_IDMAC_CH_EN_1__EMPTY          0x1E008004,0x00000000
#define IPU_IDMAC_CH_EN_1__FULL           0x1E008004,0xffffffff
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_31 0x1E008004,0x80000000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_29 0x1E008004,0x20000000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_28 0x1E008004,0x10000000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_27 0x1E008004,0x08000000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_24 0x1E008004,0x01000000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_23 0x1E008004,0x00800000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_22 0x1E008004,0x00400000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_21 0x1E008004,0x00200000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_20 0x1E008004,0x00100000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_18 0x1E008004,0x00040000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_17 0x1E008004,0x00020000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_15 0x1E008004,0x00008000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_14 0x1E008004,0x00004000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_12 0x1E008004,0x00001000
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_11 0x1E008004,0x00000800
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_7  0x1E008004,0x00000080
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_6  0x1E008004,0x00000040
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_5  0x1E008004,0x00000020
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_4  0x1E008004,0x00000010
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_3  0x1E008004,0x00000008
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_2  0x1E008004,0x00000004
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_1  0x1E008004,0x00000002
#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_0  0x1E008004,0x00000001

#define IPU_IDMAC_CH_EN_2__ADDR           0x1E008008
#define IPU_IDMAC_CH_EN_2__EMPTY          0x1E008008,0x00000000
#define IPU_IDMAC_CH_EN_2__FULL           0x1E008008,0xffffffff
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_52 0x1E008008,0x00100000
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_51 0x1E008008,0x00080000
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_50 0x1E008008,0x00040000
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_49 0x1E008008,0x00020000
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_48 0x1E008008,0x00010000
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_47 0x1E008008,0x00008000
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_46 0x1E008008,0x00004000
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_45 0x1E008008,0x00002000
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_44 0x1E008008,0x00001000
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_43 0x1E008008,0x00000800
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_42 0x1E008008,0x00000400
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_41 0x1E008008,0x00000200
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_40 0x1E008008,0x00000100
#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_33 0x1E008008,0x00000002

#define IPU_IDMAC_SEP_ALPHA__ADDR            0x1E00800C
#define IPU_IDMAC_SEP_ALPHA__EMPTY           0x1E00800C,0x00000000
#define IPU_IDMAC_SEP_ALPHA__FULL            0x1E00800C,0xffffffff
#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29 0x1E00800C,0x20000000
#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27 0x1E00800C,0x08000000
#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24 0x1E00800C,0x01000000
#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23 0x1E00800C,0x00800000
#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15 0x1E00800C,0x00008000
#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14 0x1E00800C,0x00004000

#define IPU_IDMAC_ALT_SEP_ALPHA__ADDR                0x1E008010
#define IPU_IDMAC_ALT_SEP_ALPHA__EMPTY               0x1E008010,0x00000000
#define IPU_IDMAC_ALT_SEP_ALPHA__FULL                0x1E008010,0xffffffff
#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29 0x1E008010,0x20000000
#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24 0x1E008010,0x01000000
#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23 0x1E008010,0x00800000

#define IPU_IDMAC_CH_PRI_1__ADDR            0x1E008014
#define IPU_IDMAC_CH_PRI_1__EMPTY           0x1E008014,0x00000000
#define IPU_IDMAC_CH_PRI_1__FULL            0x1E008014,0xffffffff
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29 0x1E008014,0x20000000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28 0x1E008014,0x10000000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27 0x1E008014,0x08000000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24 0x1E008014,0x01000000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23 0x1E008014,0x00800000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22 0x1E008014,0x00400000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21 0x1E008014,0x00200000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20 0x1E008014,0x00100000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15 0x1E008014,0x00008000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14 0x1E008014,0x00004000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12 0x1E008014,0x00001000
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11 0x1E008014,0x00000800
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_7  0x1E008014,0x00000080
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_6  0x1E008014,0x00000040
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_5  0x1E008014,0x00000020
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_4  0x1E008014,0x00000010
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_3  0x1E008014,0x00000008
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_2  0x1E008014,0x00000004
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_1  0x1E008014,0x00000002
#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_0  0x1E008014,0x00000001

#define IPU_IDMAC_CH_PRI_2__ADDR            0x1E008018
#define IPU_IDMAC_CH_PRI_2__EMPTY           0x1E008018,0x00000000
#define IPU_IDMAC_CH_PRI_2__FULL            0x1E008018,0xffffffff
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50 0x1E008018,0x00040000
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49 0x1E008018,0x00020000
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48 0x1E008018,0x00010000
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47 0x1E008018,0x00008000
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46 0x1E008018,0x00004000
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45 0x1E008018,0x00002000
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44 0x1E008018,0x00001000
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43 0x1E008018,0x00000800
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42 0x1E008018,0x00000400
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41 0x1E008018,0x00000200
#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40 0x1E008018,0x00000100

#define IPU_IDMAC_WM_EN_1__ADDR           0x1E00801C
#define IPU_IDMAC_WM_EN_1__EMPTY          0x1E00801C,0x00000000
#define IPU_IDMAC_WM_EN_1__FULL           0x1E00801C,0xffffffff
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_29 0x1E00801C,0x20000000
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_28 0x1E00801C,0x10000000
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_27 0x1E00801C,0x08000000
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_24 0x1E00801C,0x01000000
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_23 0x1E00801C,0x00800000
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_14 0x1E00801C,0x00004000
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_12 0x1E00801C,0x00001000
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_3  0x1E00801C,0x00000008
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_2  0x1E00801C,0x00000004
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_1  0x1E00801C,0x00000002
#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_0  0x1E00801C,0x00000001

#define IPU_IDMAC_WM_EN_2__ADDR           0x1E008020
#define IPU_IDMAC_WM_EN_2__EMPTY          0x1E008020,0x00000000
#define IPU_IDMAC_WM_EN_2__FULL           0x1E008020,0xffffffff
#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_44 0x1E008020,0x00001000
#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_43 0x1E008020,0x00000800
#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_42 0x1E008020,0x00000400
#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_41 0x1E008020,0x00000200
#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_40 0x1E008020,0x00000100

#define IPU_IDMAC_LOCK_EN_1__ADDR             0x1E008024

#define IPU_IDMAC_LOCK_EN_2__ADDR             0x1E008028
#define IPU_IDMAC_LOCK_EN_2__EMPTY            0x1E008028,0x00000000
#define IPU_IDMAC_LOCK_EN_2__FULL             0x1E008028,0xffffffff
#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50 0x1E008028,0x00040000
#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49 0x1E008028,0x00020000
#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48 0x1E008028,0x00010000
#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47 0x1E008028,0x00008000
#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46 0x1E008028,0x00004000
#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45 0x1E008028,0x00002000

#define IPU_IDMAC_SUB_ADDR_0__ADDR             0x1E00802C
#define IPU_IDMAC_SUB_ADDR_0__EMPTY            0x1E00802C,0x00000000
#define IPU_IDMAC_SUB_ADDR_0__FULL             0x1E00802C,0xffffffff
#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_7 0x1E00802C,0x7F000000
#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_6 0x1E00802C,0x007F0000
#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_5 0x1E00802C,0x00007F00
#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_4 0x1E00802C,0x0000007F

#define IPU_IDMAC_SUB_ADDR_1__ADDR              0x1E008030
#define IPU_IDMAC_SUB_ADDR_1__EMPTY             0x1E008030,0x00000000
#define IPU_IDMAC_SUB_ADDR_1__FULL              0x1E008030,0xffffffff
#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33 0x1E008030,0x7F000000
#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29 0x1E008030,0x007F0000
#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24 0x1E008030,0x00007F00
#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23 0x1E008030,0x0000007F

#define IPU_IDMAC_SUB_ADDR_2__ADDR              0x1E008034
#define IPU_IDMAC_SUB_ADDR_2__EMPTY             0x1E008034,0x00000000
#define IPU_IDMAC_SUB_ADDR_2__FULL              0x1E008034,0xffffffff
#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52 0x1E008034,0x007F0000
#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51 0x1E008034,0x00007F00
#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41 0x1E008034,0x0000007F

#define IPU_IDMAC_SUB_ADDR_3__ADDR              0x1E008038
#define IPU_IDMAC_SUB_ADDR_4__ADDR              0x1E00803C

#define IPU_IDMAC_BNDM_EN_1__ADDR             0x1E008040
#define IPU_IDMAC_BNDM_EN_1__EMPTY            0x1E008040,0x00000000
#define IPU_IDMAC_BNDM_EN_1__FULL             0x1E008040,0xffffffff
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22 0x1E008040,0x00400000
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21 0x1E008040,0x00200000
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20 0x1E008040,0x00100000
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12 0x1E008040,0x00001000
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11 0x1E008040,0x00000800
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_5  0x1E008040,0x00000020
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_3  0x1E008040,0x00000008
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_2  0x1E008040,0x00000004
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_1  0x1E008040,0x00000002
#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_0  0x1E008040,0x00000001

#define IPU_IDMAC_BNDM_EN_2__ADDR             0x1E008044
#define IPU_IDMAC_BNDM_EN_2__EMPTY            0x1E008044,0x00000000
#define IPU_IDMAC_BNDM_EN_2__FULL             0x1E008044,0xffffffff
#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50 0x1E008044,0x00040000
#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49 0x1E008044,0x00020000
#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48 0x1E008044,0x00010000
#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47 0x1E008044,0x00008000
#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46 0x1E008044,0x00004000
#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45 0x1E008044,0x00002000

#define IPU_IDMAC_SC_CORD__ADDR  0x1E008048
#define IPU_IDMAC_SC_CORD__EMPTY 0x1E008048,0x00000000
#define IPU_IDMAC_SC_CORD__FULL  0x1E008048,0xffffffff
#define IPU_IDMAC_SC_CORD__SX0   0x1E008048,0x0FFF0000
#define IPU_IDMAC_SC_CORD__SY0   0x1E008048,0x000007FF

#define IPU_IDMAC_SC_CORD2__ADDR  0x1E00804C

#define IPU_IDMAC_CH_BUSY_1__ADDR             0x1E008100
#define IPU_IDMAC_CH_BUSY_1__EMPTY            0x1E008100,0x00000000
#define IPU_IDMAC_CH_BUSY_1__FULL             0x1E008100,0xffffffff
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_31 0x1E008100,0x80000000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_29 0x1E008100,0x20000000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_28 0x1E008100,0x10000000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_27 0x1E008100,0x08000000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_24 0x1E008100,0x01000000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_23 0x1E008100,0x00800000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_22 0x1E008100,0x00400000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_21 0x1E008100,0x00200000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_20 0x1E008100,0x00100000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_18 0x1E008100,0x00040000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_17 0x1E008100,0x00020000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_15 0x1E008100,0x00008000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_14 0x1E008100,0x00004000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_12 0x1E008100,0x00001000
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_11 0x1E008100,0x00000800
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_7  0x1E008100,0x00000080
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_6  0x1E008100,0x00000040
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_5  0x1E008100,0x00000020
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_4  0x1E008100,0x00000010
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_3  0x1E008100,0x00000008
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_2  0x1E008100,0x00000004
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_1  0x1E008100,0x00000002
#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_0  0x1E008100,0x00000001

#define IPU_IDMAC_CH_BUSY_2__ADDR             0x1E008104
#define IPU_IDMAC_CH_BUSY_2__EMPTY            0x1E008104,0x00000000
#define IPU_IDMAC_CH_BUSY_2__FULL             0x1E008104,0xffffffff
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_52 0x1E008104,0x00100000
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_51 0x1E008104,0x00080000
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_50 0x1E008104,0x00040000
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_49 0x1E008104,0x00020000
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_48 0x1E008104,0x00010000
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_47 0x1E008104,0x00008000
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_46 0x1E008104,0x00004000
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_45 0x1E008104,0x00002000
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_44 0x1E008104,0x00001000
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_43 0x1E008104,0x00000800
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_42 0x1E008104,0x00000400
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_41 0x1E008104,0x00000200
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_40 0x1E008104,0x00000100
#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_33 0x1E008104,0x00000002

// ================== End of IPUV3EX IDMAC Registers ======================

// ================= Start of IPUV3EX ISP Registers =====================
#define IPU_ISP_C0__ADDR              0x1E010000
#define IPU_ISP_C0__EMPTY             0x1E010000,0x00000000
#define IPU_ISP_C0__FULL              0x1E010000,0xffffffff
#define IPU_ISP_C0__ISP_BURST_SIZE    0x1E010000,0x001C0000
#define IPU_ISP_C0__ISP_RED_ROW_BEGIN 0x1E010000,0x00020000
#define IPU_ISP_C0__ISP_GREEN_P_BEGIN 0x1E010000,0x00010000
#define IPU_ISP_C0__LINEARCCM_ON      0x1E010000,0x00004000
#define IPU_ISP_C0__LLF_G_EN          0x1E010000,0x00002000
#define IPU_ISP_C0__LLF_RB_EN         0x1E010000,0x00001000
#define IPU_ISP_C0__AD_EN             0x1E010000,0x00000800
#define IPU_ISP_C0__STS_EN            0x1E010000,0x00000400
#define IPU_ISP_C0__CL_EN             0x1E010000,0x00000200
#define IPU_ISP_C0__CS_EN             0x1E010000,0x00000100
#define IPU_ISP_C0__CCA_EN            0x1E010000,0x00000080
#define IPU_ISP_C0__HFE_EN            0x1E010000,0x00000040
#define IPU_ISP_C0__CNS_EN            0x1E010000,0x00000020
#define IPU_ISP_C0__MTF_ROC_EN        0x1E010000,0x00000010
#define IPU_ISP_C0__GAMMA_EN          0x1E010000,0x00000008
#define IPU_ISP_C0__CROC_EN           0x1E010000,0x00000004
#define IPU_ISP_C0__TBPR_EN           0x1E010000,0x00000002
#define IPU_ISP_C0__BPR_EN            0x1E010000,0x00000001

#define IPU_ISP_C1__ADDR             0x1E010004
#define IPU_ISP_C1__EMPTY            0x1E010004,0x00000000
#define IPU_ISP_C1__FULL             0x1E010004,0xffffffff
#define IPU_ISP_C1__YUV_EN           0x1E010004,0x20000000
#define IPU_ISP_C1__CSC_SAT_MODE     0x1E010004,0x10000000
#define IPU_ISP_C1__BOTTOM_CROP      0x1E010004,0x0E000000
#define IPU_ISP_C1__TOP_CROP         0x1E010004,0x01C00000
#define IPU_ISP_C1__RIGHT_CROP       0x1E010004,0x00380000
#define IPU_ISP_C1__LEFT_CROP        0x1E010004,0x00070000
#define IPU_ISP_C1__MTF_ROC_SH_M     0x1E010004,0x00006000
#define IPU_ISP_C1__MTF_ROC_SH_N     0x1E010004,0x00001800
#define IPU_ISP_C1__MTF_ROC_SH_QA    0x1E010004,0x00000700
#define IPU_ISP_C1__MTF_ROC_SH_SHARP 0x1E010004,0x000000E0
#define IPU_ISP_C1__WIDEASPECT       0x1E010004,0x00000010
#define IPU_ISP_C1__APP_SEL          0x1E010004,0x0000000C
#define IPU_ISP_C1__INT_MODE         0x1E010004,0x00000003

#define IPU_ISP_FS__ADDR    0x1E010008
#define IPU_ISP_FS__EMPTY   0x1E010008,0x00000000
#define IPU_ISP_FS__FULL    0x1E010008,0xffffffff
#define IPU_ISP_FS__FWIDTH  0x1E010008,0x0FFF0000
#define IPU_ISP_FS__FHEIGHT 0x1E010008,0x00000FFF

#define IPU_ISP_BI__ADDR   0x1E01000C
#define IPU_ISP_BI__EMPTY  0x1E01000C,0x00000000
#define IPU_ISP_BI__FULL   0x1E01000C,0xffffffff
#define IPU_ISP_BI__HBLANK 0x1E01000C,0x0FFF0000
#define IPU_ISP_BI__VBLANK 0x1E01000C,0x00000FFF

#define IPU_ISP_OCO__ADDR    0x1E010010
#define IPU_ISP_OCO__EMPTY   0x1E010010,0x00000000
#define IPU_ISP_OCO__FULL    0x1E010010,0xffffffff
#define IPU_ISP_OCO__HOFFSET 0x1E010010,0x1FFF0000
#define IPU_ISP_OCO__VOFFSET 0x1E010010,0x00001FFF

#define IPU_ISP_BPR1__ADDR  0x1E010014
#define IPU_ISP_BPR1__EMPTY 0x1E010014,0x00000000
#define IPU_ISP_BPR1__FULL  0x1E010014,0xffffffff
#define IPU_ISP_BPR1__TB    0x1E010014,0xFF000000
#define IPU_ISP_BPR1__TDR   0x1E010014,0x00FF0000
#define IPU_ISP_BPR1__TR    0x1E010014,0x0000FF00
#define IPU_ISP_BPR1__DKR   0x1E010014,0x000000FF

#define IPU_ISP_BPR2__ADDR  0x1E010018
#define IPU_ISP_BPR2__EMPTY 0x1E010018,0x00000000
#define IPU_ISP_BPR2__FULL  0x1E010018,0xffffffff
#define IPU_ISP_BPR2__BRB   0x1E010018,0xFF000000
#define IPU_ISP_BPR2__TT    0x1E010018,0x00FF0000
#define IPU_ISP_BPR2__TVDB  0x1E010018,0x0000FF00
#define IPU_ISP_BPR2__TDB   0x1E010018,0x000000FF

#define IPU_ISP_BPR3__ADDR  0x1E01001C
#define IPU_ISP_BPR3__EMPTY 0x1E01001C,0x00000000
#define IPU_ISP_BPR3__FULL  0x1E01001C,0xffffffff
#define IPU_ISP_BPR3__TG    0x1E01001C,0xFF000000
#define IPU_ISP_BPR3__TGF   0x1E01001C,0x00FF0000
#define IPU_ISP_BPR3__DKB   0x1E01001C,0x0000FF00
#define IPU_ISP_BPR3__TG2   0x1E01001C,0x000000FF

#define IPU_ISP_BPR4__ADDR  0x1E010020
#define IPU_ISP_BPR4__EMPTY 0x1E010020,0x00000000
#define IPU_ISP_BPR4__FULL  0x1E010020,0xffffffff
#define IPU_ISP_BPR4__DKRCL 0x1E010020,0xFF000000
#define IPU_ISP_BPR4__TGFCL 0x1E010020,0x00FF0000
#define IPU_ISP_BPR4__TCL2  0x1E010020,0x0000FF00
#define IPU_ISP_BPR4__TCL   0x1E010020,0x000000FF

#define IPU_ISP_BPR5__ADDR  0x1E010024
#define IPU_ISP_BPR5__EMPTY 0x1E010024,0x00000000
#define IPU_ISP_BPR5__FULL  0x1E010024,0xffffffff
#define IPU_ISP_BPR5__TGL2  0x1E010024,0x0000FF00
#define IPU_ISP_BPR5__TBC   0x1E010024,0x000000FF

#define IPU_ISP_CCMLIN0__ADDR     0x1E010028
#define IPU_ISP_CCMLIN0__EMPTY    0x1E010028,0x00000000
#define IPU_ISP_CCMLIN0__FULL     0x1E010028,0xffffffff
#define IPU_ISP_CCMLIN0__CCMLIN12 0x1E010028,0x7C000000
#define IPU_ISP_CCMLIN0__CCMLIN11 0x1E010028,0x03E00000
#define IPU_ISP_CCMLIN0__CCMLIN10 0x1E010028,0x001F0000
#define IPU_ISP_CCMLIN0__CCMLIN02 0x1E010028,0x00007C00
#define IPU_ISP_CCMLIN0__CCMLIN01 0x1E010028,0x000003E0
#define IPU_ISP_CCMLIN0__CCMLIN00 0x1E010028,0x0000001F

#define IPU_ISP_CCMLIN1__ADDR     0x1E01002C
#define IPU_ISP_CCMLIN1__EMPTY    0x1E01002C,0x00000000
#define IPU_ISP_CCMLIN1__FULL     0x1E01002C,0xffffffff
#define IPU_ISP_CCMLIN1__CCMLIN22 0x1E01002C,0x00007C00
#define IPU_ISP_CCMLIN1__CCMLIN21 0x1E01002C,0x000003E0
#define IPU_ISP_CCMLIN1__CCMLIN20 0x1E01002C,0x0000001F

#define IPU_ISP_CG_0__ADDR   0x1E010030
#define IPU_ISP_CG_0__EMPTY  0x1E010030,0x00000000
#define IPU_ISP_CG_0__FULL   0x1E010030,0xffffffff
#define IPU_ISP_CG_0__BGAIN  0x1E010030,0xFF000000
#define IPU_ISP_CG_0__GBGAIN 0x1E010030,0x00FF0000
#define IPU_ISP_CG_0__GRGAIN 0x1E010030,0x0000FF00
#define IPU_ISP_CG_0__RGAIN  0x1E010030,0x000000FF

#define IPU_ISP_CG_1__ADDR   0x1E010034
#define IPU_ISP_CG_1__EMPTY  0x1E010034,0x00000000
#define IPU_ISP_CG_1__FULL   0x1E010034,0xffffffff
#define IPU_ISP_CG_1__BSHIFT 0x1E010034,0x00000030
#define IPU_ISP_CG_1__GSHIFT 0x1E010034,0x0000000C
#define IPU_ISP_CG_1__RSHIFT 0x1E010034,0x00000003

#define IPU_ISP_ROC_0__ADDR         0x1E010038
#define IPU_ISP_ROC_0__EMPTY        0x1E010038,0x00000000
#define IPU_ISP_ROC_0__FULL         0x1E010038,0xffffffff
#define IPU_ISP_ROC_0__CROC_Q_BLIN  0x1E010038,0x01C00000
#define IPU_ISP_ROC_0__CROC_Q_GLIN  0x1E010038,0x00380000
#define IPU_ISP_ROC_0__CROC_Q_RLIN  0x1E010038,0x00070000
#define IPU_ISP_ROC_0__CROC_SH_QR   0x1E010038,0x00007000
#define IPU_ISP_ROC_0__CROC_SH_QRGB 0x1E010038,0x00000E00
#define IPU_ISP_ROC_0__CROC_SH_QB   0x1E010038,0x000001C0
#define IPU_ISP_ROC_0__CROC_R_APP   0x1E010038,0x00000030
#define IPU_ISP_ROC_0__CROC_G_APP   0x1E010038,0x0000000C
#define IPU_ISP_ROC_0__CROC_B_APP   0x1E010038,0x00000003

#define IPU_ISP_ROC_1__ADDR     0x1E01003C
#define IPU_ISP_ROC_1__EMPTY    0x1E01003C,0x00000000
#define IPU_ISP_ROC_1__FULL     0x1E01003C,0xffffffff
#define IPU_ISP_ROC_1__CROC_MYB 0x1E01003C,0xFF000000
#define IPU_ISP_ROC_1__CROC_MXB 0x1E01003C,0x00FF0000
#define IPU_ISP_ROC_1__CROC_MYG 0x1E01003C,0x0000FF00
#define IPU_ISP_ROC_1__CROC_MXG 0x1E01003C,0x000000FF

#define IPU_ISP_ROC_2__ADDR     0x1E010040
#define IPU_ISP_ROC_2__EMPTY    0x1E010040,0x00000000
#define IPU_ISP_ROC_2__FULL     0x1E010040,0xffffffff
#define IPU_ISP_ROC_2__CROC_MYR 0x1E010040,0x0000FF00
#define IPU_ISP_ROC_2__CROC_MXR 0x1E010040,0x000000FF

#define IPU_ISP_ROC_3__ADDR     0x1E010044

/*not all IPS regs defined here*/
// ================= End of IPUV3EX ISP Registers =====================

// ================= Start of IPUV3EX DP Registers =====================
#define IPU_DP_COM_CONF_SYNC__ADDR                     0x1E018000
#define IPU_DP_COM_CONF_SYNC__EMPTY                    0x1E018000,0x00000000
#define IPU_DP_COM_CONF_SYNC__FULL                     0x1E018000,0xffffffff
#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC     0x1E018000,0x00002000
#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC         0x1E018000,0x00001000
#define IPU_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1E018000,0x00000800
#define IPU_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1E018000,0x00000400
#define IPU_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC          0x1E018000,0x00000300
#define IPU_DP_COM_CONF_SYNC__DP_COC_SYNC              0x1E018000,0x00000070
#define IPU_DP_COM_CONF_SYNC__DP_GWCKE_SYNC            0x1E018000,0x00000008
#define IPU_DP_COM_CONF_SYNC__DP_GWAM_SYNC             0x1E018000,0x00000004
#define IPU_DP_COM_CONF_SYNC__DP_GWSEL_SYNC            0x1E018000,0x00000002
#define IPU_DP_COM_CONF_SYNC__DP_FG_EN_SYNC            0x1E018000,0x00000001

#define IPU_DP_GRAPH_WIND_CTRL_SYNC__ADDR          0x1E018004
#define IPU_DP_GRAPH_WIND_CTRL_SYNC__EMPTY         0x1E018004,0x00000000
#define IPU_DP_GRAPH_WIND_CTRL_SYNC__FULL          0x1E018004,0xffffffff
#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC  0x1E018004,0xFF000000
#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1E018004,0x00FF0000
#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1E018004,0x0000FF00
#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1E018004,0x000000FF

#define IPU_DP_FG_POS_SYNC__ADDR         0x1E018008
#define IPU_DP_FG_POS_SYNC__EMPTY        0x1E018008,0x00000000
#define IPU_DP_FG_POS_SYNC__FULL         0x1E018008,0xffffffff
#define IPU_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1E018008,0x07FF0000
#define IPU_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1E018008,0x000007FF

#define IPU_DP_CUR_POS_SYNC__ADDR        0x1E01800C
#define IPU_DP_CUR_POS_SYNC__EMPTY       0x1E01800C,0x00000000
#define IPU_DP_CUR_POS_SYNC__FULL        0x1E01800C,0xffffffff
#define IPU_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1E01800C,0xF8000000
#define IPU_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1E01800C,0x07FF0000
#define IPU_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1E01800C,0x0000F800
#define IPU_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1E01800C,0x000007FF

#define IPU_DP_CUR_MAP_SYNC__ADDR              0x1E018010
#define IPU_DP_CUR_MAP_SYNC__EMPTY             0x1E018010,0x00000000
#define IPU_DP_CUR_MAP_SYNC__FULL              0x1E018010,0xffffffff
#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1E018010,0x00FF0000
#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1E018010,0x0000FF00
#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1E018010,0x000000FF

#define IPU_DP_GAMMA_C_SYNC_0__ADDR              0x1E018014
#define IPU_DP_GAMMA_C_SYNC_0__EMPTY             0x1E018014,0x00000000
#define IPU_DP_GAMMA_C_SYNC_0__FULL              0x1E018014,0xffffffff
#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1E018014,0x01FF0000
#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1E018014,0x000001FF

#define IPU_DP_GAMMA_C_SYNC_1__ADDR              0x1E018018
#define IPU_DP_GAMMA_C_SYNC_1__EMPTY             0x1E018018,0x00000000
#define IPU_DP_GAMMA_C_SYNC_1__FULL              0x1E018018,0xffffffff
#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1E018018,0x01FF0000
#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1E018018,0x000001FF

#define IPU_DP_GAMMA_C_SYNC_2__ADDR              0x1E01801C
#define IPU_DP_GAMMA_C_SYNC_2__EMPTY             0x1E01801C,0x00000000
#define IPU_DP_GAMMA_C_SYNC_2__FULL              0x1E01801C,0xffffffff
#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1E01801C,0x01FF0000
#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1E01801C,0x000001FF

#define IPU_DP_GAMMA_C_SYNC_3__ADDR              0x1E018020
#define IPU_DP_GAMMA_C_SYNC_3__EMPTY             0x1E018020,0x00000000
#define IPU_DP_GAMMA_C_SYNC_3__FULL              0x1E018020,0xffffffff
#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1E018020,0x01FF0000
#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1E018020,0x000001FF

#define IPU_DP_GAMMA_C_SYNC_4__ADDR              0x1E018024
#define IPU_DP_GAMMA_C_SYNC_4__EMPTY             0x1E018024,0x00000000
#define IPU_DP_GAMMA_C_SYNC_4__FULL              0x1E018024,0xffffffff
#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1E018024,0x01FF0000
#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1E018024,0x000001FF

#define IPU_DP_GAMMA_C_SYNC_5__ADDR               0x1E018028
#define IPU_DP_GAMMA_C_SYNC_5__EMPTY              0x1E018028,0x00000000
#define IPU_DP_GAMMA_C_SYNC_5__FULL               0x1E018028,0xffffffff
#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1E018028,0x01FF0000
#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1E018028,0x000001FF

#define IPU_DP_GAMMA_C_SYNC_6__ADDR               0x1E01802C
#define IPU_DP_GAMMA_C_SYNC_6__EMPTY              0x1E01802C,0x00000000
#define IPU_DP_GAMMA_C_SYNC_6__FULL               0x1E01802C,0xffffffff
#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1E01802C,0x01FF0000
#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1E01802C,0x000001FF

#define IPU_DP_GAMMA_C_SYNC_7__ADDR               0x1E018030
#define IPU_DP_GAMMA_C_SYNC_7__EMPTY              0x1E018030,0x00000000
#define IPU_DP_GAMMA_C_SYNC_7__FULL               0x1E018030,0xffffffff
#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1E018030,0x01FF0000
#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1E018030,0x000001FF

#define IPU_DP_GAMMA_S_SYNC_0__ADDR              0x1E018034
#define IPU_DP_GAMMA_S_SYNC_0__EMPTY             0x1E018034,0x00000000
#define IPU_DP_GAMMA_S_SYNC_0__FULL              0x1E018034,0xffffffff
#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1E018034,0xFF000000
#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1E018034,0x00FF0000
#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1E018034,0x0000FF00
#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1E018034,0x000000FF

#define IPU_DP_GAMMA_S_SYNC_1__ADDR              0x1E018038
#define IPU_DP_GAMMA_S_SYNC_1__EMPTY             0x1E018038,0x00000000
#define IPU_DP_GAMMA_S_SYNC_1__FULL              0x1E018038,0xffffffff
#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1E018038,0xFF000000
#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1E018038,0x00FF0000
#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1E018038,0x0000FF00
#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1E018038,0x000000FF

#define IPU_DP_GAMMA_S_SYNC_2__ADDR               0x1E01803C
#define IPU_DP_GAMMA_S_SYNC_2__EMPTY              0x1E01803C,0x00000000
#define IPU_DP_GAMMA_S_SYNC_2__FULL               0x1E01803C,0xffffffff
#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1E01803C,0xFF000000
#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1E01803C,0x00FF0000
#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9  0x1E01803C,0x0000FF00
#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8  0x1E01803C,0x000000FF

#define IPU_DP_GAMMA_S_SYNC_3__ADDR               0x1E018040
#define IPU_DP_GAMMA_S_SYNC_3__EMPTY              0x1E018040,0x00000000
#define IPU_DP_GAMMA_S_SYNC_3__FULL               0x1E018040,0xffffffff
#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1E018040,0xFF000000
#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1E018040,0x00FF0000
#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1E018040,0x0000FF00
#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1E018040,0x000000FF

#define IPU_DP_CSCA_SYNC_0__ADDR            0x1E018044
#define IPU_DP_CSCA_SYNC_0__EMPTY           0x1E018044,0x00000000
#define IPU_DP_CSCA_SYNC_0__FULL            0x1E018044,0xffffffff
#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1E018044,0x03FF0000
#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1E018044,0x000003FF

#define IPU_DP_CSCA_SYNC_1__ADDR            0x1E018048
#define IPU_DP_CSCA_SYNC_1__EMPTY           0x1E018048,0x00000000
#define IPU_DP_CSCA_SYNC_1__FULL            0x1E018048,0xffffffff
#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1E018048,0x03FF0000
#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1E018048,0x000003FF

#define IPU_DP_CSCA_SYNC_2__ADDR            0x1E01804C
#define IPU_DP_CSCA_SYNC_2__EMPTY           0x1E01804C,0x00000000
#define IPU_DP_CSCA_SYNC_2__FULL            0x1E01804C,0xffffffff
#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1E01804C,0x03FF0000
#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1E01804C,0x000003FF

#define IPU_DP_CSCA_SYNC_3__ADDR            0x1E018050
#define IPU_DP_CSCA_SYNC_3__EMPTY           0x1E018050,0x00000000
#define IPU_DP_CSCA_SYNC_3__FULL            0x1E018050,0xffffffff
#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1E018050,0x03FF0000
#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1E018050,0x000003FF

#define IPU_DP_CSC_SYNC_0__ADDR           0x1E018054
#define IPU_DP_CSC_SYNC_0__EMPTY          0x1E018054,0x00000000
#define IPU_DP_CSC_SYNC_0__FULL           0x1E018054,0xffffffff
#define IPU_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1E018054,0xC0000000
#define IPU_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1E018054,0x3FFF0000
#define IPU_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1E018054,0x000003FF

#define IPU_DP_CSC_SYNC_1__ADDR           0x1E018058
#define IPU_DP_CSC_SYNC_1__EMPTY          0x1E018058,0x00000000
#define IPU_DP_CSC_SYNC_1__FULL           0x1E018058,0xffffffff
#define IPU_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1E018058,0xC0000000
#define IPU_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1E018058,0x3FFF0000
#define IPU_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1E018058,0x0000C000
#define IPU_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1E018058,0x00003FFF

#define IPU_DP_CUR_POS_ALT__ADDR            0x1E01805C
#define IPU_DP_CUR_POS_ALT__EMPTY           0x1E01805C,0x00000000
#define IPU_DP_CUR_POS_ALT__FULL            0x1E01805C,0xffffffff
#define IPU_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1E01805C,0xF8000000
#define IPU_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1E01805C,0x07FF0000
#define IPU_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1E01805C,0x0000F800
#define IPU_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1E01805C,0x000007FF

#define IPU_DP_COM_CONF_ASYNC__ADDR                       0x1E018060
#define IPU_DP_COM_CONF_ASYNC__EMPTY                      0x1E018060,0x00000000
#define IPU_DP_COM_CONF_ASYNC__FULL                       0x1E018060,0xffffffff
#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_YUV_EN_ASYNC     0x1E018060,0x00002000
#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_EN_ASYNC         0x1E018060,0x00001000
#define IPU_DP_COM_CONF_ASYNC__DP_CSC_YUV_SAT_MODE_ASYNC 0x1E018060,0x00000800
#define IPU_DP_COM_CONF_ASYNC__DP_CSC_GAMUT_SAT_EN_ASYNC 0x1E018060,0x00000400
#define IPU_DP_COM_CONF_ASYNC__DP_CSC_DEF_ASYNC          0x1E018060,0x00000300
#define IPU_DP_COM_CONF_ASYNC__DP_COC_ASYNC              0x1E018060,0x00000070
#define IPU_DP_COM_CONF_ASYNC__DP_GWCKE_ASYNC            0x1E018060,0x00000008
#define IPU_DP_COM_CONF_ASYNC__DP_GWAM_ASYNC             0x1E018060,0x00000004
#define IPU_DP_COM_CONF_ASYNC__DP_GWSEL_ASYNC            0x1E018060,0x00000002

#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__ADDR            0x1E018064
#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__EMPTY           0x1E018064,0x00000000
#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__FULL            0x1E018064,0xffffffff
#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWAV_ASYNC  0x1E018064,0xFF000000
#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKR_ASYNC 0x1E018064,0x00FF0000
#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKG_ASYNC 0x1E018064,0x0000FF00
#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKB_ASYNC 0x1E018064,0x000000FF

#define IPU_DP_FG_POS_ASYNC__ADDR           0x1E018068
#define IPU_DP_FG_POS_ASYNC__EMPTY          0x1E018068,0x00000000
#define IPU_DP_FG_POS_ASYNC__FULL           0x1E018068,0xffffffff
#define IPU_DP_FG_POS_ASYNC__DP_FGXP_ASYNC 0x1E018068,0x07FF0000
#define IPU_DP_FG_POS_ASYNC__DP_FGYP_ASYNC 0x1E018068,0x000007FF

#define IPU_DP_CUR_POS_ASYNC__ADDR          0x1E01806C
#define IPU_DP_CUR_POS_ASYNC__EMPTY         0x1E01806C,0x00000000
#define IPU_DP_CUR_POS_ASYNC__FULL          0x1E01806C,0xffffffff
#define IPU_DP_CUR_POS_ASYNC__DP_CXW_ASYNC 0x1E01806C,0xF8000000
#define IPU_DP_CUR_POS_ASYNC__DP_CXP_ASYNC 0x1E01806C,0x07FF0000
#define IPU_DP_CUR_POS_ASYNC__DP_CYH_ASYNC 0x1E01806C,0x0000F800
#define IPU_DP_CUR_POS_ASYNC__DP_CYP_ASYNC 0x1E01806C,0x000007FF

#define IPU_DP_CUR_MAP_ASYNC__ADDR             0x1E018070
#define IPU_DP_CUR_MAP_ASYNC__EMPTY            0x1E018070,0x00000000
#define IPU_DP_CUR_MAP_ASYNC__FULL             0x1E018070,0xffffffff
#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_R_ASYNC 0x1E018070,0x00FF0000
#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_G_ASYNC 0x1E018070,0x0000FF00
#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_B_ASYNC 0x1E018070,0x000000FF

#define IPU_DP_GAMMA_C_ASYNC_0__ADDR                0x1E018074
#define IPU_DP_GAMMA_C_ASYNC_0__EMPTY               0x1E018074,0x00000000
#define IPU_DP_GAMMA_C_ASYNC_0__FULL                0x1E018074,0xffffffff
#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_1 0x1E018074,0x01FF0000
#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_0 0x1E018074,0x000001FF

#define IPU_DP_GAMMA_C_ASYNC_1__ADDR                0x1E018078
#define IPU_DP_GAMMA_C_ASYNC_1__EMPTY               0x1E018078,0x00000000
#define IPU_DP_GAMMA_C_ASYNC_1__FULL                0x1E018078,0xffffffff
#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_3 0x1E018078,0x01FF0000
#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_2 0x1E018078,0x000001FF

#define IPU_DP_GAMMA_C_ASYNC_2__ADDR                0x1E01807C
#define IPU_DP_GAMMA_C_ASYNC_2__EMPTY               0x1E01807C,0x00000000
#define IPU_DP_GAMMA_C_ASYNC_2__FULL                0x1E01807C,0xffffffff
#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_5 0x1E01807C,0x01FF0000
#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_4 0x1E01807C,0x000001FF

#define IPU_DP_GAMMA_C_ASYNC_3__ADDR                0x1E018080
#define IPU_DP_GAMMA_C_ASYNC_3__EMPTY               0x1E018080,0x00000000
#define IPU_DP_GAMMA_C_ASYNC_3__FULL                0x1E018080,0xffffffff
#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_7 0x1E018080,0x01FF0000
#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_6 0x1E018080,0x000001FF

#define IPU_DP_GAMMA_C_ASYNC_4__ADDR                0x1E018084
#define IPU_DP_GAMMA_C_ASYNC_4__EMPTY               0x1E018084,0x00000000
#define IPU_DP_GAMMA_C_ASYNC_4__FULL                0x1E018084,0xffffffff
#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_9 0x1E018084,0x01FF0000
#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_8 0x1E018084,0x000001FF

#define IPU_DP_GAMMA_C_ASYNC_5__ADDR                 0x1E018088
#define IPU_DP_GAMMA_C_ASYNC_5__EMPTY                0x1E018088,0x00000000
#define IPU_DP_GAMMA_C_ASYNC_5__FULL                 0x1E018088,0xffffffff
#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_11 0x1E018088,0x01FF0000
#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_10 0x1E018088,0x000001FF

#define IPU_DP_GAMMA_C_ASYNC_6__ADDR                 0x1E01808C
#define IPU_DP_GAMMA_C_ASYNC_6__EMPTY                0x1E01808C,0x00000000
#define IPU_DP_GAMMA_C_ASYNC_6__FULL                 0x1E01808C,0xffffffff
#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_13 0x1E01808C,0x01FF0000
#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_12 0x1E01808C,0x000001FF

#define IPU_DP_GAMMA_C_ASYNC_7__ADDR                 0x1E018090
#define IPU_DP_GAMMA_C_ASYNC_7__EMPTY                0x1E018090,0x00000000
#define IPU_DP_GAMMA_C_ASYNC_7__FULL                 0x1E018090,0xffffffff
#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_15 0x1E018090,0x01FF0000
#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_14 0x1E018090,0x000001FF

#define IPU_DP_GAMMA_S_ASYNC_0__ADDR                0x1E018094
#define IPU_DP_GAMMA_S_ASYNC_0__EMPTY               0x1E018094,0x00000000
#define IPU_DP_GAMMA_S_ASYNC_0__FULL                0x1E018094,0xffffffff
#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_3 0x1E018094,0xFF000000
#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_2 0x1E018094,0x00FF0000
#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_1 0x1E018094,0x0000FF00
#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_0 0x1E018094,0x000000FF

#define IPU_DP_GAMMA_S_ASYNC_1__ADDR                0x1E018098
#define IPU_DP_GAMMA_S_ASYNC_1__EMPTY               0x1E018098,0x00000000
#define IPU_DP_GAMMA_S_ASYNC_1__FULL                0x1E018098,0xffffffff
#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_7 0x1E018098,0xFF000000
#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_6 0x1E018098,0x00FF0000
#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_5 0x1E018098,0x0000FF00
#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_4 0x1E018098,0x000000FF

#define IPU_DP_GAMMA_S_ASYNC_2__ADDR                 0x1E01809C
#define IPU_DP_GAMMA_S_ASYNC_2__EMPTY                0x1E01809C,0x00000000
#define IPU_DP_GAMMA_S_ASYNC_2__FULL                 0x1E01809C,0xffffffff
#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_11 0x1E01809C,0xFF000000
#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_10 0x1E01809C,0x00FF0000
#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_9  0x1E01809C,0x0000FF00
#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_8  0x1E01809C,0x000000FF

#define IPU_DP_GAMMA_S_ASYNC_3__ADDR                 0x1E0180A0
#define IPU_DP_GAMMA_S_ASYNC_3__EMPTY                0x1E0180A0,0x00000000
#define IPU_DP_GAMMA_S_ASYNC_3__FULL                 0x1E0180A0,0xffffffff
#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_15 0x1E0180A0,0xFF000000
#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_14 0x1E0180A0,0x00FF0000
#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_13 0x1E0180A0,0x0000FF00
#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_12 0x1E0180A0,0x000000FF

#define IPU_DP_CSCA_ASYNC_0__ADDR              0x1E0180A4
#define IPU_DP_CSCA_ASYNC_0__EMPTY             0x1E0180A4,0x00000000
#define IPU_DP_CSCA_ASYNC_0__FULL              0x1E0180A4,0xffffffff
#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_1 0x1E0180A4,0x03FF0000
#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_0 0x1E0180A4,0x000003FF

#define IPU_DP_CSCA_ASYNC_1__ADDR              0x1E0180A8
#define IPU_DP_CSCA_ASYNC_1__EMPTY             0x1E0180A8,0x00000000
#define IPU_DP_CSCA_ASYNC_1__FULL              0x1E0180A8,0xffffffff
#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_3 0x1E0180A8,0x03FF0000
#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_2 0x1E0180A8,0x000003FF

#define IPU_DP_CSCA_ASYNC_2__ADDR              0x1E0180AC
#define IPU_DP_CSCA_ASYNC_2__EMPTY             0x1E0180AC,0x00000000
#define IPU_DP_CSCA_ASYNC_2__FULL              0x1E0180AC,0xffffffff
#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_5 0x1E0180AC,0x03FF0000
#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_4 0x1E0180AC,0x000003FF

#define IPU_DP_CSCA_ASYNC_3__ADDR              0x1E0180B0
#define IPU_DP_CSCA_ASYNC_3__EMPTY             0x1E0180B0,0x00000000
#define IPU_DP_CSCA_ASYNC_3__FULL              0x1E0180B0,0xffffffff
#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_7 0x1E0180B0,0x03FF0000
#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_6 0x1E0180B0,0x000003FF

#define IPU_DP_CSC_ASYNC_0__ADDR             0x1E0180B4
#define IPU_DP_CSC_ASYNC_0__EMPTY            0x1E0180B4,0x00000000
#define IPU_DP_CSC_ASYNC_0__FULL             0x1E0180B4,0xffffffff
#define IPU_DP_CSC_ASYNC_0__DP_CSC_S0_ASYNC 0x1E0180B4,0xC0000000
#define IPU_DP_CSC_ASYNC_0__DP_CSC_B0_ASYNC 0x1E0180B4,0x3FFF0000
#define IPU_DP_CSC_ASYNC_0__DP_CSC_A8_ASYNC 0x1E0180B4,0x000003FF

#define IPU_DP_CSC_ASYNC_1__ADDR             0x1E0180B8
#define IPU_DP_CSC_ASYNC_1__EMPTY            0x1E0180B8,0x00000000
#define IPU_DP_CSC_ASYNC_1__FULL             0x1E0180B8,0xffffffff
#define IPU_DP_CSC_ASYNC_1__DP_CSC_S2_ASYNC 0x1E0180B8,0xC0000000
#define IPU_DP_CSC_ASYNC_1__DP_CSC_B2_ASYNC 0x1E0180B8,0x3FFF0000
#define IPU_DP_CSC_ASYNC_1__DP_CSC_S1_ASYNC 0x1E0180B8,0x0000C000
#define IPU_DP_CSC_ASYNC_1__DP_CSC_B1_ASYNC 0x1E0180B8,0x00003FFF

#define IPU_DP_DEBUG_CNT__ADDR              0x1E0180BC
#define IPU_DP_DEBUG_CNT__EMPTY             0x1E0180BC,0x00000000
#define IPU_DP_DEBUG_CNT__FULL              0x1E0180BC,0xffffffff
#define IPU_DP_DEBUG_CNT__BRAKE_CNT_1       0x1E0180BC,0x000000E0
#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_1 0x1E0180BC,0x00000010
#define IPU_DP_DEBUG_CNT__BRAKE_CNT_0       0x1E0180BC,0x0000000E
#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_0 0x1E0180BC,0x00000001

#define IPU_DP_DEBUG_STAT__ADDR            0x1E0180C0
#define IPU_DP_DEBUG_STAT__EMPTY           0x1E0180C0,0x00000000
#define IPU_DP_DEBUG_STAT__FULL            0x1E0180C0,0xffffffff
#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_1    0x1E0180C0,0x20000000
#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_1 0x1E0180C0,0x10000000
#define IPU_DP_DEBUG_STAT__FG_ACTIVE_1     0x1E0180C0,0x08000000
#define IPU_DP_DEBUG_STAT__V_CNT_OLD_1     0x1E0180C0,0x07FF0000
#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_0    0x1E0180C0,0x00002000
#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_0 0x1E0180C0,0x00001000
#define IPU_DP_DEBUG_STAT__FG_ACTIVE_0     0x1E0180C0,0x00000800
#define IPU_DP_DEBUG_STAT__V_CNT_OLD_0     0x1E0180C0,0x000007FF

// ================= Start of IPUV3EX SRM DP Registers =====================

// ================= Start of IPUV3EX IC Registers =====================
#define IPU_IC_CONF__ADDR            0x1E020000
#define IPU_IC_CONF__EMPTY           0x1E020000,0x00000000
#define IPU_IC_CONF__FULL            0x1E020000,0xffffffff
#define IPU_IC_CONF__CSI_MEM_WR_EN   0x1E020000,0x80000000
#define IPU_IC_CONF__RWS_EN          0x1E020000,0x40000000
#define IPU_IC_CONF__IC_KEY_COLOR_EN 0x1E020000,0x20000000
#define IPU_IC_CONF__IC_GLB_LOC_A    0x1E020000,0x10000000
#define IPU_IC_CONF__PP_ROT_EN       0x1E020000,0x00100000
#define IPU_IC_CONF__PP_CMB          0x1E020000,0x00080000
#define IPU_IC_CONF__PP_CSC2         0x1E020000,0x00040000
#define IPU_IC_CONF__PP_CSC1         0x1E020000,0x00020000
#define IPU_IC_CONF__PP_EN           0x1E020000,0x00010000
#define IPU_IC_CONF__PRPVF_ROT_EN    0x1E020000,0x00001000
#define IPU_IC_CONF__PRPVF_CMB       0x1E020000,0x00000800
#define IPU_IC_CONF__PRPVF_CSC2      0x1E020000,0x00000400
#define IPU_IC_CONF__PRPVF_CSC1      0x1E020000,0x00000200
#define IPU_IC_CONF__PRPVF_EN        0x1E020000,0x00000100
#define IPU_IC_CONF__PRPENC_ROT_EN   0x1E020000,0x00000004
#define IPU_IC_CONF__PRPENC_CSC1     0x1E020000,0x00000002
#define IPU_IC_CONF__PRPENC_EN       0x1E020000,0x00000001

#define IPU_IC_PRP_ENC_RSC__ADDR          0x1E020004
#define IPU_IC_PRP_ENC_RSC__EMPTY         0x1E020004,0x00000000
#define IPU_IC_PRP_ENC_RSC__FULL          0x1E020004,0xffffffff
#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_V 0x1E020004,0xC0000000
#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_V 0x1E020004,0x3FFF0000
#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_H 0x1E020004,0x0000C000
#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_H 0x1E020004,0x00003FFF

#define IPU_IC_PRP_VF_RSC__ADDR         0x1E020008
#define IPU_IC_PRP_VF_RSC__EMPTY        0x1E020008,0x00000000
#define IPU_IC_PRP_VF_RSC__FULL         0x1E020008,0xffffffff
#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_V 0x1E020008,0xC0000000
#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_V 0x1E020008,0x3FFF0000
#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_H 0x1E020008,0x0000C000
#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_H 0x1E020008,0x00003FFF

#define IPU_IC_PP_RSC__ADDR      0x1E02000C
#define IPU_IC_PP_RSC__EMPTY     0x1E02000C,0x00000000
#define IPU_IC_PP_RSC__FULL      0x1E02000C,0xffffffff
#define IPU_IC_PP_RSC__PP_DS_R_V 0x1E02000C,0xC0000000
#define IPU_IC_PP_RSC__PP_RS_R_V 0x1E02000C,0x3FFF0000
#define IPU_IC_PP_RSC__PP_DS_R_H 0x1E02000C,0x0000C000
#define IPU_IC_PP_RSC__PP_RS_R_H 0x1E02000C,0x00003FFF

#define IPU_IC_CMBP_1__ADDR             0x1E020010
#define IPU_IC_CMBP_1__EMPTY            0x1E020010,0x00000000
#define IPU_IC_CMBP_1__FULL             0x1E020010,0xffffffff
#define IPU_IC_CMBP_1__IC_PP_ALPHA_V    0x1E020010,0x0000FF00
#define IPU_IC_CMBP_1__IC_PRPVF_ALPHA_V 0x1E020010,0x000000FF

#define IPU_IC_CMBP_2__ADDR           0x1E020014
#define IPU_IC_CMBP_2__EMPTY          0x1E020014,0x00000000
#define IPU_IC_CMBP_2__FULL           0x1E020014,0xffffffff
#define IPU_IC_CMBP_2__IC_KEY_COLOR_R 0x1E020014,0x00FF0000
#define IPU_IC_CMBP_2__IC_KEY_COLOR_G 0x1E020014,0x0000FF00
#define IPU_IC_CMBP_2__IC_KEY_COLOR_B 0x1E020014,0x000000FF

#define IPU_IC_IDMAC_1__ADDR             0x1E020018
#define IPU_IC_IDMAC_1__EMPTY            0x1E020018,0x00000000
#define IPU_IC_IDMAC_1__FULL             0x1E020018,0xffffffff
#define IPU_IC_IDMAC_1__ALT_CB7_BURST_16 0x1E020018,0x02000000
#define IPU_IC_IDMAC_1__ALT_CB6_BURST_16 0x1E020018,0x01000000
#define IPU_IC_IDMAC_1__T3_FLIP_RS       0x1E020018,0x00400000
#define IPU_IC_IDMAC_1__T2_FLIP_RS       0x1E020018,0x00200000
#define IPU_IC_IDMAC_1__T1_FLIP_RS       0x1E020018,0x00100000
#define IPU_IC_IDMAC_1__T3_FLIP_UD       0x1E020018,0x00080000
#define IPU_IC_IDMAC_1__T3_FLIP_LR       0x1E020018,0x00040000
#define IPU_IC_IDMAC_1__T3_ROT           0x1E020018,0x00020000
#define IPU_IC_IDMAC_1__T2_FLIP_UD       0x1E020018,0x00010000
#define IPU_IC_IDMAC_1__T2_FLIP_LR       0x1E020018,0x00008000
#define IPU_IC_IDMAC_1__T2_ROT           0x1E020018,0x00004000
#define IPU_IC_IDMAC_1__T1_FLIP_UD       0x1E020018,0x00002000
#define IPU_IC_IDMAC_1__T1_FLIP_LR       0x1E020018,0x00001000
#define IPU_IC_IDMAC_1__T1_ROT           0x1E020018,0x00000800
#define IPU_IC_IDMAC_1__CB7_BURST_16     0x1E020018,0x00000080
#define IPU_IC_IDMAC_1__CB6_BURST_16     0x1E020018,0x00000040
#define IPU_IC_IDMAC_1__CB5_BURST_16     0x1E020018,0x00000020
#define IPU_IC_IDMAC_1__CB4_BURST_16     0x1E020018,0x00000010
#define IPU_IC_IDMAC_1__CB3_BURST_16     0x1E020018,0x00000008
#define IPU_IC_IDMAC_1__CB2_BURST_16     0x1E020018,0x00000004
#define IPU_IC_IDMAC_1__CB1_BURST_16     0x1E020018,0x00000002
#define IPU_IC_IDMAC_1__CB0_BURST_16     0x1E020018,0x00000001

#define IPU_IC_IDMAC_2__ADDR         0x1E02001C
#define IPU_IC_IDMAC_2__EMPTY        0x1E02001C,0x00000000
#define IPU_IC_IDMAC_2__FULL         0x1E02001C,0xffffffff
#define IPU_IC_IDMAC_2__T3_FR_HEIGHT 0x1E02001C,0x3FF00000
#define IPU_IC_IDMAC_2__T2_FR_HEIGHT 0x1E02001C,0x000FFC00
#define IPU_IC_IDMAC_2__T1_FR_HEIGHT 0x1E02001C,0x000003FF

#define IPU_IC_IDMAC_3__ADDR        0x1E020020
#define IPU_IC_IDMAC_3__EMPTY       0x1E020020,0x00000000
#define IPU_IC_IDMAC_3__FULL        0x1E020020,0xffffffff
#define IPU_IC_IDMAC_3__T3_FR_WIDTH 0x1E020020,0x3FF00000
#define IPU_IC_IDMAC_3__T2_FR_WIDTH 0x1E020020,0x000FFC00
#define IPU_IC_IDMAC_3__T1_FR_WIDTH 0x1E020020,0x000003FF

#define IPU_IC_IDMAC_4__ADDR                 0x1E020024
#define IPU_IC_IDMAC_4__EMPTY                0x1E020024,0x00000000
#define IPU_IC_IDMAC_4__FULL                 0x1E020024,0xffffffff
#define IPU_IC_IDMAC_4__RM_BRDG_MAX_RQ       0x1E020024,0x0000F000
#define IPU_IC_IDMAC_4__IBM_BRDG_MAX_RQ      0x1E020024,0x00000F00
#define IPU_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ 0x1E020024,0x000000F0
#define IPU_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ   0x1E020024,0x0000000F
// ================= End of IPUV3EX IC Registers =====================

// ================= Start of IPUV3EX CSI Registers =====================
#define IPU_CSI0_SENS_CONF__ADDR                  0x1E030000
#define IPU_CSI0_SENS_CONF__EMPTY                 0x1E030000,0x00000000
#define IPU_CSI0_SENS_CONF__FULL                  0x1E030000,0xffffffff
#define IPU_CSI0_SENS_CONF__CSI0_FORCE_EOF        0x1E030000,0x20000000
#define IPU_CSI0_SENS_CONF__CSI0_JPEG_MODE        0x1E030000,0x10000000
#define IPU_CSI0_SENS_CONF__CSI0_JPEG8_EN         0x1E030000,0x08000000
#define IPU_CSI0_SENS_CONF__CSI0_DATA_DEST        0x1E030000,0x07000000
#define IPU_CSI0_SENS_CONF__CSI0_DIV_RATIO        0x1E030000,0x00FF0000
#define IPU_CSI0_SENS_CONF__CSI0_EXT_VSYNC        0x1E030000,0x00008000
#define IPU_CSI0_SENS_CONF__CSI0_DATA_WIDTH       0x1E030000,0x00007800
#define IPU_CSI0_SENS_CONF__CSI0_SENS_DATA_FORMAT 0x1E030000,0x00000700
#define IPU_CSI0_SENS_CONF__CSI0_PACK_TIGHT       0x1E030000,0x00000080
#define IPU_CSI0_SENS_CONF__CSI0_SENS_PRTCL       0x1E030000,0x00000070
#define IPU_CSI0_SENS_CONF__CSI0_SENS_PIX_CLK_POL 0x1E030000,0x00000008
#define IPU_CSI0_SENS_CONF__CSI0_DATA_POL         0x1E030000,0x00000004
#define IPU_CSI0_SENS_CONF__CSI0_HSYNC_POL        0x1E030000,0x00000002
#define IPU_CSI0_SENS_CONF__CSI0_VSYNC_POL        0x1E030000,0x00000001

#define IPU_CSI0_SENS_FRM_SIZE__ADDR                 0x1E030004
#define IPU_CSI0_SENS_FRM_SIZE__EMPTY                0x1E030004,0x00000000
#define IPU_CSI0_SENS_FRM_SIZE__FULL                 0x1E030004,0xffffffff
#define IPU_CSI0_SENS_FRM_SIZE__CSI0_SENS_FRM_HEIGHT 0x1E030004,0x0FFF0000
#define IPU_CSI0_SENS_FRM_SIZE__CSI0_SENS_FRM_WIDTH  0x1E030004,0x00001FFF

#define IPU_CSI0_ACT_FRM_SIZE__ADDR                0x1E030008
#define IPU_CSI0_ACT_FRM_SIZE__EMPTY               0x1E030008,0x00000000
#define IPU_CSI0_ACT_FRM_SIZE__FULL                0x1E030008,0xffffffff
#define IPU_CSI0_ACT_FRM_SIZE__CSI0_ACT_FRM_HEIGHT 0x1E030008,0x0FFF0000
#define IPU_CSI0_ACT_FRM_SIZE__CSI0_ACT_FRM_WIDTH  0x1E030008,0x00001FFF

#define IPU_CSI0_OUT_FRM_CTRL__ADDR           0x1E03000C
#define IPU_CSI0_OUT_FRM_CTRL__EMPTY          0x1E03000C,0x00000000
#define IPU_CSI0_OUT_FRM_CTRL__FULL           0x1E03000C,0xffffffff
#define IPU_CSI0_OUT_FRM_CTRL__CSI0_HORZ_DWNS 0x1E03000C,0x80000000
#define IPU_CSI0_OUT_FRM_CTRL__CSI0_VERT_DWNS 0x1E03000C,0x40000000
#define IPU_CSI0_OUT_FRM_CTRL__CSI0_HSC       0x1E03000C,0x1FFF0000
#define IPU_CSI0_OUT_FRM_CTRL__CSI0_VSC       0x1E03000C,0x00000FFF

#define IPU_CSI0_TST_CTRL__ADDR               0x1E030010
#define IPU_CSI0_TST_CTRL__EMPTY              0x1E030010,0x00000000
#define IPU_CSI0_TST_CTRL__FULL               0x1E030010,0xffffffff
#define IPU_CSI0_TST_CTRL__CSI0_TEST_GEN_MODE 0x1E030010,0x01000000
#define IPU_CSI0_TST_CTRL__CSI0_PG_B_VALUE    0x1E030010,0x00FF0000
#define IPU_CSI0_TST_CTRL__CSI0_PG_G_VALUE    0x1E030010,0x0000FF00
#define IPU_CSI0_TST_CTRL__CSI0_PG_R_VALUE    0x1E030010,0x000000FF

#define IPU_CSI0_CCIR_CODE_1__ADDR                    0x1E030014
#define IPU_CSI0_CCIR_CODE_1__EMPTY                   0x1E030014,0x00000000
#define IPU_CSI0_CCIR_CODE_1__FULL                    0x1E030014,0xffffffff
#define IPU_CSI0_CCIR_CODE_1__CSI0_CCIR_ERR_DET_EN    0x1E030014,0x01000000
#define IPU_CSI0_CCIR_CODE_1__CSI0_STRT_FLD0_ACTV     0x1E030014,0x00380000
#define IPU_CSI0_CCIR_CODE_1__CSI0_END_FLD0_ACTV      0x1E030014,0x00070000
#define IPU_CSI0_CCIR_CODE_1__CSI0_STRT_FLD0_BLNK_2ND 0x1E030014,0x00000E00
#define IPU_CSI0_CCIR_CODE_1__CSI0_END_FLD0_BLNK_2ND  0x1E030014,0x000001C0
#define IPU_CSI0_CCIR_CODE_1__CSI0_STRT_FLD0_BLNK_1ST 0x1E030014,0x00000038
#define IPU_CSI0_CCIR_CODE_1__CSI0_END_FLD0_BLNK_1ST  0x1E030014,0x00000007

#define IPU_CSI0_CCIR_CODE_2__ADDR                    0x1E030018
#define IPU_CSI0_CCIR_CODE_2__EMPTY                   0x1E030018,0x00000000
#define IPU_CSI0_CCIR_CODE_2__FULL                    0x1E030018,0xffffffff
#define IPU_CSI0_CCIR_CODE_2__CSI0_STRT_FLD1_ACTV     0x1E030018,0x00380000
#define IPU_CSI0_CCIR_CODE_2__CSI0_END_FLD1_ACTV      0x1E030018,0x00070000
#define IPU_CSI0_CCIR_CODE_2__CSI0_STRT_FLD1_BLNK_2ND 0x1E030018,0x00000E00
#define IPU_CSI0_CCIR_CODE_2__CSI0_END_FLD1_BLNK_2ND  0x1E030018,0x000001C0
#define IPU_CSI0_CCIR_CODE_2__CSI0_STRT_FLD1_BLNK_1ST 0x1E030018,0x00000038
#define IPU_CSI0_CCIR_CODE_2__CSI0_END_FLD1_BLNK_1ST  0x1E030018,0x00000007

#define IPU_CSI0_CCIR_CODE_3__ADDR             0x1E03001C
#define IPU_CSI0_CCIR_CODE_3__EMPTY            0x1E03001C,0x00000000
#define IPU_CSI0_CCIR_CODE_3__FULL             0x1E03001C,0xffffffff
#define IPU_CSI0_CCIR_CODE_3__CSI0_CCIR_PRECOM 0x1E03001C,0x3FFFFFFF

#define IPU_CSI0_DI__ADDR          0x1E030020
#define IPU_CSI0_DI__EMPTY         0x1E030020,0x00000000
#define IPU_CSI0_DI__FULL          0x1E030020,0xffffffff
#define IPU_CSI0_DI__CSI0_MIPI_DI3 0x1E030020,0xFF000000
#define IPU_CSI0_DI__CSI0_MIPI_DI2 0x1E030020,0x00FF0000
#define IPU_CSI0_DI__CSI0_MIPI_DI1 0x1E030020,0x0000FF00
#define IPU_CSI0_DI__CSI0_MIPI_DI0 0x1E030020,0x000000FF

#define IPU_CSI0_SKIP__ADDR                     0x1E030024
#define IPU_CSI0_SKIP__EMPTY                    0x1E030024,0x00000000
#define IPU_CSI0_SKIP__FULL                     0x1E030024,0xffffffff
#define IPU_CSI0_SKIP__CSI0_SKIP_ISP            0x1E030024,0x00F80000
#define IPU_CSI0_SKIP__CSI0_MAX_RATIO_SKIP_ISP  0x1E030024,0x00070000
#define IPU_CSI0_SKIP__CSI0_ID_2_SKIP           0x1E030024,0x00000300
#define IPU_CSI0_SKIP__CSI0_SKIP_SMFC           0x1E030024,0x000000F8
#define IPU_CSI0_SKIP__CSI0_MAX_RATIO_SKIP_SMFC 0x1E030024,0x00000007

#define IPU_CSI0_CPD_CTRL__ADDR               0x1E030028
#define IPU_CSI0_CPD_CTRL__EMPTY              0x1E030028,0x00000000
#define IPU_CSI0_CPD_CTRL__FULL               0x1E030028,0xffffffff
#define IPU_CSI0_CPD_CTRL__CSI0_CPD           0x1E030028,0x0000001C
#define IPU_CSI0_CPD_CTRL__CSI0_RED_ROW_BEGIN 0x1E030028,0x00000002
#define IPU_CSI0_CPD_CTRL__CSI0_GREEN_P_BEGIN 0x1E030028,0x00000001

#define IPU_CSI0_CPD_RC_0__ADDR          0x1E03002C
#define IPU_CSI0_CPD_RC_0__EMPTY         0x1E03002C,0x00000000
#define IPU_CSI0_CPD_RC_0__FULL          0x1E03002C,0xffffffff
#define IPU_CSI0_CPD_RC_0__CSI0_CPD_RC_1 0x1E03002C,0x01FF0000
#define IPU_CSI0_CPD_RC_0__CSI0_CPD_RC_0 0x1E03002C,0x000001FF

#define IPU_CSI0_CPD_RC_1__ADDR          0x1E030030
#define IPU_CSI0_CPD_RC_1__EMPTY         0x1E030030,0x00000000
#define IPU_CSI0_CPD_RC_1__FULL          0x1E030030,0xffffffff
#define IPU_CSI0_CPD_RC_1__CSI0_CPD_RC_3 0x1E030030,0x01FF0000
#define IPU_CSI0_CPD_RC_1__CSI0_CPD_RC_2 0x1E030030,0x000001FF

#define IPU_CSI0_CPD_RC_2__ADDR          0x1E030034
#define IPU_CSI0_CPD_RC_2__EMPTY         0x1E030034,0x00000000
#define IPU_CSI0_CPD_RC_2__FULL          0x1E030034,0xffffffff
#define IPU_CSI0_CPD_RC_2__CSI0_CPD_RC_5 0x1E030034,0x01FF0000
#define IPU_CSI0_CPD_RC_2__CSI0_CPD_RC_4 0x1E030034,0x000001FF

#define IPU_CSI0_CPD_RC_3__ADDR          0x1E030038
#define IPU_CSI0_CPD_RC_3__EMPTY         0x1E030038,0x00000000
#define IPU_CSI0_CPD_RC_3__FULL          0x1E030038,0xffffffff
#define IPU_CSI0_CPD_RC_3__CSI0_CPD_RC_7 0x1E030038,0x01FF0000
#define IPU_CSI0_CPD_RC_3__CSI0_CPD_RC_6 0x1E030038,0x000001FF

#define IPU_CSI0_CPD_RC_4__ADDR          0x1E03003C
#define IPU_CSI0_CPD_RC_4__EMPTY         0x1E03003C,0x00000000
#define IPU_CSI0_CPD_RC_4__FULL          0x1E03003C,0xffffffff
#define IPU_CSI0_CPD_RC_4__CSI0_CPD_RC_9 0x1E03003C,0x01FF0000
#define IPU_CSI0_CPD_RC_4__CSI0_CPD_RC_8 0x1E03003C,0x000001FF

#define IPU_CSI0_CPD_RC_5__ADDR           0x1E030040
#define IPU_CSI0_CPD_RC_5__EMPTY          0x1E030040,0x00000000
#define IPU_CSI0_CPD_RC_5__FULL           0x1E030040,0xffffffff
#define IPU_CSI0_CPD_RC_5__CSI0_CPD_RC_11 0x1E030040,0x01FF0000
#define IPU_CSI0_CPD_RC_5__CSI0_CPD_RC_10 0x1E030040,0x000001FF

#define IPU_CSI0_CPD_RC_6__ADDR           0x1E030044
#define IPU_CSI0_CPD_RC_6__EMPTY          0x1E030044,0x00000000
#define IPU_CSI0_CPD_RC_6__FULL           0x1E030044,0xffffffff
#define IPU_CSI0_CPD_RC_6__CSI0_CPD_RC_13 0x1E030044,0x01FF0000
#define IPU_CSI0_CPD_RC_6__CSI0_CPD_RC_12 0x1E030044,0x000001FF

#define IPU_CSI0_CPD_RC_7__ADDR           0x1E030048
#define IPU_CSI0_CPD_RC_7__EMPTY          0x1E030048,0x00000000
#define IPU_CSI0_CPD_RC_7__FULL           0x1E030048,0xffffffff
#define IPU_CSI0_CPD_RC_7__CSI0_CPD_RC_15 0x1E030048,0x01FF0000
#define IPU_CSI0_CPD_RC_7__CSI0_CPD_RC_14 0x1E030048,0x000001FF

#define IPU_CSI0_CPD_RS_0__ADDR         0x1E03004C
#define IPU_CSI0_CPD_RS_0__EMPTY        0x1E03004C,0x00000000
#define IPU_CSI0_CPD_RS_0__FULL         0x1E03004C,0xffffffff
#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS3 0x1E03004C,0xFF000000
#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS2 0x1E03004C,0x00FF0000
#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS1 0x1E03004C,0x0000FF00
#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS0 0x1E03004C,0x000000FF

#define IPU_CSI0_CPD_RS_1__ADDR         0x1E030050
#define IPU_CSI0_CPD_RS_1__EMPTY        0x1E030050,0x00000000
#define IPU_CSI0_CPD_RS_1__FULL         0x1E030050,0xffffffff
#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS7 0x1E030050,0xFF000000
#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS6 0x1E030050,0x00FF0000
#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS5 0x1E030050,0x0000FF00
#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS4 0x1E030050,0x000000FF

#define IPU_CSI0_CPD_RS_2__ADDR          0x1E030054
#define IPU_CSI0_CPD_RS_2__EMPTY         0x1E030054,0x00000000
#define IPU_CSI0_CPD_RS_2__FULL          0x1E030054,0xffffffff
#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS11 0x1E030054,0xFF000000
#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS10 0x1E030054,0x00FF0000
#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS9  0x1E030054,0x0000FF00
#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS8  0x1E030054,0x000000FF

#define IPU_CSI0_CPD_RS_3__ADDR          0x1E030058
#define IPU_CSI0_CPD_RS_3__EMPTY         0x1E030058,0x00000000
#define IPU_CSI0_CPD_RS_3__FULL          0x1E030058,0xffffffff
#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS15 0x1E030058,0xFF000000
#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS14 0x1E030058,0x00FF0000
#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS13 0x1E030058,0x0000FF00
#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS12 0x1E030058,0x000000FF

#define IPU_CSI0_CPD_GRC_0__ADDR          0x1E03005C
#define IPU_CSI0_CPD_GRC_0__EMPTY         0x1E03005C,0x00000000
#define IPU_CSI0_CPD_GRC_0__FULL          0x1E03005C,0xffffffff
#define IPU_CSI0_CPD_GRC_0__CSI0_CPD_GRC1 0x1E03005C,0x01FF0000
#define IPU_CSI0_CPD_GRC_0__CSI0_CPD_GRC0 0x1E03005C,0x000001FF

#define IPU_CSI0_CPD_GRC_1__ADDR          0x1E030060
#define IPU_CSI0_CPD_GRC_1__EMPTY         0x1E030060,0x00000000
#define IPU_CSI0_CPD_GRC_1__FULL          0x1E030060,0xffffffff
#define IPU_CSI0_CPD_GRC_1__CSI0_CPD_GRC3 0x1E030060,0x01FF0000
#define IPU_CSI0_CPD_GRC_1__CSI0_CPD_GRC2 0x1E030060,0x000001FF

#define IPU_CSI0_CPD_GRC_2__ADDR          0x1E030064
#define IPU_CSI0_CPD_GRC_2__EMPTY         0x1E030064,0x00000000
#define IPU_CSI0_CPD_GRC_2__FULL          0x1E030064,0xffffffff
#define IPU_CSI0_CPD_GRC_2__CSI0_CPD_GRC5 0x1E030064,0x01FF0000
#define IPU_CSI0_CPD_GRC_2__CSI0_CPD_GRC4 0x1E030064,0x000001FF

#define IPU_CSI0_CPD_GRC_3__ADDR          0x1E030068
#define IPU_CSI0_CPD_GRC_3__EMPTY         0x1E030068,0x00000000
#define IPU_CSI0_CPD_GRC_3__FULL          0x1E030068,0xffffffff
#define IPU_CSI0_CPD_GRC_3__CSI0_CPD_GRC7 0x1E030068,0x01FF0000
#define IPU_CSI0_CPD_GRC_3__CSI0_CPD_GRC6 0x1E030068,0x000001FF

#define IPU_CSI0_CPD_GRC_4__ADDR          0x1E03006C
#define IPU_CSI0_CPD_GRC_4__EMPTY         0x1E03006C,0x00000000
#define IPU_CSI0_CPD_GRC_4__FULL          0x1E03006C,0xffffffff
#define IPU_CSI0_CPD_GRC_4__CSI0_CPD_GRC9 0x1E03006C,0x01FF0000
#define IPU_CSI0_CPD_GRC_4__CSI0_CPD_GRC8 0x1E03006C,0x000001FF

#define IPU_CSI0_CPD_GRC_5__ADDR           0x1E030070
#define IPU_CSI0_CPD_GRC_5__EMPTY          0x1E030070,0x00000000
#define IPU_CSI0_CPD_GRC_5__FULL           0x1E030070,0xffffffff
#define IPU_CSI0_CPD_GRC_5__CSI0_CPD_GRC11 0x1E030070,0x01FF0000
#define IPU_CSI0_CPD_GRC_5__CSI0_CPD_GRC10 0x1E030070,0x000001FF

#define IPU_CSI0_CPD_GRC_6__ADDR           0x1E030074
#define IPU_CSI0_CPD_GRC_6__EMPTY          0x1E030074,0x00000000
#define IPU_CSI0_CPD_GRC_6__FULL           0x1E030074,0xffffffff
#define IPU_CSI0_CPD_GRC_6__CSI0_CPD_GRC13 0x1E030074,0x01FF0000
#define IPU_CSI0_CPD_GRC_6__CSI0_CPD_GRC12 0x1E030074,0x000001FF

#define IPU_CSI0_CPD_GRC_7__ADDR           0x1E030078
#define IPU_CSI0_CPD_GRC_7__EMPTY          0x1E030078,0x00000000
#define IPU_CSI0_CPD_GRC_7__FULL           0x1E030078,0xffffffff
#define IPU_CSI0_CPD_GRC_7__CSI0_CPD_GRC15 0x1E030078,0x01FF0000
#define IPU_CSI0_CPD_GRC_7__CSI0_CPD_GRC14 0x1E030078,0x000001FF

#define IPU_CSI0_CPD_GRS_0__ADDR          0x1E03007C
#define IPU_CSI0_CPD_GRS_0__EMPTY         0x1E03007C,0x00000000
#define IPU_CSI0_CPD_GRS_0__FULL          0x1E03007C,0xffffffff
#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS3 0x1E03007C,0xFF000000
#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS2 0x1E03007C,0x00FF0000
#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS1 0x1E03007C,0x0000FF00
#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS0 0x1E03007C,0x000000FF

#define IPU_CSI0_CPD_GRS_1__ADDR          0x1E030080
#define IPU_CSI0_CPD_GRS_1__EMPTY         0x1E030080,0x00000000
#define IPU_CSI0_CPD_GRS_1__FULL          0x1E030080,0xffffffff
#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS7 0x1E030080,0xFF000000
#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS6 0x1E030080,0x00FF0000
#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS5 0x1E030080,0x0000FF00
#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS4 0x1E030080,0x000000FF

#define IPU_CSI0_CPD_GRS_2__ADDR           0x1E030084
#define IPU_CSI0_CPD_GRS_2__EMPTY          0x1E030084,0x00000000
#define IPU_CSI0_CPD_GRS_2__FULL           0x1E030084,0xffffffff
#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS11 0x1E030084,0xFF000000
#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS10 0x1E030084,0x00FF0000
#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS9  0x1E030084,0x0000FF00
#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS8  0x1E030084,0x000000FF

#define IPU_CSI0_CPD_GRS_3__ADDR           0x1E030088
#define IPU_CSI0_CPD_GRS_3__EMPTY          0x1E030088,0x00000000
#define IPU_CSI0_CPD_GRS_3__FULL           0x1E030088,0xffffffff
#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS15 0x1E030088,0xFF000000
#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS14 0x1E030088,0x00FF0000
#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS13 0x1E030088,0x0000FF00
#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS12 0x1E030088,0x000000FF

#define IPU_CSI0_CPD_GBC_0__ADDR          0x1E03008C
#define IPU_CSI0_CPD_GBC_0__EMPTY         0x1E03008C,0x00000000
#define IPU_CSI0_CPD_GBC_0__FULL          0x1E03008C,0xffffffff
#define IPU_CSI0_CPD_GBC_0__CSI0_CPD_GBC1 0x1E03008C,0x01FF0000
#define IPU_CSI0_CPD_GBC_0__CSI0_CPD_GBC0 0x1E03008C,0x000001FF

#define IPU_CSI0_CPD_GBC_1__ADDR          0x1E030090
#define IPU_CSI0_CPD_GBC_1__EMPTY         0x1E030090,0x00000000
#define IPU_CSI0_CPD_GBC_1__FULL          0x1E030090,0xffffffff
#define IPU_CSI0_CPD_GBC_1__CSI0_CPD_GBC3 0x1E030090,0x01FF0000
#define IPU_CSI0_CPD_GBC_1__CSI0_CPD_GBC2 0x1E030090,0x000001FF

#define IPU_CSI0_CPD_GBC_2__ADDR          0x1E030094
#define IPU_CSI0_CPD_GBC_2__EMPTY         0x1E030094,0x00000000
#define IPU_CSI0_CPD_GBC_2__FULL          0x1E030094,0xffffffff
#define IPU_CSI0_CPD_GBC_2__CSI0_CPD_GBC5 0x1E030094,0x01FF0000
#define IPU_CSI0_CPD_GBC_2__CSI0_CPD_GBC4 0x1E030094,0x000001FF

#define IPU_CSI0_CPD_GBC_3__ADDR          0x1E030098
#define IPU_CSI0_CPD_GBC_3__EMPTY         0x1E030098,0x00000000
#define IPU_CSI0_CPD_GBC_3__FULL          0x1E030098,0xffffffff
#define IPU_CSI0_CPD_GBC_3__CSI0_CPD_GBC7 0x1E030098,0x01FF0000
#define IPU_CSI0_CPD_GBC_3__CSI0_CPD_GBC6 0x1E030098,0x000001FF

#define IPU_CSI0_CPD_GBC_4__ADDR          0x1E03009C
#define IPU_CSI0_CPD_GBC_4__EMPTY         0x1E03009C,0x00000000
#define IPU_CSI0_CPD_GBC_4__FULL          0x1E03009C,0xffffffff
#define IPU_CSI0_CPD_GBC_4__CSI0_CPD_GBC9 0x1E03009C,0x01FF0000
#define IPU_CSI0_CPD_GBC_4__CSI0_CPD_GBC8 0x1E03009C,0x000001FF

#define IPU_CSI0_CPD_GBC_5__ADDR           0x1E0300A0
#define IPU_CSI0_CPD_GBC_5__EMPTY          0x1E0300A0,0x00000000
#define IPU_CSI0_CPD_GBC_5__FULL           0x1E0300A0,0xffffffff
#define IPU_CSI0_CPD_GBC_5__CSI0_CPD_GBC11 0x1E0300A0,0x01FF0000
#define IPU_CSI0_CPD_GBC_5__CSI0_CPD_GBC10 0x1E0300A0,0x000001FF

#define IPU_CSI0_CPD_GBC_6__ADDR           0x1E0300A4
#define IPU_CSI0_CPD_GBC_6__EMPTY          0x1E0300A4,0x00000000
#define IPU_CSI0_CPD_GBC_6__FULL           0x1E0300A4,0xffffffff
#define IPU_CSI0_CPD_GBC_6__CSI0_CPD_GBC13 0x1E0300A4,0x01FF0000
#define IPU_CSI0_CPD_GBC_6__CSI0_CPD_GBC12 0x1E0300A4,0x000001FF

#define IPU_CSI0_CPD_GBC_7__ADDR           0x1E0300A8
#define IPU_CSI0_CPD_GBC_7__EMPTY          0x1E0300A8,0x00000000
#define IPU_CSI0_CPD_GBC_7__FULL           0x1E0300A8,0xffffffff
#define IPU_CSI0_CPD_GBC_7__CSI0_CPD_GBC15 0x1E0300A8,0x01FF0000
#define IPU_CSI0_CPD_GBC_7__CSI0_CPD_GBC14 0x1E0300A8,0x000001FF

#define IPU_CSI0_CPD_GBS_0__ADDR          0x1E0300AC
#define IPU_CSI0_CPD_GBS_0__EMPTY         0x1E0300AC,0x00000000
#define IPU_CSI0_CPD_GBS_0__FULL          0x1E0300AC,0xffffffff
#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS3 0x1E0300AC,0xFF000000
#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS2 0x1E0300AC,0x00FF0000
#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS1 0x1E0300AC,0x0000FF00
#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS0 0x1E0300AC,0x000000FF

#define IPU_CSI0_CPD_GBS_1__ADDR          0x1E0300B0
#define IPU_CSI0_CPD_GBS_1__EMPTY         0x1E0300B0,0x00000000
#define IPU_CSI0_CPD_GBS_1__FULL          0x1E0300B0,0xffffffff
#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS7 0x1E0300B0,0xFF000000
#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS6 0x1E0300B0,0x00FF0000
#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS5 0x1E0300B0,0x0000FF00
#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS4 0x1E0300B0,0x000000FF

#define IPU_CSI0_CPD_GBS_2__ADDR           0x1E0300B4
#define IPU_CSI0_CPD_GBS_2__EMPTY          0x1E0300B4,0x00000000
#define IPU_CSI0_CPD_GBS_2__FULL           0x1E0300B4,0xffffffff
#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS11 0x1E0300B4,0xFF000000
#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS10 0x1E0300B4,0x00FF0000
#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS9  0x1E0300B4,0x0000FF00
#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS8  0x1E0300B4,0x000000FF

#define IPU_CSI0_CPD_GBS_3__ADDR           0x1E0300B8
#define IPU_CSI0_CPD_GBS_3__EMPTY          0x1E0300B8,0x00000000
#define IPU_CSI0_CPD_GBS_3__FULL           0x1E0300B8,0xffffffff
#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS15 0x1E0300B8,0xFF000000
#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS14 0x1E0300B8,0x00FF0000
#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS13 0x1E0300B8,0x0000FF00
#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS12 0x1E0300B8,0x000000FF

#define IPU_CSI0_CPD_BC_0__ADDR         0x1E0300BC
#define IPU_CSI0_CPD_BC_0__EMPTY        0x1E0300BC,0x00000000
#define IPU_CSI0_CPD_BC_0__FULL         0x1E0300BC,0xffffffff
#define IPU_CSI0_CPD_BC_0__CSI0_CPD_BC1 0x1E0300BC,0x01FF0000
#define IPU_CSI0_CPD_BC_0__CSI0_CPD_BC0 0x1E0300BC,0x000001FF

#define IPU_CSI0_CPD_BC_1__ADDR         0x1E0300C0
#define IPU_CSI0_CPD_BC_1__EMPTY        0x1E0300C0,0x00000000
#define IPU_CSI0_CPD_BC_1__FULL         0x1E0300C0,0xffffffff
#define IPU_CSI0_CPD_BC_1__CSI0_CPD_BC3 0x1E0300C0,0x01FF0000
#define IPU_CSI0_CPD_BC_1__CSI0_CPD_BC2 0x1E0300C0,0x000001FF

#define IPU_CSI0_CPD_BC_2__ADDR         0x1E0300C4
#define IPU_CSI0_CPD_BC_2__EMPTY        0x1E0300C4,0x00000000
#define IPU_CSI0_CPD_BC_2__FULL         0x1E0300C4,0xffffffff
#define IPU_CSI0_CPD_BC_2__CSI0_CPD_BC5 0x1E0300C4,0x01FF0000
#define IPU_CSI0_CPD_BC_2__CSI0_CPD_BC4 0x1E0300C4,0x000001FF

#define IPU_CSI0_CPD_BC_3__ADDR         0x1E0300C8
#define IPU_CSI0_CPD_BC_3__EMPTY        0x1E0300C8,0x00000000
#define IPU_CSI0_CPD_BC_3__FULL         0x1E0300C8,0xffffffff
#define IPU_CSI0_CPD_BC_3__CSI0_CPD_BC7 0x1E0300C8,0x01FF0000
#define IPU_CSI0_CPD_BC_3__CSI0_CPD_BC6 0x1E0300C8,0x000001FF

#define IPU_CSI0_CPD_BC_4__ADDR         0x1E0300CC
#define IPU_CSI0_CPD_BC_4__EMPTY        0x1E0300CC,0x00000000
#define IPU_CSI0_CPD_BC_4__FULL         0x1E0300CC,0xffffffff
#define IPU_CSI0_CPD_BC_4__CSI0_CPD_BC9 0x1E0300CC,0x01FF0000
#define IPU_CSI0_CPD_BC_4__CSI0_CPD_BC8 0x1E0300CC,0x000001FF

#define IPU_CSI0_CPD_BC_5__ADDR          0x1E0300D0
#define IPU_CSI0_CPD_BC_5__EMPTY         0x1E0300D0,0x00000000
#define IPU_CSI0_CPD_BC_5__FULL          0x1E0300D0,0xffffffff
#define IPU_CSI0_CPD_BC_5__CSI0_CPD_BC11 0x1E0300D0,0x01FF0000
#define IPU_CSI0_CPD_BC_5__CSI0_CPD_BC10 0x1E0300D0,0x000001FF

#define IPU_CSI0_CPD_BC_6__ADDR          0x1E0300D4
#define IPU_CSI0_CPD_BC_6__EMPTY         0x1E0300D4,0x00000000
#define IPU_CSI0_CPD_BC_6__FULL          0x1E0300D4,0xffffffff
#define IPU_CSI0_CPD_BC_6__CSI0_CPD_BC13 0x1E0300D4,0x01FF0000
#define IPU_CSI0_CPD_BC_6__CSI0_CPD_BC12 0x1E0300D4,0x000001FF

#define IPU_CSI0_CPD_BC_7__ADDR          0x1E0300D8
#define IPU_CSI0_CPD_BC_7__EMPTY         0x1E0300D8,0x00000000
#define IPU_CSI0_CPD_BC_7__FULL          0x1E0300D8,0xffffffff
#define IPU_CSI0_CPD_BC_7__CSI0_CPD_BC15 0x1E0300D8,0x01FF0000
#define IPU_CSI0_CPD_BC_7__CSI0_CPD_BC14 0x1E0300D8,0x000001FF

#define IPU_CSI0_CPD_BS_0__ADDR         0x1E0300DC
#define IPU_CSI0_CPD_BS_0__EMPTY        0x1E0300DC,0x00000000
#define IPU_CSI0_CPD_BS_0__FULL         0x1E0300DC,0xffffffff
#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS3 0x1E0300DC,0xFF000000
#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS2 0x1E0300DC,0x00FF0000
#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS1 0x1E0300DC,0x0000FF00
#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS0 0x1E0300DC,0x000000FF

#define IPU_CSI0_CPD_BS_1__ADDR         0x1E0300E0
#define IPU_CSI0_CPD_BS_1__EMPTY        0x1E0300E0,0x00000000
#define IPU_CSI0_CPD_BS_1__FULL         0x1E0300E0,0xffffffff
#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS7 0x1E0300E0,0xFF000000
#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS6 0x1E0300E0,0x00FF0000
#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS5 0x1E0300E0,0x0000FF00
#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS4 0x1E0300E0,0x000000FF

#define IPU_CSI0_CPD_BS_2__ADDR          0x1E0300E4
#define IPU_CSI0_CPD_BS_2__EMPTY         0x1E0300E4,0x00000000
#define IPU_CSI0_CPD_BS_2__FULL          0x1E0300E4,0xffffffff
#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS11 0x1E0300E4,0xFF000000
#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS10 0x1E0300E4,0x00FF0000
#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS9  0x1E0300E4,0x0000FF00
#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS8  0x1E0300E4,0x000000FF

#define IPU_CSI0_CPD_BS_3__ADDR          0x1E0300E8
#define IPU_CSI0_CPD_BS_3__EMPTY         0x1E0300E8,0x00000000
#define IPU_CSI0_CPD_BS_3__FULL          0x1E0300E8,0xffffffff
#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS15 0x1E0300E8,0xFF000000
#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS14 0x1E0300E8,0x00FF0000
#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS13 0x1E0300E8,0x0000FF00
#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS12 0x1E0300E8,0x000000FF

#define IPU_CSI0_CPD_OFFSET1__ADDR               0x1E0300EC
#define IPU_CSI0_CPD_OFFSET1__EMPTY              0x1E0300EC,0x00000000
#define IPU_CSI0_CPD_OFFSET1__FULL               0x1E0300EC,0xffffffff
#define IPU_CSI0_CPD_OFFSET1__CSI0_CPD_B_OFFSET  0x1E0300EC,0x3FF00000
#define IPU_CSI0_CPD_OFFSET1__CSI0_CPD_GB_OFFSET 0x1E0300EC,0x000FFC00
#define IPU_CSI0_CPD_OFFSET1__CSI0_CPD_GR_OFFSET 0x1E0300EC,0x000003FF

#define IPU_CSI0_CPD_OFFSET2__ADDR              0x1E0300F0
#define IPU_CSI0_CPD_OFFSET2__EMPTY             0x1E0300F0,0x00000000
#define IPU_CSI0_CPD_OFFSET2__FULL              0x1E0300F0,0xffffffff
#define IPU_CSI0_CPD_OFFSET2__CSI0_CPD_R_OFFSET 0x1E0300F0,0x000003FF

#define IPU_CSI1_SENS_CONF__ADDR                  0x1E038000
#define IPU_CSI1_SENS_CONF__EMPTY                 0x1E038000,0x00000000
#define IPU_CSI1_SENS_CONF__FULL                  0x1E038000,0xffffffff
#define IPU_CSI1_SENS_CONF__CSI1_DATA_EN_POL      0x1E038000,0x80000000
#define IPU_CSI1_SENS_CONF__CSI1_FORCE_EOF        0x1E038000,0x20000000
#define IPU_CSI1_SENS_CONF__CSI1_JPEG_MODE        0x1E038000,0x10000000
#define IPU_CSI1_SENS_CONF__CSI1_JPEG8_EN         0x1E038000,0x08000000
#define IPU_CSI1_SENS_CONF__CSI1_DATA_DEST        0x1E038000,0x07000000
#define IPU_CSI1_SENS_CONF__CSI1_DIV_RATIO        0x1E038000,0x00FF0000
#define IPU_CSI1_SENS_CONF__CSI1_EXT_VSYNC        0x1E038000,0x00008000
#define IPU_CSI1_SENS_CONF__CSI1_DATA_WIDTH       0x1E038000,0x00007800
#define IPU_CSI1_SENS_CONF__CSI1_SENS_DATA_FORMAT 0x1E038000,0x00000700
#define IPU_CSI1_SENS_CONF__CSI1_PACK_TIGHT       0x1E038000,0x00000080
#define IPU_CSI1_SENS_CONF__CSI1_SENS_PRTCL       0x1E038000,0x00000070
#define IPU_CSI1_SENS_CONF__CSI1_SENS_PIX_CLK_POL 0x1E038000,0x00000008
#define IPU_CSI1_SENS_CONF__CSI1_DATA_POL         0x1E038000,0x00000004
#define IPU_CSI1_SENS_CONF__CSI1_HSYNC_POL        0x1E038000,0x00000002
#define IPU_CSI1_SENS_CONF__CSI1_VSYNC_POL        0x1E038000,0x00000001

#define IPU_CSI1_SENS_FRM_SIZE__ADDR                 0x1E038004
#define IPU_CSI1_SENS_FRM_SIZE__EMPTY                0x1E038004,0x00000000
#define IPU_CSI1_SENS_FRM_SIZE__FULL                 0x1E038004,0xffffffff
#define IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_HEIGHT 0x1E038004,0x0FFF0000
#define IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_WIDTH  0x1E038004,0x00001FFF

#define IPU_CSI1_ACT_FRM_SIZE__ADDR                0x1E038008
#define IPU_CSI1_ACT_FRM_SIZE__EMPTY               0x1E038008,0x00000000
#define IPU_CSI1_ACT_FRM_SIZE__FULL                0x1E038008,0xffffffff
#define IPU_CSI1_ACT_FRM_SIZE__CSI1_ACT_FRM_HEIGHT 0x1E038008,0x0FFF0000
#define IPU_CSI1_ACT_FRM_SIZE__CSI1_ACT_FRM_WIDTH  0x1E038008,0x00001FFF

#define IPU_CSI1_OUT_FRM_CTRL__ADDR           0x1E03800C
#define IPU_CSI1_OUT_FRM_CTRL__EMPTY          0x1E03800C,0x00000000
#define IPU_CSI1_OUT_FRM_CTRL__FULL           0x1E03800C,0xffffffff
#define IPU_CSI1_OUT_FRM_CTRL__CSI1_HORZ_DWNS 0x1E03800C,0x80000000
#define IPU_CSI1_OUT_FRM_CTRL__CSI1_VERT_DWNS 0x1E03800C,0x40000000
#define IPU_CSI1_OUT_FRM_CTRL__CSI1_HSC       0x1E03800C,0x1FFF0000
#define IPU_CSI1_OUT_FRM_CTRL__CSI1_VSC       0x1E03800C,0x00000FFF

#define IPU_CSI1_TST_CTRL__ADDR               0x1E038010
#define IPU_CSI1_TST_CTRL__EMPTY              0x1E038010,0x00000000
#define IPU_CSI1_TST_CTRL__FULL               0x1E038010,0xffffffff
#define IPU_CSI1_TST_CTRL__CSI1_TEST_GEN_MODE 0x1E038010,0x01000000
#define IPU_CSI1_TST_CTRL__CSI1_PG_B_VALUE    0x1E038010,0x00FF0000
#define IPU_CSI1_TST_CTRL__CSI1_PG_G_VALUE    0x1E038010,0x0000FF00
#define IPU_CSI1_TST_CTRL__CSI1_PG_R_VALUE    0x1E038010,0x000000FF

#define IPU_CSI1_CCIR_CODE_1__ADDR                    0x1E038014
#define IPU_CSI1_CCIR_CODE_1__EMPTY                   0x1E038014,0x00000000
#define IPU_CSI1_CCIR_CODE_1__FULL                    0x1E038014,0xffffffff
#define IPU_CSI1_CCIR_CODE_1__CSI1_CCIR_ERR_DET_EN    0x1E038014,0x01000000
#define IPU_CSI1_CCIR_CODE_1__CSI1_STRT_FLD0_ACTV     0x1E038014,0x00380000
#define IPU_CSI1_CCIR_CODE_1__CSI1_END_FLD0_ACTV      0x1E038014,0x00070000
#define IPU_CSI1_CCIR_CODE_1__CSI1_STRT_FLD0_BLNK_2ND 0x1E038014,0x00000E00
#define IPU_CSI1_CCIR_CODE_1__CSI1_END_FLD0_BLNK_2ND  0x1E038014,0x000001C0
#define IPU_CSI1_CCIR_CODE_1__CSI1_STRT_FLD0_BLNK_1ST 0x1E038014,0x00000038
#define IPU_CSI1_CCIR_CODE_1__CSI1_END_FLD0_BLNK_1ST  0x1E038014,0x00000007

#define IPU_CSI1_CCIR_CODE_2__ADDR                    0x1E038018
#define IPU_CSI1_CCIR_CODE_2__EMPTY                   0x1E038018,0x00000000
#define IPU_CSI1_CCIR_CODE_2__FULL                    0x1E038018,0xffffffff
#define IPU_CSI1_CCIR_CODE_2__CSI1_STRT_FLD1_ACTV     0x1E038018,0x00380000
#define IPU_CSI1_CCIR_CODE_2__CSI1_END_FLD1_ACTV      0x1E038018,0x00070000
#define IPU_CSI1_CCIR_CODE_2__CSI1_STRT_FLD1_BLNK_2ND 0x1E038018,0x00000E00
#define IPU_CSI1_CCIR_CODE_2__CSI1_END_FLD1_BLNK_2ND  0x1E038018,0x000001C0
#define IPU_CSI1_CCIR_CODE_2__CSI1_STRT_FLD1_BLNK_1ST 0x1E038018,0x00000038
#define IPU_CSI1_CCIR_CODE_2__CSI1_END_FLD1_BLNK_1ST  0x1E038018,0x00000007

#define IPU_CSI1_CCIR_CODE_3__ADDR             0x1E03801C
#define IPU_CSI1_CCIR_CODE_3__EMPTY            0x1E03801C,0x00000000
#define IPU_CSI1_CCIR_CODE_3__FULL             0x1E03801C,0xffffffff
#define IPU_CSI1_CCIR_CODE_3__CSI1_CCIR_PRECOM 0x1E03801C,0x3FFFFFFF

#define IPU_CSI1_DI__ADDR          0x1E038020
#define IPU_CSI1_DI__EMPTY         0x1E038020,0x00000000
#define IPU_CSI1_DI__FULL          0x1E038020,0xffffffff
#define IPU_CSI1_DI__CSI1_MIPI_DI3 0x1E038020,0xFF000000
#define IPU_CSI1_DI__CSI1_MIPI_DI2 0x1E038020,0x00FF0000
#define IPU_CSI1_DI__CSI1_MIPI_DI1 0x1E038020,0x0000FF00
#define IPU_CSI1_DI__CSI1_MIPI_DI0 0x1E038020,0x000000FF

#define IPU_CSI1_SKIP__ADDR                     0x1E038024
#define IPU_CSI1_SKIP__EMPTY                    0x1E038024,0x00000000
#define IPU_CSI1_SKIP__FULL                     0x1E038024,0xffffffff
#define IPU_CSI1_SKIP__CSI1_SKIP_ISP            0x1E038024,0x00F80000
#define IPU_CSI1_SKIP__CSI1_MAX_RATIO_SKIP_ISP  0x1E038024,0x00070000
#define IPU_CSI1_SKIP__CSI1_ID_2_SKIP           0x1E038024,0x00000300
#define IPU_CSI1_SKIP__CSI1_SKIP_SMFC           0x1E038024,0x000000F8
#define IPU_CSI1_SKIP__CSI1_MAX_RATIO_SKIP_SMFC 0x1E038024,0x00000007

#define IPU_CSI1_CPD_CTRL__ADDR               0x1E038028
#define IPU_CSI1_CPD_CTRL__EMPTY              0x1E038028,0x00000000
#define IPU_CSI1_CPD_CTRL__FULL               0x1E038028,0xffffffff
#define IPU_CSI1_CPD_CTRL__CSI1_CPD           0x1E038028,0x0000001C
#define IPU_CSI1_CPD_CTRL__CSI1_RED_ROW_BEGIN 0x1E038028,0x00000002
#define IPU_CSI1_CPD_CTRL__CSI1_GREEN_P_BEGIN 0x1E038028,0x00000001

#define IPU_CSI1_CPD_RC_0__ADDR          0x1E03802C
#define IPU_CSI1_CPD_RC_0__EMPTY         0x1E03802C,0x00000000
#define IPU_CSI1_CPD_RC_0__FULL          0x1E03802C,0xffffffff
#define IPU_CSI1_CPD_RC_0__CSI1_CPD_RC_1 0x1E03802C,0x01FF0000
#define IPU_CSI1_CPD_RC_0__CSI1_CPD_RC_0 0x1E03802C,0x000001FF

#define IPU_CSI1_CPD_RC_1__ADDR          0x1E038030
#define IPU_CSI1_CPD_RC_1__EMPTY         0x1E038030,0x00000000
#define IPU_CSI1_CPD_RC_1__FULL          0x1E038030,0xffffffff
#define IPU_CSI1_CPD_RC_1__CSI1_CPD_RC_3 0x1E038030,0x01FF0000
#define IPU_CSI1_CPD_RC_1__CSI1_CPD_RC_2 0x1E038030,0x000001FF

#define IPU_CSI1_CPD_RC_2__ADDR          0x1E038034
#define IPU_CSI1_CPD_RC_2__EMPTY         0x1E038034,0x00000000
#define IPU_CSI1_CPD_RC_2__FULL          0x1E038034,0xffffffff
#define IPU_CSI1_CPD_RC_2__CSI1_CPD_RC_5 0x1E038034,0x01FF0000
#define IPU_CSI1_CPD_RC_2__CSI1_CPD_RC_4 0x1E038034,0x000001FF

#define IPU_CSI1_CPD_RC_3__ADDR          0x1E038038
#define IPU_CSI1_CPD_RC_3__EMPTY         0x1E038038,0x00000000
#define IPU_CSI1_CPD_RC_3__FULL          0x1E038038,0xffffffff
#define IPU_CSI1_CPD_RC_3__CSI1_CPD_RC_7 0x1E038038,0x01FF0000
#define IPU_CSI1_CPD_RC_3__CSI1_CPD_RC_6 0x1E038038,0x000001FF

#define IPU_CSI1_CPD_RC_4__ADDR          0x1E03803C
#define IPU_CSI1_CPD_RC_4__EMPTY         0x1E03803C,0x00000000
#define IPU_CSI1_CPD_RC_4__FULL          0x1E03803C,0xffffffff
#define IPU_CSI1_CPD_RC_4__CSI1_CPD_RC_9 0x1E03803C,0x01FF0000
#define IPU_CSI1_CPD_RC_4__CSI1_CPD_RC_8 0x1E03803C,0x000001FF

#define IPU_CSI1_CPD_RC_5__ADDR           0x1E038040
#define IPU_CSI1_CPD_RC_5__EMPTY          0x1E038040,0x00000000
#define IPU_CSI1_CPD_RC_5__FULL           0x1E038040,0xffffffff
#define IPU_CSI1_CPD_RC_5__CSI1_CPD_RC_11 0x1E038040,0x01FF0000
#define IPU_CSI1_CPD_RC_5__CSI1_CPD_RC_10 0x1E038040,0x000001FF

#define IPU_CSI1_CPD_RC_6__ADDR           0x1E038044
#define IPU_CSI1_CPD_RC_6__EMPTY          0x1E038044,0x00000000
#define IPU_CSI1_CPD_RC_6__FULL           0x1E038044,0xffffffff
#define IPU_CSI1_CPD_RC_6__CSI1_CPD_RC_13 0x1E038044,0x01FF0000
#define IPU_CSI1_CPD_RC_6__CSI1_CPD_RC_12 0x1E038044,0x000001FF

#define IPU_CSI1_CPD_RC_7__ADDR           0x1E038048
#define IPU_CSI1_CPD_RC_7__EMPTY          0x1E038048,0x00000000
#define IPU_CSI1_CPD_RC_7__FULL           0x1E038048,0xffffffff
#define IPU_CSI1_CPD_RC_7__CSI1_CPD_RC_15 0x1E038048,0x01FF0000
#define IPU_CSI1_CPD_RC_7__CSI1_CPD_RC_14 0x1E038048,0x000001FF

#define IPU_CSI1_CPD_RS_0__ADDR         0x1E03804C
#define IPU_CSI1_CPD_RS_0__EMPTY        0x1E03804C,0x00000000
#define IPU_CSI1_CPD_RS_0__FULL         0x1E03804C,0xffffffff
#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS3 0x1E03804C,0xFF000000
#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS2 0x1E03804C,0x00FF0000
#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS1 0x1E03804C,0x0000FF00
#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS0 0x1E03804C,0x000000FF

#define IPU_CSI1_CPD_RS_1__ADDR         0x1E038050
#define IPU_CSI1_CPD_RS_1__EMPTY        0x1E038050,0x00000000
#define IPU_CSI1_CPD_RS_1__FULL         0x1E038050,0xffffffff
#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS7 0x1E038050,0xFF000000
#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS6 0x1E038050,0x00FF0000
#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS5 0x1E038050,0x0000FF00
#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS4 0x1E038050,0x000000FF

#define IPU_CSI1_CPD_RS_2__ADDR          0x1E038054
#define IPU_CSI1_CPD_RS_2__EMPTY         0x1E038054,0x00000000
#define IPU_CSI1_CPD_RS_2__FULL          0x1E038054,0xffffffff
#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS11 0x1E038054,0xFF000000
#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS10 0x1E038054,0x00FF0000
#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS9  0x1E038054,0x0000FF00
#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS8  0x1E038054,0x000000FF

#define IPU_CSI1_CPD_RS_3__ADDR          0x1E038058
#define IPU_CSI1_CPD_RS_3__EMPTY         0x1E038058,0x00000000
#define IPU_CSI1_CPD_RS_3__FULL          0x1E038058,0xffffffff
#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS15 0x1E038058,0xFF000000
#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS14 0x1E038058,0x00FF0000
#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS13 0x1E038058,0x0000FF00
#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS12 0x1E038058,0x000000FF

#define IPU_CSI1_CPD_GRC_0__ADDR          0x1E03805C
#define IPU_CSI1_CPD_GRC_0__EMPTY         0x1E03805C,0x00000000
#define IPU_CSI1_CPD_GRC_0__FULL          0x1E03805C,0xffffffff
#define IPU_CSI1_CPD_GRC_0__CSI1_CPD_GRC1 0x1E03805C,0x01FF0000
#define IPU_CSI1_CPD_GRC_0__CSI1_CPD_GRC0 0x1E03805C,0x000001FF

#define IPU_CSI1_CPD_GRC_1__ADDR          0x1E038060
#define IPU_CSI1_CPD_GRC_1__EMPTY         0x1E038060,0x00000000
#define IPU_CSI1_CPD_GRC_1__FULL          0x1E038060,0xffffffff
#define IPU_CSI1_CPD_GRC_1__CSI1_CPD_GRC3 0x1E038060,0x01FF0000
#define IPU_CSI1_CPD_GRC_1__CSI1_CPD_GRC2 0x1E038060,0x000001FF

#define IPU_CSI1_CPD_GRC_2__ADDR          0x1E038064
#define IPU_CSI1_CPD_GRC_2__EMPTY         0x1E038064,0x00000000
#define IPU_CSI1_CPD_GRC_2__FULL          0x1E038064,0xffffffff
#define IPU_CSI1_CPD_GRC_2__CSI1_CPD_GRC5 0x1E038064,0x01FF0000
#define IPU_CSI1_CPD_GRC_2__CSI1_CPD_GRC4 0x1E038064,0x000001FF

#define IPU_CSI1_CPD_GRC_3__ADDR          0x1E038068
#define IPU_CSI1_CPD_GRC_3__EMPTY         0x1E038068,0x00000000
#define IPU_CSI1_CPD_GRC_3__FULL          0x1E038068,0xffffffff
#define IPU_CSI1_CPD_GRC_3__CSI1_CPD_GRC7 0x1E038068,0x01FF0000
#define IPU_CSI1_CPD_GRC_3__CSI1_CPD_GRC6 0x1E038068,0x000001FF

#define IPU_CSI1_CPD_GRC_4__ADDR          0x1E03806C
#define IPU_CSI1_CPD_GRC_4__EMPTY         0x1E03806C,0x00000000
#define IPU_CSI1_CPD_GRC_4__FULL          0x1E03806C,0xffffffff
#define IPU_CSI1_CPD_GRC_4__CSI1_CPD_GRC9 0x1E03806C,0x01FF0000
#define IPU_CSI1_CPD_GRC_4__CSI1_CPD_GRC8 0x1E03806C,0x000001FF

#define IPU_CSI1_CPD_GRC_5__ADDR           0x1E038070
#define IPU_CSI1_CPD_GRC_5__EMPTY          0x1E038070,0x00000000
#define IPU_CSI1_CPD_GRC_5__FULL           0x1E038070,0xffffffff
#define IPU_CSI1_CPD_GRC_5__CSI1_CPD_GRC11 0x1E038070,0x01FF0000
#define IPU_CSI1_CPD_GRC_5__CSI1_CPD_GRC10 0x1E038070,0x000001FF

#define IPU_CSI1_CPD_GRC_6__ADDR           0x1E038074
#define IPU_CSI1_CPD_GRC_6__EMPTY          0x1E038074,0x00000000
#define IPU_CSI1_CPD_GRC_6__FULL           0x1E038074,0xffffffff
#define IPU_CSI1_CPD_GRC_6__CSI1_CPD_GRC13 0x1E038074,0x01FF0000
#define IPU_CSI1_CPD_GRC_6__CSI1_CPD_GRC12 0x1E038074,0x000001FF

#define IPU_CSI1_CPD_GRC_7__ADDR           0x1E038078
#define IPU_CSI1_CPD_GRC_7__EMPTY          0x1E038078,0x00000000
#define IPU_CSI1_CPD_GRC_7__FULL           0x1E038078,0xffffffff
#define IPU_CSI1_CPD_GRC_7__CSI1_CPD_GRC15 0x1E038078,0x01FF0000
#define IPU_CSI1_CPD_GRC_7__CSI1_CPD_GRC14 0x1E038078,0x000001FF

#define IPU_CSI1_CPD_GRS_0__ADDR          0x1E03807C
#define IPU_CSI1_CPD_GRS_0__EMPTY         0x1E03807C,0x00000000
#define IPU_CSI1_CPD_GRS_0__FULL          0x1E03807C,0xffffffff
#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS3 0x1E03807C,0xFF000000
#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS2 0x1E03807C,0x00FF0000
#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS1 0x1E03807C,0x0000FF00
#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS0 0x1E03807C,0x000000FF

#define IPU_CSI1_CPD_GRS_1__ADDR          0x1E038080
#define IPU_CSI1_CPD_GRS_1__EMPTY         0x1E038080,0x00000000
#define IPU_CSI1_CPD_GRS_1__FULL          0x1E038080,0xffffffff
#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS7 0x1E038080,0xFF000000
#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS6 0x1E038080,0x00FF0000
#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS5 0x1E038080,0x0000FF00
#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS4 0x1E038080,0x000000FF

#define IPU_CSI1_CPD_GRS_2__ADDR           0x1E038084
#define IPU_CSI1_CPD_GRS_2__EMPTY          0x1E038084,0x00000000
#define IPU_CSI1_CPD_GRS_2__FULL           0x1E038084,0xffffffff
#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS11 0x1E038084,0xFF000000
#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS10 0x1E038084,0x00FF0000
#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS9  0x1E038084,0x0000FF00
#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS8  0x1E038084,0x000000FF

#define IPU_CSI1_CPD_GRS_3__ADDR           0x1E038088
#define IPU_CSI1_CPD_GRS_3__EMPTY          0x1E038088,0x00000000
#define IPU_CSI1_CPD_GRS_3__FULL           0x1E038088,0xffffffff
#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS15 0x1E038088,0xFF000000
#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS14 0x1E038088,0x00FF0000
#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS13 0x1E038088,0x0000FF00
#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS12 0x1E038088,0x000000FF

#define IPU_CSI1_CPD_GBC_0__ADDR          0x1E03808C
#define IPU_CSI1_CPD_GBC_0__EMPTY         0x1E03808C,0x00000000
#define IPU_CSI1_CPD_GBC_0__FULL          0x1E03808C,0xffffffff
#define IPU_CSI1_CPD_GBC_0__CSI1_CPD_GBC1 0x1E03808C,0x01FF0000
#define IPU_CSI1_CPD_GBC_0__CSI1_CPD_GBC0 0x1E03808C,0x000001FF

#define IPU_CSI1_CPD_GBC_1__ADDR          0x1E038090
#define IPU_CSI1_CPD_GBC_1__EMPTY         0x1E038090,0x00000000
#define IPU_CSI1_CPD_GBC_1__FULL          0x1E038090,0xffffffff
#define IPU_CSI1_CPD_GBC_1__CSI1_CPD_GBC3 0x1E038090,0x01FF0000
#define IPU_CSI1_CPD_GBC_1__CSI1_CPD_GBC2 0x1E038090,0x000001FF

#define IPU_CSI1_CPD_GBC_2__ADDR          0x1E038094
#define IPU_CSI1_CPD_GBC_2__EMPTY         0x1E038094,0x00000000
#define IPU_CSI1_CPD_GBC_2__FULL          0x1E038094,0xffffffff
#define IPU_CSI1_CPD_GBC_2__CSI1_CPD_GBC5 0x1E038094,0x01FF0000
#define IPU_CSI1_CPD_GBC_2__CSI1_CPD_GBC4 0x1E038094,0x000001FF

#define IPU_CSI1_CPD_GBC_3__ADDR          0x1E038098
#define IPU_CSI1_CPD_GBC_3__EMPTY         0x1E038098,0x00000000
#define IPU_CSI1_CPD_GBC_3__FULL          0x1E038098,0xffffffff
#define IPU_CSI1_CPD_GBC_3__CSI1_CPD_GBC7 0x1E038098,0x01FF0000
#define IPU_CSI1_CPD_GBC_3__CSI1_CPD_GBC6 0x1E038098,0x000001FF

#define IPU_CSI1_CPD_GBC_4__ADDR          0x1E03809C
#define IPU_CSI1_CPD_GBC_4__EMPTY         0x1E03809C,0x00000000
#define IPU_CSI1_CPD_GBC_4__FULL          0x1E03809C,0xffffffff
#define IPU_CSI1_CPD_GBC_4__CSI1_CPD_GBC9 0x1E03809C,0x01FF0000
#define IPU_CSI1_CPD_GBC_4__CSI1_CPD_GBC8 0x1E03809C,0x000001FF

#define IPU_CSI1_CPD_GBC_5__ADDR           0x1E0380A0
#define IPU_CSI1_CPD_GBC_5__EMPTY          0x1E0380A0,0x00000000
#define IPU_CSI1_CPD_GBC_5__FULL           0x1E0380A0,0xffffffff
#define IPU_CSI1_CPD_GBC_5__CSI1_CPD_GBC11 0x1E0380A0,0x01FF0000
#define IPU_CSI1_CPD_GBC_5__CSI1_CPD_GBC10 0x1E0380A0,0x000001FF

#define IPU_CSI1_CPD_GBC_6__ADDR           0x1E0380A4
#define IPU_CSI1_CPD_GBC_6__EMPTY          0x1E0380A4,0x00000000
#define IPU_CSI1_CPD_GBC_6__FULL           0x1E0380A4,0xffffffff
#define IPU_CSI1_CPD_GBC_6__CSI1_CPD_GBC13 0x1E0380A4,0x01FF0000
#define IPU_CSI1_CPD_GBC_6__CSI1_CPD_GBC12 0x1E0380A4,0x000001FF

#define IPU_CSI1_CPD_GBC_7__ADDR           0x1E0380A8
#define IPU_CSI1_CPD_GBC_7__EMPTY          0x1E0380A8,0x00000000
#define IPU_CSI1_CPD_GBC_7__FULL           0x1E0380A8,0xffffffff
#define IPU_CSI1_CPD_GBC_7__CSI1_CPD_GBC15 0x1E0380A8,0x01FF0000
#define IPU_CSI1_CPD_GBC_7__CSI1_CPD_GBC14 0x1E0380A8,0x000001FF

#define IPU_CSI1_CPD_GBS_0__ADDR          0x1E0380AC
#define IPU_CSI1_CPD_GBS_0__EMPTY         0x1E0380AC,0x00000000
#define IPU_CSI1_CPD_GBS_0__FULL          0x1E0380AC,0xffffffff
#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS3 0x1E0380AC,0xFF000000
#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS2 0x1E0380AC,0x00FF0000
#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS1 0x1E0380AC,0x0000FF00
#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS0 0x1E0380AC,0x000000FF

#define IPU_CSI1_CPD_GBS_1__ADDR          0x1E0380B0
#define IPU_CSI1_CPD_GBS_1__EMPTY         0x1E0380B0,0x00000000
#define IPU_CSI1_CPD_GBS_1__FULL          0x1E0380B0,0xffffffff
#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS7 0x1E0380B0,0xFF000000
#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS6 0x1E0380B0,0x00FF0000
#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS5 0x1E0380B0,0x0000FF00
#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS4 0x1E0380B0,0x000000FF

#define IPU_CSI1_CPD_GBS_2__ADDR           0x1E0380B4
#define IPU_CSI1_CPD_GBS_2__EMPTY          0x1E0380B4,0x00000000
#define IPU_CSI1_CPD_GBS_2__FULL           0x1E0380B4,0xffffffff
#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS11 0x1E0380B4,0xFF000000
#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS10 0x1E0380B4,0x00FF0000
#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS9  0x1E0380B4,0x0000FF00
#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS8  0x1E0380B4,0x000000FF

#define IPU_CSI1_CPD_GBS_3__ADDR           0x1E0380B8
#define IPU_CSI1_CPD_GBS_3__EMPTY          0x1E0380B8,0x00000000
#define IPU_CSI1_CPD_GBS_3__FULL           0x1E0380B8,0xffffffff
#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS15 0x1E0380B8,0xFF000000
#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS14 0x1E0380B8,0x00FF0000
#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS13 0x1E0380B8,0x0000FF00
#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS12 0x1E0380B8,0x000000FF

#define IPU_CSI1_CPD_BC_0__ADDR         0x1E0380BC
#define IPU_CSI1_CPD_BC_0__EMPTY        0x1E0380BC,0x00000000
#define IPU_CSI1_CPD_BC_0__FULL         0x1E0380BC,0xffffffff
#define IPU_CSI1_CPD_BC_0__CSI1_CPD_BC1 0x1E0380BC,0x01FF0000
#define IPU_CSI1_CPD_BC_0__CSI1_CPD_BC0 0x1E0380BC,0x000001FF

#define IPU_CSI1_CPD_BC_1__ADDR         0x1E0380C0
#define IPU_CSI1_CPD_BC_1__EMPTY        0x1E0380C0,0x00000000
#define IPU_CSI1_CPD_BC_1__FULL         0x1E0380C0,0xffffffff
#define IPU_CSI1_CPD_BC_1__CSI1_CPD_BC3 0x1E0380C0,0x01FF0000
#define IPU_CSI1_CPD_BC_1__CSI1_CPD_BC2 0x1E0380C0,0x000001FF

#define IPU_CSI1_CPD_BC_2__ADDR         0x1E0380C4
#define IPU_CSI1_CPD_BC_2__EMPTY        0x1E0380C4,0x00000000
#define IPU_CSI1_CPD_BC_2__FULL         0x1E0380C4,0xffffffff
#define IPU_CSI1_CPD_BC_2__CSI1_CPD_BC5 0x1E0380C4,0x01FF0000
#define IPU_CSI1_CPD_BC_2__CSI1_CPD_BC4 0x1E0380C4,0x000001FF

#define IPU_CSI1_CPD_BC_3__ADDR         0x1E0380C8
#define IPU_CSI1_CPD_BC_3__EMPTY        0x1E0380C8,0x00000000
#define IPU_CSI1_CPD_BC_3__FULL         0x1E0380C8,0xffffffff
#define IPU_CSI1_CPD_BC_3__CSI1_CPD_BC7 0x1E0380C8,0x01FF0000
#define IPU_CSI1_CPD_BC_3__CSI1_CPD_BC6 0x1E0380C8,0x000001FF

#define IPU_CSI1_CPD_BC_4__ADDR         0x1E0380CC
#define IPU_CSI1_CPD_BC_4__EMPTY        0x1E0380CC,0x00000000
#define IPU_CSI1_CPD_BC_4__FULL         0x1E0380CC,0xffffffff
#define IPU_CSI1_CPD_BC_4__CSI1_CPD_BC9 0x1E0380CC,0x01FF0000
#define IPU_CSI1_CPD_BC_4__CSI1_CPD_BC8 0x1E0380CC,0x000001FF

#define IPU_CSI1_CPD_BC_5__ADDR          0x1E0380D0
#define IPU_CSI1_CPD_BC_5__EMPTY         0x1E0380D0,0x00000000
#define IPU_CSI1_CPD_BC_5__FULL          0x1E0380D0,0xffffffff
#define IPU_CSI1_CPD_BC_5__CSI1_CPD_BC11 0x1E0380D0,0x01FF0000
#define IPU_CSI1_CPD_BC_5__CSI1_CPD_BC10 0x1E0380D0,0x000001FF

#define IPU_CSI1_CPD_BC_6__ADDR          0x1E0380D4
#define IPU_CSI1_CPD_BC_6__EMPTY         0x1E0380D4,0x00000000
#define IPU_CSI1_CPD_BC_6__FULL          0x1E0380D4,0xffffffff
#define IPU_CSI1_CPD_BC_6__CSI1_CPD_BC13 0x1E0380D4,0x01FF0000
#define IPU_CSI1_CPD_BC_6__CSI1_CPD_BC12 0x1E0380D4,0x000001FF

#define IPU_CSI1_CPD_BC_7__ADDR          0x1E0380D8
#define IPU_CSI1_CPD_BC_7__EMPTY         0x1E0380D8,0x00000000
#define IPU_CSI1_CPD_BC_7__FULL          0x1E0380D8,0xffffffff
#define IPU_CSI1_CPD_BC_7__CSI1_CPD_BC15 0x1E0380D8,0x01FF0000
#define IPU_CSI1_CPD_BC_7__CSI1_CPD_BC14 0x1E0380D8,0x000001FF

#define IPU_CSI1_CPD_BS_0__ADDR         0x1E0380DC
#define IPU_CSI1_CPD_BS_0__EMPTY        0x1E0380DC,0x00000000
#define IPU_CSI1_CPD_BS_0__FULL         0x1E0380DC,0xffffffff
#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS3 0x1E0380DC,0xFF000000
#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS2 0x1E0380DC,0x00FF0000
#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS1 0x1E0380DC,0x0000FF00
#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS0 0x1E0380DC,0x000000FF

#define IPU_CSI1_CPD_BS_1__ADDR         0x1E0380E0
#define IPU_CSI1_CPD_BS_1__EMPTY        0x1E0380E0,0x00000000
#define IPU_CSI1_CPD_BS_1__FULL         0x1E0380E0,0xffffffff
#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS7 0x1E0380E0,0xFF000000
#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS6 0x1E0380E0,0x00FF0000
#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS5 0x1E0380E0,0x0000FF00
#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS4 0x1E0380E0,0x000000FF

#define IPU_CSI1_CPD_BS_2__ADDR          0x1E0380E4
#define IPU_CSI1_CPD_BS_2__EMPTY         0x1E0380E4,0x00000000
#define IPU_CSI1_CPD_BS_2__FULL          0x1E0380E4,0xffffffff
#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS11 0x1E0380E4,0xFF000000
#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS10 0x1E0380E4,0x00FF0000
#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS9  0x1E0380E4,0x0000FF00
#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS8  0x1E0380E4,0x000000FF

#define IPU_CSI1_CPD_BS_3__ADDR          0x1E0380E8
#define IPU_CSI1_CPD_BS_3__EMPTY         0x1E0380E8,0x00000000
#define IPU_CSI1_CPD_BS_3__FULL          0x1E0380E8,0xffffffff
#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS15 0x1E0380E8,0xFF000000
#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS14 0x1E0380E8,0x00FF0000
#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS13 0x1E0380E8,0x0000FF00
#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS12 0x1E0380E8,0x000000FF

#define IPU_CSI1_CPD_OFFSET1__ADDR               0x1E0380EC
#define IPU_CSI1_CPD_OFFSET1__EMPTY              0x1E0380EC,0x00000000
#define IPU_CSI1_CPD_OFFSET1__FULL               0x1E0380EC,0xffffffff
#define IPU_CSI1_CPD_OFFSET1__CSI1_CPD_B_OFFSET  0x1E0380EC,0x3FF00000
#define IPU_CSI1_CPD_OFFSET1__CSI1_CPD_GB_OFFSET 0x1E0380EC,0x000FFC00
#define IPU_CSI1_CPD_OFFSET1__CSI1_CPD_GR_OFFSET 0x1E0380EC,0x000003FF

#define IPU_CSI1_CPD_OFFSET2__ADDR              0x1E0380F0
#define IPU_CSI1_CPD_OFFSET2__EMPTY             0x1E0380F0,0x00000000
#define IPU_CSI1_CPD_OFFSET2__FULL              0x1E0380F0,0xffffffff
#define IPU_CSI1_CPD_OFFSET2__CSI1_CPD_R_OFFSET 0x1E0380F0,0x000003FF
// ================= End of IPUV3EX CSI Registers =====================

// ================= Start of IPUV3EX DI Registers =====================
#define IPU_DI0_GENERAL__ADDR                      0x1E040000
#define IPU_DI0_GENERAL__EMPTY                     0x1E040000,0x00000000
#define IPU_DI0_GENERAL__FULL                      0x1E040000,0xffffffff
#define IPU_DI0_GENERAL__DI0_DISP_Y_SEL            0x1E040000,0x70000000
#define IPU_DI0_GENERAL__DI0_CLOCK_STOP_MODE   0x1E040000,0x0F000000
#define IPU_DI0_GENERAL__DI0_DISP_CLOCK_INIT   0x1E040000,0x00800000
#define IPU_DI0_GENERAL__DI0_MASK_SEL              0x1E040000,0x00400000
#define IPU_DI0_GENERAL__DI0_VSYNC_EXT             0x1E040000,0x00200000
#define IPU_DI0_GENERAL__DI0_CLK_EXT               0x1E040000,0x00100000
#define IPU_DI0_GENERAL__DI0_WATCHDOG_MODE         0x1E040000,0x000C0000
#define IPU_DI0_GENERAL__DI0_POLARITY_DISP_CLK 0x1E040000,0x00020000
#define IPU_DI0_GENERAL__DI0_SYNC_COUNT_SEL        0x1E040000,0x0000F000
#define IPU_DI0_GENERAL__DI0_ERR_TREATMENT         0x1E040000,0x00000800
#define IPU_DI0_GENERAL__DI0_ERM_VSYNC_SEL         0x1E040000,0x00000400
#define IPU_DI0_GENERAL__DI0_POLARITY_CS1          0x1E040000,0x00000200
#define IPU_DI0_GENERAL__DI0_POLARITY_CS0          0x1E040000,0x00000100
#define IPU_DI0_GENERAL__DI0_POLARITY_8            0x1E040000,0x00000080
#define IPU_DI0_GENERAL__DI0_POLARITY_7            0x1E040000,0x00000040
#define IPU_DI0_GENERAL__DI0_POLARITY_6            0x1E040000,0x00000020
#define IPU_DI0_GENERAL__DI0_POLARITY_5            0x1E040000,0x00000010
#define IPU_DI0_GENERAL__DI0_POLARITY_4            0x1E040000,0x00000008
#define IPU_DI0_GENERAL__DI0_POLARITY_3            0x1E040000,0x00000004
#define IPU_DI0_GENERAL__DI0_POLARITY_2            0x1E040000,0x00000002
#define IPU_DI0_GENERAL__DI0_POLARITY_1            0x1E040000,0x00000001

#define IPU_DI0_BS_CLKGEN0__ADDR                0x1E040004
#define IPU_DI0_BS_CLKGEN0__EMPTY               0x1E040004,0x00000000
#define IPU_DI0_BS_CLKGEN0__FULL                0x1E040004,0xffffffff
#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET 0x1E040004,0x01FF0000
#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD 0x1E040004,0x00000FFF

#define IPU_DI0_BS_CLKGEN1__ADDR                  0x1E040008
#define IPU_DI0_BS_CLKGEN1__EMPTY                 0x1E040008,0x00000000
#define IPU_DI0_BS_CLKGEN1__FULL                  0x1E040008,0xffffffff
#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN 0x1E040008,0x01FF0000
#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP       0x1E040008,0x000001FF

#define DI_SWGEN0_ADDR(di, pointer)                             (IPU_DI0_GENERAL__ADDR + \
                                                                                        di *0x8000 +                            \
                                                                                        (pointer-1) * 0x4 + 0x000C)
#define DI_SWGEN0_EMPTY(di, pointer)                                            DI_SWGEN0_ADDR(di, pointer), 0x00000000
#define DI_SWGEN0_FULL(di, pointer)                                                     DI_SWGEN0_ADDR(di, pointer), 0xFFFFFFFF

#define DI_SWGEN0_RUN_VALUE_M1(di, pointer)             DI_SWGEN0_ADDR(di, pointer), 0x7FF80000
#define DI_SWGEN0_RUN_RESOL(di, pointer)                                DI_SWGEN0_ADDR(di, pointer), 0x00070000
#define DI_SWGEN0_OFFSET_VALUE(di, pointer)                     DI_SWGEN0_ADDR(di, pointer), 0x00007FF8
#define DI_SWGEN0_OFFSET_RESOL(di, pointer)                     DI_SWGEN0_ADDR(di, pointer), 0x00000007

#define DI_SWGEN1_ADDR(di, pointer)                                                     (IPU_DI0_GENERAL__ADDR + \
                                                                                                                                                                                        di *0x8000 + \
                                                                                                                                                                                        (pointer-1) * 0x4 + 0x0030)
#define DI_SWGEN1_EMPTY(di, pointer)                                            DI_SWGEN1_ADDR(di, pointer), 0x00000000
#define DI_SWGEN1_FULL(di, pointer)                                                     DI_SWGEN1_ADDR(di, pointer), 0xFFFFFFFF

#define DI_SWGEN1_CNT_POL_GEN_EN(di, pointer)   DI_SWGEN1_ADDR(di, pointer), 0x60000000
#define DI_SWGEN1_CNT_AUTOLOAD(di, pointer)             DI_SWGEN1_ADDR(di, pointer), 0x10000000
#define DI_SWGEN1_CNT_CLR_SEL(di, pointer)                      DI_SWGEN1_ADDR(di, pointer), 0x0E000000
#define DI_SWGEN1_CNT_DOW(di, pointer)                                  DI_SWGEN1_ADDR(di, pointer), 0x01FF0000
#define DI_SWGEN1_CNT_POL_TRIG_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00007000
#define DI_SWGEN1_CNT_POL_CLR_SEL(di, pointer)  DI_SWGEN1_ADDR(di, pointer), 0x00000E00
#define DI_SWGEN1_CNT_CNT_UP(di, pointer)                               DI_SWGEN1_ADDR(di, pointer), 0x000001FF

/*sync waveform generator 9 is special*/
#define IPU_DI0_SW_GEN0_9__ADDR                    0x1E04002C
#define IPU_DI0_SW_GEN0_9__EMPTY                   0x1E04002C,0x00000000
#define IPU_DI0_SW_GEN0_9__FULL                    0x1E04002C,0xffffffff
#define IPU_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9      0x1E04002C,0x7FF80000
#define IPU_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9    0x1E04002C,0x00070000
#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9      0x1E04002C,0x00007FF8
#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9 0x1E04002C,0x00000007

#define IPU_DI0_SW_GEN1_9__ADDR                  0x1E040050
#define IPU_DI0_SW_GEN1_9__EMPTY                 0x1E040050,0x00000000
#define IPU_DI0_SW_GEN1_9__FULL                  0x1E040050,0xffffffff
#define IPU_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9     0x1E040050,0xE0000000
#define IPU_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9 0x1E040050,0x10000000
#define IPU_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9     0x1E040050,0x0E000000
#define IPU_DI0_SW_GEN1_9__DI0_CNT_DOWN_9        0x1E040050,0x01FF0000
#define IPU_DI0_SW_GEN1_9__DI0_TAG_SEL_9         0x1E040050,0x00008000
#define IPU_DI0_SW_GEN1_9__DI0_CNT_UP_9          0x1E040050,0x000001FF

#define IPU_DI0_SYNC_AS_GEN__ADDR              0x1E040054
#define IPU_DI0_SYNC_AS_GEN__EMPTY             0x1E040054,0x00000000
#define IPU_DI0_SYNC_AS_GEN__FULL              0x1E040054,0xffffffff
#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN 0x1E040054,0x10000000
#define IPU_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL     0x1E040054,0x0000E000
#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START    0x1E040054,0x00000FFF

#define IPU_DI0_DW_GEN_0__ADDR                  0x1E040058
#define IPU_DI0_DW_GEN_0__EMPTY                 0x1E040058,0x00000000
#define IPU_DI0_DW_GEN_0__FULL                  0x1E040058,0xffffffff
#define IPU_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0     0x1E040058,0xFF000000
#define IPU_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1E040058,0x00FF0000
#define IPU_DI0_DW_GEN_0__DI0_CST_0             0x1E040058,0x0000C000
#define IPU_DI0_DW_GEN_0__DI0_PT_6_0            0x1E040058,0x00003000
#define IPU_DI0_DW_GEN_0__DI0_PT_5_0            0x1E040058,0x00000C00
#define IPU_DI0_DW_GEN_0__DI0_PT_4_0            0x1E040058,0x00000300
#define IPU_DI0_DW_GEN_0__DI0_PT_3_0            0x1E040058,0x000000C0
#define IPU_DI0_DW_GEN_0__DI0_PT_2_0            0x1E040058,0x00000030
#define IPU_DI0_DW_GEN_0__DI0_PT_1_0            0x1E040058,0x0000000C
#define IPU_DI0_DW_GEN_0__DI0_PT_0_0            0x1E040058,0x00000003

#define IPU_DI0_DW_GEN_0__ADDR                    0x1E040058
#define IPU_DI0_DW_GEN_0__EMPTY                   0x1E040058,0x00000000
#define IPU_DI0_DW_GEN_0__FULL                    0x1E040058,0xffffffff
#define IPU_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0     0x1E040058,0xFF000000
#define IPU_DI0_DW_GEN_0__DI0_START_PERIOD_0      0x1E040058,0x00FF0000
#define IPU_DI0_DW_GEN_0__DI0_CST_0               0x1E040058,0x0000C000
#define IPU_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1E040058,0x000001F0
#define IPU_DI0_DW_GEN_0__DI0_SERIAL_RS_0         0x1E040058,0x0000000C
#define IPU_DI0_DW_GEN_0__DI0_SERIAL_CLK_0        0x1E040058,0x00000003

#define IPU_DI0_DW_GEN_1__ADDR                  0x1E04005C
#define IPU_DI0_DW_GEN_1__EMPTY                 0x1E04005C,0x00000000
#define IPU_DI0_DW_GEN_1__FULL                  0x1E04005C,0xffffffff
#define IPU_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1     0x1E04005C,0xFF000000
#define IPU_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1E04005C,0x00FF0000
#define IPU_DI0_DW_GEN_1__DI0_CST_1             0x1E04005C,0x0000C000
#define IPU_DI0_DW_GEN_1__DI0_PT_6_1            0x1E04005C,0x00003000
#define IPU_DI0_DW_GEN_1__DI0_PT_5_1            0x1E04005C,0x00000C00
#define IPU_DI0_DW_GEN_1__DI0_PT_4_1            0x1E04005C,0x00000300
#define IPU_DI0_DW_GEN_1__DI0_PT_3_1            0x1E04005C,0x000000C0
#define IPU_DI0_DW_GEN_1__DI0_PT_2_1            0x1E04005C,0x00000030
#define IPU_DI0_DW_GEN_1__DI0_PT_1_1            0x1E04005C,0x0000000C
#define IPU_DI0_DW_GEN_1__DI0_PT_0_1            0x1E04005C,0x00000003

#define IPU_DI0_DW_GEN_1__ADDR                    0x1E04005C
#define IPU_DI0_DW_GEN_1__EMPTY                   0x1E04005C,0x00000000
#define IPU_DI0_DW_GEN_1__FULL                    0x1E04005C,0xffffffff
#define IPU_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1     0x1E04005C,0xFF000000
#define IPU_DI0_DW_GEN_1__DI0_START_PERIOD_1      0x1E04005C,0x00FF0000
#define IPU_DI0_DW_GEN_1__DI0_CST_1               0x1E04005C,0x0000C000
#define IPU_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1E04005C,0x000001F0
#define IPU_DI0_DW_GEN_1__DI0_SERIAL_RS_1         0x1E04005C,0x0000000C
#define IPU_DI0_DW_GEN_1__DI0_SERIAL_CLK_1        0x1E04005C,0x00000003

#define IPU_DI0_DW_GEN_2__ADDR                  0x1E040060
#define IPU_DI0_DW_GEN_2__EMPTY                 0x1E040060,0x00000000
#define IPU_DI0_DW_GEN_2__FULL                  0x1E040060,0xffffffff
#define IPU_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2     0x1E040060,0xFF000000
#define IPU_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1E040060,0x00FF0000
#define IPU_DI0_DW_GEN_2__DI0_CST_2             0x1E040060,0x0000C000
#define IPU_DI0_DW_GEN_2__DI0_PT_6_2            0x1E040060,0x00003000
#define IPU_DI0_DW_GEN_2__DI0_PT_5_2            0x1E040060,0x00000C00
#define IPU_DI0_DW_GEN_2__DI0_PT_4_2            0x1E040060,0x00000300
#define IPU_DI0_DW_GEN_2__DI0_PT_3_2            0x1E040060,0x000000C0
#define IPU_DI0_DW_GEN_2__DI0_PT_2_2            0x1E040060,0x00000030
#define IPU_DI0_DW_GEN_2__DI0_PT_1_2            0x1E040060,0x0000000C
#define IPU_DI0_DW_GEN_2__DI0_PT_0_2            0x1E040060,0x00000003

#define IPU_DI0_DW_GEN_2__ADDR                    0x1E040060
#define IPU_DI0_DW_GEN_2__EMPTY                   0x1E040060,0x00000000
#define IPU_DI0_DW_GEN_2__FULL                    0x1E040060,0xffffffff
#define IPU_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2     0x1E040060,0xFF000000
#define IPU_DI0_DW_GEN_2__DI0_START_PERIOD_2      0x1E040060,0x00FF0000
#define IPU_DI0_DW_GEN_2__DI0_CST_2               0x1E040060,0x0000C000
#define IPU_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1E040060,0x000001F0
#define IPU_DI0_DW_GEN_2__DI0_SERIAL_RS_2         0x1E040060,0x0000000C
#define IPU_DI0_DW_GEN_2__DI0_SERIAL_CLK_2        0x1E040060,0x00000003

#define IPU_DI0_DW_GEN_3__ADDR                  0x1E040064
#define IPU_DI0_DW_GEN_3__EMPTY                 0x1E040064,0x00000000
#define IPU_DI0_DW_GEN_3__FULL                  0x1E040064,0xffffffff
#define IPU_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3     0x1E040064,0xFF000000
#define IPU_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1E040064,0x00FF0000
#define IPU_DI0_DW_GEN_3__DI0_CST_3             0x1E040064,0x0000C000
#define IPU_DI0_DW_GEN_3__DI0_PT_6_3            0x1E040064,0x00003000
#define IPU_DI0_DW_GEN_3__DI0_PT_5_3            0x1E040064,0x00000C00
#define IPU_DI0_DW_GEN_3__DI0_PT_4_3            0x1E040064,0x00000300
#define IPU_DI0_DW_GEN_3__DI0_PT_3_3            0x1E040064,0x000000C0
#define IPU_DI0_DW_GEN_3__DI0_PT_2_3            0x1E040064,0x00000030
#define IPU_DI0_DW_GEN_3__DI0_PT_1_3            0x1E040064,0x0000000C
#define IPU_DI0_DW_GEN_3__DI0_PT_0_3            0x1E040064,0x00000003

#define IPU_DI0_DW_GEN_3__ADDR                    0x1E040064
#define IPU_DI0_DW_GEN_3__EMPTY                   0x1E040064,0x00000000
#define IPU_DI0_DW_GEN_3__FULL                    0x1E040064,0xffffffff
#define IPU_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3     0x1E040064,0xFF000000
#define IPU_DI0_DW_GEN_3__DI0_START_PERIOD_3      0x1E040064,0x00FF0000
#define IPU_DI0_DW_GEN_3__DI0_CST_3               0x1E040064,0x0000C000
#define IPU_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1E040064,0x000001F0
#define IPU_DI0_DW_GEN_3__DI0_SERIAL_RS_3         0x1E040064,0x0000000C
#define IPU_DI0_DW_GEN_3__DI0_SERIAL_CLK_3        0x1E040064,0x00000003

#define IPU_DI0_DW_GEN_4__ADDR                  0x1E040068
#define IPU_DI0_DW_GEN_4__EMPTY                 0x1E040068,0x00000000
#define IPU_DI0_DW_GEN_4__FULL                  0x1E040068,0xffffffff
#define IPU_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4     0x1E040068,0xFF000000
#define IPU_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1E040068,0x00FF0000
#define IPU_DI0_DW_GEN_4__DI0_CST_4             0x1E040068,0x0000C000
#define IPU_DI0_DW_GEN_4__DI0_PT_6_4            0x1E040068,0x00003000
#define IPU_DI0_DW_GEN_4__DI0_PT_5_4            0x1E040068,0x00000C00
#define IPU_DI0_DW_GEN_4__DI0_PT_4_4            0x1E040068,0x00000300
#define IPU_DI0_DW_GEN_4__DI0_PT_3_4            0x1E040068,0x000000C0
#define IPU_DI0_DW_GEN_4__DI0_PT_2_4            0x1E040068,0x00000030
#define IPU_DI0_DW_GEN_4__DI0_PT_1_4            0x1E040068,0x0000000C
#define IPU_DI0_DW_GEN_4__DI0_PT_0_4            0x1E040068,0x00000003

#define IPU_DI0_DW_GEN_4__ADDR                    0x1E040068
#define IPU_DI0_DW_GEN_4__EMPTY                   0x1E040068,0x00000000
#define IPU_DI0_DW_GEN_4__FULL                    0x1E040068,0xffffffff
#define IPU_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4     0x1E040068,0xFF000000
#define IPU_DI0_DW_GEN_4__DI0_START_PERIOD_4      0x1E040068,0x00FF0000
#define IPU_DI0_DW_GEN_4__DI0_CST_4               0x1E040068,0x0000C000
#define IPU_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1E040068,0x000001F0
#define IPU_DI0_DW_GEN_4__DI0_SERIAL_RS_4         0x1E040068,0x0000000C
#define IPU_DI0_DW_GEN_4__DI0_SERIAL_CLK_4        0x1E040068,0x00000003

#define IPU_DI0_DW_GEN_5__ADDR                  0x1E04006C
#define IPU_DI0_DW_GEN_5__EMPTY                 0x1E04006C,0x00000000
#define IPU_DI0_DW_GEN_5__FULL                  0x1E04006C,0xffffffff
#define IPU_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5     0x1E04006C,0xFF000000
#define IPU_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1E04006C,0x00FF0000
#define IPU_DI0_DW_GEN_5__DI0_CST_5             0x1E04006C,0x0000C000
#define IPU_DI0_DW_GEN_5__DI0_PT_6_5            0x1E04006C,0x00003000
#define IPU_DI0_DW_GEN_5__DI0_PT_5_5            0x1E04006C,0x00000C00
#define IPU_DI0_DW_GEN_5__DI0_PT_4_5            0x1E04006C,0x00000300
#define IPU_DI0_DW_GEN_5__DI0_PT_3_5            0x1E04006C,0x000000C0
#define IPU_DI0_DW_GEN_5__DI0_PT_2_5            0x1E04006C,0x00000030
#define IPU_DI0_DW_GEN_5__DI0_PT_1_5            0x1E04006C,0x0000000C
#define IPU_DI0_DW_GEN_5__DI0_PT_0_5            0x1E04006C,0x00000003

#define IPU_DI0_DW_GEN_5__ADDR                    0x1E04006C
#define IPU_DI0_DW_GEN_5__EMPTY                   0x1E04006C,0x00000000
#define IPU_DI0_DW_GEN_5__FULL                    0x1E04006C,0xffffffff
#define IPU_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5     0x1E04006C,0xFF000000
#define IPU_DI0_DW_GEN_5__DI0_START_PERIOD_5      0x1E04006C,0x00FF0000
#define IPU_DI0_DW_GEN_5__DI0_CST_5               0x1E04006C,0x0000C000
#define IPU_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1E04006C,0x000001F0
#define IPU_DI0_DW_GEN_5__DI0_SERIAL_RS_5         0x1E04006C,0x0000000C
#define IPU_DI0_DW_GEN_5__DI0_SERIAL_CLK_5        0x1E04006C,0x00000003

#define IPU_DI0_DW_GEN_6__ADDR                  0x1E040070
#define IPU_DI0_DW_GEN_6__EMPTY                 0x1E040070,0x00000000
#define IPU_DI0_DW_GEN_6__FULL                  0x1E040070,0xffffffff
#define IPU_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6     0x1E040070,0xFF000000
#define IPU_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1E040070,0x00FF0000
#define IPU_DI0_DW_GEN_6__DI0_CST_6             0x1E040070,0x0000C000
#define IPU_DI0_DW_GEN_6__DI0_PT_6_6            0x1E040070,0x00003000
#define IPU_DI0_DW_GEN_6__DI0_PT_5_6            0x1E040070,0x00000C00
#define IPU_DI0_DW_GEN_6__DI0_PT_4_6            0x1E040070,0x00000300
#define IPU_DI0_DW_GEN_6__DI0_PT_3_6            0x1E040070,0x000000C0
#define IPU_DI0_DW_GEN_6__DI0_PT_2_6            0x1E040070,0x00000030
#define IPU_DI0_DW_GEN_6__DI0_PT_1_6            0x1E040070,0x0000000C
#define IPU_DI0_DW_GEN_6__DI0_PT_0_6            0x1E040070,0x00000003

#define IPU_DI0_DW_GEN_6__ADDR                    0x1E040070
#define IPU_DI0_DW_GEN_6__EMPTY                   0x1E040070,0x00000000
#define IPU_DI0_DW_GEN_6__FULL                    0x1E040070,0xffffffff
#define IPU_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6     0x1E040070,0xFF000000
#define IPU_DI0_DW_GEN_6__DI0_START_PERIOD_6      0x1E040070,0x00FF0000
#define IPU_DI0_DW_GEN_6__DI0_CST_6               0x1E040070,0x0000C000
#define IPU_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1E040070,0x000001F0
#define IPU_DI0_DW_GEN_6__DI0_SERIAL_RS_6         0x1E040070,0x0000000C
#define IPU_DI0_DW_GEN_6__DI0_SERIAL_CLK_6        0x1E040070,0x00000003

#define IPU_DI0_DW_GEN_7__ADDR                  0x1E040074
#define IPU_DI0_DW_GEN_7__EMPTY                 0x1E040074,0x00000000
#define IPU_DI0_DW_GEN_7__FULL                  0x1E040074,0xffffffff
#define IPU_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7     0x1E040074,0xFF000000
#define IPU_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1E040074,0x00FF0000
#define IPU_DI0_DW_GEN_7__DI0_CST_7             0x1E040074,0x0000C000
#define IPU_DI0_DW_GEN_7__DI0_PT_6_7            0x1E040074,0x00003000
#define IPU_DI0_DW_GEN_7__DI0_PT_5_7            0x1E040074,0x00000C00
#define IPU_DI0_DW_GEN_7__DI0_PT_4_7            0x1E040074,0x00000300
#define IPU_DI0_DW_GEN_7__DI0_PT_3_7            0x1E040074,0x000000C0
#define IPU_DI0_DW_GEN_7__DI0_PT_2_7            0x1E040074,0x00000030
#define IPU_DI0_DW_GEN_7__DI0_PT_1_7            0x1E040074,0x0000000C
#define IPU_DI0_DW_GEN_7__DI0_PT_0_7            0x1E040074,0x00000003

#define IPU_DI0_DW_GEN_7__ADDR                    0x1E040074
#define IPU_DI0_DW_GEN_7__EMPTY                   0x1E040074,0x00000000
#define IPU_DI0_DW_GEN_7__FULL                    0x1E040074,0xffffffff
#define IPU_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7     0x1E040074,0xFF000000
#define IPU_DI0_DW_GEN_7__DI0_START_PERIOD_7      0x1E040074,0x00FF0000
#define IPU_DI0_DW_GEN_7__DI0_CST_7               0x1E040074,0x0000C000
#define IPU_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1E040074,0x000001F0
#define IPU_DI0_DW_GEN_7__DI0_SERIAL_RS_7         0x1E040074,0x0000000C
#define IPU_DI0_DW_GEN_7__DI0_SERIAL_CLK_7        0x1E040074,0x00000003

#define IPU_DI0_DW_GEN_8__ADDR                  0x1E040078
#define IPU_DI0_DW_GEN_8__EMPTY                 0x1E040078,0x00000000
#define IPU_DI0_DW_GEN_8__FULL                  0x1E040078,0xffffffff
#define IPU_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8     0x1E040078,0xFF000000
#define IPU_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1E040078,0x00FF0000
#define IPU_DI0_DW_GEN_8__DI0_CST_8             0x1E040078,0x0000C000
#define IPU_DI0_DW_GEN_8__DI0_PT_6_8            0x1E040078,0x00003000
#define IPU_DI0_DW_GEN_8__DI0_PT_5_8            0x1E040078,0x00000C00
#define IPU_DI0_DW_GEN_8__DI0_PT_4_8            0x1E040078,0x00000300
#define IPU_DI0_DW_GEN_8__DI0_PT_3_8            0x1E040078,0x000000C0
#define IPU_DI0_DW_GEN_8__DI0_PT_2_8            0x1E040078,0x00000030
#define IPU_DI0_DW_GEN_8__DI0_PT_1_8            0x1E040078,0x0000000C
#define IPU_DI0_DW_GEN_8__DI0_PT_0_8            0x1E040078,0x00000003

#define IPU_DI0_DW_GEN_8__ADDR                    0x1E040078
#define IPU_DI0_DW_GEN_8__EMPTY                   0x1E040078,0x00000000
#define IPU_DI0_DW_GEN_8__FULL                    0x1E040078,0xffffffff
#define IPU_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8     0x1E040078,0xFF000000
#define IPU_DI0_DW_GEN_8__DI0_START_PERIOD_8      0x1E040078,0x00FF0000
#define IPU_DI0_DW_GEN_8__DI0_CST_8               0x1E040078,0x0000C000
#define IPU_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1E040078,0x000001F0
#define IPU_DI0_DW_GEN_8__DI0_SERIAL_RS_8         0x1E040078,0x0000000C
#define IPU_DI0_DW_GEN_8__DI0_SERIAL_CLK_8        0x1E040078,0x00000003

#define IPU_DI0_DW_GEN_9__ADDR                  0x1E04007C
#define IPU_DI0_DW_GEN_9__EMPTY                 0x1E04007C,0x00000000
#define IPU_DI0_DW_GEN_9__FULL                  0x1E04007C,0xffffffff
#define IPU_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9     0x1E04007C,0xFF000000
#define IPU_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1E04007C,0x00FF0000
#define IPU_DI0_DW_GEN_9__DI0_CST_9             0x1E04007C,0x0000C000
#define IPU_DI0_DW_GEN_9__DI0_PT_6_9            0x1E04007C,0x00003000
#define IPU_DI0_DW_GEN_9__DI0_PT_5_9            0x1E04007C,0x00000C00
#define IPU_DI0_DW_GEN_9__DI0_PT_4_9            0x1E04007C,0x00000300
#define IPU_DI0_DW_GEN_9__DI0_PT_3_9            0x1E04007C,0x000000C0
#define IPU_DI0_DW_GEN_9__DI0_PT_2_9            0x1E04007C,0x00000030
#define IPU_DI0_DW_GEN_9__DI0_PT_1_9            0x1E04007C,0x0000000C
#define IPU_DI0_DW_GEN_9__DI0_PT_0_9            0x1E04007C,0x00000003

#define IPU_DI0_DW_GEN_9__ADDR                    0x1E04007C
#define IPU_DI0_DW_GEN_9__EMPTY                   0x1E04007C,0x00000000
#define IPU_DI0_DW_GEN_9__FULL                    0x1E04007C,0xffffffff
#define IPU_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9     0x1E04007C,0xFF000000
#define IPU_DI0_DW_GEN_9__DI0_START_PERIOD_9      0x1E04007C,0x00FF0000
#define IPU_DI0_DW_GEN_9__DI0_CST_9               0x1E04007C,0x0000C000
#define IPU_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1E04007C,0x000001F0
#define IPU_DI0_DW_GEN_9__DI0_SERIAL_RS_9         0x1E04007C,0x0000000C
#define IPU_DI0_DW_GEN_9__DI0_SERIAL_CLK_9        0x1E04007C,0x00000003

#define IPU_DI0_DW_GEN_10__ADDR                   0x1E040080
#define IPU_DI0_DW_GEN_10__EMPTY                  0x1E040080,0x00000000
#define IPU_DI0_DW_GEN_10__FULL                   0x1E040080,0xffffffff
#define IPU_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10     0x1E040080,0xFF000000
#define IPU_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1E040080,0x00FF0000
#define IPU_DI0_DW_GEN_10__DI0_CST_10             0x1E040080,0x0000C000
#define IPU_DI0_DW_GEN_10__DI0_PT_6_10            0x1E040080,0x00003000
#define IPU_DI0_DW_GEN_10__DI0_PT_5_10            0x1E040080,0x00000C00
#define IPU_DI0_DW_GEN_10__DI0_PT_4_10            0x1E040080,0x00000300
#define IPU_DI0_DW_GEN_10__DI0_PT_3_10            0x1E040080,0x000000C0
#define IPU_DI0_DW_GEN_10__DI0_PT_2_10            0x1E040080,0x00000030
#define IPU_DI0_DW_GEN_10__DI0_PT_1_10            0x1E040080,0x0000000C
#define IPU_DI0_DW_GEN_10__DI0_PT_0_10            0x1E040080,0x00000003

#define IPU_DI0_DW_GEN_10__ADDR                     0x1E040080
#define IPU_DI0_DW_GEN_10__EMPTY                    0x1E040080,0x00000000
#define IPU_DI0_DW_GEN_10__FULL                     0x1E040080,0xffffffff
#define IPU_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10     0x1E040080,0xFF000000
#define IPU_DI0_DW_GEN_10__DI0_START_PERIOD_10      0x1E040080,0x00FF0000
#define IPU_DI0_DW_GEN_10__DI0_CST_10               0x1E040080,0x0000C000
#define IPU_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E040080,0x000001F0
#define IPU_DI0_DW_GEN_10__DI0_SERIAL_RS_10         0x1E040080,0x0000000C
#define IPU_DI0_DW_GEN_10__DI0_SERIAL_CLK_10        0x1E040080,0x00000003

#define IPU_DI0_DW_GEN_11__ADDR                   0x1E040084
#define IPU_DI0_DW_GEN_11__EMPTY                  0x1E040084,0x00000000
#define IPU_DI0_DW_GEN_11__FULL                   0x1E040084,0xffffffff
#define IPU_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11     0x1E040084,0xFF000000
#define IPU_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1E040084,0x00FF0000
#define IPU_DI0_DW_GEN_11__DI0_CST_11             0x1E040084,0x0000C000
#define IPU_DI0_DW_GEN_11__DI0_PT_6_11            0x1E040084,0x00003000
#define IPU_DI0_DW_GEN_11__DI0_PT_5_11            0x1E040084,0x00000C00
#define IPU_DI0_DW_GEN_11__DI0_PT_4_11            0x1E040084,0x00000300
#define IPU_DI0_DW_GEN_11__DI0_PT_3_11            0x1E040084,0x000000C0
#define IPU_DI0_DW_GEN_11__DI0_PT_2_11            0x1E040084,0x00000030
#define IPU_DI0_DW_GEN_11__DI0_PT_1_11            0x1E040084,0x0000000C
#define IPU_DI0_DW_GEN_11__DI0_PT_0_11            0x1E040084,0x00000003

#define IPU_DI0_DW_GEN_11__ADDR                     0x1E040084
#define IPU_DI0_DW_GEN_11__EMPTY                    0x1E040084,0x00000000
#define IPU_DI0_DW_GEN_11__FULL                     0x1E040084,0xffffffff
#define IPU_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11     0x1E040084,0xFF000000
#define IPU_DI0_DW_GEN_11__DI0_START_PERIOD_11      0x1E040084,0x00FF0000
#define IPU_DI0_DW_GEN_11__DI0_CST_11               0x1E040084,0x0000C000
#define IPU_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E040084,0x000001F0
#define IPU_DI0_DW_GEN_11__DI0_SERIAL_RS_11         0x1E040084,0x0000000C
#define IPU_DI0_DW_GEN_11__DI0_SERIAL_CLK_11        0x1E040084,0x00000003

#define IPU_DI_DW_OFFSET                                                                0x0088
#define DI_WAVESET_ADDR(di, pointer, set)               (IPU_DI0_GENERAL__ADDR + \
                                                                                                                                                                di*0x8000 + IPU_DI_DW_OFFSET + \
                                                                                                                                                                pointer*0x4 + set * 0x30)
#define DI_WAVESET_UP(di, pointer, set)                         DI_WAVESET_ADDR(di, pointer, set), 0x000001FF
#define DI_WAVESET_DOWN(di, pointer, set)       DI_WAVESET_ADDR(di, pointer, set), 0x01FF0000

#define IPU_DI_STEP_RPT_OFFSET                                  0x0148
#define DI_STEP_RPT_ADDR(di, pointer)                   (IPU_DI0_GENERAL__ADDR + \
                                                                                                                                                                di*0x8000 + IPU_DI_STEP_RPT_OFFSET + \
                                                                                                                                                                ((pointer-1) / 2)*0x4 )
#define DI_STEP_RPT(di, pointer)                                                DI_STEP_RPT_ADDR(di, pointer), 0x0FFF<<((pointer-1)%2)*16

#define IPU_DI0_STP_REP_9__ADDR              0x1E040158
#define IPU_DI0_STP_REP_9__EMPTY             0x1E040158,0x00000000
#define IPU_DI0_STP_REP_9__FULL              0x1E040158,0xffffffff
#define IPU_DI0_STP_REP_9__DI0_STEP_REPEAT_9 0x1E040158,0x00000FFF

#define IPU_DI0_SER_CONF__ADDR                       0x1E04015C
#define IPU_DI0_SER_CONF__EMPTY                      0x1E04015C,0x00000000
#define IPU_DI0_SER_CONF__FULL                       0x1E04015C,0xffffffff
#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1 0x1E04015C,0xF0000000
#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0 0x1E04015C,0x0F000000
#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1 0x1E04015C,0x00F00000
#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0 0x1E04015C,0x000F0000
#define IPU_DI0_SER_CONF__DI0_SERIAL_LATCH           0x1E04015C,0x0000FF00
#define IPU_DI0_SER_CONF__DI0_LLA_SER_ACCESS         0x1E04015C,0x00000020
#define IPU_DI0_SER_CONF__DI0_SER_CLK_POLARITY       0x1E04015C,0x00000010
#define IPU_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY   0x1E04015C,0x00000008
#define IPU_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY     0x1E04015C,0x00000004
#define IPU_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY     0x1E04015C,0x00000002
#define IPU_DI0_SER_CONF__DI0_WAIT4SERIAL            0x1E04015C,0x00000001

#define IPU_DI0_SSC__ADDR              0x1E040160
#define IPU_DI0_SSC__EMPTY             0x1E040160,0x00000000
#define IPU_DI0_SSC__FULL              0x1E040160,0xffffffff
#define IPU_DI0_SSC__DI0_PIN17_ERM     0x1E040160,0x00800000
#define IPU_DI0_SSC__DI0_PIN16_ERM     0x1E040160,0x00400000
#define IPU_DI0_SSC__DI0_PIN15_ERM     0x1E040160,0x00200000
#define IPU_DI0_SSC__DI0_PIN14_ERM     0x1E040160,0x00100000
#define IPU_DI0_SSC__DI0_PIN13_ERM     0x1E040160,0x00080000
#define IPU_DI0_SSC__DI0_PIN12_ERM     0x1E040160,0x00040000
#define IPU_DI0_SSC__DI0_PIN11_ERM     0x1E040160,0x00020000
#define IPU_DI0_SSC__DI0_CS_ERM        0x1E040160,0x00010000
#define IPU_DI0_SSC__DI0_WAIT_ON       0x1E040160,0x00000020
#define IPU_DI0_SSC__DI0_BYTE_EN_RD_IN 0x1E040160,0x00000008
#define IPU_DI0_SSC__DI0_BYTE_EN_PNTR  0x1E040160,0x00000007

#define IPU_DI0_POL__ADDR                     0x1E040164
#define IPU_DI0_POL__EMPTY                    0x1E040164,0x00000000
#define IPU_DI0_POL__FULL                     0x1E040164,0xffffffff
#define IPU_DI0_POL__DI0_WAIT_POLARITY        0x1E040164,0x04000000
#define IPU_DI0_POL__DI0_CS1_BYTE_EN_POLARITY 0x1E040164,0x02000000
#define IPU_DI0_POL__DI0_CS0_BYTE_EN_POLARITY 0x1E040164,0x01000000
#define IPU_DI0_POL__DI0_CS1_DATA_POLARITY    0x1E040164,0x00800000
#define IPU_DI0_POL__DI0_CS1_POLARITY_17      0x1E040164,0x00400000
#define IPU_DI0_POL__DI0_CS1_POLARITY_16      0x1E040164,0x00200000
#define IPU_DI0_POL__DI0_CS1_POLARITY_15      0x1E040164,0x00100000
#define IPU_DI0_POL__DI0_CS1_POLARITY_14      0x1E040164,0x00080000
#define IPU_DI0_POL__DI0_CS1_POLARITY_13      0x1E040164,0x00040000
#define IPU_DI0_POL__DI0_CS1_POLARITY_12      0x1E040164,0x00020000
#define IPU_DI0_POL__DI0_CS1_POLARITY_11      0x1E040164,0x00010000
#define IPU_DI0_POL__DI0_CS0_DATA_POLARITY    0x1E040164,0x00008000
#define IPU_DI0_POL__DI0_CS0_POLARITY_17      0x1E040164,0x00004000
#define IPU_DI0_POL__DI0_CS0_POLARITY_16      0x1E040164,0x00002000
#define IPU_DI0_POL__DI0_CS0_POLARITY_15      0x1E040164,0x00001000
#define IPU_DI0_POL__DI0_CS0_POLARITY_14      0x1E040164,0x00000800
#define IPU_DI0_POL__DI0_CS0_POLARITY_13      0x1E040164,0x00000400
#define IPU_DI0_POL__DI0_CS0_POLARITY_12      0x1E040164,0x00000200
#define IPU_DI0_POL__DI0_CS0_POLARITY_11      0x1E040164,0x00000100
#define IPU_DI0_POL__DI0_DRDY_DATA_POLARITY   0x1E040164,0x00000080
#define IPU_DI0_POL__DI0_DRDY_POLARITY_17     0x1E040164,0x00000040
#define IPU_DI0_POL__DI0_DRDY_POLARITY_16     0x1E040164,0x00000020
#define IPU_DI0_POL__DI0_DRDY_POLARITY_15     0x1E040164,0x00000010
#define IPU_DI0_POL__DI0_DRDY_POLARITY_14     0x1E040164,0x00000008
#define IPU_DI0_POL__DI0_DRDY_POLARITY_13     0x1E040164,0x00000004
#define IPU_DI0_POL__DI0_DRDY_POLARITY_12     0x1E040164,0x00000002
#define IPU_DI0_POL__DI0_DRDY_POLARITY_11     0x1E040164,0x00000001

#define IPU_DI0_AW0__ADDR              0x1E040168
#define IPU_DI0_AW0__EMPTY             0x1E040168,0x00000000
#define IPU_DI0_AW0__FULL              0x1E040168,0xffffffff
#define IPU_DI0_AW0__DI0_AW_TRIG_SEL   0x1E040168,0xF0000000
#define IPU_DI0_AW0__DI0_AW_HEND       0x1E040168,0x0FFF0000
#define IPU_DI0_AW0__DI0_AW_HCOUNT_SEL 0x1E040168,0x0000F000
#define IPU_DI0_AW0__DI0_AW_HSTART     0x1E040168,0x00000FFF

#define IPU_DI0_AW1__ADDR              0x1E04016C
#define IPU_DI0_AW1__EMPTY             0x1E04016C,0x00000000
#define IPU_DI0_AW1__FULL              0x1E04016C,0xffffffff
#define IPU_DI0_AW1__DI0_AW_VEND       0x1E04016C,0x0FFF0000
#define IPU_DI0_AW1__DI0_AW_VCOUNT_SEL 0x1E04016C,0x0000F000
#define IPU_DI0_AW1__DI0_AW_VSTART     0x1E04016C,0x00000FFF

#define IPU_DI0_SCR_CONF__ADDR              0x1E040170
#define IPU_DI0_SCR_CONF__EMPTY             0x1E040170,0x00000000
#define IPU_DI0_SCR_CONF__FULL              0x1E040170,0xffffffff
#define IPU_DI0_SCR_CONF__DI0_SCREEN_HEIGHT 0x1E040170,0x00000FFF

#define IPU_DI0_STAT__ADDR                0x1E040174
#define IPU_DI0_STAT__EMPTY               0x1E040174,0x00000000
#define IPU_DI0_STAT__FULL                0x1E040174,0xffffffff
#define IPU_DI0_STAT__DI0_CNTR_FIFO_FULL  0x1E040174,0x00000008
#define IPU_DI0_STAT__DI0_CNTR_FIFO_EMPTY 0x1E040174,0x00000004
#define IPU_DI0_STAT__DI0_READ_FIFO_FULL  0x1E040174,0x00000002
#define IPU_DI0_STAT__DI0_READ_FIFO_EMPTY 0x1E040174,0x00000001

#define IPU_DI1_GENERAL__ADDR                  0x1E048000
#define IPU_DI1_GENERAL__EMPTY                 0x1E048000,0x00000000
#define IPU_DI1_GENERAL__FULL                  0x1E048000,0xffffffff
#define IPU_DI1_GENERAL__DI1_DISP_Y_SEL        0x1E048000,0x70000000
#define IPU_DI1_GENERAL__DI1_CLOCK_STOP_MODE   0x1E048000,0x0F000000
#define IPU_DI1_GENERAL__DI1_DISP_CLOCK_INIT   0x1E048000,0x00800000
#define IPU_DI1_GENERAL__DI1_MASK_SEL          0x1E048000,0x00400000
#define IPU_DI1_GENERAL__DI1_VSYNC_EXT         0x1E048000,0x00200000
#define IPU_DI1_GENERAL__DI1_CLK_EXT           0x1E048000,0x00100000
#define IPU_DI1_GENERAL__DI1_WATCHDOG_MODE     0x1E048000,0x000C0000
#define IPU_DI1_GENERAL__DI1_POLARITY_DISP_CLK 0x1E048000,0x00020000
#define IPU_DI1_GENERAL__DI1_SYNC_COUNT_SEL    0x1E048000,0x0000F000
#define IPU_DI1_GENERAL__DI1_ERR_TREATMENT     0x1E048000,0x00000800
#define IPU_DI1_GENERAL__DI1_ERM_VSYNC_SEL     0x1E048000,0x00000400
#define IPU_DI1_GENERAL__DI1_POLARITY_CS1      0x1E048000,0x00000200
#define IPU_DI1_GENERAL__DI1_POLARITY_CS0      0x1E048000,0x00000100
#define IPU_DI1_GENERAL__DI1_POLARITY_8        0x1E048000,0x00000080
#define IPU_DI1_GENERAL__DI1_POLARITY_7        0x1E048000,0x00000040
#define IPU_DI1_GENERAL__DI1_POLARITY_6        0x1E048000,0x00000020
#define IPU_DI1_GENERAL__DI1_POLARITY_5        0x1E048000,0x00000010
#define IPU_DI1_GENERAL__DI1_POLARITY_4        0x1E048000,0x00000008
#define IPU_DI1_GENERAL__DI1_POLARITY_3        0x1E048000,0x00000004
#define IPU_DI1_GENERAL__DI1_POLARITY_2        0x1E048000,0x00000002
#define IPU_DI1_GENERAL__DI1_POLARITY_1        0x1E048000,0x00000001

#define IPU_DI1_BS_CLKGEN0__ADDR                0x1E048004
#define IPU_DI1_BS_CLKGEN0__EMPTY               0x1E048004,0x00000000
#define IPU_DI1_BS_CLKGEN0__FULL                0x1E048004,0xffffffff
#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET 0x1E048004,0x01FF0000
#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD 0x1E048004,0x00000FFF

#define IPU_DI1_BS_CLKGEN1__ADDR              0x1E048008
#define IPU_DI1_BS_CLKGEN1__EMPTY             0x1E048008,0x00000000
#define IPU_DI1_BS_CLKGEN1__FULL              0x1E048008,0xffffffff
#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN 0x1E048008,0x01FF0000
#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP   0x1E048008,0x000001FF

#define IPU_DI1_SW_GEN0_9__ADDR                    0x1E04802C
#define IPU_DI1_SW_GEN0_9__EMPTY                   0x1E04802C,0x00000000
#define IPU_DI1_SW_GEN0_9__FULL                    0x1E04802C,0xffffffff
#define IPU_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9      0x1E04802C,0x7FF80000
#define IPU_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9    0x1E04802C,0x00070000
#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9      0x1E04802C,0x00007FF8
#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9 0x1E04802C,0x00000007

#define IPU_DI1_SW_GEN1_9__ADDR                  0x1E048050
#define IPU_DI1_SW_GEN1_9__EMPTY                 0x1E048050,0x00000000
#define IPU_DI1_SW_GEN1_9__FULL                  0x1E048050,0xffffffff
#define IPU_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9     0x1E048050,0xE0000000
#define IPU_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9 0x1E048050,0x10000000
#define IPU_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9     0x1E048050,0x0E000000
#define IPU_DI1_SW_GEN1_9__DI1_CNT_DOWN_9        0x1E048050,0x01FF0000
#define IPU_DI1_SW_GEN1_9__DI1_TAG_SEL_9         0x1E048050,0x00008000
#define IPU_DI1_SW_GEN1_9__DI1_CNT_UP_9          0x1E048050,0x000001FF

#define IPU_DI1_SYNC_AS_GEN__ADDR              0x1E048054
#define IPU_DI1_SYNC_AS_GEN__EMPTY             0x1E048054,0x00000000
#define IPU_DI1_SYNC_AS_GEN__FULL              0x1E048054,0xffffffff
#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN 0x1E048054,0x10000000
#define IPU_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL     0x1E048054,0x0000E000
#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START    0x1E048054,0x00000FFF

#define IPU_DI1_DW_GEN_0__ADDR                  0x1E048058
#define IPU_DI1_DW_GEN_0__EMPTY                 0x1E048058,0x00000000
#define IPU_DI1_DW_GEN_0__FULL                  0x1E048058,0xffffffff
#define IPU_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0     0x1E048058,0xFF000000
#define IPU_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1E048058,0x00FF0000
#define IPU_DI1_DW_GEN_0__DI1_CST_0             0x1E048058,0x0000C000
#define IPU_DI1_DW_GEN_0__DI1_PT_6_0            0x1E048058,0x00003000
#define IPU_DI1_DW_GEN_0__DI1_PT_5_0            0x1E048058,0x00000C00
#define IPU_DI1_DW_GEN_0__DI1_PT_4_0            0x1E048058,0x00000300
#define IPU_DI1_DW_GEN_0__DI1_PT_3_0            0x1E048058,0x000000C0
#define IPU_DI1_DW_GEN_0__DI1_PT_2_0            0x1E048058,0x00000030
#define IPU_DI1_DW_GEN_0__DI1_PT_1_0            0x1E048058,0x0000000C
#define IPU_DI1_DW_GEN_0__DI1_PT_0_0            0x1E048058,0x00000003

#define IPU_DI1_DW_GEN_0__ADDR                    0x1E048058
#define IPU_DI1_DW_GEN_0__EMPTY                   0x1E048058,0x00000000
#define IPU_DI1_DW_GEN_0__FULL                    0x1E048058,0xffffffff
#define IPU_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0     0x1E048058,0xFF000000
#define IPU_DI1_DW_GEN_0__DI1_START_PERIOD_0      0x1E048058,0x00FF0000
#define IPU_DI1_DW_GEN_0__DI1_CST_0               0x1E048058,0x0000C000
#define IPU_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1E048058,0x000001F0
#define IPU_DI1_DW_GEN_0__DI1_SERIAL_RS_0         0x1E048058,0x0000000C
#define IPU_DI1_DW_GEN_0__DI1_SERIAL_CLK_0        0x1E048058,0x00000003

#define IPU_DI1_DW_GEN_1__ADDR                  0x1E04805C
#define IPU_DI1_DW_GEN_1__EMPTY                 0x1E04805C,0x00000000
#define IPU_DI1_DW_GEN_1__FULL                  0x1E04805C,0xffffffff
#define IPU_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1     0x1E04805C,0xFF000000
#define IPU_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1E04805C,0x00FF0000
#define IPU_DI1_DW_GEN_1__DI1_CST_1             0x1E04805C,0x0000C000
#define IPU_DI1_DW_GEN_1__DI1_PT_6_1            0x1E04805C,0x00003000
#define IPU_DI1_DW_GEN_1__DI1_PT_5_1            0x1E04805C,0x00000C00
#define IPU_DI1_DW_GEN_1__DI1_PT_4_1            0x1E04805C,0x00000300
#define IPU_DI1_DW_GEN_1__DI1_PT_3_1            0x1E04805C,0x000000C0
#define IPU_DI1_DW_GEN_1__DI1_PT_2_1            0x1E04805C,0x00000030
#define IPU_DI1_DW_GEN_1__DI1_PT_1_1            0x1E04805C,0x0000000C
#define IPU_DI1_DW_GEN_1__DI1_PT_0_1            0x1E04805C,0x00000003

#define IPU_DI1_DW_GEN_1__ADDR                    0x1E04805C
#define IPU_DI1_DW_GEN_1__EMPTY                   0x1E04805C,0x00000000
#define IPU_DI1_DW_GEN_1__FULL                    0x1E04805C,0xffffffff
#define IPU_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1     0x1E04805C,0xFF000000
#define IPU_DI1_DW_GEN_1__DI1_START_PERIOD_1      0x1E04805C,0x00FF0000
#define IPU_DI1_DW_GEN_1__DI1_CST_1               0x1E04805C,0x0000C000
#define IPU_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1E04805C,0x000001F0
#define IPU_DI1_DW_GEN_1__DI1_SERIAL_RS_1         0x1E04805C,0x0000000C
#define IPU_DI1_DW_GEN_1__DI1_SERIAL_CLK_1        0x1E04805C,0x00000003

#define IPU_DI1_DW_GEN_2__ADDR                  0x1E048060
#define IPU_DI1_DW_GEN_2__EMPTY                 0x1E048060,0x00000000
#define IPU_DI1_DW_GEN_2__FULL                  0x1E048060,0xffffffff
#define IPU_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2     0x1E048060,0xFF000000
#define IPU_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1E048060,0x00FF0000
#define IPU_DI1_DW_GEN_2__DI1_CST_2             0x1E048060,0x0000C000
#define IPU_DI1_DW_GEN_2__DI1_PT_6_2            0x1E048060,0x00003000
#define IPU_DI1_DW_GEN_2__DI1_PT_5_2            0x1E048060,0x00000C00
#define IPU_DI1_DW_GEN_2__DI1_PT_4_2            0x1E048060,0x00000300
#define IPU_DI1_DW_GEN_2__DI1_PT_3_2            0x1E048060,0x000000C0
#define IPU_DI1_DW_GEN_2__DI1_PT_2_2            0x1E048060,0x00000030
#define IPU_DI1_DW_GEN_2__DI1_PT_1_2            0x1E048060,0x0000000C
#define IPU_DI1_DW_GEN_2__DI1_PT_0_2            0x1E048060,0x00000003

#define IPU_DI1_DW_GEN_2__ADDR                    0x1E048060
#define IPU_DI1_DW_GEN_2__EMPTY                   0x1E048060,0x00000000
#define IPU_DI1_DW_GEN_2__FULL                    0x1E048060,0xffffffff
#define IPU_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2     0x1E048060,0xFF000000
#define IPU_DI1_DW_GEN_2__DI1_START_PERIOD_2      0x1E048060,0x00FF0000
#define IPU_DI1_DW_GEN_2__DI1_CST_2               0x1E048060,0x0000C000
#define IPU_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1E048060,0x000001F0
#define IPU_DI1_DW_GEN_2__DI1_SERIAL_RS_2         0x1E048060,0x0000000C
#define IPU_DI1_DW_GEN_2__DI1_SERIAL_CLK_2        0x1E048060,0x00000003

#define IPU_DI1_DW_GEN_3__ADDR                  0x1E048064
#define IPU_DI1_DW_GEN_3__EMPTY                 0x1E048064,0x00000000
#define IPU_DI1_DW_GEN_3__FULL                  0x1E048064,0xffffffff
#define IPU_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3     0x1E048064,0xFF000000
#define IPU_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1E048064,0x00FF0000
#define IPU_DI1_DW_GEN_3__DI1_CST_3             0x1E048064,0x0000C000
#define IPU_DI1_DW_GEN_3__DI1_PT_6_3            0x1E048064,0x00003000
#define IPU_DI1_DW_GEN_3__DI1_PT_5_3            0x1E048064,0x00000C00
#define IPU_DI1_DW_GEN_3__DI1_PT_4_3            0x1E048064,0x00000300
#define IPU_DI1_DW_GEN_3__DI1_PT_3_3            0x1E048064,0x000000C0
#define IPU_DI1_DW_GEN_3__DI1_PT_2_3            0x1E048064,0x00000030
#define IPU_DI1_DW_GEN_3__DI1_PT_1_3            0x1E048064,0x0000000C
#define IPU_DI1_DW_GEN_3__DI1_PT_0_3            0x1E048064,0x00000003

#define IPU_DI1_DW_GEN_3__ADDR                    0x1E048064
#define IPU_DI1_DW_GEN_3__EMPTY                   0x1E048064,0x00000000
#define IPU_DI1_DW_GEN_3__FULL                    0x1E048064,0xffffffff
#define IPU_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3     0x1E048064,0xFF000000
#define IPU_DI1_DW_GEN_3__DI1_START_PERIOD_3      0x1E048064,0x00FF0000
#define IPU_DI1_DW_GEN_3__DI1_CST_3               0x1E048064,0x0000C000
#define IPU_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1E048064,0x000001F0
#define IPU_DI1_DW_GEN_3__DI1_SERIAL_RS_3         0x1E048064,0x0000000C
#define IPU_DI1_DW_GEN_3__DI1_SERIAL_CLK_3        0x1E048064,0x00000003

#define IPU_DI1_DW_GEN_4__ADDR                  0x1E048068
#define IPU_DI1_DW_GEN_4__EMPTY                 0x1E048068,0x00000000
#define IPU_DI1_DW_GEN_4__FULL                  0x1E048068,0xffffffff
#define IPU_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4     0x1E048068,0xFF000000
#define IPU_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1E048068,0x00FF0000
#define IPU_DI1_DW_GEN_4__DI1_CST_4             0x1E048068,0x0000C000
#define IPU_DI1_DW_GEN_4__DI1_PT_6_4            0x1E048068,0x00003000
#define IPU_DI1_DW_GEN_4__DI1_PT_5_4            0x1E048068,0x00000C00
#define IPU_DI1_DW_GEN_4__DI1_PT_4_4            0x1E048068,0x00000300
#define IPU_DI1_DW_GEN_4__DI1_PT_3_4            0x1E048068,0x000000C0
#define IPU_DI1_DW_GEN_4__DI1_PT_2_4            0x1E048068,0x00000030
#define IPU_DI1_DW_GEN_4__DI1_PT_1_4            0x1E048068,0x0000000C
#define IPU_DI1_DW_GEN_4__DI1_PT_0_4            0x1E048068,0x00000003

#define IPU_DI1_DW_GEN_4__ADDR                    0x1E048068
#define IPU_DI1_DW_GEN_4__EMPTY                   0x1E048068,0x00000000
#define IPU_DI1_DW_GEN_4__FULL                    0x1E048068,0xffffffff
#define IPU_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4     0x1E048068,0xFF000000
#define IPU_DI1_DW_GEN_4__DI1_START_PERIOD_4      0x1E048068,0x00FF0000
#define IPU_DI1_DW_GEN_4__DI1_CST_4               0x1E048068,0x0000C000
#define IPU_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1E048068,0x000001F0
#define IPU_DI1_DW_GEN_4__DI1_SERIAL_RS_4         0x1E048068,0x0000000C
#define IPU_DI1_DW_GEN_4__DI1_SERIAL_CLK_4        0x1E048068,0x00000003

#define IPU_DI1_DW_GEN_5__ADDR                  0x1E04806C
#define IPU_DI1_DW_GEN_5__EMPTY                 0x1E04806C,0x00000000
#define IPU_DI1_DW_GEN_5__FULL                  0x1E04806C,0xffffffff
#define IPU_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5     0x1E04806C,0xFF000000
#define IPU_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1E04806C,0x00FF0000
#define IPU_DI1_DW_GEN_5__DI1_CST_5             0x1E04806C,0x0000C000
#define IPU_DI1_DW_GEN_5__DI1_PT_6_5            0x1E04806C,0x00003000
#define IPU_DI1_DW_GEN_5__DI1_PT_5_5            0x1E04806C,0x00000C00
#define IPU_DI1_DW_GEN_5__DI1_PT_4_5            0x1E04806C,0x00000300
#define IPU_DI1_DW_GEN_5__DI1_PT_3_5            0x1E04806C,0x000000C0
#define IPU_DI1_DW_GEN_5__DI1_PT_2_5            0x1E04806C,0x00000030
#define IPU_DI1_DW_GEN_5__DI1_PT_1_5            0x1E04806C,0x0000000C
#define IPU_DI1_DW_GEN_5__DI1_PT_0_5            0x1E04806C,0x00000003

#define IPU_DI1_DW_GEN_5__ADDR                    0x1E04806C
#define IPU_DI1_DW_GEN_5__EMPTY                   0x1E04806C,0x00000000
#define IPU_DI1_DW_GEN_5__FULL                    0x1E04806C,0xffffffff
#define IPU_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5     0x1E04806C,0xFF000000
#define IPU_DI1_DW_GEN_5__DI1_START_PERIOD_5      0x1E04806C,0x00FF0000
#define IPU_DI1_DW_GEN_5__DI1_CST_5               0x1E04806C,0x0000C000
#define IPU_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1E04806C,0x000001F0
#define IPU_DI1_DW_GEN_5__DI1_SERIAL_RS_5         0x1E04806C,0x0000000C
#define IPU_DI1_DW_GEN_5__DI1_SERIAL_CLK_5        0x1E04806C,0x00000003

#define IPU_DI1_DW_GEN_6__ADDR                  0x1E048070
#define IPU_DI1_DW_GEN_6__EMPTY                 0x1E048070,0x00000000
#define IPU_DI1_DW_GEN_6__FULL                  0x1E048070,0xffffffff
#define IPU_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6     0x1E048070,0xFF000000
#define IPU_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1E048070,0x00FF0000
#define IPU_DI1_DW_GEN_6__DI1_CST_6             0x1E048070,0x0000C000
#define IPU_DI1_DW_GEN_6__DI1_PT_6_6            0x1E048070,0x00003000
#define IPU_DI1_DW_GEN_6__DI1_PT_5_6            0x1E048070,0x00000C00
#define IPU_DI1_DW_GEN_6__DI1_PT_4_6            0x1E048070,0x00000300
#define IPU_DI1_DW_GEN_6__DI1_PT_3_6            0x1E048070,0x000000C0
#define IPU_DI1_DW_GEN_6__DI1_PT_2_6            0x1E048070,0x00000030
#define IPU_DI1_DW_GEN_6__DI1_PT_1_6            0x1E048070,0x0000000C
#define IPU_DI1_DW_GEN_6__DI1_PT_0_6            0x1E048070,0x00000003

#define IPU_DI1_DW_GEN_6__ADDR                    0x1E048070
#define IPU_DI1_DW_GEN_6__EMPTY                   0x1E048070,0x00000000
#define IPU_DI1_DW_GEN_6__FULL                    0x1E048070,0xffffffff
#define IPU_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6     0x1E048070,0xFF000000
#define IPU_DI1_DW_GEN_6__DI1_START_PERIOD_6      0x1E048070,0x00FF0000
#define IPU_DI1_DW_GEN_6__DI1_CST_6               0x1E048070,0x0000C000
#define IPU_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1E048070,0x000001F0
#define IPU_DI1_DW_GEN_6__DI1_SERIAL_RS_6         0x1E048070,0x0000000C
#define IPU_DI1_DW_GEN_6__DI1_SERIAL_CLK_6        0x1E048070,0x00000003

#define IPU_DI1_DW_GEN_7__ADDR                  0x1E048074
#define IPU_DI1_DW_GEN_7__EMPTY                 0x1E048074,0x00000000
#define IPU_DI1_DW_GEN_7__FULL                  0x1E048074,0xffffffff
#define IPU_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7     0x1E048074,0xFF000000
#define IPU_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1E048074,0x00FF0000
#define IPU_DI1_DW_GEN_7__DI1_CST_7             0x1E048074,0x0000C000
#define IPU_DI1_DW_GEN_7__DI1_PT_6_7            0x1E048074,0x00003000
#define IPU_DI1_DW_GEN_7__DI1_PT_5_7            0x1E048074,0x00000C00
#define IPU_DI1_DW_GEN_7__DI1_PT_4_7            0x1E048074,0x00000300
#define IPU_DI1_DW_GEN_7__DI1_PT_3_7            0x1E048074,0x000000C0
#define IPU_DI1_DW_GEN_7__DI1_PT_2_7            0x1E048074,0x00000030
#define IPU_DI1_DW_GEN_7__DI1_PT_1_7            0x1E048074,0x0000000C
#define IPU_DI1_DW_GEN_7__DI1_PT_0_7            0x1E048074,0x00000003

#define IPU_DI1_DW_GEN_7__ADDR                    0x1E048074
#define IPU_DI1_DW_GEN_7__EMPTY                   0x1E048074,0x00000000
#define IPU_DI1_DW_GEN_7__FULL                    0x1E048074,0xffffffff
#define IPU_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7     0x1E048074,0xFF000000
#define IPU_DI1_DW_GEN_7__DI1_START_PERIOD_7      0x1E048074,0x00FF0000
#define IPU_DI1_DW_GEN_7__DI1_CST_7               0x1E048074,0x0000C000
#define IPU_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1E048074,0x000001F0
#define IPU_DI1_DW_GEN_7__DI1_SERIAL_RS_7         0x1E048074,0x0000000C
#define IPU_DI1_DW_GEN_7__DI1_SERIAL_CLK_7        0x1E048074,0x00000003

#define IPU_DI1_DW_GEN_8__ADDR                  0x1E048078
#define IPU_DI1_DW_GEN_8__EMPTY                 0x1E048078,0x00000000
#define IPU_DI1_DW_GEN_8__FULL                  0x1E048078,0xffffffff
#define IPU_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8     0x1E048078,0xFF000000
#define IPU_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1E048078,0x00FF0000
#define IPU_DI1_DW_GEN_8__DI1_CST_8             0x1E048078,0x0000C000
#define IPU_DI1_DW_GEN_8__DI1_PT_6_8            0x1E048078,0x00003000
#define IPU_DI1_DW_GEN_8__DI1_PT_5_8            0x1E048078,0x00000C00
#define IPU_DI1_DW_GEN_8__DI1_PT_4_8            0x1E048078,0x00000300
#define IPU_DI1_DW_GEN_8__DI1_PT_3_8            0x1E048078,0x000000C0
#define IPU_DI1_DW_GEN_8__DI1_PT_2_8            0x1E048078,0x00000030
#define IPU_DI1_DW_GEN_8__DI1_PT_1_8            0x1E048078,0x0000000C
#define IPU_DI1_DW_GEN_8__DI1_PT_0_8            0x1E048078,0x00000003

#define IPU_DI1_DW_GEN_8__ADDR                    0x1E048078
#define IPU_DI1_DW_GEN_8__EMPTY                   0x1E048078,0x00000000
#define IPU_DI1_DW_GEN_8__FULL                    0x1E048078,0xffffffff
#define IPU_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8     0x1E048078,0xFF000000
#define IPU_DI1_DW_GEN_8__DI1_START_PERIOD_8      0x1E048078,0x00FF0000
#define IPU_DI1_DW_GEN_8__DI1_CST_8               0x1E048078,0x0000C000
#define IPU_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1E048078,0x000001F0
#define IPU_DI1_DW_GEN_8__DI1_SERIAL_RS_8         0x1E048078,0x0000000C
#define IPU_DI1_DW_GEN_8__DI1_SERIAL_CLK_8        0x1E048078,0x00000003

#define IPU_DI1_DW_GEN_9__ADDR                  0x1E04807C
#define IPU_DI1_DW_GEN_9__EMPTY                 0x1E04807C,0x00000000
#define IPU_DI1_DW_GEN_9__FULL                  0x1E04807C,0xffffffff
#define IPU_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9     0x1E04807C,0xFF000000
#define IPU_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1E04807C,0x00FF0000
#define IPU_DI1_DW_GEN_9__DI1_CST_9             0x1E04807C,0x0000C000
#define IPU_DI1_DW_GEN_9__DI1_PT_6_9            0x1E04807C,0x00003000
#define IPU_DI1_DW_GEN_9__DI1_PT_5_9            0x1E04807C,0x00000C00
#define IPU_DI1_DW_GEN_9__DI1_PT_4_9            0x1E04807C,0x00000300
#define IPU_DI1_DW_GEN_9__DI1_PT_3_9            0x1E04807C,0x000000C0
#define IPU_DI1_DW_GEN_9__DI1_PT_2_9            0x1E04807C,0x00000030
#define IPU_DI1_DW_GEN_9__DI1_PT_1_9            0x1E04807C,0x0000000C
#define IPU_DI1_DW_GEN_9__DI1_PT_0_9            0x1E04807C,0x00000003

#define IPU_DI1_DW_GEN_9__ADDR                    0x1E04807C
#define IPU_DI1_DW_GEN_9__EMPTY                   0x1E04807C,0x00000000
#define IPU_DI1_DW_GEN_9__FULL                    0x1E04807C,0xffffffff
#define IPU_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9     0x1E04807C,0xFF000000
#define IPU_DI1_DW_GEN_9__DI1_START_PERIOD_9      0x1E04807C,0x00FF0000
#define IPU_DI1_DW_GEN_9__DI1_CST_9               0x1E04807C,0x0000C000
#define IPU_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1E04807C,0x000001F0
#define IPU_DI1_DW_GEN_9__DI1_SERIAL_RS_9         0x1E04807C,0x0000000C
#define IPU_DI1_DW_GEN_9__DI1_SERIAL_CLK_9        0x1E04807C,0x00000003

#define IPU_DI1_DW_GEN_10__ADDR                   0x1E048080
#define IPU_DI1_DW_GEN_10__EMPTY                  0x1E048080,0x00000000
#define IPU_DI1_DW_GEN_10__FULL                   0x1E048080,0xffffffff
#define IPU_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10     0x1E048080,0xFF000000
#define IPU_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1E048080,0x00FF0000
#define IPU_DI1_DW_GEN_10__DI1_CST_10             0x1E048080,0x0000C000
#define IPU_DI1_DW_GEN_10__DI1_PT_6_10            0x1E048080,0x00003000
#define IPU_DI1_DW_GEN_10__DI1_PT_5_10            0x1E048080,0x00000C00
#define IPU_DI1_DW_GEN_10__DI1_PT_4_10            0x1E048080,0x00000300
#define IPU_DI1_DW_GEN_10__DI1_PT_3_10            0x1E048080,0x000000C0
#define IPU_DI1_DW_GEN_10__DI1_PT_2_10            0x1E048080,0x00000030
#define IPU_DI1_DW_GEN_10__DI1_PT_1_10            0x1E048080,0x0000000C
#define IPU_DI1_DW_GEN_10__DI1_PT_0_10            0x1E048080,0x00000003

#define IPU_DI1_DW_GEN_10__ADDR                     0x1E048080
#define IPU_DI1_DW_GEN_10__EMPTY                    0x1E048080,0x00000000
#define IPU_DI1_DW_GEN_10__FULL                     0x1E048080,0xffffffff
#define IPU_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10     0x1E048080,0xFF000000
#define IPU_DI1_DW_GEN_10__DI1_START_PERIOD_10      0x1E048080,0x00FF0000
#define IPU_DI1_DW_GEN_10__DI1_CST_10               0x1E048080,0x0000C000
#define IPU_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E048080,0x000001F0
#define IPU_DI1_DW_GEN_10__DI1_SERIAL_RS_10         0x1E048080,0x0000000C
#define IPU_DI1_DW_GEN_10__DI1_SERIAL_CLK_10        0x1E048080,0x00000003

#define IPU_DI1_DW_GEN_11__ADDR                   0x1E048084
#define IPU_DI1_DW_GEN_11__EMPTY                  0x1E048084,0x00000000
#define IPU_DI1_DW_GEN_11__FULL                   0x1E048084,0xffffffff
#define IPU_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11     0x1E048084,0xFF000000
#define IPU_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1E048084,0x00FF0000
#define IPU_DI1_DW_GEN_11__DI1_CST_11             0x1E048084,0x0000C000
#define IPU_DI1_DW_GEN_11__DI1_PT_6_11            0x1E048084,0x00003000
#define IPU_DI1_DW_GEN_11__DI1_PT_5_11            0x1E048084,0x00000C00
#define IPU_DI1_DW_GEN_11__DI1_PT_4_11            0x1E048084,0x00000300
#define IPU_DI1_DW_GEN_11__DI1_PT_3_11            0x1E048084,0x000000C0
#define IPU_DI1_DW_GEN_11__DI1_PT_2_11            0x1E048084,0x00000030
#define IPU_DI1_DW_GEN_11__DI1_PT_1_11            0x1E048084,0x0000000C
#define IPU_DI1_DW_GEN_11__DI1_PT_0_11            0x1E048084,0x00000003

#define IPU_DI1_DW_GEN_11__ADDR                     0x1E048084
#define IPU_DI1_DW_GEN_11__EMPTY                    0x1E048084,0x00000000
#define IPU_DI1_DW_GEN_11__FULL                     0x1E048084,0xffffffff
#define IPU_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11     0x1E048084,0xFF000000
#define IPU_DI1_DW_GEN_11__DI1_START_PERIOD_11      0x1E048084,0x00FF0000
#define IPU_DI1_DW_GEN_11__DI1_CST_11               0x1E048084,0x0000C000
#define IPU_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E048084,0x000001F0
#define IPU_DI1_DW_GEN_11__DI1_SERIAL_RS_11         0x1E048084,0x0000000C
#define IPU_DI1_DW_GEN_11__DI1_SERIAL_CLK_11        0x1E048084,0x00000003

#define IPU_DI1_STP_REP_9__ADDR              0x1E048158
#define IPU_DI1_STP_REP_9__EMPTY             0x1E048158,0x00000000
#define IPU_DI1_STP_REP_9__FULL              0x1E048158,0xffffffff
#define IPU_DI1_STP_REP_9__DI1_STEP_REPEAT_9 0x1E048158,0x00000FFF

#define IPU_DI1_SER_CONF__ADDR                       0x1E04815C
#define IPU_DI1_SER_CONF__EMPTY                      0x1E04815C,0x00000000
#define IPU_DI1_SER_CONF__FULL                       0x1E04815C,0xffffffff
#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1 0x1E04815C,0xF0000000
#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0 0x1E04815C,0x0F000000
#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1 0x1E04815C,0x00F00000
#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0 0x1E04815C,0x000F0000
#define IPU_DI1_SER_CONF__DI1_SERIAL_LATCH           0x1E04815C,0x0000FF00
#define IPU_DI1_SER_CONF__DI1_LLA_SER_ACCESS         0x1E04815C,0x00000020
#define IPU_DI1_SER_CONF__DI1_SER_CLK_POLARITY       0x1E04815C,0x00000010
#define IPU_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY   0x1E04815C,0x00000008
#define IPU_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY     0x1E04815C,0x00000004
#define IPU_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY     0x1E04815C,0x00000002
#define IPU_DI1_SER_CONF__DI1_WAIT4SERIAL            0x1E04815C,0x00000001

#define IPU_DI1_SSC__ADDR              0x1E048160
#define IPU_DI1_SSC__EMPTY             0x1E048160,0x00000000
#define IPU_DI1_SSC__FULL              0x1E048160,0xffffffff
#define IPU_DI1_SSC__DI1_PIN17_ERM     0x1E048160,0x00800000
#define IPU_DI1_SSC__DI1_PIN16_ERM     0x1E048160,0x00400000
#define IPU_DI1_SSC__DI1_PIN15_ERM     0x1E048160,0x00200000
#define IPU_DI1_SSC__DI1_PIN14_ERM     0x1E048160,0x00100000
#define IPU_DI1_SSC__DI1_PIN13_ERM     0x1E048160,0x00080000
#define IPU_DI1_SSC__DI1_PIN12_ERM     0x1E048160,0x00040000
#define IPU_DI1_SSC__DI1_PIN11_ERM     0x1E048160,0x00020000
#define IPU_DI1_SSC__DI1_CS_ERM        0x1E048160,0x00010000
#define IPU_DI1_SSC__DI1_WAIT_ON       0x1E048160,0x00000020
#define IPU_DI1_SSC__DI1_BYTE_EN_RD_IN 0x1E048160,0x00000008
#define IPU_DI1_SSC__DI1_BYTE_EN_PNTR  0x1E048160,0x00000007

#define IPU_DI1_POL__ADDR                     0x1E048164
#define IPU_DI1_POL__EMPTY                    0x1E048164,0x00000000
#define IPU_DI1_POL__FULL                     0x1E048164,0xffffffff
#define IPU_DI1_POL__DI1_WAIT_POLARITY        0x1E048164,0x04000000
#define IPU_DI1_POL__DI1_CS1_BYTE_EN_POLARITY 0x1E048164,0x02000000
#define IPU_DI1_POL__DI1_CS0_BYTE_EN_POLARITY 0x1E048164,0x01000000
#define IPU_DI1_POL__DI1_CS1_DATA_POLARITY    0x1E048164,0x00800000
#define IPU_DI1_POL__DI1_CS1_POLARITY_17      0x1E048164,0x00400000
#define IPU_DI1_POL__DI1_CS1_POLARITY_16      0x1E048164,0x00200000
#define IPU_DI1_POL__DI1_CS1_POLARITY_15      0x1E048164,0x00100000
#define IPU_DI1_POL__DI1_CS1_POLARITY_14      0x1E048164,0x00080000
#define IPU_DI1_POL__DI1_CS1_POLARITY_13      0x1E048164,0x00040000
#define IPU_DI1_POL__DI1_CS1_POLARITY_12      0x1E048164,0x00020000
#define IPU_DI1_POL__DI1_CS1_POLARITY_11      0x1E048164,0x00010000
#define IPU_DI1_POL__DI1_CS0_DATA_POLARITY    0x1E048164,0x00008000
#define IPU_DI1_POL__DI1_CS0_POLARITY_17      0x1E048164,0x00004000
#define IPU_DI1_POL__DI1_CS0_POLARITY_16      0x1E048164,0x00002000
#define IPU_DI1_POL__DI1_CS0_POLARITY_15      0x1E048164,0x00001000
#define IPU_DI1_POL__DI1_CS0_POLARITY_14      0x1E048164,0x00000800
#define IPU_DI1_POL__DI1_CS0_POLARITY_13      0x1E048164,0x00000400
#define IPU_DI1_POL__DI1_CS0_POLARITY_12      0x1E048164,0x00000200
#define IPU_DI1_POL__DI1_CS0_POLARITY_11      0x1E048164,0x00000100
#define IPU_DI1_POL__DI1_DRDY_DATA_POLARITY   0x1E048164,0x00000080
#define IPU_DI1_POL__DI1_DRDY_POLARITY_17     0x1E048164,0x00000040
#define IPU_DI1_POL__DI1_DRDY_POLARITY_16     0x1E048164,0x00000020
#define IPU_DI1_POL__DI1_DRDY_POLARITY_15     0x1E048164,0x00000010
#define IPU_DI1_POL__DI1_DRDY_POLARITY_14     0x1E048164,0x00000008
#define IPU_DI1_POL__DI1_DRDY_POLARITY_13     0x1E048164,0x00000004
#define IPU_DI1_POL__DI1_DRDY_POLARITY_12     0x1E048164,0x00000002
#define IPU_DI1_POL__DI1_DRDY_POLARITY_11     0x1E048164,0x00000001

#define IPU_DI1_AW0__ADDR              0x1E048168
#define IPU_DI1_AW0__EMPTY             0x1E048168,0x00000000
#define IPU_DI1_AW0__FULL              0x1E048168,0xffffffff
#define IPU_DI1_AW0__DI1_AW_TRIG_SEL   0x1E048168,0xF0000000
#define IPU_DI1_AW0__DI1_AW_HEND       0x1E048168,0x0FFF0000
#define IPU_DI1_AW0__DI1_AW_HCOUNT_SEL 0x1E048168,0x0000F000
#define IPU_DI1_AW0__DI1_AW_HSTART     0x1E048168,0x00000FFF

#define IPU_DI1_AW1__ADDR              0x1E04816C
#define IPU_DI1_AW1__EMPTY             0x1E04816C,0x00000000
#define IPU_DI1_AW1__FULL              0x1E04816C,0xffffffff
#define IPU_DI1_AW1__DI1_AW_VEND       0x1E04816C,0x0FFF0000
#define IPU_DI1_AW1__DI1_AW_VCOUNT_SEL 0x1E04816C,0x0000F000
#define IPU_DI1_AW1__DI1_AW_VSTART     0x1E04816C,0x00000FFF

#define IPU_DI1_SCR_CONF__ADDR              0x1E048170
#define IPU_DI1_SCR_CONF__EMPTY             0x1E048170,0x00000000
#define IPU_DI1_SCR_CONF__FULL              0x1E048170,0xffffffff
#define IPU_DI1_SCR_CONF__DI1_SCREEN_HEIGHT 0x1E048170,0x00000FFF

#define IPU_DI1_STAT__ADDR                0x1E048174
#define IPU_DI1_STAT__EMPTY               0x1E048174,0x00000000
#define IPU_DI1_STAT__FULL                0x1E048174,0xffffffff
#define IPU_DI1_STAT__DI1_CNTR_FIFO_FULL  0x1E048174,0x00000008
#define IPU_DI1_STAT__DI1_CNTR_FIFO_EMPTY 0x1E048174,0x00000004
#define IPU_DI1_STAT__DI1_READ_FIFO_FULL  0x1E048174,0x00000002
#define IPU_DI1_STAT__DI1_READ_FIFO_EMPTY 0x1E048174,0x00000001
// ================= End of IPUV3EX DI Registers =====================

// ================= Start of IPUV3EX SMFC Registers =====================
#define IPU_SMFC_MAP__ADDR    0x1E050000
#define IPU_SMFC_MAP__EMPTY   0x1E050000,0x00000000
#define IPU_SMFC_MAP__FULL    0x1E050000,0xffffffff
#define IPU_SMFC_MAP__MAP_CH3 0x1E050000,0x00000E00
#define IPU_SMFC_MAP__MAP_CH2 0x1E050000,0x000001C0
#define IPU_SMFC_MAP__MAP_CH1 0x1E050000,0x00000038
#define IPU_SMFC_MAP__MAP_CH0 0x1E050000,0x00000007

#define IPU_SMFC_WMC__ADDR    0x1E050004
#define IPU_SMFC_WMC__EMPTY   0x1E050004,0x00000000
#define IPU_SMFC_WMC__FULL    0x1E050004,0xffffffff
#define IPU_SMFC_WMC__WM3_CLR 0x1E050004,0x0E000000
#define IPU_SMFC_WMC__WM3_SET 0x1E050004,0x01C00000
#define IPU_SMFC_WMC__WM2_CLR 0x1E050004,0x00380000
#define IPU_SMFC_WMC__WM2_SET 0x1E050004,0x00070000
#define IPU_SMFC_WMC__WM1_CLR 0x1E050004,0x00000E00
#define IPU_SMFC_WMC__WM1_SET 0x1E050004,0x000001C0
#define IPU_SMFC_WMC__WM0_CLR 0x1E050004,0x00000038
#define IPU_SMFC_WMC__WM0_SET 0x1E050004,0x00000007

#define IPU_SMFC_BS__ADDR        0x1E050008
#define IPU_SMFC_BS__EMPTY       0x1E050008,0x00000000
#define IPU_SMFC_BS__FULL        0x1E050008,0xffffffff
#define IPU_SMFC_BS__BURST3_SIZE 0x1E050008,0x0000F000
#define IPU_SMFC_BS__BURST2_SIZE 0x1E050008,0x00000F00
#define IPU_SMFC_BS__BURST1_SIZE 0x1E050008,0x000000F0
#define IPU_SMFC_BS__BURST0_SIZE 0x1E050008,0x0000000F
// ================= End of IPUV3EX SMFC Registers =====================

// ================= Start of IPUV3EX DC Registers =====================
#define IPU_DC_READ_CH_CONF__ADDR                0x1E058000
#define IPU_DC_READ_CH_CONF__EMPTY               0x1E058000,0x00000000
#define IPU_DC_READ_CH_CONF__FULL                0x1E058000,0xffffffff
#define IPU_DC_READ_CH_CONF__TIME_OUT_VALUE      0x1E058000,0xFFFF0000
#define IPU_DC_READ_CH_CONF__CS_ID_3             0x1E058000,0x00000800
#define IPU_DC_READ_CH_CONF__CS_ID_2             0x1E058000,0x00000400
#define IPU_DC_READ_CH_CONF__CS_ID_1             0x1E058000,0x00000200
#define IPU_DC_READ_CH_CONF__CS_ID_0             0x1E058000,0x00000100
#define IPU_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0 0x1E058000,0x00000040
#define IPU_DC_READ_CH_CONF__W_SIZE_0            0x1E058000,0x00000030
#define IPU_DC_READ_CH_CONF__PROG_DISP_ID_0      0x1E058000,0x0000000C
#define IPU_DC_READ_CH_CONF__PROG_DI_ID_0        0x1E058000,0x00000002
#define IPU_DC_READ_CH_CONF__RD_CHANNEL_EN       0x1E058000,0x00000001

#define IPU_DC_READ_CH_ADDR__ADDR      0x1E058004
#define IPU_DC_READ_CH_ADDR__EMPTY     0x1E058004,0x00000000
#define IPU_DC_READ_CH_ADDR__FULL      0x1E058004,0xffffffff
#define IPU_DC_READ_CH_ADDR__ST_ADDR_0 0x1E058004,0x1FFFFFFF

#define IPU_DC_RL0_CH_0__ADDR                   0x1E058008
#define IPU_DC_RL0_CH_0__EMPTY                  0x1E058008,0x00000000
#define IPU_DC_RL0_CH_0__FULL                   0x1E058008,0xffffffff
#define IPU_DC_RL0_CH_0__COD_NL_START_CHAN_0    0x1E058008,0xFF000000
#define IPU_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0 0x1E058008,0x000F0000
#define IPU_DC_RL0_CH_0__COD_NF_START_CHAN_0    0x1E058008,0x0000FF00
#define IPU_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0 0x1E058008,0x0000000F

#define IPU_DC_RL1_CH_0__ADDR                       0x1E05800C
#define IPU_DC_RL1_CH_0__EMPTY                      0x1E05800C,0x00000000
#define IPU_DC_RL1_CH_0__FULL                       0x1E05800C,0xffffffff
#define IPU_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0    0x1E05800C,0xFF000000
#define IPU_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0 0x1E05800C,0x000F0000
#define IPU_DC_RL1_CH_0__COD_EOF_START_CHAN_0       0x1E05800C,0x0000FF00
#define IPU_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0    0x1E05800C,0x0000000F

#define IPU_DC_RL2_CH_0__ADDR                        0x1E058010
#define IPU_DC_RL2_CH_0__EMPTY                       0x1E058010,0x00000000
#define IPU_DC_RL2_CH_0__FULL                        0x1E058010,0xffffffff
#define IPU_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0    0x1E058010,0xFF000000
#define IPU_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0 0x1E058010,0x000F0000
#define IPU_DC_RL2_CH_0__COD_EOL_START_CHAN_0        0x1E058010,0x0000FF00
#define IPU_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0     0x1E058010,0x0000000F

#define IPU_DC_RL3_CH_0__ADDR                         0x1E058014
#define IPU_DC_RL3_CH_0__EMPTY                        0x1E058014,0x00000000
#define IPU_DC_RL3_CH_0__FULL                         0x1E058014,0xffffffff
#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0    0x1E058014,0xFF000000
#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0 0x1E058014,0x000F0000
#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0    0x1E058014,0x0000FF00
#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0 0x1E058014,0x0000000F

#define IPU_DC_RL4_CH_0__ADDR                         0x1E058018
#define IPU_DC_RL4_CH_0__EMPTY                        0x1E058018,0x00000000
#define IPU_DC_RL4_CH_0__FULL                         0x1E058018,0xffffffff
#define IPU_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0    0x1E058018,0x0000FF00
#define IPU_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0 0x1E058018,0x0000000F

#define IPU_DC_WR_CH_CONF_1__ADDR                0x1E05801C
#define IPU_DC_WR_CH_CONF_1__EMPTY               0x1E05801C,0x00000000
#define IPU_DC_WR_CH_CONF_1__FULL                0x1E05801C,0xffffffff
#define IPU_DC_WR_CH_CONF_1__PROG_START_TIME_1   0x1E05801C,0x07FF0000
#define IPU_DC_WR_CH_CONF_1__FIELD_MODE_1        0x1E05801C,0x00000200
#define IPU_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1 0x1E05801C,0x00000100
#define IPU_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1     0x1E05801C,0x000000E0
#define IPU_DC_WR_CH_CONF_1__PROG_DISP_ID_1      0x1E05801C,0x00000018
#define IPU_DC_WR_CH_CONF_1__PROG_DI_ID_1        0x1E05801C,0x00000004
#define IPU_DC_WR_CH_CONF_1__W_SIZE_1            0x1E05801C,0x00000003

#define IPU_DC_WR_CH_ADDR_1__ADDR      0x1E058020
#define IPU_DC_WR_CH_ADDR_1__EMPTY     0x1E058020,0x00000000
#define IPU_DC_WR_CH_ADDR_1__FULL      0x1E058020,0xffffffff
#define IPU_DC_WR_CH_ADDR_1__ST_ADDR_1 0x1E058020,0x1FFFFFFF

#define IPU_DC_RL0_CH_1__ADDR                   0x1E058024
#define IPU_DC_RL0_CH_1__EMPTY                  0x1E058024,0x00000000
#define IPU_DC_RL0_CH_1__FULL                   0x1E058024,0xffffffff
#define IPU_DC_RL0_CH_1__COD_NL_START_CHAN_1    0x1E058024,0xFF000000
#define IPU_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1 0x1E058024,0x000F0000
#define IPU_DC_RL0_CH_1__COD_NF_START_CHAN_1    0x1E058024,0x0000FF00
#define IPU_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1 0x1E058024,0x0000000F

#define IPU_DC_RL1_CH_1__ADDR                       0x1E058028
#define IPU_DC_RL1_CH_1__EMPTY                      0x1E058028,0x00000000
#define IPU_DC_RL1_CH_1__FULL                       0x1E058028,0xffffffff
#define IPU_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1    0x1E058028,0xFF000000
#define IPU_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1 0x1E058028,0x000F0000
#define IPU_DC_RL1_CH_1__COD_EOF_START_CHAN_1       0x1E058028,0x0000FF00
#define IPU_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1    0x1E058028,0x0000000F

#define IPU_DC_RL2_CH_1__ADDR                        0x1E05802C
#define IPU_DC_RL2_CH_1__EMPTY                       0x1E05802C,0x00000000
#define IPU_DC_RL2_CH_1__FULL                        0x1E05802C,0xffffffff
#define IPU_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1    0x1E05802C,0xFF000000
#define IPU_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1 0x1E05802C,0x000F0000
#define IPU_DC_RL2_CH_1__COD_EOL_START_CHAN_1        0x1E05802C,0x0000FF00
#define IPU_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1     0x1E05802C,0x0000000F

#define IPU_DC_RL3_CH_1__ADDR                         0x1E058030
#define IPU_DC_RL3_CH_1__EMPTY                        0x1E058030,0x00000000
#define IPU_DC_RL3_CH_1__FULL                         0x1E058030,0xffffffff
#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1    0x1E058030,0xFF000000
#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1 0x1E058030,0x000F0000
#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1    0x1E058030,0x0000FF00
#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1 0x1E058030,0x0000000F

#define IPU_DC_RL4_CH_1__ADDR                         0x1E058034
#define IPU_DC_RL4_CH_1__EMPTY                        0x1E058034,0x00000000
#define IPU_DC_RL4_CH_1__FULL                         0x1E058034,0xffffffff
#define IPU_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1    0x1E058034,0x0000FF00
#define IPU_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1 0x1E058034,0x0000000F

#define IPU_DC_WR_CH_CONF_2__ADDR                0x1E058038
#define IPU_DC_WR_CH_CONF_2__EMPTY               0x1E058038,0x00000000
#define IPU_DC_WR_CH_CONF_2__FULL                0x1E058038,0xffffffff
#define IPU_DC_WR_CH_CONF_2__PROG_START_TIME_2   0x1E058038,0x07FF0000
#define IPU_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2 0x1E058038,0x00000100
#define IPU_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2     0x1E058038,0x000000E0
#define IPU_DC_WR_CH_CONF_2__PROG_DISP_ID_2      0x1E058038,0x00000018
#define IPU_DC_WR_CH_CONF_2__PROG_DI_ID_2        0x1E058038,0x00000004
#define IPU_DC_WR_CH_CONF_2__W_SIZE_2            0x1E058038,0x00000003

#define IPU_DC_WR_CH_ADDR_2__ADDR      0x1E05803C
#define IPU_DC_WR_CH_ADDR_2__EMPTY     0x1E05803C,0x00000000
#define IPU_DC_WR_CH_ADDR_2__FULL      0x1E05803C,0xffffffff
#define IPU_DC_WR_CH_ADDR_2__ST_ADDR_2 0x1E05803C,0x1FFFFFFF

#define IPU_DC_RL0_CH_2__ADDR                   0x1E058040
#define IPU_DC_RL0_CH_2__EMPTY                  0x1E058040,0x00000000
#define IPU_DC_RL0_CH_2__FULL                   0x1E058040,0xffffffff
#define IPU_DC_RL0_CH_2__COD_NL_START_CHAN_2    0x1E058040,0xFF000000
#define IPU_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2 0x1E058040,0x000F0000
#define IPU_DC_RL0_CH_2__COD_NF_START_CHAN_2    0x1E058040,0x0000FF00
#define IPU_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2 0x1E058040,0x0000000F

#define IPU_DC_RL1_CH_2__ADDR                       0x1E058044
#define IPU_DC_RL1_CH_2__EMPTY                      0x1E058044,0x00000000
#define IPU_DC_RL1_CH_2__FULL                       0x1E058044,0xffffffff
#define IPU_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2    0x1E058044,0xFF000000
#define IPU_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2 0x1E058044,0x000F0000
#define IPU_DC_RL1_CH_2__COD_EOF_START_CHAN_2       0x1E058044,0x0000FF00
#define IPU_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2    0x1E058044,0x0000000F

#define IPU_DC_RL2_CH_2__ADDR                        0x1E058048
#define IPU_DC_RL2_CH_2__EMPTY                       0x1E058048,0x00000000
#define IPU_DC_RL2_CH_2__FULL                        0x1E058048,0xffffffff
#define IPU_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2    0x1E058048,0xFF000000
#define IPU_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2 0x1E058048,0x000F0000
#define IPU_DC_RL2_CH_2__COD_EOL_START_CHAN_2        0x1E058048,0x0000FF00
#define IPU_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2     0x1E058048,0x0000000F

#define IPU_DC_RL3_CH_2__ADDR                         0x1E05804C
#define IPU_DC_RL3_CH_2__EMPTY                        0x1E05804C,0x00000000
#define IPU_DC_RL3_CH_2__FULL                         0x1E05804C,0xffffffff
#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2    0x1E05804C,0xFF000000
#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2 0x1E05804C,0x000F0000
#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2    0x1E05804C,0x0000FF00
#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2 0x1E05804C,0x0000000F

#define IPU_DC_RL4_CH_2__ADDR                         0x1E058050
#define IPU_DC_RL4_CH_2__EMPTY                        0x1E058050,0x00000000
#define IPU_DC_RL4_CH_2__FULL                         0x1E058050,0xffffffff
#define IPU_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2    0x1E058050,0x0000FF00
#define IPU_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2 0x1E058050,0x0000000F

#define IPU_DC_CMD_CH_CONF_3__ADDR                      0x1E058054
#define IPU_DC_CMD_CH_CONF_3__EMPTY                     0x1E058054,0x00000000
#define IPU_DC_CMD_CH_CONF_3__FULL                      0x1E058054,0xffffffff
#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3 0x1E058054,0xFF000000
#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3 0x1E058054,0x0000FF00
#define IPU_DC_CMD_CH_CONF_3__W_SIZE_3                  0x1E058054,0x00000003

#define IPU_DC_CMD_CH_CONF_4__ADDR                      0x1E058058
#define IPU_DC_CMD_CH_CONF_4__EMPTY                     0x1E058058,0x00000000
#define IPU_DC_CMD_CH_CONF_4__FULL                      0x1E058058,0xffffffff
#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4 0x1E058058,0xFF000000
#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4 0x1E058058,0x0000FF00
#define IPU_DC_CMD_CH_CONF_4__W_SIZE_4                  0x1E058058,0x00000003

#define IPU_DC_WR_CH_CONF_5__ADDR                0x1E05805C
#define IPU_DC_WR_CH_CONF_5__EMPTY               0x1E05805C,0x00000000
#define IPU_DC_WR_CH_CONF_5__FULL                0x1E05805C,0xffffffff
#define IPU_DC_WR_CH_CONF_5__PROG_START_TIME_5   0x1E05805C,0x07FF0000
#define IPU_DC_WR_CH_CONF_5__FIELD_MODE_5        0x1E05805C,0x00000200
#define IPU_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5 0x1E05805C,0x00000100
#define IPU_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5     0x1E05805C,0x000000E0
#define IPU_DC_WR_CH_CONF_5__PROG_DISP_ID_5      0x1E05805C,0x00000018
#define IPU_DC_WR_CH_CONF_5__PROG_DI_ID_5        0x1E05805C,0x00000004
#define IPU_DC_WR_CH_CONF_5__W_SIZE_5            0x1E05805C,0x00000003

#define IPU_DC_WR_CH_ADDR_5__ADDR      0x1E058060
#define IPU_DC_WR_CH_ADDR_5__EMPTY     0x1E058060,0x00000000
#define IPU_DC_WR_CH_ADDR_5__FULL      0x1E058060,0xffffffff
#define IPU_DC_WR_CH_ADDR_5__ST_ADDR_5 0x1E058060,0x1FFFFFFF

#define IPU_DC_RL0_CH_5__ADDR                   0x1E058064
#define IPU_DC_RL0_CH_5__EMPTY                  0x1E058064,0x00000000
#define IPU_DC_RL0_CH_5__FULL                   0x1E058064,0xffffffff
#define IPU_DC_RL0_CH_5__COD_NL_START_CHAN_5    0x1E058064,0xFF000000
#define IPU_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5 0x1E058064,0x000F0000
#define IPU_DC_RL0_CH_5__COD_NF_START_CHAN_5    0x1E058064,0x0000FF00
#define IPU_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5 0x1E058064,0x0000000F

#define IPU_DC_RL1_CH_5__ADDR                       0x1E058068
#define IPU_DC_RL1_CH_5__EMPTY                      0x1E058068,0x00000000
#define IPU_DC_RL1_CH_5__FULL                       0x1E058068,0xffffffff
#define IPU_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5    0x1E058068,0xFF000000
#define IPU_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5 0x1E058068,0x000F0000
#define IPU_DC_RL1_CH_5__COD_EOF_START_CHAN_5       0x1E058068,0x0000FF00
#define IPU_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5    0x1E058068,0x0000000F

#define IPU_DC_RL2_CH_5__ADDR                        0x1E05806C
#define IPU_DC_RL2_CH_5__EMPTY                       0x1E05806C,0x00000000
#define IPU_DC_RL2_CH_5__FULL                        0x1E05806C,0xffffffff
#define IPU_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5    0x1E05806C,0xFF000000
#define IPU_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5 0x1E05806C,0x000F0000
#define IPU_DC_RL2_CH_5__COD_EOL_START_CHAN_5        0x1E05806C,0x0000FF00
#define IPU_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5     0x1E05806C,0x0000000F

#define IPU_DC_RL3_CH_5__ADDR                         0x1E058070
#define IPU_DC_RL3_CH_5__EMPTY                        0x1E058070,0x00000000
#define IPU_DC_RL3_CH_5__FULL                         0x1E058070,0xffffffff
#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5    0x1E058070,0xFF000000
#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5 0x1E058070,0x000F0000
#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5    0x1E058070,0x0000FF00
#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5 0x1E058070,0x0000000F

#define IPU_DC_RL4_CH_5__ADDR                         0x1E058074
#define IPU_DC_RL4_CH_5__EMPTY                        0x1E058074,0x00000000
#define IPU_DC_RL4_CH_5__FULL                         0x1E058074,0xffffffff
#define IPU_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5    0x1E058074,0x0000FF00
#define IPU_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5 0x1E058074,0x0000000F

#define IPU_DC_WR_CH_CONF_6__ADDR                0x1E058078
#define IPU_DC_WR_CH_CONF_6__EMPTY               0x1E058078,0x00000000
#define IPU_DC_WR_CH_CONF_6__FULL                0x1E058078,0xffffffff
#define IPU_DC_WR_CH_CONF_6__PROG_START_TIME_6   0x1E058078,0x07FF0000
#define IPU_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6 0x1E058078,0x00000100
#define IPU_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6     0x1E058078,0x000000E0
#define IPU_DC_WR_CH_CONF_6__PROG_DISP_ID_6      0x1E058078,0x00000018
#define IPU_DC_WR_CH_CONF_6__PROG_DI_ID_6        0x1E058078,0x00000004
#define IPU_DC_WR_CH_CONF_6__W_SIZE_6            0x1E058078,0x00000003

#define IPU_DC_WR_CH_ADDR_6__ADDR      0x1E05807C
#define IPU_DC_WR_CH_ADDR_6__EMPTY     0x1E05807C,0x00000000
#define IPU_DC_WR_CH_ADDR_6__FULL      0x1E05807C,0xffffffff
#define IPU_DC_WR_CH_ADDR_6__ST_ADDR_6 0x1E05807C,0x1FFFFFFF

#define IPU_DC_RL0_CH_6__ADDR                   0x1E058080
#define IPU_DC_RL0_CH_6__EMPTY                  0x1E058080,0x00000000
#define IPU_DC_RL0_CH_6__FULL                   0x1E058080,0xffffffff
#define IPU_DC_RL0_CH_6__COD_NL_START_CHAN_6    0x1E058080,0xFF000000
#define IPU_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6 0x1E058080,0x000F0000
#define IPU_DC_RL0_CH_6__COD_NF_START_CHAN_6    0x1E058080,0x0000FF00
#define IPU_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6 0x1E058080,0x0000000F

#define IPU_DC_RL1_CH_6__ADDR                       0x1E058084
#define IPU_DC_RL1_CH_6__EMPTY                      0x1E058084,0x00000000
#define IPU_DC_RL1_CH_6__FULL                       0x1E058084,0xffffffff
#define IPU_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6    0x1E058084,0xFF000000
#define IPU_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6 0x1E058084,0x000F0000
#define IPU_DC_RL1_CH_6__COD_EOF_START_CHAN_6       0x1E058084,0x0000FF00
#define IPU_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6    0x1E058084,0x0000000F

#define IPU_DC_RL2_CH_6__ADDR                        0x1E058088
#define IPU_DC_RL2_CH_6__EMPTY                       0x1E058088,0x00000000
#define IPU_DC_RL2_CH_6__FULL                        0x1E058088,0xffffffff
#define IPU_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6    0x1E058088,0xFF000000
#define IPU_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6 0x1E058088,0x000F0000
#define IPU_DC_RL2_CH_6__COD_EOL_START_CHAN_6        0x1E058088,0x0000FF00
#define IPU_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6     0x1E058088,0x0000000F

#define IPU_DC_RL3_CH_6__ADDR                         0x1E05808C
#define IPU_DC_RL3_CH_6__EMPTY                        0x1E05808C,0x00000000
#define IPU_DC_RL3_CH_6__FULL                         0x1E05808C,0xffffffff
#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6    0x1E05808C,0xFF000000
#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6 0x1E05808C,0x000F0000
#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6    0x1E05808C,0x0000FF00
#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6 0x1E05808C,0x0000000F

#define IPU_DC_RL4_CH_6__ADDR                         0x1E058090
#define IPU_DC_RL4_CH_6__EMPTY                        0x1E058090,0x00000000
#define IPU_DC_RL4_CH_6__FULL                         0x1E058090,0xffffffff
#define IPU_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6    0x1E058090,0x0000FF00
#define IPU_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6 0x1E058090,0x0000000F

#define IPU_DC_WR_CH_CONF1_8__ADDR                0x1E058094
#define IPU_DC_WR_CH_CONF1_8__EMPTY               0x1E058094,0x00000000
#define IPU_DC_WR_CH_CONF1_8__FULL                0x1E058094,0xffffffff
#define IPU_DC_WR_CH_CONF1_8__MCU_DISP_ID_8       0x1E058094,0x00000018
#define IPU_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8 0x1E058094,0x00000004
#define IPU_DC_WR_CH_CONF1_8__W_SIZE_8            0x1E058094,0x00000003

#define IPU_DC_WR_CH_CONF2_8__ADDR                0x1E058098
#define IPU_DC_WR_CH_CONF2_8__EMPTY               0x1E058098,0x00000000
#define IPU_DC_WR_CH_CONF2_8__FULL                0x1E058098,0xffffffff
#define IPU_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8 0x1E058098,0x1FFFFFFF

#define IPU_DC_RL1_CH_8__ADDR                          0x1E05809C
#define IPU_DC_RL1_CH_8__EMPTY                         0x1E05809C,0x00000000
#define IPU_DC_RL1_CH_8__FULL                          0x1E05809C,0xffffffff
#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1 0x1E05809C,0xFF000000
#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0 0x1E05809C,0x0000FF00
#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8  0x1E05809C,0x0000000F

#define IPU_DC_RL2_CH_8__ADDR                          0x1E0580A0
#define IPU_DC_RL2_CH_8__EMPTY                         0x1E0580A0,0x00000000
#define IPU_DC_RL2_CH_8__FULL                          0x1E0580A0,0xffffffff
#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1 0x1E0580A0,0xFF000000
#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0 0x1E0580A0,0x0000FF00
#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8  0x1E0580A0,0x0000000F

#define IPU_DC_RL3_CH_8__ADDR                          0x1E0580A4
#define IPU_DC_RL3_CH_8__EMPTY                         0x1E0580A4,0x00000000
#define IPU_DC_RL3_CH_8__FULL                          0x1E0580A4,0xffffffff
#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1 0x1E0580A4,0xFF000000
#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0 0x1E0580A4,0x0000FF00
#define IPU_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8  0x1E0580A4,0x0000000F

#define IPU_DC_RL4_CH_8__ADDR                          0x1E0580A8
#define IPU_DC_RL4_CH_8__EMPTY                         0x1E0580A8,0x00000000
#define IPU_DC_RL4_CH_8__FULL                          0x1E0580A8,0xffffffff
#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1 0x1E0580A8,0xFF000000
#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0 0x1E0580A8,0x0000FF00

#define IPU_DC_RL5_CH_8__ADDR                          0x1E0580AC
#define IPU_DC_RL5_CH_8__EMPTY                         0x1E0580AC,0x00000000
#define IPU_DC_RL5_CH_8__FULL                          0x1E0580AC,0xffffffff
#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1 0x1E0580AC,0xFF000000
#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0 0x1E0580AC,0x0000FF00

#define IPU_DC_RL6_CH_8__ADDR                          0x1E0580B0
#define IPU_DC_RL6_CH_8__EMPTY                         0x1E0580B0,0x00000000
#define IPU_DC_RL6_CH_8__FULL                          0x1E0580B0,0xffffffff
#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1 0x1E0580B0,0xFF000000
#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0 0x1E0580B0,0x0000FF00

#define IPU_DC_WR_CH_CONF1_9__ADDR                0x1E0580B4
#define IPU_DC_WR_CH_CONF1_9__EMPTY               0x1E0580B4,0x00000000
#define IPU_DC_WR_CH_CONF1_9__FULL                0x1E0580B4,0xffffffff
#define IPU_DC_WR_CH_CONF1_9__MCU_DISP_ID_9       0x1E0580B4,0x00000018
#define IPU_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9 0x1E0580B4,0x00000004
#define IPU_DC_WR_CH_CONF1_9__W_SIZE_9            0x1E0580B4,0x00000003

#define IPU_DC_WR_CH_CONF2_9__ADDR                0x1E0580B8
#define IPU_DC_WR_CH_CONF2_9__EMPTY               0x1E0580B8,0x00000000
#define IPU_DC_WR_CH_CONF2_9__FULL                0x1E0580B8,0xffffffff
#define IPU_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9 0x1E0580B8,0x1FFFFFFF

#define IPU_DC_RL1_CH_9__ADDR                          0x1E0580BC
#define IPU_DC_RL1_CH_9__EMPTY                         0x1E0580BC,0x00000000
#define IPU_DC_RL1_CH_9__FULL                          0x1E0580BC,0xffffffff
#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1 0x1E0580BC,0xFF000000
#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0 0x1E0580BC,0x0000FF00
#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9  0x1E0580BC,0x0000000F

#define IPU_DC_RL2_CH_9__ADDR                          0x1E0580C0
#define IPU_DC_RL2_CH_9__EMPTY                         0x1E0580C0,0x00000000
#define IPU_DC_RL2_CH_9__FULL                          0x1E0580C0,0xffffffff
#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1 0x1E0580C0,0xFF000000
#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0 0x1E0580C0,0x0000FF00
#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9  0x1E0580C0,0x0000000F

#define IPU_DC_RL3_CH_9__ADDR                          0x1E0580C4
#define IPU_DC_RL3_CH_9__EMPTY                         0x1E0580C4,0x00000000
#define IPU_DC_RL3_CH_9__FULL                          0x1E0580C4,0xffffffff
#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1 0x1E0580C4,0xFF000000
#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0 0x1E0580C4,0x0000FF00
#define IPU_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9  0x1E0580C4,0x0000000F

#define IPU_DC_RL4_CH_9__ADDR                          0x1E0580C8
#define IPU_DC_RL4_CH_9__EMPTY                         0x1E0580C8,0x00000000
#define IPU_DC_RL4_CH_9__FULL                          0x1E0580C8,0xffffffff
#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1 0x1E0580C8,0xFF000000
#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0 0x1E0580C8,0x0000FF00

#define IPU_DC_RL5_CH_9__ADDR                          0x1E0580CC
#define IPU_DC_RL5_CH_9__EMPTY                         0x1E0580CC,0x00000000
#define IPU_DC_RL5_CH_9__FULL                          0x1E0580CC,0xffffffff
#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1 0x1E0580CC,0xFF000000
#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0 0x1E0580CC,0x0000FF00

#define IPU_DC_RL6_CH_9__ADDR                          0x1E0580D0
#define IPU_DC_RL6_CH_9__EMPTY                         0x1E0580D0,0x00000000
#define IPU_DC_RL6_CH_9__FULL                          0x1E0580D0,0xffffffff
#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1 0x1E0580D0,0xFF000000
#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0 0x1E0580D0,0x0000FF00

#define IPU_DC_GEN__ADDR            0x1E0580D4
#define IPU_DC_GEN__EMPTY           0x1E0580D4,0x00000000
#define IPU_DC_GEN__FULL            0x1E0580D4,0xffffffff
#define IPU_DC_GEN__DC_BK_EN        0x1E0580D4,0x01000000
#define IPU_DC_GEN__DC_BKDIV        0x1E0580D4,0x00FF0000
#define IPU_DC_GEN__DC_CH5_TYPE     0x1E0580D4,0x00000100
#define IPU_DC_GEN__SYNC_PRIORITY_1 0x1E0580D4,0x00000080
#define IPU_DC_GEN__SYNC_PRIORITY_5 0x1E0580D4,0x00000040
#define IPU_DC_GEN__MASK4CHAN_5     0x1E0580D4,0x00000020
#define IPU_DC_GEN__MASK_EN         0x1E0580D4,0x00000010
#define IPU_DC_GEN__SYNC_1_6        0x1E0580D4,0x00000006

#define IPU_DC_DISP_CONF1_0__ADDR                0x1E0580D8
#define IPU_DC_DISP_CONF1_0__EMPTY               0x1E0580D8,0x00000000
#define IPU_DC_DISP_CONF1_0__FULL                0x1E0580D8,0xffffffff
#define IPU_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1E0580D8,0x00000080
#define IPU_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0   0x1E0580D8,0x00000040
#define IPU_DC_DISP_CONF1_0__ADDR_BE_L_INC_0     0x1E0580D8,0x00000030
#define IPU_DC_DISP_CONF1_0__ADDR_INCREMENT_0    0x1E0580D8,0x0000000C
#define IPU_DC_DISP_CONF1_0__DISP_TYP_0          0x1E0580D8,0x00000003

#define IPU_DC_DISP_CONF1_1__ADDR                0x1E0580DC
#define IPU_DC_DISP_CONF1_1__EMPTY               0x1E0580DC,0x00000000
#define IPU_DC_DISP_CONF1_1__FULL                0x1E0580DC,0xffffffff
#define IPU_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1E0580DC,0x00000080
#define IPU_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1   0x1E0580DC,0x00000040
#define IPU_DC_DISP_CONF1_1__ADDR_BE_L_INC_1     0x1E0580DC,0x00000030
#define IPU_DC_DISP_CONF1_1__ADDR_INCREMENT_1    0x1E0580DC,0x0000000C
#define IPU_DC_DISP_CONF1_1__DISP_TYP_1          0x1E0580DC,0x00000003

#define IPU_DC_DISP_CONF1_2__ADDR                0x1E0580E0
#define IPU_DC_DISP_CONF1_2__EMPTY               0x1E0580E0,0x00000000
#define IPU_DC_DISP_CONF1_2__FULL                0x1E0580E0,0xffffffff
#define IPU_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1E0580E0,0x00000080
#define IPU_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2   0x1E0580E0,0x00000040
#define IPU_DC_DISP_CONF1_2__ADDR_BE_L_INC_2     0x1E0580E0,0x00000030
#define IPU_DC_DISP_CONF1_2__ADDR_INCREMENT_2    0x1E0580E0,0x0000000C
#define IPU_DC_DISP_CONF1_2__DISP_TYP_2          0x1E0580E0,0x00000003

#define IPU_DC_DISP_CONF1_3__ADDR                0x1E0580E4
#define IPU_DC_DISP_CONF1_3__EMPTY               0x1E0580E4,0x00000000
#define IPU_DC_DISP_CONF1_3__FULL                0x1E0580E4,0xffffffff
#define IPU_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1E0580E4,0x00000080
#define IPU_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3   0x1E0580E4,0x00000040
#define IPU_DC_DISP_CONF1_3__ADDR_BE_L_INC_3     0x1E0580E4,0x00000030
#define IPU_DC_DISP_CONF1_3__ADDR_INCREMENT_3    0x1E0580E4,0x0000000C
#define IPU_DC_DISP_CONF1_3__DISP_TYP_3          0x1E0580E4,0x00000003

#define IPU_DC_DISP_CONF2_0__ADDR  0x1E0580E8
#define IPU_DC_DISP_CONF2_0__EMPTY 0x1E0580E8,0x00000000
#define IPU_DC_DISP_CONF2_0__FULL  0x1E0580E8,0xffffffff
#define IPU_DC_DISP_CONF2_0__SL_0  0x1E0580E8,0x1FFFFFFF

#define IPU_DC_DISP_CONF2_1__ADDR  0x1E0580EC
#define IPU_DC_DISP_CONF2_1__EMPTY 0x1E0580EC,0x00000000
#define IPU_DC_DISP_CONF2_1__FULL  0x1E0580EC,0xffffffff
#define IPU_DC_DISP_CONF2_1__SL_1  0x1E0580EC,0x1FFFFFFF

#define IPU_DC_DISP_CONF2_2__ADDR  0x1E0580F0
#define IPU_DC_DISP_CONF2_2__EMPTY 0x1E0580F0,0x00000000
#define IPU_DC_DISP_CONF2_2__FULL  0x1E0580F0,0xffffffff
#define IPU_DC_DISP_CONF2_2__SL_2  0x1E0580F0,0x1FFFFFFF

#define IPU_DC_DISP_CONF2_3__ADDR  0x1E0580F4
#define IPU_DC_DISP_CONF2_3__EMPTY 0x1E0580F4,0x00000000
#define IPU_DC_DISP_CONF2_3__FULL  0x1E0580F4,0xffffffff
#define IPU_DC_DISP_CONF2_3__SL_3  0x1E0580F4,0x1FFFFFFF

#define IPU_DC_DI0_CONF_1__ADDR                0x1E0580F8
#define IPU_DC_DI0_CONF_1__EMPTY               0x1E0580F8,0x00000000
#define IPU_DC_DI0_CONF_1__FULL                0x1E0580F8,0xffffffff
#define IPU_DC_DI0_CONF_1__DI_READ_DATA_MASK_0 0x1E0580F8,0xFFFFFFFF

#define IPU_DC_DI0_CONF_2__ADDR                     0x1E0580FC
#define IPU_DC_DI0_CONF_2__EMPTY                    0x1E0580FC,0x00000000
#define IPU_DC_DI0_CONF_2__FULL                     0x1E0580FC,0xffffffff
#define IPU_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0 0x1E0580FC,0xFFFFFFFF

#define IPU_DC_DI1_CONF_1__ADDR                0x1E058100
#define IPU_DC_DI1_CONF_1__EMPTY               0x1E058100,0x00000000
#define IPU_DC_DI1_CONF_1__FULL                0x1E058100,0xffffffff
#define IPU_DC_DI1_CONF_1__DI_READ_DATA_MASK_1 0x1E058100,0xFFFFFFFF

#define IPU_DC_DI1_CONF_2__ADDR                     0x1E058104
#define IPU_DC_DI1_CONF_2__EMPTY                    0x1E058104,0x00000000
#define IPU_DC_DI1_CONF_2__FULL                     0x1E058104,0xffffffff
#define IPU_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1 0x1E058104,0xFFFFFFFF

#define IPU_DC_MAP_CONF_0__ADDR                 0x1E058108
#define IPU_DC_MAP_CONF_0__EMPTY                0x1E058108,0x00000000
#define IPU_DC_MAP_CONF_0__FULL                 0x1E058108,0xffffffff
#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1 0x1E058108,0x7C000000
#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1 0x1E058108,0x03E00000
#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1 0x1E058108,0x001F0000
#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0 0x1E058108,0x00007C00
#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0 0x1E058108,0x000003E0
#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0 0x1E058108,0x0000001F

#define IPU_DC_MAP_CONF_1__ADDR                 0x1E05810C
#define IPU_DC_MAP_CONF_1__EMPTY                0x1E05810C,0x00000000
#define IPU_DC_MAP_CONF_1__FULL                 0x1E05810C,0xffffffff
#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3 0x1E05810C,0x7C000000
#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3 0x1E05810C,0x03E00000
#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3 0x1E05810C,0x001F0000
#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2 0x1E05810C,0x00007C00
#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2 0x1E05810C,0x000003E0
#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2 0x1E05810C,0x0000001F

#define IPU_DC_MAP_CONF_2__ADDR                 0x1E058110
#define IPU_DC_MAP_CONF_2__EMPTY                0x1E058110,0x00000000
#define IPU_DC_MAP_CONF_2__FULL                 0x1E058110,0xffffffff
#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5 0x1E058110,0x7C000000
#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5 0x1E058110,0x03E00000
#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5 0x1E058110,0x001F0000
#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4 0x1E058110,0x00007C00
#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4 0x1E058110,0x000003E0
#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4 0x1E058110,0x0000001F

#define IPU_DC_MAP_CONF_3__ADDR                 0x1E058114
#define IPU_DC_MAP_CONF_3__EMPTY                0x1E058114,0x00000000
#define IPU_DC_MAP_CONF_3__FULL                 0x1E058114,0xffffffff
#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7 0x1E058114,0x7C000000
#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7 0x1E058114,0x03E00000
#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7 0x1E058114,0x001F0000
#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6 0x1E058114,0x00007C00
#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6 0x1E058114,0x000003E0
#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6 0x1E058114,0x0000001F

#define IPU_DC_MAP_CONF_4__ADDR                 0x1E058118
#define IPU_DC_MAP_CONF_4__EMPTY                0x1E058118,0x00000000
#define IPU_DC_MAP_CONF_4__FULL                 0x1E058118,0xffffffff
#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9 0x1E058118,0x7C000000
#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9 0x1E058118,0x03E00000
#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9 0x1E058118,0x001F0000
#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8 0x1E058118,0x00007C00
#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8 0x1E058118,0x000003E0
#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8 0x1E058118,0x0000001F

#define IPU_DC_MAP_CONF_5__ADDR                  0x1E05811C
#define IPU_DC_MAP_CONF_5__EMPTY                 0x1E05811C,0x00000000
#define IPU_DC_MAP_CONF_5__FULL                  0x1E05811C,0xffffffff
#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11 0x1E05811C,0x7C000000
#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11 0x1E05811C,0x03E00000
#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11 0x1E05811C,0x001F0000
#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10 0x1E05811C,0x00007C00
#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10 0x1E05811C,0x000003E0
#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10 0x1E05811C,0x0000001F

#define IPU_DC_MAP_CONF_6__ADDR                  0x1E058120
#define IPU_DC_MAP_CONF_6__EMPTY                 0x1E058120,0x00000000
#define IPU_DC_MAP_CONF_6__FULL                  0x1E058120,0xffffffff
#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13 0x1E058120,0x7C000000
#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13 0x1E058120,0x03E00000
#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13 0x1E058120,0x001F0000
#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12 0x1E058120,0x00007C00
#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12 0x1E058120,0x000003E0
#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12 0x1E058120,0x0000001F

#define IPU_DC_MAP_CONF_7__ADDR                  0x1E058124
#define IPU_DC_MAP_CONF_7__EMPTY                 0x1E058124,0x00000000
#define IPU_DC_MAP_CONF_7__FULL                  0x1E058124,0xffffffff
#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15 0x1E058124,0x7C000000
#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15 0x1E058124,0x03E00000
#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15 0x1E058124,0x001F0000
#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14 0x1E058124,0x00007C00
#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14 0x1E058124,0x000003E0
#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14 0x1E058124,0x0000001F

#define IPU_DC_MAP_CONF_8__ADDR                  0x1E058128
#define IPU_DC_MAP_CONF_8__EMPTY                 0x1E058128,0x00000000
#define IPU_DC_MAP_CONF_8__FULL                  0x1E058128,0xffffffff
#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17 0x1E058128,0x7C000000
#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17 0x1E058128,0x03E00000
#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17 0x1E058128,0x001F0000
#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16 0x1E058128,0x00007C00
#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16 0x1E058128,0x000003E0
#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16 0x1E058128,0x0000001F

#define IPU_DC_MAP_CONF_9__ADDR                  0x1E05812C
#define IPU_DC_MAP_CONF_9__EMPTY                 0x1E05812C,0x00000000
#define IPU_DC_MAP_CONF_9__FULL                  0x1E05812C,0xffffffff
#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19 0x1E05812C,0x7C000000
#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19 0x1E05812C,0x03E00000
#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19 0x1E05812C,0x001F0000
#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18 0x1E05812C,0x00007C00
#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18 0x1E05812C,0x000003E0
#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18 0x1E05812C,0x0000001F

#define IPU_DC_MAP_CONF_10__ADDR                  0x1E058130
#define IPU_DC_MAP_CONF_10__EMPTY                 0x1E058130,0x00000000
#define IPU_DC_MAP_CONF_10__FULL                  0x1E058130,0xffffffff
#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21 0x1E058130,0x7C000000
#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21 0x1E058130,0x03E00000
#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21 0x1E058130,0x001F0000
#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20 0x1E058130,0x00007C00
#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20 0x1E058130,0x000003E0
#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20 0x1E058130,0x0000001F

#define IPU_DC_MAP_CONF_11__ADDR                  0x1E058134
#define IPU_DC_MAP_CONF_11__EMPTY                 0x1E058134,0x00000000
#define IPU_DC_MAP_CONF_11__FULL                  0x1E058134,0xffffffff
#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23 0x1E058134,0x7C000000
#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23 0x1E058134,0x03E00000
#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23 0x1E058134,0x001F0000
#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22 0x1E058134,0x00007C00
#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22 0x1E058134,0x000003E0
#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22 0x1E058134,0x0000001F

#define IPU_DC_MAP_CONF_12__ADDR                  0x1E058138
#define IPU_DC_MAP_CONF_12__EMPTY                 0x1E058138,0x00000000
#define IPU_DC_MAP_CONF_12__FULL                  0x1E058138,0xffffffff
#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25 0x1E058138,0x7C000000
#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25 0x1E058138,0x03E00000
#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25 0x1E058138,0x001F0000
#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24 0x1E058138,0x00007C00
#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24 0x1E058138,0x000003E0
#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24 0x1E058138,0x0000001F

#define IPU_DC_MAP_CONF_13__ADDR                  0x1E05813C
#define IPU_DC_MAP_CONF_13__EMPTY                 0x1E05813C,0x00000000
#define IPU_DC_MAP_CONF_13__FULL                  0x1E05813C,0xffffffff
#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27 0x1E05813C,0x7C000000
#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27 0x1E05813C,0x03E00000
#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27 0x1E05813C,0x001F0000
#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26 0x1E05813C,0x00007C00
#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26 0x1E05813C,0x000003E0
#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26 0x1E05813C,0x0000001F

#define IPU_DC_MAP_CONF_14__ADDR                  0x1E058140
#define IPU_DC_MAP_CONF_14__EMPTY                 0x1E058140,0x00000000
#define IPU_DC_MAP_CONF_14__FULL                  0x1E058140,0xffffffff
#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29 0x1E058140,0x7C000000
#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29 0x1E058140,0x03E00000
#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29 0x1E058140,0x001F0000
#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28 0x1E058140,0x00007C00
#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28 0x1E058140,0x000003E0
#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28 0x1E058140,0x0000001F

#define IPU_DC_MAP_CONF_15__ADDR        0x1E058144
#define IPU_DC_MAP_CONF_15__EMPTY       0x1E058144,0x00000000
#define IPU_DC_MAP_CONF_15__FULL        0x1E058144,0xffffffff
#define IPU_DC_MAP_CONF_15__MD_OFFSET_1 0x1E058144,0x1F000000
#define IPU_DC_MAP_CONF_15__MD_MASK_1   0x1E058144,0x00FF0000
#define IPU_DC_MAP_CONF_15__MD_OFFSET_0 0x1E058144,0x00001F00
#define IPU_DC_MAP_CONF_15__MD_MASK_0   0x1E058144,0x000000FF

#define IPU_DC_MAP_CONF_16__ADDR        0x1E058148
#define IPU_DC_MAP_CONF_16__EMPTY       0x1E058148,0x00000000
#define IPU_DC_MAP_CONF_16__FULL        0x1E058148,0xffffffff
#define IPU_DC_MAP_CONF_16__MD_OFFSET_3 0x1E058148,0x1F000000
#define IPU_DC_MAP_CONF_16__MD_MASK_3   0x1E058148,0x00FF0000
#define IPU_DC_MAP_CONF_16__MD_OFFSET_2 0x1E058148,0x00001F00
#define IPU_DC_MAP_CONF_16__MD_MASK_2   0x1E058148,0x000000FF

#define IPU_DC_MAP_CONF_17__ADDR        0x1E05814C
#define IPU_DC_MAP_CONF_17__EMPTY       0x1E05814C,0x00000000
#define IPU_DC_MAP_CONF_17__FULL        0x1E05814C,0xffffffff
#define IPU_DC_MAP_CONF_17__MD_OFFSET_5 0x1E05814C,0x1F000000
#define IPU_DC_MAP_CONF_17__MD_MASK_5   0x1E05814C,0x00FF0000
#define IPU_DC_MAP_CONF_17__MD_OFFSET_4 0x1E05814C,0x00001F00
#define IPU_DC_MAP_CONF_17__MD_MASK_4   0x1E05814C,0x000000FF

#define IPU_DC_MAP_CONF_18__ADDR        0x1E058150
#define IPU_DC_MAP_CONF_18__EMPTY       0x1E058150,0x00000000
#define IPU_DC_MAP_CONF_18__FULL        0x1E058150,0xffffffff
#define IPU_DC_MAP_CONF_18__MD_OFFSET_7 0x1E058150,0x1F000000
#define IPU_DC_MAP_CONF_18__MD_MASK_7   0x1E058150,0x00FF0000
#define IPU_DC_MAP_CONF_18__MD_OFFSET_6 0x1E058150,0x00001F00
#define IPU_DC_MAP_CONF_18__MD_MASK_6   0x1E058150,0x000000FF

#define IPU_DC_MAP_CONF_19__ADDR        0x1E058154
#define IPU_DC_MAP_CONF_19__EMPTY       0x1E058154,0x00000000
#define IPU_DC_MAP_CONF_19__FULL        0x1E058154,0xffffffff
#define IPU_DC_MAP_CONF_19__MD_OFFSET_9 0x1E058154,0x1F000000
#define IPU_DC_MAP_CONF_19__MD_MASK_9   0x1E058154,0x00FF0000
#define IPU_DC_MAP_CONF_19__MD_OFFSET_8 0x1E058154,0x00001F00
#define IPU_DC_MAP_CONF_19__MD_MASK_8   0x1E058154,0x000000FF

#define IPU_DC_MAP_CONF_20__ADDR         0x1E058158
#define IPU_DC_MAP_CONF_20__EMPTY        0x1E058158,0x00000000
#define IPU_DC_MAP_CONF_20__FULL         0x1E058158,0xffffffff
#define IPU_DC_MAP_CONF_20__MD_OFFSET_11 0x1E058158,0x1F000000
#define IPU_DC_MAP_CONF_20__MD_MASK_11   0x1E058158,0x00FF0000
#define IPU_DC_MAP_CONF_20__MD_OFFSET_10 0x1E058158,0x00001F00
#define IPU_DC_MAP_CONF_20__MD_MASK_10   0x1E058158,0x000000FF

#define IPU_DC_MAP_CONF_21__ADDR         0x1E05815C
#define IPU_DC_MAP_CONF_21__EMPTY        0x1E05815C,0x00000000
#define IPU_DC_MAP_CONF_21__FULL         0x1E05815C,0xffffffff
#define IPU_DC_MAP_CONF_21__MD_OFFSET_13 0x1E05815C,0x1F000000
#define IPU_DC_MAP_CONF_21__MD_MASK_13   0x1E05815C,0x00FF0000
#define IPU_DC_MAP_CONF_21__MD_OFFSET_12 0x1E05815C,0x00001F00
#define IPU_DC_MAP_CONF_21__MD_MASK_12   0x1E05815C,0x000000FF

#define IPU_DC_MAP_CONF_22__ADDR         0x1E058160
#define IPU_DC_MAP_CONF_22__EMPTY        0x1E058160,0x00000000
#define IPU_DC_MAP_CONF_22__FULL         0x1E058160,0xffffffff
#define IPU_DC_MAP_CONF_22__MD_OFFSET_15 0x1E058160,0x1F000000
#define IPU_DC_MAP_CONF_22__MD_MASK_15   0x1E058160,0x00FF0000
#define IPU_DC_MAP_CONF_22__MD_OFFSET_14 0x1E058160,0x00001F00
#define IPU_DC_MAP_CONF_22__MD_MASK_14   0x1E058160,0x000000FF

#define IPU_DC_MAP_CONF_23__ADDR         0x1E058164
#define IPU_DC_MAP_CONF_23__EMPTY        0x1E058164,0x00000000
#define IPU_DC_MAP_CONF_23__FULL         0x1E058164,0xffffffff
#define IPU_DC_MAP_CONF_23__MD_OFFSET_17 0x1E058164,0x1F000000
#define IPU_DC_MAP_CONF_23__MD_MASK_17   0x1E058164,0x00FF0000
#define IPU_DC_MAP_CONF_23__MD_OFFSET_16 0x1E058164,0x00001F00
#define IPU_DC_MAP_CONF_23__MD_MASK_16   0x1E058164,0x000000FF

#define IPU_DC_MAP_CONF_24__ADDR         0x1E058168
#define IPU_DC_MAP_CONF_24__EMPTY        0x1E058168,0x00000000
#define IPU_DC_MAP_CONF_24__FULL         0x1E058168,0xffffffff
#define IPU_DC_MAP_CONF_24__MD_OFFSET_19 0x1E058168,0x1F000000
#define IPU_DC_MAP_CONF_24__MD_MASK_19   0x1E058168,0x00FF0000
#define IPU_DC_MAP_CONF_24__MD_OFFSET_18 0x1E058168,0x00001F00
#define IPU_DC_MAP_CONF_24__MD_MASK_18   0x1E058168,0x000000FF

#define IPU_DC_MAP_CONF_25__ADDR         0x1E05816C
#define IPU_DC_MAP_CONF_25__EMPTY        0x1E05816C,0x00000000
#define IPU_DC_MAP_CONF_25__FULL         0x1E05816C,0xffffffff
#define IPU_DC_MAP_CONF_25__MD_OFFSET_21 0x1E05816C,0x1F000000
#define IPU_DC_MAP_CONF_25__MD_MASK_21   0x1E05816C,0x00FF0000
#define IPU_DC_MAP_CONF_25__MD_OFFSET_20 0x1E05816C,0x00001F00
#define IPU_DC_MAP_CONF_25__MD_MASK_20   0x1E05816C,0x000000FF

#define IPU_DC_MAP_CONF_26__ADDR         0x1E058170
#define IPU_DC_MAP_CONF_26__EMPTY        0x1E058170,0x00000000
#define IPU_DC_MAP_CONF_26__FULL         0x1E058170,0xffffffff
#define IPU_DC_MAP_CONF_26__MD_OFFSET_23 0x1E058170,0x1F000000
#define IPU_DC_MAP_CONF_26__MD_MASK_23   0x1E058170,0x00FF0000
#define IPU_DC_MAP_CONF_26__MD_OFFSET_22 0x1E058170,0x00001F00
#define IPU_DC_MAP_CONF_26__MD_MASK_22   0x1E058170,0x000000FF

#define IPU_DC_UGDE0_0__ADDR              0x1E058174
#define IPU_DC_UGDE0_0__EMPTY             0x1E058174,0x00000000
#define IPU_DC_UGDE0_0__FULL              0x1E058174,0xffffffff
#define IPU_DC_UGDE0_0__NF_NL_0           0x1E058174,0x18000000
#define IPU_DC_UGDE0_0__AUTORESTART_0     0x1E058174,0x04000000
#define IPU_DC_UGDE0_0__ODD_EN_0          0x1E058174,0x02000000
#define IPU_DC_UGDE0_0__COD_ODD_START_0   0x1E058174,0x00FF0000
#define IPU_DC_UGDE0_0__COD_EV_START_0    0x1E058174,0x0000FF00
#define IPU_DC_UGDE0_0__COD_EV_PRIORITY_0 0x1E058174,0x00000078
#define IPU_DC_UGDE0_0__ID_CODED_0        0x1E058174,0x00000007

#define IPU_DC_UGDE0_1__ADDR   0x1E058178
#define IPU_DC_UGDE0_1__EMPTY  0x1E058178,0x00000000
#define IPU_DC_UGDE0_1__FULL   0x1E058178,0xffffffff
#define IPU_DC_UGDE0_1__STEP_0 0x1E058178,0x1FFFFFFF

#define IPU_DC_UGDE0_2__ADDR        0x1E05817C
#define IPU_DC_UGDE0_2__EMPTY       0x1E05817C,0x00000000
#define IPU_DC_UGDE0_2__FULL        0x1E05817C,0xffffffff
#define IPU_DC_UGDE0_2__OFFSET_DT_0 0x1E05817C,0x1FFFFFFF

#define IPU_DC_UGDE0_3__ADDR          0x1E058180
#define IPU_DC_UGDE0_3__EMPTY         0x1E058180,0x00000000
#define IPU_DC_UGDE0_3__FULL          0x1E058180,0xffffffff
#define IPU_DC_UGDE0_3__STEP_REPEAT_0 0x1E058180,0x1FFFFFFF

#define IPU_DC_UGDE1_0__ADDR              0x1E058184
#define IPU_DC_UGDE1_0__EMPTY             0x1E058184,0x00000000
#define IPU_DC_UGDE1_0__FULL              0x1E058184,0xffffffff
#define IPU_DC_UGDE1_0__NF_NL_1           0x1E058184,0x18000000
#define IPU_DC_UGDE1_0__AUTORESTART_1     0x1E058184,0x04000000
#define IPU_DC_UGDE1_0__ODD_EN_1          0x1E058184,0x02000000
#define IPU_DC_UGDE1_0__COD_ODD_START_1   0x1E058184,0x00FF0000
#define IPU_DC_UGDE1_0__COD_EV_START_1    0x1E058184,0x00007F80
#define IPU_DC_UGDE1_0__COD_EV_PRIORITY_1 0x1E058184,0x00000078
#define IPU_DC_UGDE1_0__ID_CODED_1        0x1E058184,0x00000007

#define IPU_DC_UGDE1_1__ADDR   0x1E058188
#define IPU_DC_UGDE1_1__EMPTY  0x1E058188,0x00000000
#define IPU_DC_UGDE1_1__FULL   0x1E058188,0xffffffff
#define IPU_DC_UGDE1_1__STEP_1 0x1E058188,0x1FFFFFFF

#define IPU_DC_UGDE1_2__ADDR        0x1E05818C
#define IPU_DC_UGDE1_2__EMPTY       0x1E05818C,0x00000000
#define IPU_DC_UGDE1_2__FULL        0x1E05818C,0xffffffff
#define IPU_DC_UGDE1_2__OFFSET_DT_1 0x1E05818C,0x1FFFFFFF

#define IPU_DC_UGDE1_3__ADDR          0x1E058190
#define IPU_DC_UGDE1_3__EMPTY         0x1E058190,0x00000000
#define IPU_DC_UGDE1_3__FULL          0x1E058190,0xffffffff
#define IPU_DC_UGDE1_3__STEP_REPEAT_1 0x1E058190,0x1FFFFFFF

#define IPU_DC_UGDE2_0__ADDR              0x1E058194
#define IPU_DC_UGDE2_0__EMPTY             0x1E058194,0x00000000
#define IPU_DC_UGDE2_0__FULL              0x1E058194,0xffffffff
#define IPU_DC_UGDE2_0__NF_NL_2           0x1E058194,0x18000000
#define IPU_DC_UGDE2_0__AUTORESTART_2     0x1E058194,0x04000000
#define IPU_DC_UGDE2_0__ODD_EN_2          0x1E058194,0x02000000
#define IPU_DC_UGDE2_0__COD_ODD_START_2   0x1E058194,0x00FF0000
#define IPU_DC_UGDE2_0__COD_EV_START_2    0x1E058194,0x00007F80
#define IPU_DC_UGDE2_0__COD_EV_PRIORITY_2 0x1E058194,0x00000078
#define IPU_DC_UGDE2_0__ID_CODED_2        0x1E058194,0x00000007

#define IPU_DC_UGDE2_1__ADDR   0x1E058198
#define IPU_DC_UGDE2_1__EMPTY  0x1E058198,0x00000000
#define IPU_DC_UGDE2_1__FULL   0x1E058198,0xffffffff
#define IPU_DC_UGDE2_1__STEP_2 0x1E058198,0x1FFFFFFF

#define IPU_DC_UGDE2_2__ADDR        0x1E05819C
#define IPU_DC_UGDE2_2__EMPTY       0x1E05819C,0x00000000
#define IPU_DC_UGDE2_2__FULL        0x1E05819C,0xffffffff
#define IPU_DC_UGDE2_2__OFFSET_DT_2 0x1E05819C,0x1FFFFFFF

#define IPU_DC_UGDE2_3__ADDR          0x1E0581A0
#define IPU_DC_UGDE2_3__EMPTY         0x1E0581A0,0x00000000
#define IPU_DC_UGDE2_3__FULL          0x1E0581A0,0xffffffff
#define IPU_DC_UGDE2_3__STEP_REPEAT_2 0x1E0581A0,0x1FFFFFFF

#define IPU_DC_UGDE3_0__ADDR              0x1E0581A4
#define IPU_DC_UGDE3_0__EMPTY             0x1E0581A4,0x00000000
#define IPU_DC_UGDE3_0__FULL              0x1E0581A4,0xffffffff
#define IPU_DC_UGDE3_0__NF_NL_3           0x1E0581A4,0x18000000
#define IPU_DC_UGDE3_0__AUTORESTART_3     0x1E0581A4,0x04000000
#define IPU_DC_UGDE3_0__ODD_EN_3          0x1E0581A4,0x02000000
#define IPU_DC_UGDE3_0__COD_ODD_START_3   0x1E0581A4,0x00FF0000
#define IPU_DC_UGDE3_0__COD_EV_START_3    0x1E0581A4,0x00007F80
#define IPU_DC_UGDE3_0__COD_EV_PRIORITY_3 0x1E0581A4,0x00000078
#define IPU_DC_UGDE3_0__ID_CODED_3        0x1E0581A4,0x00000007

#define IPU_DC_UGDE3_1__ADDR   0x1E0581A8
#define IPU_DC_UGDE3_1__EMPTY  0x1E0581A8,0x00000000
#define IPU_DC_UGDE3_1__FULL   0x1E0581A8,0xffffffff
#define IPU_DC_UGDE3_1__STEP_3 0x1E0581A8,0x1FFFFFFF

#define IPU_DC_UGDE3_2__ADDR        0x1E0581AC
#define IPU_DC_UGDE3_2__EMPTY       0x1E0581AC,0x00000000
#define IPU_DC_UGDE3_2__FULL        0x1E0581AC,0xffffffff
#define IPU_DC_UGDE3_2__OFFSET_DT_3 0x1E0581AC,0x1FFFFFFF

#define IPU_DC_UGDE3_3__ADDR          0x1E0581B0
#define IPU_DC_UGDE3_3__EMPTY         0x1E0581B0,0x00000000
#define IPU_DC_UGDE3_3__FULL          0x1E0581B0,0xffffffff
#define IPU_DC_UGDE3_3__STEP_REPEAT_3 0x1E0581B0,0x1FFFFFFF

#define IPU_DC_LLA0__ADDR       0x1E0581B4
#define IPU_DC_LLA0__EMPTY      0x1E0581B4,0x00000000
#define IPU_DC_LLA0__FULL       0x1E0581B4,0xffffffff
#define IPU_DC_LLA0__MCU_RS_3_0 0x1E0581B4,0xFF000000
#define IPU_DC_LLA0__MCU_RS_2_0 0x1E0581B4,0x00FF0000
#define IPU_DC_LLA0__MCU_RS_1_0 0x1E0581B4,0x0000FF00
#define IPU_DC_LLA0__MCU_RS_0_0 0x1E0581B4,0x000000FF

#define IPU_DC_LLA1__ADDR       0x1E0581B8
#define IPU_DC_LLA1__EMPTY      0x1E0581B8,0x00000000
#define IPU_DC_LLA1__FULL       0x1E0581B8,0xffffffff
#define IPU_DC_LLA1__MCU_RS_3_1 0x1E0581B8,0xFF000000
#define IPU_DC_LLA1__MCU_RS_2_1 0x1E0581B8,0x00FF0000
#define IPU_DC_LLA1__MCU_RS_1_1 0x1E0581B8,0x0000FF00
#define IPU_DC_LLA1__MCU_RS_0_1 0x1E0581B8,0x000000FF

#define IPU_DC_R_LLA0__ADDR         0x1E0581BC
#define IPU_DC_R_LLA0__EMPTY        0x1E0581BC,0x00000000
#define IPU_DC_R_LLA0__FULL         0x1E0581BC,0xffffffff
#define IPU_DC_R_LLA0__MCU_RS_R_3_0 0x1E0581BC,0xFF000000
#define IPU_DC_R_LLA0__MCU_RS_R_2_0 0x1E0581BC,0x00FF0000
#define IPU_DC_R_LLA0__MCU_RS_R_1_0 0x1E0581BC,0x0000FF00
#define IPU_DC_R_LLA0__MCU_RS_R_0_0 0x1E0581BC,0x000000FF

#define IPU_DC_R_LLA1__ADDR         0x1E0581C0
#define IPU_DC_R_LLA1__EMPTY        0x1E0581C0,0x00000000
#define IPU_DC_R_LLA1__FULL         0x1E0581C0,0xffffffff
#define IPU_DC_R_LLA1__MCU_RS_R_3_1 0x1E0581C0,0xFF000000
#define IPU_DC_R_LLA1__MCU_RS_R_2_1 0x1E0581C0,0x00FF0000
#define IPU_DC_R_LLA1__MCU_RS_R_1_1 0x1E0581C0,0x0000FF00
#define IPU_DC_R_LLA1__MCU_RS_R_0_1 0x1E0581C0,0x000000FF

#define IPU_DC_WR_CH_ADDR_5_ALT__ADDR          0x1E0581C4
#define IPU_DC_WR_CH_ADDR_5_ALT__EMPTY         0x1E0581C4,0x00000000
#define IPU_DC_WR_CH_ADDR_5_ALT__FULL          0x1E0581C4,0xffffffff
#define IPU_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT 0x1E0581C4,0x1FFFFFFF

#define IPU_DC_STAT__ADDR                       0x1E0581C8
#define IPU_DC_STAT__EMPTY                      0x1E0581C8,0x00000000
#define IPU_DC_STAT__FULL                       0x1E0581C8,0xffffffff
#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_1 0x1E0581C8,0x00000080
#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_1  0x1E0581C8,0x00000040
#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_1  0x1E0581C8,0x00000020
#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_1   0x1E0581C8,0x00000010
#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_0 0x1E0581C8,0x00000008
#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_0  0x1E0581C8,0x00000004
#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_0  0x1E0581C8,0x00000002
#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_0   0x1E0581C8,0x00000001
// ================= End of IPUV3EX DC Registers =====================

// ================= Start of IPUV3EX DMFC Registers =====================
#define IPU_DMFC_RD_CHAN__ADDR              0x1E060000
#define IPU_DMFC_RD_CHAN__EMPTY             0x1E060000,0x00000000
#define IPU_DMFC_RD_CHAN__FULL              0x1E060000,0xffffffff
#define IPU_DMFC_RD_CHAN__DMFC_PPW_C        0x1E060000,0x03000000
#define IPU_DMFC_RD_CHAN__DMFC_WM_CLR_0     0x1E060000,0x00E00000
#define IPU_DMFC_RD_CHAN__DMFC_WM_SET_0     0x1E060000,0x001C0000
#define IPU_DMFC_RD_CHAN__DMFC_WM_EN_0      0x1E060000,0x00020000
#define IPU_DMFC_RD_CHAN__DMFC_BURST_SIZE_0 0x1E060000,0x000000C0

#define IPU_DMFC_WR_CHAN__ADDR               0x1E060004
#define IPU_DMFC_WR_CHAN__EMPTY              0x1E060004,0x00000000
#define IPU_DMFC_WR_CHAN__FULL               0x1E060004,0xffffffff
#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C 0x1E060004,0xC0000000
#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C  0x1E060004,0x38000000
#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2C    0x1E060004,0x07000000
#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C 0x1E060004,0x00C00000
#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C  0x1E060004,0x00380000
#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1C    0x1E060004,0x00070000
#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2  0x1E060004,0x0000C000
#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2   0x1E060004,0x00003800
#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2     0x1E060004,0x00000700
#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1  0x1E060004,0x000000C0
#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1   0x1E060004,0x00000038
#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1     0x1E060004,0x00000007

#define IPU_DMFC_WR_CHAN_DEF__ADDR           0x1E060008
#define IPU_DMFC_WR_CHAN_DEF__EMPTY          0x1E060008,0x00000000
#define IPU_DMFC_WR_CHAN_DEF__FULL           0x1E060008,0xffffffff
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C 0x1E060008,0xE0000000
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C 0x1E060008,0x1C000000
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C  0x1E060008,0x02000000
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C 0x1E060008,0x00E00000
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C 0x1E060008,0x001C0000
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C  0x1E060008,0x00020000
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2  0x1E060008,0x0000E000
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2  0x1E060008,0x00001C00
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2   0x1E060008,0x00000200
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1  0x1E060008,0x000000E0
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1  0x1E060008,0x0000001C
#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1   0x1E060008,0x00000002

#define IPU_DMFC_DP_CHAN__ADDR               0x1E06000C
#define IPU_DMFC_DP_CHAN__EMPTY              0x1E06000C,0x00000000
#define IPU_DMFC_DP_CHAN__FULL               0x1E06000C,0xffffffff
#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F 0x1E06000C,0xC0000000
#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F  0x1E06000C,0x38000000
#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6F    0x1E06000C,0x07000000
#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B 0x1E06000C,0x00C00000
#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B  0x1E06000C,0x00380000
#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6B    0x1E06000C,0x00070000
#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F 0x1E06000C,0x0000C000
#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F  0x1E06000C,0x00003800
#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5F    0x1E06000C,0x00000700
#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B 0x1E06000C,0x000000C0
#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B  0x1E06000C,0x00000038
#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5B    0x1E06000C,0x00000007

#define IPU_DMFC_DP_CHAN_DEF__ADDR           0x1E060010
#define IPU_DMFC_DP_CHAN_DEF__EMPTY          0x1E060010,0x00000000
#define IPU_DMFC_DP_CHAN_DEF__FULL           0x1E060010,0xffffffff
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F 0x1E060010,0xE0000000
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F 0x1E060010,0x1C000000
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F  0x1E060010,0x02000000
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B 0x1E060010,0x00E00000
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B 0x1E060010,0x001C0000
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B  0x1E060010,0x00020000
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F 0x1E060010,0x0000E000
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F 0x1E060010,0x00001C00
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F  0x1E060010,0x00000200
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B 0x1E060010,0x000000E0
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B 0x1E060010,0x0000001C
#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B  0x1E060010,0x00000002

#define IPU_DMFC_GENERAL1__ADDR              0x1E060014
#define IPU_DMFC_GENERAL1__EMPTY             0x1E060014,0x00000000
#define IPU_DMFC_GENERAL1__FULL              0x1E060014,0xffffffff
#define IPU_DMFC_GENERAL1__WAIT4EOT_9        0x1E060014,0x01000000
#define IPU_DMFC_GENERAL1__WAIT4EOT_6F       0x1E060014,0x00800000
#define IPU_DMFC_GENERAL1__WAIT4EOT_6B       0x1E060014,0x00400000
#define IPU_DMFC_GENERAL1__WAIT4EOT_5F       0x1E060014,0x00200000
#define IPU_DMFC_GENERAL1__WAIT4EOT_5B       0x1E060014,0x00100000
#define IPU_DMFC_GENERAL1__WAIT4EOT_4        0x1E060014,0x00080000
#define IPU_DMFC_GENERAL1__WAIT4EOT_3        0x1E060014,0x00040000
#define IPU_DMFC_GENERAL1__WAIT4EOT_2        0x1E060014,0x00020000
#define IPU_DMFC_GENERAL1__WAIT4EOT_1        0x1E060014,0x00010000
#define IPU_DMFC_GENERAL1__DMFC_WM_CLR_9     0x1E060014,0x0000E000
#define IPU_DMFC_GENERAL1__DMFC_WM_SET_9     0x1E060014,0x00001C00
#define IPU_DMFC_GENERAL1__DMFC_WM_EN_9      0x1E060014,0x00000200
#define IPU_DMFC_GENERAL1__DMFC_BURST_SIZE_9 0x1E060014,0x00000060
#define IPU_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR 0x1E060014,0x00000003

#define IPU_DMFC_GENERAL2__ADDR                 0x1E060018
#define IPU_DMFC_GENERAL2__EMPTY                0x1E060018,0x00000000
#define IPU_DMFC_GENERAL2__FULL                 0x1E060018,0xffffffff
#define IPU_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD 0x1E060018,0x1FFF0000
#define IPU_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD  0x1E060018,0x00001FFF

#define IPU_DMFC_IC_CTRL__ADDR                    0x1E06001C
#define IPU_DMFC_IC_CTRL__EMPTY                   0x1E06001C,0x00000000
#define IPU_DMFC_IC_CTRL__FULL                    0x1E06001C,0xffffffff
#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD 0x1E06001C,0xFFF80000
#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD  0x1E06001C,0x0007FFC0
#define IPU_DMFC_IC_CTRL__DMFC_IC_PPW_C           0x1E06001C,0x00000030
#define IPU_DMFC_IC_CTRL__DMFC_IC_IN_PORT         0x1E06001C,0x00000007

#define IPU_DMFC_WR_CHAN_ALT__ADDR                  0x1E060020
#define IPU_DMFC_WR_CHAN_ALT__EMPTY                 0x1E060020,0x00000000
#define IPU_DMFC_WR_CHAN_ALT__FULL                  0x1E060020,0xffffffff
#define IPU_DMFC_WR_CHAN_ALT__DMFC_BURST_SIZE_2_ALT 0x1E060020,0x0000C000
#define IPU_DMFC_WR_CHAN_ALT__DMFC_FIFO_SIZE_2_ALT  0x1E060020,0x00003800
#define IPU_DMFC_WR_CHAN_ALT__DMFC_ST_ADDR_2_ALT    0x1E060020,0x00000700

#define IPU_DMFC_WR_CHAN_DEF_ALT__ADDR              0x1E060024
#define IPU_DMFC_WR_CHAN_DEF_ALT__EMPTY             0x1E060024,0x00000000
#define IPU_DMFC_WR_CHAN_DEF_ALT__FULL              0x1E060024,0xffffffff
#define IPU_DMFC_WR_CHAN_DEF_ALT__DMFC_WM_CLR_2_ALT 0x1E060024,0x0000E000
#define IPU_DMFC_WR_CHAN_DEF_ALT__DMFC_WM_SET_2_ALT 0x1E060024,0x00001C00
#define IPU_DMFC_WR_CHAN_DEF_ALT__DMFC_WM_EN_2_ALT  0x1E060024,0x00000200

#define IPU_DMFC_DP_CHAN_ALT__ADDR                   0x1E060028
#define IPU_DMFC_DP_CHAN_ALT__EMPTY                  0x1E060028,0x00000000
#define IPU_DMFC_DP_CHAN_ALT__FULL                   0x1E060028,0xffffffff
#define IPU_DMFC_DP_CHAN_ALT__DMFC_BURST_SIZE_6F_ALT 0x1E060028,0xC0000000
#define IPU_DMFC_DP_CHAN_ALT__DMFC_FIFO_SIZE_6F_ALT  0x1E060028,0x38000000
#define IPU_DMFC_DP_CHAN_ALT__DMFC_ST_ADDR_6F_ALT    0x1E060028,0x07000000
#define IPU_DMFC_DP_CHAN_ALT__DMFC_BURST_SIZE_6B_ALT 0x1E060028,0x00C00000
#define IPU_DMFC_DP_CHAN_ALT__DMFC_FIFO_SIZE_6B_ALT  0x1E060028,0x00380000
#define IPU_DMFC_DP_CHAN_ALT__DMFC_ST_ADDR_6B_ALT    0x1E060028,0x00070000
#define IPU_DMFC_DP_CHAN_ALT__DMFC_BURST_SIZE_5B_ALT 0x1E060028,0x000000C0
#define IPU_DMFC_DP_CHAN_ALT__DMFC_FIFO_SIZE_5B_ALT  0x1E060028,0x00000038
#define IPU_DMFC_DP_CHAN_ALT__DMFC_ST_ADDR_5B_ALT    0x1E060028,0x00000007

#define IPU_DMFC_DP_CHAN_DEF_ALT__ADDR               0x1E06002C
#define IPU_DMFC_DP_CHAN_DEF_ALT__EMPTY              0x1E06002C,0x00000000
#define IPU_DMFC_DP_CHAN_DEF_ALT__FULL               0x1E06002C,0xffffffff
#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_CLR_6F_ALT 0x1E06002C,0xE0000000
#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_SET_6F_ALT 0x1E06002C,0x1C000000
#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_EN_6F_ALT  0x1E06002C,0x02000000
#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_CLR_6B_ALT 0x1E06002C,0x00E00000
#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_SET_6B_ALT 0x1E06002C,0x001C0000
#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_EN_6B_ALT  0x1E06002C,0x00020000
#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_CLR_5B_ALT 0x1E06002C,0x000000E0
#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_SET_5B_ALT 0x1E06002C,0x0000001C
#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_EN_5B_ALT  0x1E06002C,0x00000002

#define IPU_DMFC_GENERAL1_ALT__ADDR            0x1E060030
#define IPU_DMFC_GENERAL1_ALT__EMPTY           0x1E060030,0x00000000
#define IPU_DMFC_GENERAL1_ALT__FULL            0x1E060030,0xffffffff
#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_6F_ALT 0x1E060030,0x00800000
#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_6B_ALT 0x1E060030,0x00400000
#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_5B_ALT 0x1E060030,0x00100000
#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_2_ALT  0x1E060030,0x00020000

#define IPU_DMFC_STAT__ADDR                 0x1E060034
#define IPU_DMFC_STAT__EMPTY                0x1E060034,0x00000000
#define IPU_DMFC_STAT__FULL                 0x1E060034,0xffffffff
#define IPU_DMFC_STAT__DMFC_IC_BUFFER_EMPTY 0x1E060034,0x02000000
#define IPU_DMFC_STAT__DMFC_IC_BUFFER_FULL  0x1E060034,0x01000000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_11   0x1E060034,0x00800000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_10   0x1E060034,0x00400000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_9    0x1E060034,0x00200000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_8    0x1E060034,0x00100000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_7    0x1E060034,0x00080000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_6    0x1E060034,0x00040000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_5    0x1E060034,0x00020000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_4    0x1E060034,0x00010000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_3    0x1E060034,0x00008000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_2    0x1E060034,0x00004000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_1    0x1E060034,0x00002000
#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_0    0x1E060034,0x00001000
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_11    0x1E060034,0x00000800
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_10    0x1E060034,0x00000400
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_9     0x1E060034,0x00000200
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_8     0x1E060034,0x00000100
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_7     0x1E060034,0x00000080
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_6     0x1E060034,0x00000040
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_5     0x1E060034,0x00000020
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_4     0x1E060034,0x00000010
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_3     0x1E060034,0x00000008
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_2     0x1E060034,0x00000004
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_1     0x1E060034,0x00000002
#define IPU_DMFC_STAT__DMFC_FIFO_FULL_0     0x1E060034,0x00000001
// ================= End of IPUV3EX DMFC Registers =====================

// ================= Start of IPUV3EX CPMEM Registers =====================
#define CPMEM_WORD0_DATA0_INT__ADDR  0x1F000000
#define CPMEM_WORD0_DATA0_INT__EMPTY 0x1F000000,0x00000000
#define CPMEM_WORD0_DATA0_INT__FULL  0x1F000000,0xffffffff
#define CPMEM_WORD0_DATA0_INT__XB    0x1F000000,0xFFF80000
#define CPMEM_WORD0_DATA0_INT__YV    0x1F000000,0x0007FC00
#define CPMEM_WORD0_DATA0_INT__XV    0x1F000000,0x000003FF

#define CPMEM_WORD0_DATA1_INT__ADDR   0x1F000004
#define CPMEM_WORD0_DATA1_INT__EMPTY  0x1F000004,0x00000000
#define CPMEM_WORD0_DATA1_INT__FULL   0x1F000004,0xffffffff
#define CPMEM_WORD0_DATA1_INT__SY_LOW 0x1F000004,0xFC000000
#define CPMEM_WORD0_DATA1_INT__SX     0x1F000004,0x03FFC000
#define CPMEM_WORD0_DATA1_INT__CF     0x1F000004,0x00002000
#define CPMEM_WORD0_DATA1_INT__NSB_B  0x1F000004,0x00001000
#define CPMEM_WORD0_DATA1_INT__YB     0x1F000004,0x00000FFF

#define CPMEM_WORD0_DATA2_INT__ADDR    0x1F000008
#define CPMEM_WORD0_DATA2_INT__EMPTY   0x1F000008,0x00000000
#define CPMEM_WORD0_DATA2_INT__FULL    0x1F000008,0xffffffff
#define CPMEM_WORD0_DATA2_INT__SM      0x1F000008,0xFFC00000
#define CPMEM_WORD0_DATA2_INT__SDX     0x1F000008,0x003F8000
#define CPMEM_WORD0_DATA2_INT__NS      0x1F000008,0x00007FE0
#define CPMEM_WORD0_DATA2_INT__SY_HIGH 0x1F000008,0x0000001F

#define CPMEM_WORD0_DATA3_INT__ADDR    0x1F00000C
#define CPMEM_WORD0_DATA3_INT__EMPTY   0x1F00000C,0x00000000
#define CPMEM_WORD0_DATA3_INT__FULL    0x1F00000C,0xffffffff
#define CPMEM_WORD0_DATA3_INT__FW_LOW  0x1F00000C,0xE0000000
#define CPMEM_WORD0_DATA3_INT__CAE     0x1F00000C,0x10000000
#define CPMEM_WORD0_DATA3_INT__CAP     0x1F00000C,0x08000000
#define CPMEM_WORD0_DATA3_INT__THE     0x1F00000C,0x04000000
#define CPMEM_WORD0_DATA3_INT__VF      0x1F00000C,0x02000000
#define CPMEM_WORD0_DATA3_INT__HF      0x1F00000C,0x01000000
#define CPMEM_WORD0_DATA3_INT__ROT     0x1F00000C,0x00800000
#define CPMEM_WORD0_DATA3_INT__BM      0x1F00000C,0x00600000
#define CPMEM_WORD0_DATA3_INT__BNDM    0x1F00000C,0x001C0000
#define CPMEM_WORD0_DATA3_INT__SO      0x1F00000C,0x00020000
#define CPMEM_WORD0_DATA3_INT__DIM     0x1F00000C,0x00010000
#define CPMEM_WORD0_DATA3_INT__DEC_SEL 0x1F00000C,0x0000C000
#define CPMEM_WORD0_DATA3_INT__BPP     0x1F00000C,0x00003800
#define CPMEM_WORD0_DATA3_INT__SDRY    0x1F00000C,0x00000400
#define CPMEM_WORD0_DATA3_INT__SDRX    0x1F00000C,0x00000200
#define CPMEM_WORD0_DATA3_INT__SDY     0x1F00000C,0x000001FC
#define CPMEM_WORD0_DATA3_INT__SCE     0x1F00000C,0x00000002
#define CPMEM_WORD0_DATA3_INT__SCC     0x1F00000C,0x00000001

#define CPMEM_WORD0_DATA4_INT__ADDR     0x1F000010
#define CPMEM_WORD0_DATA4_INT__EMPTY    0x1F000010,0x00000000
#define CPMEM_WORD0_DATA4_INT__FULL     0x1F000010,0xffffffff
#define CPMEM_WORD0_DATA4_INT__RESERVED 0x1F000010,0xFFC00000
#define CPMEM_WORD0_DATA4_INT__FH       0x1F000010,0x003FFC00
#define CPMEM_WORD0_DATA4_INT__FW_HIGH  0x1F000010,0x000003FF

#define CPMEM_WORD0_DATA0_N_INT__ADDR  0x1F000000
#define CPMEM_WORD0_DATA0_N_INT__EMPTY 0x1F000000,0x00000000
#define CPMEM_WORD0_DATA0_N_INT__FULL  0x1F000000,0xffffffff
#define CPMEM_WORD0_DATA0_N_INT__XB    0x1F000000,0xFFF80000
#define CPMEM_WORD0_DATA0_N_INT__YV    0x1F000000,0x0007FC00
#define CPMEM_WORD0_DATA0_N_INT__XV    0x1F000000,0x000003FF

#define CPMEM_WORD0_DATA1_N_INT__ADDR    0x1F000004
#define CPMEM_WORD0_DATA1_N_INT__EMPTY   0x1F000004,0x00000000
#define CPMEM_WORD0_DATA1_N_INT__FULL    0x1F000004,0xffffffff
#define CPMEM_WORD0_DATA1_N_INT__UBO_LOW 0x1F000004,0xFFFFC000
#define CPMEM_WORD0_DATA1_N_INT__CF      0x1F000004,0x00002000
#define CPMEM_WORD0_DATA1_N_INT__NSB_B   0x1F000004,0x00001000
#define CPMEM_WORD0_DATA1_N_INT__YB      0x1F000004,0x00000FFF

#define CPMEM_WORD0_DATA2_N_INT__ADDR     0x1F000008
#define CPMEM_WORD0_DATA2_N_INT__EMPTY    0x1F000008,0x00000000
#define CPMEM_WORD0_DATA2_N_INT__FULL     0x1F000008,0xffffffff
#define CPMEM_WORD0_DATA2_N_INT__RESERVED 0x1F000008,0xFC000000
#define CPMEM_WORD0_DATA2_N_INT__IOX      0x1F000008,0x3c000000
#define CPMEM_WORD0_DATA2_N_INT__VBO      0x1F000008,0x03FFFFF0
#define CPMEM_WORD0_DATA2_N_INT__UBO_HIGH 0x1F000008,0x0000000F

#define CPMEM_WORD0_DATA3_N_INT__ADDR     0x1F00000C
#define CPMEM_WORD0_DATA3_N_INT__EMPTY    0x1F00000C,0x00000000
#define CPMEM_WORD0_DATA3_N_INT__FULL     0x1F00000C,0xffffffff
#define CPMEM_WORD0_DATA3_N_INT__FW_LOW   0x1F00000C,0xE0000000
#define CPMEM_WORD0_DATA3_N_INT__CAE      0x1F00000C,0x10000000
#define CPMEM_WORD0_DATA3_N_INT__CAP      0x1F00000C,0x08000000
#define CPMEM_WORD0_DATA3_N_INT__THE      0x1F00000C,0x04000000
#define CPMEM_WORD0_DATA3_N_INT__VF       0x1F00000C,0x02000000
#define CPMEM_WORD0_DATA3_N_INT__HF       0x1F00000C,0x01000000
#define CPMEM_WORD0_DATA3_N_INT__ROT      0x1F00000C,0x00800000
#define CPMEM_WORD0_DATA3_N_INT__BM       0x1F00000C,0x00600000
#define CPMEM_WORD0_DATA3_N_INT__BNDM     0x1F00000C,0x001C0000
#define CPMEM_WORD0_DATA3_N_INT__SO       0x1F00000C,0x00020000
#define CPMEM_WORD0_DATA3_N_INT__RESERVED 0x1F00000C,0x0001FFFF

#define CPMEM_WORD0_DATA4_N_INT__ADDR     0x1F000010
#define CPMEM_WORD0_DATA4_N_INT__EMPTY    0x1F000010,0x00000000
#define CPMEM_WORD0_DATA4_N_INT__FULL     0x1F000010,0xffffffff
#define CPMEM_WORD0_DATA4_N_INT__RESERVED 0x1F000010,0xFFC00000
#define CPMEM_WORD0_DATA4_N_INT__FH       0x1F000010,0x003FFC00
#define CPMEM_WORD0_DATA4_N_INT__FW_HIGH  0x1F000010,0x000003FF

#define CPMEM_WORD1_DATA0_INT__ADDR     0x1F000020
#define CPMEM_WORD1_DATA0_INT__EMPTY    0x1F000020,0x00000000
#define CPMEM_WORD1_DATA0_INT__FULL     0x1F000020,0xffffffff
#define CPMEM_WORD1_DATA0_INT__EBA1_LOW 0x1F000020,0xE0000000
#define CPMEM_WORD1_DATA0_INT__EBA0     0x1F000020,0x1FFFFFFF

#define CPMEM_WORD1_DATA1_INT__ADDR      0x1F000024
#define CPMEM_WORD1_DATA1_INT__EMPTY     0x1F000024,0x00000000
#define CPMEM_WORD1_DATA1_INT__FULL      0x1F000024,0xffffffff
#define CPMEM_WORD1_DATA1_INT__ILO_LOW   0x1F000024,0xFC000000
#define CPMEM_WORD1_DATA1_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF

#define CPMEM_WORD1_DATA2_INT__ADDR     0x1F000028
#define CPMEM_WORD1_DATA2_INT__EMPTY    0x1F000028,0x00000000
#define CPMEM_WORD1_DATA2_INT__FULL     0x1F000028,0xffffffff
#define CPMEM_WORD1_DATA2_INT__TH_LOW   0x1F000028,0x80000000
#define CPMEM_WORD1_DATA2_INT__ID       0x1F000028,0x60000000
#define CPMEM_WORD1_DATA2_INT__ALBM     0x1F000028,0x1C000000
#define CPMEM_WORD1_DATA2_INT__ALU      0x1F000028,0x02000000
#define CPMEM_WORD1_DATA2_INT__PFS      0x1F000028,0x01E00000
#define CPMEM_WORD1_DATA2_INT__NPB      0x1F000028,0x001FC000
#define CPMEM_WORD1_DATA2_INT__ILO_HIGH 0x1F000028,0x00003FFF

#define CPMEM_WORD1_DATA3_INT__ADDR    0x1F00002C
#define CPMEM_WORD1_DATA3_INT__EMPTY   0x1F00002C,0x00000000
#define CPMEM_WORD1_DATA3_INT__FULL    0x1F00002C,0xffffffff
#define CPMEM_WORD1_DATA3_INT__WID3    0x1F00002C,0xE0000000
#define CPMEM_WORD1_DATA3_INT__WID2    0x1F00002C,0x1C000000
#define CPMEM_WORD1_DATA3_INT__WID1    0x1F00002C,0x03800000
#define CPMEM_WORD1_DATA3_INT__WID0    0x1F00002C,0x00700000
#define CPMEM_WORD1_DATA3_INT__SL      0x1F00002C,0x000FFFC0
#define CPMEM_WORD1_DATA3_INT__TH_HIGH 0x1F00002C,0x0000003F

#define CPMEM_WORD1_DATA4_INT__ADDR     0x1F000030
#define CPMEM_WORD1_DATA4_INT__EMPTY    0x1F000030,0x00000000
#define CPMEM_WORD1_DATA4_INT__FULL     0x1F000030,0xffffffff
#define CPMEM_WORD1_DATA4_INT__RESERVED 0x1F000030,0xFFF00000
#define CPMEM_WORD1_DATA4_INT__SXYS     0x1F000030,0x00100000
#define CPMEM_WORD1_DATA4_INT__OFS3     0x1F000030,0x000F8000
#define CPMEM_WORD1_DATA4_INT__OFS2     0x1F000030,0x00007C00
#define CPMEM_WORD1_DATA4_INT__OFS1     0x1F000030,0x000003E0
#define CPMEM_WORD1_DATA4_INT__OFS0     0x1F000030,0x0000001F

#define CPMEM_WORD1_DATA0_N_INT__ADDR     0x1F000020
#define CPMEM_WORD1_DATA0_N_INT__EMPTY    0x1F000020,0x00000000
#define CPMEM_WORD1_DATA0_N_INT__FULL     0x1F000020,0xffffffff
#define CPMEM_WORD1_DATA0_N_INT__EBA1_LOW 0x1F000020,0xE0000000
#define CPMEM_WORD1_DATA0_N_INT__EBA0     0x1F000020,0x1FFFFFFF

#define CPMEM_WORD1_DATA1_N_INT__ADDR      0x1F000024
#define CPMEM_WORD1_DATA1_N_INT__EMPTY     0x1F000024,0x00000000
#define CPMEM_WORD1_DATA1_N_INT__FULL      0x1F000024,0xffffffff
#define CPMEM_WORD1_DATA1_N_INT__ILO_LOW   0x1F000024,0xFC000000
#define CPMEM_WORD1_DATA1_N_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF

#define CPMEM_WORD1_DATA2_N_INT__ADDR     0x1F000028
#define CPMEM_WORD1_DATA2_N_INT__EMPTY    0x1F000028,0x00000000
#define CPMEM_WORD1_DATA2_N_INT__FULL     0x1F000028,0xffffffff
#define CPMEM_WORD1_DATA2_N_INT__TH_LOW   0x1F000028,0x80000000
#define CPMEM_WORD1_DATA2_N_INT__ID       0x1F000028,0x60000000
#define CPMEM_WORD1_DATA2_N_INT__ALBM     0x1F000028,0x1C000000
#define CPMEM_WORD1_DATA2_N_INT__ALU      0x1F000028,0x02000000
#define CPMEM_WORD1_DATA2_N_INT__PFS      0x1F000028,0x01E00000
#define CPMEM_WORD1_DATA2_N_INT__NPB      0x1F000028,0x001FC000
#define CPMEM_WORD1_DATA2_N_INT__ILO_HIGH 0x1F000028,0x00003FFF

#define CPMEM_WORD1_DATA3_N_INT__ADDR     0x1F00002C
#define CPMEM_WORD1_DATA3_N_INT__EMPTY    0x1F00002C,0x00000000
#define CPMEM_WORD1_DATA3_N_INT__FULL     0x1F00002C,0xffffffff
#define CPMEM_WORD1_DATA3_N_INT__SLY      0x1F00002C,0x000FFFC0
#define CPMEM_WORD1_DATA3_N_INT__WID3     0x1F00002C,0xE0000000
#define CPMEM_WORD1_DATA3_N_INT__TH_HIGH  0x1F00002C,0x0000003F

#define CPMEM_WORD1_DATA4_N_INT__ADDR      0x1F000030
#define CPMEM_WORD1_DATA4_N_INT__EMPTY     0x1F000030,0x00000000
#define CPMEM_WORD1_DATA4_N_INT__FULL      0x1F000030,0xffffffff
#define CPMEM_WORD1_DATA4_N_INT__RESERVED  0x1F000030,0xFFFFC000
#define CPMEM_WORD1_DATA4_N_INT__SLUV      0x1F000030,0x00003FFF
// ================= End of IPUV3EX CPMEM Registers =====================

#define IC_INTERNAL_MEM_FW 0x400
#define TASK1_TMP_COEF IC_INTERNAL_MEM_FW
#define TASK1_CSC1_W0    TASK1_TMP_COEF+1
#define TASK1_CSC1_W1    TASK1_CSC1_W0+1
#define TASK1_CSC1_W2    TASK1_CSC1_W1+1

#define IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR   0x1F060000 + (TASK1_CSC1_W0 << 3)
#define IPU_IC_TPMEM_ENC_CSC1_WORD0__EMPTY  IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x00000000
#define IPU_IC_TPMEM_ENC_CSC1_WORD0__FULL   IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xffffffff
#define IPU_IC_TPMEM_ENC_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xF8000000
#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C00    IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x07FC0000
#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C11    IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x0003FE00
#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C22    IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x000001FF

#define IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR     0x1F060000 + (TASK1_CSC1_W0 << 3) + 4
#define IPU_IC_TPMEM_ENC_CSC1_WORD1__EMPTY    IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000000
#define IPU_IC_TPMEM_ENC_CSC1_WORD1__FULL     IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0xffffffff
#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000400
#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SCALE    IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000300
#define IPU_IC_TPMEM_ENC_CSC1_WORD1__A0_HIGH  IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x000000FF

#define IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR   0x1F060000 + (TASK1_CSC1_W1 << 3)
#define IPU_IC_TPMEM_ENC_CSC1_WORD2__EMPTY  IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x00000000
#define IPU_IC_TPMEM_ENC_CSC1_WORD2__FULL   IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xffffffff
#define IPU_IC_TPMEM_ENC_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xF8000000
#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C01    IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x07FC0000
#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C10    IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x0003FE00
#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C20    IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x000001FF

#define IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR    0x1F060000 + (TASK1_CSC1_W1 << 3) + 4
#define IPU_IC_TPMEM_ENC_CSC1_WORD3__EMPTY   IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x00000000
#define IPU_IC_TPMEM_ENC_CSC1_WORD3__FULL    IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0xffffffff
#define IPU_IC_TPMEM_ENC_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x000000FF

#define IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR   0x1F060000 + (TASK1_CSC1_W2 << 3)
#define IPU_IC_TPMEM_ENC_CSC1_WORD4__EMPTY  IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x00000000
#define IPU_IC_TPMEM_ENC_CSC1_WORD4__FULL   IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xffffffff
#define IPU_IC_TPMEM_ENC_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xF8000000
#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C02    IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x07FC0000
#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C12    IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x0003FE00
#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C21    IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x000001FF

#define IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR    0x1F060000 + (TASK1_CSC1_W2 << 3) + 4
#define IPU_IC_TPMEM_ENC_CSC1_WORD5__EMPTY   IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x00000000
#define IPU_IC_TPMEM_ENC_CSC1_WORD5__FULL    IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0xffffffff
#define IPU_IC_TPMEM_ENC_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x000000FF

#define TASK2_TMP_COEF TASK1_CSC1_W2+IC_INTERNAL_MEM_FW+1
#define TASK2_CSC1_W0    TASK2_TMP_COEF+1
#define TASK2_CSC1_W1    TASK2_CSC1_W0+1
#define TASK2_CSC1_W2    TASK2_CSC1_W1+1
#define TASK2_CSC2_W0    TASK2_CSC1_W2+1
#define TASK2_CSC2_W1    TASK2_CSC2_W0+1
#define TASK2_CSC2_W2    TASK2_CSC2_W1+1

#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR   0x1F060000 + (TASK2_CSC1_W0 << 3)
#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__EMPTY  IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__FULL   IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xF8000000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C00    IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x07FC0000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C11    IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x0003FE00
#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C22    IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x000001FF

#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR     0x1F060000 + (TASK2_CSC1_W0 << 3) + 4
#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__EMPTY    IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__FULL     IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000400
#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SCALE    IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000300
#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__A0_HIGH  IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x000000FF

#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR   0x1F060000 + (TASK2_CSC1_W1 << 3)
#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__EMPTY  IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__FULL   IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xF8000000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C01    IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x07FC0000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C10    IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x0003FE00
#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C20    IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x000001FF

#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR    0x1F060000 + (TASK2_CSC1_W1 << 3) + 4
#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__EMPTY   IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__FULL    IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x000000FF

#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR   0x1F060000 + (TASK2_CSC1_W2 << 3)
#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__EMPTY  IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__FULL   IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xF8000000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C02    IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x07FC0000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C12    IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x0003FE00
#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C21    IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x000001FF

#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR    0x1F060000 + (TASK2_CSC1_W2 << 3) + 4
#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__EMPTY   IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__FULL    IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x000000FF

#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR   0x1F060000 + (TASK2_CSC2_W0 << 3)
#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__EMPTY  IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__FULL   IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xF8000000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C00    IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x07FC0000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C11    IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x0003FE00
#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C22    IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x000001FF

#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR     0x1F060000 + (TASK2_CSC2_W0 << 3) + 4
#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__EMPTY    IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__FULL     IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000400
#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SCALE    IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000300
#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__A0_HIGH  IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x000000FF

#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR   0x1F060000 + (TASK2_CSC2_W1 << 3)
#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__EMPTY  IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__FULL   IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xF8000000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C01    IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x07FC0000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C10    IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x0003FE00
#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C20    IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x000001FF

#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR    0x1F060000 + (TASK2_CSC2_W1 << 3) + 4
#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__EMPTY   IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__FULL    IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x000000FF

#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR   0x1F060000 + (TASK2_CSC2_W2 << 3)
#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__EMPTY  IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__FULL   IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xF8000000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C02    IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x07FC0000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C12    IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x0003FE00
#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C21    IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x000001FF

#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR    0x1F060000 + (TASK2_CSC2_W2 << 3) + 4
#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__EMPTY   IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x00000000
#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__FULL    IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0xffffffff
#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x000000FF

#define TASK3_TMP_COEF TASK2_CSC2_W2+IC_INTERNAL_MEM_FW+1
#define TASK3_CSC1_W0    TASK3_TMP_COEF+1
#define TASK3_CSC1_W1    TASK3_CSC1_W0+1
#define TASK3_CSC1_W2    TASK3_CSC1_W1+1
#define TASK3_CSC2_W0    TASK3_CSC1_W2+1
#define TASK3_CSC2_W1    TASK3_CSC2_W0+1
#define TASK3_CSC2_W2    TASK3_CSC2_W1+1

#define IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR   0x1F060000 + (TASK3_CSC1_W0 << 3)
#define IPU_IC_TPMEM_POST_CSC1_WORD0__EMPTY  IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC1_WORD0__FULL   IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xF8000000
#define IPU_IC_TPMEM_POST_CSC1_WORD0__C00    IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x07FC0000
#define IPU_IC_TPMEM_POST_CSC1_WORD0__C11    IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x0003FE00
#define IPU_IC_TPMEM_POST_CSC1_WORD0__C22    IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x000001FF

#define IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR     0x1F060000 + (TASK3_CSC1_W0 << 3) + 4
#define IPU_IC_TPMEM_POST_CSC1_WORD1__EMPTY    IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC1_WORD1__FULL     IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000400
#define IPU_IC_TPMEM_POST_CSC1_WORD1__SCALE    IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000300
#define IPU_IC_TPMEM_POST_CSC1_WORD1__A0_HIGH  IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x000000FF

#define IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR   0x1F060000 + (TASK3_CSC1_W1 << 3)
#define IPU_IC_TPMEM_POST_CSC1_WORD2__EMPTY  IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC1_WORD2__FULL   IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xF8000000
#define IPU_IC_TPMEM_POST_CSC1_WORD2__C01    IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x07FC0000
#define IPU_IC_TPMEM_POST_CSC1_WORD2__C10    IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x0003FE00
#define IPU_IC_TPMEM_POST_CSC1_WORD2__C20    IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x000001FF

#define IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR    0x1F060000 + (TASK3_CSC1_W1 << 3) + 4
#define IPU_IC_TPMEM_POST_CSC1_WORD3__EMPTY   IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC1_WORD3__FULL    IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x000000FF

#define IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR   0x1F060000 + (TASK3_CSC1_W2 << 3)
#define IPU_IC_TPMEM_POST_CSC1_WORD4__EMPTY  IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC1_WORD4__FULL   IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xF8000000
#define IPU_IC_TPMEM_POST_CSC1_WORD4__C02    IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x07FC0000
#define IPU_IC_TPMEM_POST_CSC1_WORD4__C12    IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x0003FE00
#define IPU_IC_TPMEM_POST_CSC1_WORD4__C21    IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x000001FF

#define IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR    0x1F060000 + (TASK3_CSC1_W2 << 3) + 4
#define IPU_IC_TPMEM_POST_CSC1_WORD5__EMPTY   IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC1_WORD5__FULL    IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x000000FF

#define IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR   0x1F060000 + (TASK3_CSC2_W0 << 3)
#define IPU_IC_TPMEM_POST_CSC2_WORD0__EMPTY  IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC2_WORD0__FULL   IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xF8000000
#define IPU_IC_TPMEM_POST_CSC2_WORD0__C00    IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x07FC0000
#define IPU_IC_TPMEM_POST_CSC2_WORD0__C11    IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x0003FE00
#define IPU_IC_TPMEM_POST_CSC2_WORD0__C22    IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x000001FF

#define IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR     0x1F060000 + (TASK3_CSC2_W0 << 3) + 4
#define IPU_IC_TPMEM_POST_CSC2_WORD1__EMPTY    IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC2_WORD1__FULL     IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000400
#define IPU_IC_TPMEM_POST_CSC2_WORD1__SCALE    IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000300
#define IPU_IC_TPMEM_POST_CSC2_WORD1__A0_HIGH  IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x000000FF

#define IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR   0x1F060000 + (TASK3_CSC2_W1 << 3)
#define IPU_IC_TPMEM_POST_CSC2_WORD2__EMPTY  IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC2_WORD2__FULL   IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xF8000000
#define IPU_IC_TPMEM_POST_CSC2_WORD2__C01    IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x07FC0000
#define IPU_IC_TPMEM_POST_CSC2_WORD2__C10    IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x0003FE00
#define IPU_IC_TPMEM_POST_CSC2_WORD2__C20    IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x000001FF

#define IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR    0x1F060000 + (TASK3_CSC2_W1 << 3) + 4
#define IPU_IC_TPMEM_POST_CSC2_WORD3__EMPTY   IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC2_WORD3__FULL    IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x000000FF

#define IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR   0x1F060000 + (TASK3_CSC2_W2 << 3)
#define IPU_IC_TPMEM_POST_CSC2_WORD4__EMPTY  IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC2_WORD4__FULL   IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xF8000000
#define IPU_IC_TPMEM_POST_CSC2_WORD4__C02    IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x07FC0000
#define IPU_IC_TPMEM_POST_CSC2_WORD4__C12    IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x0003FE00
#define IPU_IC_TPMEM_POST_CSC2_WORD4__C21    IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x000001FF

#define IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR    0x1F060000 + (TASK3_CSC2_W2 << 3) + 4
#define IPU_IC_TPMEM_POST_CSC2_WORD5__EMPTY   IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x00000000
#define IPU_IC_TPMEM_POST_CSC2_WORD5__FULL    IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0xffffffff
#define IPU_IC_TPMEM_POST_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x000000FF

#define SRM_DP_COM_CONF_SYNC__ADDR                     0x1F040000
#define SRM_DP_COM_CONF_SYNC__EMPTY                    0x1F040000,0x00000000
#define SRM_DP_COM_CONF_SYNC__FULL                     0x1F040000,0xffffffff
#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC     0x1F040000,0x00002000
#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC         0x1F040000,0x00001000
#define SRM_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1F040000,0x00000800
#define SRM_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1F040000,0x00000400
#define SRM_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC          0x1F040000,0x00000300
#define SRM_DP_COM_CONF_SYNC__DP_COC_SYNC              0x1F040000,0x00000070
#define SRM_DP_COM_CONF_SYNC__DP_GWCKE_SYNC            0x1F040000,0x00000008
#define SRM_DP_COM_CONF_SYNC__DP_GWAM_SYNC             0x1F040000,0x00000004
#define SRM_DP_COM_CONF_SYNC__DP_GWSEL_SYNC            0x1F040000,0x00000002
#define SRM_DP_COM_CONF_SYNC__DP_FG_EN_SYNC            0x1F040000,0x00000001

#define SRM_DP_GRAPH_WIND_CTRL_SYNC__ADDR          0x1F040004
#define SRM_DP_GRAPH_WIND_CTRL_SYNC__EMPTY         0x1F040004,0x00000000
#define SRM_DP_GRAPH_WIND_CTRL_SYNC__FULL          0x1F040004,0xffffffff
#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC  0x1F040004,0xFF000000
#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1F040004,0x00FF0000
#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1F040004,0x0000FF00
#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1F040004,0x000000FF

#define SRM_DP_FG_POS_SYNC__ADDR         0x1F040008
#define SRM_DP_FG_POS_SYNC__EMPTY        0x1F040008,0x00000000
#define SRM_DP_FG_POS_SYNC__FULL         0x1F040008,0xffffffff
#define SRM_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1F040008,0x07FF0000
#define SRM_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1F040008,0x000007FF

#define SRM_DP_CUR_POS_SYNC__ADDR        0x1F04000C
#define SRM_DP_CUR_POS_SYNC__EMPTY       0x1F04000C,0x00000000
#define SRM_DP_CUR_POS_SYNC__FULL        0x1F04000C,0xffffffff
#define SRM_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1F04000C,0xF8000000
#define SRM_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1F04000C,0x07FF0000
#define SRM_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1F04000C,0x0000F800
#define SRM_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1F04000C,0x000007FF

#define SRM_DP_CUR_MAP_SYNC__ADDR              0x1F040010
#define SRM_DP_CUR_MAP_SYNC__EMPTY             0x1F040010,0x00000000
#define SRM_DP_CUR_MAP_SYNC__FULL              0x1F040010,0xffffffff
#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1F040010,0x00FF0000
#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1F040010,0x0000FF00
#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1F040010,0x000000FF

#define SRM_DP_GAMMA_C_SYNC_0__ADDR              0x1F040014
#define SRM_DP_GAMMA_C_SYNC_0__EMPTY             0x1F040014,0x00000000
#define SRM_DP_GAMMA_C_SYNC_0__FULL              0x1F040014,0xffffffff
#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1F040014,0x01FF0000
#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1F040014,0x000001FF

#define SRM_DP_GAMMA_C_SYNC_1__ADDR              0x1F040018
#define SRM_DP_GAMMA_C_SYNC_1__EMPTY             0x1F040018,0x00000000
#define SRM_DP_GAMMA_C_SYNC_1__FULL              0x1F040018,0xffffffff
#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1F040018,0x01FF0000
#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1F040018,0x000001FF

#define SRM_DP_GAMMA_C_SYNC_2__ADDR              0x1F04001C
#define SRM_DP_GAMMA_C_SYNC_2__EMPTY             0x1F04001C,0x00000000
#define SRM_DP_GAMMA_C_SYNC_2__FULL              0x1F04001C,0xffffffff
#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1F04001C,0x01FF0000
#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1F04001C,0x000001FF

#define SRM_DP_GAMMA_C_SYNC_3__ADDR              0x1F040020
#define SRM_DP_GAMMA_C_SYNC_3__EMPTY             0x1F040020,0x00000000
#define SRM_DP_GAMMA_C_SYNC_3__FULL              0x1F040020,0xffffffff
#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1F040020,0x01FF0000
#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1F040020,0x000001FF

#define SRM_DP_GAMMA_C_SYNC_4__ADDR              0x1F040024
#define SRM_DP_GAMMA_C_SYNC_4__EMPTY             0x1F040024,0x00000000
#define SRM_DP_GAMMA_C_SYNC_4__FULL              0x1F040024,0xffffffff
#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1F040024,0x01FF0000
#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1F040024,0x000001FF

#define SRM_DP_GAMMA_C_SYNC_5__ADDR               0x1F040028
#define SRM_DP_GAMMA_C_SYNC_5__EMPTY              0x1F040028,0x00000000
#define SRM_DP_GAMMA_C_SYNC_5__FULL               0x1F040028,0xffffffff
#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1F040028,0x01FF0000
#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1F040028,0x000001FF

#define SRM_DP_GAMMA_C_SYNC_6__ADDR               0x1F04002C
#define SRM_DP_GAMMA_C_SYNC_6__EMPTY              0x1F04002C,0x00000000
#define SRM_DP_GAMMA_C_SYNC_6__FULL               0x1F04002C,0xffffffff
#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1F04002C,0x01FF0000
#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1F04002C,0x000001FF

#define SRM_DP_GAMMA_C_SYNC_7__ADDR               0x1F040030
#define SRM_DP_GAMMA_C_SYNC_7__EMPTY              0x1F040030,0x00000000
#define SRM_DP_GAMMA_C_SYNC_7__FULL               0x1F040030,0xffffffff
#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1F040030,0x01FF0000
#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1F040030,0x000001FF

#define SRM_DP_GAMMA_S_SYNC_0__ADDR              0x1F040034
#define SRM_DP_GAMMA_S_SYNC_0__EMPTY             0x1F040034,0x00000000
#define SRM_DP_GAMMA_S_SYNC_0__FULL              0x1F040034,0xffffffff
#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1F040034,0xFF000000
#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1F040034,0x00FF0000
#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1F040034,0x0000FF00
#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1F040034,0x000000FF

#define SRM_DP_GAMMA_S_SYNC_1__ADDR              0x1F040038
#define SRM_DP_GAMMA_S_SYNC_1__EMPTY             0x1F040038,0x00000000
#define SRM_DP_GAMMA_S_SYNC_1__FULL              0x1F040038,0xffffffff
#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1F040038,0xFF000000
#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1F040038,0x00FF0000
#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1F040038,0x0000FF00
#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1F040038,0x000000FF

#define SRM_DP_GAMMA_S_SYNC_2__ADDR               0x1F04003C
#define SRM_DP_GAMMA_S_SYNC_2__EMPTY              0x1F04003C,0x00000000
#define SRM_DP_GAMMA_S_SYNC_2__FULL               0x1F04003C,0xffffffff
#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1F04003C,0xFF000000
#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1F04003C,0x00FF0000
#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9  0x1F04003C,0x0000FF00
#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8  0x1F04003C,0x000000FF

#define SRM_DP_GAMMA_S_SYNC_3__ADDR               0x1F040040
#define SRM_DP_GAMMA_S_SYNC_3__EMPTY              0x1F040040,0x00000000
#define SRM_DP_GAMMA_S_SYNC_3__FULL               0x1F040040,0xffffffff
#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1F040040,0xFF000000
#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1F040040,0x00FF0000
#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1F040040,0x0000FF00
#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1F040040,0x000000FF

#define SRM_DP_CSCA_SYNC_0__ADDR            0x1F040044
#define SRM_DP_CSCA_SYNC_0__EMPTY           0x1F040044,0x00000000
#define SRM_DP_CSCA_SYNC_0__FULL            0x1F040044,0xffffffff
#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1F040044,0x03FF0000
#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1F040044,0x000003FF

#define SRM_DP_CSCA_SYNC_1__ADDR            0x1F040048
#define SRM_DP_CSCA_SYNC_1__EMPTY           0x1F040048,0x00000000
#define SRM_DP_CSCA_SYNC_1__FULL            0x1F040048,0xffffffff
#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1F040048,0x03FF0000
#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1F040048,0x000003FF

#define SRM_DP_CSCA_SYNC_2__ADDR            0x1F04004C
#define SRM_DP_CSCA_SYNC_2__EMPTY           0x1F04004C,0x00000000
#define SRM_DP_CSCA_SYNC_2__FULL            0x1F04004C,0xffffffff
#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1F04004C,0x03FF0000
#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1F04004C,0x000003FF

#define SRM_DP_CSCA_SYNC_3__ADDR            0x1F040050
#define SRM_DP_CSCA_SYNC_3__EMPTY           0x1F040050,0x00000000
#define SRM_DP_CSCA_SYNC_3__FULL            0x1F040050,0xffffffff
#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1F040050,0x03FF0000
#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1F040050,0x000003FF

#define SRM_DP_CSC_SYNC_0__ADDR           0x1F040054
#define SRM_DP_CSC_SYNC_0__EMPTY          0x1F040054,0x00000000
#define SRM_DP_CSC_SYNC_0__FULL           0x1F040054,0xffffffff
#define SRM_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1F040054,0xC0000000
#define SRM_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1F040054,0x3FFF0000
#define SRM_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1F040054,0x000003FF

#define SRM_DP_CSC_SYNC_1__ADDR           0x1F040058
#define SRM_DP_CSC_SYNC_1__EMPTY          0x1F040058,0x00000000
#define SRM_DP_CSC_SYNC_1__FULL           0x1F040058,0xffffffff
#define SRM_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1F040058,0xC0000000
#define SRM_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1F040058,0x3FFF0000
#define SRM_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1F040058,0x0000C000
#define SRM_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1F040058,0x00003FFF

#define SRM_DP_CUR_POS_ALT__ADDR            0x1F04005C
#define SRM_DP_CUR_POS_ALT__EMPTY           0x1F04005C,0x00000000
#define SRM_DP_CUR_POS_ALT__FULL            0x1F04005C,0xffffffff
#define SRM_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1F04005C,0xF8000000
#define SRM_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1F04005C,0x07FF0000
#define SRM_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1F04005C,0x0000F800
#define SRM_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1F04005C,0x000007FF

#define SRM_DP_COM_CONF_ASYNC0__ADDR                       0x1F040060
#define SRM_DP_COM_CONF_ASYNC0__EMPTY                      0x1F040060,0x00000000
#define SRM_DP_COM_CONF_ASYNC0__FULL                       0x1F040060,0xffffffff
#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_YUV_EN_ASYNC0     0x1F040060,0x00002000
#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_EN_ASYNC0         0x1F040060,0x00001000
#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_YUV_SAT_MODE_ASYNC0 0x1F040060,0x00000800
#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_GAMUT_SAT_EN_ASYNC0 0x1F040060,0x00000400
#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_DEF_ASYNC0          0x1F040060,0x00000300
#define SRM_DP_COM_CONF_ASYNC0__DP_COC_ASYNC0              0x1F040060,0x00000070
#define SRM_DP_COM_CONF_ASYNC0__DP_GWCKE_ASYNC0            0x1F040060,0x00000008
#define SRM_DP_COM_CONF_ASYNC0__DP_GWAM_ASYNC0             0x1F040060,0x00000004
#define SRM_DP_COM_CONF_ASYNC0__DP_GWSEL_ASYNC0            0x1F040060,0x00000002

#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__ADDR            0x1F040064
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__EMPTY           0x1F040064,0x00000000
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__FULL            0x1F040064,0xffffffff
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWAV_ASYNC0  0x1F040064,0xFF000000
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKR_ASYNC0 0x1F040064,0x00FF0000
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKG_ASYNC0 0x1F040064,0x0000FF00
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKB_ASYNC0 0x1F040064,0x000000FF

#define SRM_DP_FG_POS_ASYNC0__ADDR           0x1F040068
#define SRM_DP_FG_POS_ASYNC0__EMPTY          0x1F040068,0x00000000
#define SRM_DP_FG_POS_ASYNC0__FULL           0x1F040068,0xffffffff
#define SRM_DP_FG_POS_ASYNC0__DP_FGXP_ASYNC0 0x1F040068,0x07FF0000
#define SRM_DP_FG_POS_ASYNC0__DP_FGYP_ASYNC0 0x1F040068,0x000007FF

#define SRM_DP_CUR_POS_ASYNC0__ADDR          0x1F04006C
#define SRM_DP_CUR_POS_ASYNC0__EMPTY         0x1F04006C,0x00000000
#define SRM_DP_CUR_POS_ASYNC0__FULL          0x1F04006C,0xffffffff
#define SRM_DP_CUR_POS_ASYNC0__DP_CXW_ASYNC0 0x1F04006C,0xF8000000
#define SRM_DP_CUR_POS_ASYNC0__DP_CXP_ASYNC0 0x1F04006C,0x07FF0000
#define SRM_DP_CUR_POS_ASYNC0__DP_CYH_ASYNC0 0x1F04006C,0x0000F800
#define SRM_DP_CUR_POS_ASYNC0__DP_CYP_ASYNC0 0x1F04006C,0x000007FF

#define SRM_DP_CUR_MAP_ASYNC0__ADDR             0x1F040070
#define SRM_DP_CUR_MAP_ASYNC0__EMPTY            0x1F040070,0x00000000
#define SRM_DP_CUR_MAP_ASYNC0__FULL             0x1F040070,0xffffffff
#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_R_ASYNC0 0x1F040070,0x00FF0000
#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_G_ASYNC0 0x1F040070,0x0000FF00
#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_B_ASYNC0 0x1F040070,0x000000FF

#define SRM_DP_GAMMA_C_ASYNC0_0__ADDR                0x1F040074
#define SRM_DP_GAMMA_C_ASYNC0_0__EMPTY               0x1F040074,0x00000000
#define SRM_DP_GAMMA_C_ASYNC0_0__FULL                0x1F040074,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_1 0x1F040074,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_0 0x1F040074,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC0_1__ADDR                0x1F040078
#define SRM_DP_GAMMA_C_ASYNC0_1__EMPTY               0x1F040078,0x00000000
#define SRM_DP_GAMMA_C_ASYNC0_1__FULL                0x1F040078,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_3 0x1F040078,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_2 0x1F040078,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC0_2__ADDR                0x1F04007C
#define SRM_DP_GAMMA_C_ASYNC0_2__EMPTY               0x1F04007C,0x00000000
#define SRM_DP_GAMMA_C_ASYNC0_2__FULL                0x1F04007C,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_5 0x1F04007C,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_4 0x1F04007C,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC0_3__ADDR                0x1F040080
#define SRM_DP_GAMMA_C_ASYNC0_3__EMPTY               0x1F040080,0x00000000
#define SRM_DP_GAMMA_C_ASYNC0_3__FULL                0x1F040080,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_7 0x1F040080,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_6 0x1F040080,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC0_4__ADDR                0x1F040084
#define SRM_DP_GAMMA_C_ASYNC0_4__EMPTY               0x1F040084,0x00000000
#define SRM_DP_GAMMA_C_ASYNC0_4__FULL                0x1F040084,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_9 0x1F040084,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_8 0x1F040084,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC0_5__ADDR                 0x1F040088
#define SRM_DP_GAMMA_C_ASYNC0_5__EMPTY                0x1F040088,0x00000000
#define SRM_DP_GAMMA_C_ASYNC0_5__FULL                 0x1F040088,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_11 0x1F040088,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_10 0x1F040088,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC0_6__ADDR                 0x1F04008C
#define SRM_DP_GAMMA_C_ASYNC0_6__EMPTY                0x1F04008C,0x00000000
#define SRM_DP_GAMMA_C_ASYNC0_6__FULL                 0x1F04008C,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_13 0x1F04008C,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_12 0x1F04008C,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC0_7__ADDR                 0x1F040090
#define SRM_DP_GAMMA_C_ASYNC0_7__EMPTY                0x1F040090,0x00000000
#define SRM_DP_GAMMA_C_ASYNC0_7__FULL                 0x1F040090,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_15 0x1F040090,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_14 0x1F040090,0x000001FF

#define SRM_DP_GAMMA_S_ASYNC0_0__ADDR                0x1F040094
#define SRM_DP_GAMMA_S_ASYNC0_0__EMPTY               0x1F040094,0x00000000
#define SRM_DP_GAMMA_S_ASYNC0_0__FULL                0x1F040094,0xffffffff
#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_3 0x1F040094,0xFF000000
#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_2 0x1F040094,0x00FF0000
#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_1 0x1F040094,0x0000FF00
#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_0 0x1F040094,0x000000FF

#define SRM_DP_GAMMA_S_ASYNC0_1__ADDR                0x1F040098
#define SRM_DP_GAMMA_S_ASYNC0_1__EMPTY               0x1F040098,0x00000000
#define SRM_DP_GAMMA_S_ASYNC0_1__FULL                0x1F040098,0xffffffff
#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_7 0x1F040098,0xFF000000
#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_6 0x1F040098,0x00FF0000
#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_5 0x1F040098,0x0000FF00
#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_4 0x1F040098,0x000000FF

#define SRM_DP_GAMMA_S_ASYNC0_2__ADDR                 0x1F04009C
#define SRM_DP_GAMMA_S_ASYNC0_2__EMPTY                0x1F04009C,0x00000000
#define SRM_DP_GAMMA_S_ASYNC0_2__FULL                 0x1F04009C,0xffffffff
#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_11 0x1F04009C,0xFF000000
#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_10 0x1F04009C,0x00FF0000
#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_9  0x1F04009C,0x0000FF00
#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_8  0x1F04009C,0x000000FF

#define SRM_DP_GAMMA_S_ASYNC0_3__ADDR                 0x1F0400A0
#define SRM_DP_GAMMA_S_ASYNC0_3__EMPTY                0x1F0400A0,0x00000000
#define SRM_DP_GAMMA_S_ASYNC0_3__FULL                 0x1F0400A0,0xffffffff
#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_15 0x1F0400A0,0xFF000000
#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_14 0x1F0400A0,0x00FF0000
#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_13 0x1F0400A0,0x0000FF00
#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_12 0x1F0400A0,0x000000FF

#define SRM_DP_CSCA_ASYNC0_0__ADDR              0x1F0400A4
#define SRM_DP_CSCA_ASYNC0_0__EMPTY             0x1F0400A4,0x00000000
#define SRM_DP_CSCA_ASYNC0_0__FULL              0x1F0400A4,0xffffffff
#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_1 0x1F0400A4,0x03FF0000
#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_0 0x1F0400A4,0x000003FF

#define SRM_DP_CSCA_ASYNC0_1__ADDR              0x1F0400A8
#define SRM_DP_CSCA_ASYNC0_1__EMPTY             0x1F0400A8,0x00000000
#define SRM_DP_CSCA_ASYNC0_1__FULL              0x1F0400A8,0xffffffff
#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_3 0x1F0400A8,0x03FF0000
#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_2 0x1F0400A8,0x000003FF

#define SRM_DP_CSCA_ASYNC0_2__ADDR              0x1F0400AC
#define SRM_DP_CSCA_ASYNC0_2__EMPTY             0x1F0400AC,0x00000000
#define SRM_DP_CSCA_ASYNC0_2__FULL              0x1F0400AC,0xffffffff
#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_5 0x1F0400AC,0x03FF0000
#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_4 0x1F0400AC,0x000003FF

#define SRM_DP_CSCA_ASYNC0_3__ADDR              0x1F0400B0
#define SRM_DP_CSCA_ASYNC0_3__EMPTY             0x1F0400B0,0x00000000
#define SRM_DP_CSCA_ASYNC0_3__FULL              0x1F0400B0,0xffffffff
#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_7 0x1F0400B0,0x03FF0000
#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_6 0x1F0400B0,0x000003FF

#define SRM_DP_CSC_ASYNC0_0__ADDR             0x1F0400B4
#define SRM_DP_CSC_ASYNC0_0__EMPTY            0x1F0400B4,0x00000000
#define SRM_DP_CSC_ASYNC0_0__FULL             0x1F0400B4,0xffffffff
#define SRM_DP_CSC_ASYNC0_0__DP_CSC_S0_ASYNC0 0x1F0400B4,0xC0000000
#define SRM_DP_CSC_ASYNC0_0__DP_CSC_B0_ASYNC0 0x1F0400B4,0x3FFF0000
#define SRM_DP_CSC_ASYNC0_0__DP_CSC_A8_ASYNC0 0x1F0400B4,0x000003FF

#define SRM_DP_CSC_ASYNC0_1__ADDR             0x1F0400B8
#define SRM_DP_CSC_ASYNC0_1__EMPTY            0x1F0400B8,0x00000000
#define SRM_DP_CSC_ASYNC0_1__FULL             0x1F0400B8,0xffffffff
#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S2_ASYNC0 0x1F0400B8,0xC0000000
#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B2_ASYNC0 0x1F0400B8,0x3FFF0000
#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S1_ASYNC0 0x1F0400B8,0x0000C000
#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B1_ASYNC0 0x1F0400B8,0x00003FFF

#define SRM_DP_COM_CONF_ASYNC1__ADDR                       0x1F0400BC
#define SRM_DP_COM_CONF_ASYNC1__EMPTY                      0x1F0400BC,0x00000000
#define SRM_DP_COM_CONF_ASYNC1__FULL                       0x1F0400BC,0xffffffff
#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_YUV_EN_ASYNC1     0x1F0400BC,0x00002000
#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_EN_ASYNC1         0x1F0400BC,0x00001000
#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_YUV_SAT_MODE_ASYNC1 0x1F0400BC,0x00000800
#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_GAMUT_SAT_EN_ASYNC1 0x1F0400BC,0x00000400
#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_DEF_ASYNC1          0x1F0400BC,0x00000300
#define SRM_DP_COM_CONF_ASYNC1__DP_COC_ASYNC1              0x1F0400BC,0x00000070
#define SRM_DP_COM_CONF_ASYNC1__DP_GWCKE_ASYNC1            0x1F0400BC,0x00000008
#define SRM_DP_COM_CONF_ASYNC1__DP_GWAM_ASYNC1             0x1F0400BC,0x00000004
#define SRM_DP_COM_CONF_ASYNC1__DP_GWSEL_ASYNC1            0x1F0400BC,0x00000002

#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__ADDR            0x1F0400C0
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__EMPTY           0x1F0400C0,0x00000000
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__FULL            0x1F0400C0,0xffffffff
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWAV_ASYNC1  0x1F0400C0,0xFF000000
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKR_ASYNC1 0x1F0400C0,0x00FF0000
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKG_ASYNC1 0x1F0400C0,0x0000FF00
#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKB_ASYNC1 0x1F0400C0,0x000000FF

#define SRM_DP_FG_POS_ASYNC1__ADDR           0x1F0400C4
#define SRM_DP_FG_POS_ASYNC1__EMPTY          0x1F0400C4,0x00000000
#define SRM_DP_FG_POS_ASYNC1__FULL           0x1F0400C4,0xffffffff
#define SRM_DP_FG_POS_ASYNC1__DP_FGXP_ASYNC1 0x1F0400C4,0x07FF0000
#define SRM_DP_FG_POS_ASYNC1__DP_FGYP_ASYNC1 0x1F0400C4,0x000007FF

#define SRM_DP_CUR_POS_ASYNC1__ADDR          0x1F0400C8
#define SRM_DP_CUR_POS_ASYNC1__EMPTY         0x1F0400C8,0x00000000
#define SRM_DP_CUR_POS_ASYNC1__FULL          0x1F0400C8,0xffffffff
#define SRM_DP_CUR_POS_ASYNC1__DP_CXW_ASYNC1 0x1F0400C8,0xF8000000
#define SRM_DP_CUR_POS_ASYNC1__DP_CXP_ASYNC1 0x1F0400C8,0x07FF0000
#define SRM_DP_CUR_POS_ASYNC1__DP_CYH_ASYNC1 0x1F0400C8,0x0000F800
#define SRM_DP_CUR_POS_ASYNC1__DP_CYP_ASYNC1 0x1F0400C8,0x000007FF

#define SRM_DP_CUR_MAP_ASYNC1__ADDR             0x1F0400CC
#define SRM_DP_CUR_MAP_ASYNC1__EMPTY            0x1F0400CC,0x00000000
#define SRM_DP_CUR_MAP_ASYNC1__FULL             0x1F0400CC,0xffffffff
#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_R_ASYNC1 0x1F0400CC,0x00FF0000
#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_G_ASYNC1 0x1F0400CC,0x0000FF00
#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_B_ASYNC1 0x1F0400CC,0x000000FF

#define SRM_DP_GAMMA_C_ASYNC1_0__ADDR                0x1F0400D0
#define SRM_DP_GAMMA_C_ASYNC1_0__EMPTY               0x1F0400D0,0x00000000
#define SRM_DP_GAMMA_C_ASYNC1_0__FULL                0x1F0400D0,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_1 0x1F0400D0,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_0 0x1F0400D0,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC1_1__ADDR                0x1F0400D4
#define SRM_DP_GAMMA_C_ASYNC1_1__EMPTY               0x1F0400D4,0x00000000
#define SRM_DP_GAMMA_C_ASYNC1_1__FULL                0x1F0400D4,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_3 0x1F0400D4,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_2 0x1F0400D4,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC1_2__ADDR                0x1F0400D8
#define SRM_DP_GAMMA_C_ASYNC1_2__EMPTY               0x1F0400D8,0x00000000
#define SRM_DP_GAMMA_C_ASYNC1_2__FULL                0x1F0400D8,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_5 0x1F0400D8,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_4 0x1F0400D8,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC1_3__ADDR                0x1F0400DC
#define SRM_DP_GAMMA_C_ASYNC1_3__EMPTY               0x1F0400DC,0x00000000
#define SRM_DP_GAMMA_C_ASYNC1_3__FULL                0x1F0400DC,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_7 0x1F0400DC,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_6 0x1F0400DC,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC1_4__ADDR                0x1F0400E0
#define SRM_DP_GAMMA_C_ASYNC1_4__EMPTY               0x1F0400E0,0x00000000
#define SRM_DP_GAMMA_C_ASYNC1_4__FULL                0x1F0400E0,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_9 0x1F0400E0,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_8 0x1F0400E0,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC1_5__ADDR                 0x1F0400E4
#define SRM_DP_GAMMA_C_ASYNC1_5__EMPTY                0x1F0400E4,0x00000000
#define SRM_DP_GAMMA_C_ASYNC1_5__FULL                 0x1F0400E4,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_11 0x1F0400E4,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_10 0x1F0400E4,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC1_6__ADDR                 0x1F0400E8
#define SRM_DP_GAMMA_C_ASYNC1_6__EMPTY                0x1F0400E8,0x00000000
#define SRM_DP_GAMMA_C_ASYNC1_6__FULL                 0x1F0400E8,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_13 0x1F0400E8,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_12 0x1F0400E8,0x000001FF

#define SRM_DP_GAMMA_C_ASYNC1_7__ADDR                 0x1F0400EC
#define SRM_DP_GAMMA_C_ASYNC1_7__EMPTY                0x1F0400EC,0x00000000
#define SRM_DP_GAMMA_C_ASYNC1_7__FULL                 0x1F0400EC,0xffffffff
#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_15 0x1F0400EC,0x01FF0000
#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_14 0x1F0400EC,0x000001FF

#define SRM_DP_GAMMA_S_ASYNC1_0__ADDR                0x1F0400F0
#define SRM_DP_GAMMA_S_ASYNC1_0__EMPTY               0x1F0400F0,0x00000000
#define SRM_DP_GAMMA_S_ASYNC1_0__FULL                0x1F0400F0,0xffffffff
#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_3 0x1F0400F0,0xFF000000
#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_2 0x1F0400F0,0x00FF0000
#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_1 0x1F0400F0,0x0000FF00
#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_0 0x1F0400F0,0x000000FF

#define SRM_DP_GAMMA_S_ASYNC1_1__ADDR                0x1F0400F4
#define SRM_DP_GAMMA_S_ASYNC1_1__EMPTY               0x1F0400F4,0x00000000
#define SRM_DP_GAMMA_S_ASYNC1_1__FULL                0x1F0400F4,0xffffffff
#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_7 0x1F0400F4,0xFF000000
#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_6 0x1F0400F4,0x00FF0000
#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_5 0x1F0400F4,0x0000FF00
#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_4 0x1F0400F4,0x000000FF

#define SRM_DP_GAMMA_S_ASYNC1_2__ADDR                 0x1F0400F8
#define SRM_DP_GAMMA_S_ASYNC1_2__EMPTY                0x1F0400F8,0x00000000
#define SRM_DP_GAMMA_S_ASYNC1_2__FULL                 0x1F0400F8,0xffffffff
#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_11 0x1F0400F8,0xFF000000
#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_10 0x1F0400F8,0x00FF0000
#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_9  0x1F0400F8,0x0000FF00
#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_8  0x1F0400F8,0x000000FF

#define SRM_DP_GAMMA_S_ASYNC1_3__ADDR                 0x1F0400FC
#define SRM_DP_GAMMA_S_ASYNC1_3__EMPTY                0x1F0400FC,0x00000000
#define SRM_DP_GAMMA_S_ASYNC1_3__FULL                 0x1F0400FC,0xffffffff
#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_15 0x1F0400FC,0xFF000000
#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_14 0x1F0400FC,0x00FF0000
#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_13 0x1F0400FC,0x0000FF00
#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_12 0x1F0400FC,0x000000FF

#define SRM_DP_CSCA_ASYNC1_0__ADDR              0x1F040100
#define SRM_DP_CSCA_ASYNC1_0__EMPTY             0x1F040100,0x00000000
#define SRM_DP_CSCA_ASYNC1_0__FULL              0x1F040100,0xffffffff
#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_1 0x1F040100,0x03FF0000
#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_0 0x1F040100,0x000003FF

#define SRM_DP_CSCA_ASYNC1_1__ADDR              0x1F040104
#define SRM_DP_CSCA_ASYNC1_1__EMPTY             0x1F040104,0x00000000
#define SRM_DP_CSCA_ASYNC1_1__FULL              0x1F040104,0xffffffff
#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_3 0x1F040104,0x03FF0000
#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_2 0x1F040104,0x000003FF

#define SRM_DP_CSCA_ASYNC1_2__ADDR              0x1F040108
#define SRM_DP_CSCA_ASYNC1_2__EMPTY             0x1F040108,0x00000000
#define SRM_DP_CSCA_ASYNC1_2__FULL              0x1F040108,0xffffffff
#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_5 0x1F040108,0x03FF0000
#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_4 0x1F040108,0x000003FF

#define SRM_DP_CSCA_ASYNC1_3__ADDR              0x1F04010C
#define SRM_DP_CSCA_ASYNC1_3__EMPTY             0x1F04010C,0x00000000
#define SRM_DP_CSCA_ASYNC1_3__FULL              0x1F04010C,0xffffffff
#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_7 0x1F04010C,0x03FF0000
#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_6 0x1F04010C,0x000003FF

#define SRM_DP_CSC_ASYNC1_0__ADDR             0x1F040110
#define SRM_DP_CSC_ASYNC1_0__EMPTY            0x1F040110,0x00000000
#define SRM_DP_CSC_ASYNC1_0__FULL             0x1F040110,0xffffffff
#define SRM_DP_CSC_ASYNC1_0__DP_CSC_S0_ASYNC1 0x1F040110,0xC0000000
#define SRM_DP_CSC_ASYNC1_0__DP_CSC_B0_ASYNC1 0x1F040110,0x3FFF0000
#define SRM_DP_CSC_ASYNC1_0__DP_CSC_A8_ASYNC1 0x1F040110,0x000003FF

#define SRM_DP_CSC_ASYNC1_1__ADDR             0x1F040114
#define SRM_DP_CSC_ASYNC1_1__EMPTY            0x1F040114,0x00000000
#define SRM_DP_CSC_ASYNC1_1__FULL             0x1F040114,0xffffffff
#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S2_ASYNC1 0x1F040114,0xC0000000
#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B2_ASYNC1 0x1F040114,0x3FFF0000
#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S1_ASYNC1 0x1F040114,0x0000C000
#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B1_ASYNC1 0x1F040114,0x00003FFF

#define SRM_ISP_C0__ADDR                   0x1F040118
#define SRM_ISP_C0__EMPTY       0x1F040118,0x00000000
#define SRM_ISP_C0__FULL       0x1F040118,0xffffffff
#define SRM_ISP_C0__ISP_BURST_SIZE       0x1F040118,0x001C0000
#define SRM_ISP_C0__ISP_RED_ROW_BEGIN       0x1F040118,0x00020000
#define SRM_ISP_C0__ISP_GREEN_P_BEGIN       0x1F040118,0x00010000
#define SRM_ISP_C0__LINEARCCM_ON       0x1F040118,0x00004000
#define SRM_ISP_C0__LLF_G_EN       0x1F040118,0x00002000
#define SRM_ISP_C0__LLF_RB_EN       0x1F040118,0x00001000
#define SRM_ISP_C0__AD_EN       0x1F040118,0x00000800
#define SRM_ISP_C0__STS_EN       0x1F040118,0x00000400
#define SRM_ISP_C0__CL_EN       0x1F040118,0x00000200
#define SRM_ISP_C0__CS_EN       0x1F040118,0x00000100
#define SRM_ISP_C0__CCA_EN       0x1F040118,0x00000080
#define SRM_ISP_C0__HFE_EN       0x1F040118,0x00000040
#define SRM_ISP_C0__CNS_EN       0x1F040118,0x00000020
#define SRM_ISP_C0__MTF_ROC_EN       0x1F040118,0x00000010
#define SRM_ISP_C0__GAMMA_EN       0x1F040118,0x00000008
#define SRM_ISP_C0__CROC_EN       0x1F040118,0x00000004
#define SRM_ISP_C0__TBPR_EN       0x1F040118,0x00000002
#define SRM_ISP_C0__BPR_EN       0x1F040118,0x00000001

#define SRM_ISP_C1__ADDR                   0x1F04011C
#define SRM_ISP_C1__EMPTY       0x1F04011C,0x00000000
#define SRM_ISP_C1__FULL       0x1F04011C,0xffffffff
#define SRM_ISP_C1__YUV_EN       0x1F04011C,0x20000000
#define SRM_ISP_C1__CSC_SAT_MODE       0x1F04011C,0x10000000
#define SRM_ISP_C1__BOTTOM_CROP       0x1F04011C,0x0E000000
#define SRM_ISP_C1__TOP_CROP       0x1F04011C,0x01C00000
#define SRM_ISP_C1__RIGHT_CROP       0x1F04011C,0x00380000
#define SRM_ISP_C1__LEFT_CROP       0x1F04011C,0x00070000
#define SRM_ISP_C1__MTF_ROC_SH_M       0x1F04011C,0x00006000
#define SRM_ISP_C1__MTF_ROC_SH_N       0x1F04011C,0x00001800
#define SRM_ISP_C1__MTF_ROC_SH_QA       0x1F04011C,0x00000700
#define SRM_ISP_C1__MTF_ROC_SH_SHARP       0x1F04011C,0x000000E0
#define SRM_ISP_C1__WIDEASPECT       0x1F04011C,0x00000010
#define SRM_ISP_C1__APP_SEL       0x1F04011C,0x0000000C
#define SRM_ISP_C1__INT_MODE       0x1F04011C,0x00000003

#define SRM_ISP_FS__ADDR                   0x1F040120
#define SRM_ISP_FS__EMPTY       0x1F040120,0x00000000
#define SRM_ISP_FS__FULL       0x1F040120,0xffffffff
#define SRM_ISP_FS__FWIDTH       0x1F040120,0x0FFF0000
#define SRM_ISP_FS__FHEIGHT       0x1F040120,0x00000FFF

#define SRM_ISP_BI__ADDR                   0x1F040124
#define SRM_ISP_BI__EMPTY       0x1F040124,0x00000000
#define SRM_ISP_BI__FULL       0x1F040124,0xffffffff
#define SRM_ISP_BI__HBLANK       0x1F040124,0x0FFF0000
#define SRM_ISP_BI__VBLANK       0x1F040124,0x00000FFF

#define SRM_ISP_OCO__ADDR                   0x1F040128
#define SRM_ISP_OCO__EMPTY       0x1F040128,0x00000000
#define SRM_ISP_OCO__FULL       0x1F040128,0xffffffff
#define SRM_ISP_OCO__HOFFSET       0x1F040128,0x1FFF0000
#define SRM_ISP_OCO__VOFFSET       0x1F040128,0x00001FFF

#define SRM_ISP_BPR1__ADDR                   0x1F04012C
#define SRM_ISP_BPR1__EMPTY       0x1F04012C,0x00000000
#define SRM_ISP_BPR1__FULL       0x1F04012C,0xffffffff
#define SRM_ISP_BPR1__TB       0x1F04012C,0xFF000000
#define SRM_ISP_BPR1__TDR       0x1F04012C,0x00FF0000
#define SRM_ISP_BPR1__TR       0x1F04012C,0x0000FF00
#define SRM_ISP_BPR1__DKR       0x1F04012C,0x000000FF

#define SRM_ISP_BPR2__ADDR                   0x1F040130
#define SRM_ISP_BPR2__EMPTY       0x1F040130,0x00000000
#define SRM_ISP_BPR2__FULL       0x1F040130,0xffffffff
#define SRM_ISP_BPR2__BRB       0x1F040130,0xFF000000
#define SRM_ISP_BPR2__TT       0x1F040130,0x00FF0000
#define SRM_ISP_BPR2__TVDB       0x1F040130,0x0000FF00
#define SRM_ISP_BPR2__TDB       0x1F040130,0x000000FF

#define SRM_ISP_BPR3__ADDR                   0x1F040134
#define SRM_ISP_BPR3__EMPTY       0x1F040134,0x00000000
#define SRM_ISP_BPR3__FULL       0x1F040134,0xffffffff
#define SRM_ISP_BPR3__TG       0x1F040134,0xFF000000
#define SRM_ISP_BPR3__TGF       0x1F040134,0x00FF0000
#define SRM_ISP_BPR3__DKB       0x1F040134,0x0000FF00
#define SRM_ISP_BPR3__TG2       0x1F040134,0x000000FF

#define SRM_ISP_BPR4__ADDR                   0x1F040138
#define SRM_ISP_BPR4__EMPTY       0x1F040138,0x00000000
#define SRM_ISP_BPR4__FULL       0x1F040138,0xffffffff
#define SRM_ISP_BPR4__DKRCL       0x1F040138,0xFF000000
#define SRM_ISP_BPR4__TGFCL       0x1F040138,0x00FF0000
#define SRM_ISP_BPR4__TCL2       0x1F040138,0x0000FF00
#define SRM_ISP_BPR4__TCL       0x1F040138,0x000000FF

#define SRM_ISP_BPR5__ADDR                   0x1F04013C
#define SRM_ISP_BPR5__EMPTY       0x1F04013C,0x00000000
#define SRM_ISP_BPR5__FULL       0x1F04013C,0xffffffff
#define SRM_ISP_BPR5__TGL2  0x1E010024,0x0000FF00
#define SRM_ISP_BPR5__TBC       0x1F04013C,0x000000FF

#define SRM_ISP_CCMLIN0__ADDR                   0x1F040140
#define SRM_ISP_CCMLIN0__EMPTY       0x1F040140,0x00000000
#define SRM_ISP_CCMLIN0__FULL       0x1F040140,0xffffffff
#define SRM_ISP_CCMLIN0__CCMLIN12       0x1F040140,0x7C000000
#define SRM_ISP_CCMLIN0__CCMLIN11       0x1F040140,0x03E00000
#define SRM_ISP_CCMLIN0__CCMLIN10       0x1F040140,0x001F0000
#define SRM_ISP_CCMLIN0__CCMLIN02       0x1F040140,0x00007C00
#define SRM_ISP_CCMLIN0__CCMLIN01       0x1F040140,0x000003E0
#define SRM_ISP_CCMLIN0__CCMLIN00       0x1F040140,0x0000001F

#define SRM_ISP_CCMLIN1__ADDR                   0x1F040144
#define SRM_ISP_CCMLIN1__EMPTY       0x1F040144,0x00000000
#define SRM_ISP_CCMLIN1__FULL       0x1F040144,0xffffffff
#define SRM_ISP_CCMLIN1__CCMLIN22       0x1F040144,0x00007C00
#define SRM_ISP_CCMLIN1__CCMLIN21       0x1F040144,0x000003E0
#define SRM_ISP_CCMLIN1__CCMLIN20       0x1F040144,0x0000001F

#define SRM_ISP_CG_0__ADDR                   0x1F040148
#define SRM_ISP_CG_0__EMPTY       0x1F040148,0x00000000
#define SRM_ISP_CG_0__FULL       0x1F040148,0xffffffff
#define SRM_ISP_CG_0__BGAIN       0x1F040148,0xFF000000
#define SRM_ISP_CG_0__GBGAIN       0x1F040148,0x00FF0000
#define SRM_ISP_CG_0__GRGAIN       0x1F040148,0x0000FF00
#define SRM_ISP_CG_0__RGAIN       0x1F040148,0x000000FF

#define SRM_ISP_CG_1__ADDR                   0x1F04014C
#define SRM_ISP_CG_1__EMPTY       0x1F04014C,0x00000000
#define SRM_ISP_CG_1__FULL       0x1F04014C,0xffffffff
#define SRM_ISP_CG_1__BSHIFT       0x1F04014C,0x00000030
#define SRM_ISP_CG_1__GSHIFT       0x1F04014C,0x0000000C
#define SRM_ISP_CG_1__RSHIFT       0x1F04014C,0x00000003

#define SRM_ISP_ROC_0__ADDR                   0x1F040150
#define SRM_ISP_ROC_0__EMPTY       0x1F040150,0x00000000
#define SRM_ISP_ROC_0__FULL       0x1F040150,0xffffffff
#define SRM_ISP_ROC_0__CROC_Q_BLIN       0x1F040150,0x01C00000
#define SRM_ISP_ROC_0__CROC_Q_GLIN       0x1F040150,0x00380000
#define SRM_ISP_ROC_0__CROC_Q_RLIN       0x1F040150,0x00070000
#define SRM_ISP_ROC_0__CROC_SH_QR       0x1F040150,0x00007000
#define SRM_ISP_ROC_0__CROC_SH_QRGB       0x1F040150,0x00000E00
#define SRM_ISP_ROC_0__CROC_SH_QB       0x1F040150,0x000001C0
#define SRM_ISP_ROC_0__CROC_R_APP       0x1F040150,0x00000030
#define SRM_ISP_ROC_0__CROC_G_APP       0x1F040150,0x0000000C
#define SRM_ISP_ROC_0__CROC_B_APP       0x1F040150,0x00000003

#define SRM_ISP_ROC_1__ADDR                   0x1F040154
#define SRM_ISP_ROC_1__EMPTY       0x1F040154,0x00000000
#define SRM_ISP_ROC_1__FULL       0x1F040154,0xffffffff
#define SRM_ISP_ROC_1__CROC_MYB       0x1F040154,0xFF000000
#define SRM_ISP_ROC_1__CROC_MXB       0x1F040154,0x00FF0000
#define SRM_ISP_ROC_1__CROC_MYG       0x1F040154,0x0000FF00
#define SRM_ISP_ROC_1__CROC_MXG       0x1F040154,0x000000FF

#define SRM_ISP_ROC_2__ADDR                   0x1F040158
#define SRM_ISP_ROC_2__EMPTY       0x1F040158,0x00000000
#define SRM_ISP_ROC_2__FULL       0x1F040158,0xffffffff
#define SRM_ISP_ROC_2__CROC_MYR       0x1F040158,0x0000FF00
#define SRM_ISP_ROC_2__CROC_MXR       0x1F040158,0x000000FF

#define SRM_ISP_RROC_0__ADDR                   0x1F04015C
#define SRM_ISP_RROC_0__EMPTY       0x1F04015C,0x00000000
#define SRM_ISP_RROC_0__FULL       0x1F04015C,0xffffffff
#define SRM_ISP_RROC_0__CROC_RC1       0x1F04015C,0x07FF0000
#define SRM_ISP_RROC_0__CROC_RC0       0x1F04015C,0x000007FF

#define SRM_ISP_RROC_1__ADDR                   0x1F040160
#define SRM_ISP_RROC_1__EMPTY       0x1F040160,0x00000000
#define SRM_ISP_RROC_1__FULL       0x1F040160,0xffffffff
#define SRM_ISP_RROC_1__CROC_RC3       0x1F040160,0x07FF0000
#define SRM_ISP_RROC_1__CROC_RC2       0x1F040160,0x000007FF

#define SRM_ISP_RROC_2__ADDR                   0x1F040164
#define SRM_ISP_RROC_2__EMPTY       0x1F040164,0x00000000
#define SRM_ISP_RROC_2__FULL       0x1F040164,0xffffffff
#define SRM_ISP_RROC_2__CROC_RC5       0x1F040164,0x07FF0000
#define SRM_ISP_RROC_2__CROC_RC4       0x1F040164,0x000007FF

#define SRM_ISP_RROC_3__ADDR                   0x1F040168
#define SRM_ISP_RROC_3__EMPTY       0x1F040168,0x00000000
#define SRM_ISP_RROC_3__FULL       0x1F040168,0xffffffff
#define SRM_ISP_RROC_3__CROC_RC7       0x1F040168,0x07FF0000
#define SRM_ISP_RROC_3__CROC_RC6       0x1F040168,0x000007FF

#define SRM_ISP_RROC_4__ADDR                   0x1F04016C
#define SRM_ISP_RROC_4__EMPTY       0x1F04016C,0x00000000
#define SRM_ISP_RROC_4__FULL       0x1F04016C,0xffffffff
#define SRM_ISP_RROC_4__CROC_RC9       0x1F04016C,0x07FF0000
#define SRM_ISP_RROC_4__CROC_RC8       0x1F04016C,0x000007FF

#define SRM_ISP_RROC_5__ADDR                   0x1F040170
#define SRM_ISP_RROC_5__EMPTY       0x1F040170,0x00000000
#define SRM_ISP_RROC_5__FULL       0x1F040170,0xffffffff
#define SRM_ISP_RROC_5__CROC_RC11       0x1F040170,0x07FF0000
#define SRM_ISP_RROC_5__CROC_RC10       0x1F040170,0x000007FF

#define SRM_ISP_RROC_6__ADDR                   0x1F040174
#define SRM_ISP_RROC_6__EMPTY       0x1F040174,0x00000000
#define SRM_ISP_RROC_6__FULL       0x1F040174,0xffffffff
#define SRM_ISP_RROC_6__CROC_RC13       0x1F040174,0x07FF0000
#define SRM_ISP_RROC_6__CROC_RC12       0x1F040174,0x000007FF

#define SRM_ISP_RROC_7__ADDR                   0x1F040178
#define SRM_ISP_RROC_7__EMPTY       0x1F040178,0x00000000
#define SRM_ISP_RROC_7__FULL       0x1F040178,0xffffffff
#define SRM_ISP_RROC_7__CROC_RC15       0x1F040178,0x07FF0000
#define SRM_ISP_RROC_7__CROC_RC14       0x1F040178,0x000007FF

#define SRM_ISP_RROS_0__ADDR                   0x1F04017C
#define SRM_ISP_RROS_0__EMPTY       0x1F04017C,0x00000000
#define SRM_ISP_RROS_0__FULL       0x1F04017C,0xffffffff
#define SRM_ISP_RROS_0__CROC_RS3       0x1F04017C,0x7F000000
#define SRM_ISP_RROS_0__CROC_RS2       0x1F04017C,0x007F0000
#define SRM_ISP_RROS_0__CROC_RS1       0x1F04017C,0x00007F00
#define SRM_ISP_RROS_0__CROC_RS0       0x1F04017C,0x0000007F

#define SRM_ISP_RROS_1__ADDR                   0x1F040180
#define SRM_ISP_RROS_1__EMPTY       0x1F040180,0x00000000
#define SRM_ISP_RROS_1__FULL       0x1F040180,0xffffffff
#define SRM_ISP_RROS_1__CROC_RS7       0x1F040180,0x7F000000
#define SRM_ISP_RROS_1__CROC_RS6       0x1F040180,0x007F0000
#define SRM_ISP_RROS_1__CROC_RS5       0x1F040180,0x00007F00
#define SRM_ISP_RROS_1__CROC_RS4       0x1F040180,0x0000007F

#define SRM_ISP_RROS_2__ADDR                   0x1F040184
#define SRM_ISP_RROS_2__EMPTY       0x1F040184,0x00000000
#define SRM_ISP_RROS_2__FULL       0x1F040184,0xffffffff
#define SRM_ISP_RROS_2__CROC_RS11       0x1F040184,0x7F000000
#define SRM_ISP_RROS_2__CROC_RS10       0x1F040184,0x007F0000
#define SRM_ISP_RROS_2__CROC_RS9       0x1F040184,0x00007F00
#define SRM_ISP_RROS_2__CROC_RS8       0x1F040184,0x0000007F

#define SRM_ISP_RROS_3__ADDR                   0x1F040188
#define SRM_ISP_RROS_3__EMPTY       0x1F040188,0x00000000
#define SRM_ISP_RROS_3__FULL       0x1F040188,0xffffffff
#define SRM_ISP_RROS_3__CROC_RS15       0x1F040188,0x7F000000
#define SRM_ISP_RROS_3__CROC_RS14       0x1F040188,0x007F0000
#define SRM_ISP_RROS_3__CROC_RS13       0x1F040188,0x00007F00
#define SRM_ISP_RROS_3__CROC_RS12       0x1F040188,0x0000007F

#define SRM_ISP_GROC_0__ADDR                   0x1F04018C
#define SRM_ISP_GROC_0__EMPTY       0x1F04018C,0x00000000
#define SRM_ISP_GROC_0__FULL       0x1F04018C,0xffffffff
#define SRM_ISP_GROC_0__CROC_GC1       0x1F04018C,0x07FF0000
#define SRM_ISP_GROC_0__CROC_GC0       0x1F04018C,0x000007FF

#define SRM_ISP_GROC_1__ADDR                   0x1F040190
#define SRM_ISP_GROC_1__EMPTY       0x1F040190,0x00000000
#define SRM_ISP_GROC_1__FULL       0x1F040190,0xffffffff
#define SRM_ISP_GROC_1__CROC_GC3       0x1F040190,0x07FF0000
#define SRM_ISP_GROC_1__CROC_GC2       0x1F040190,0x000007FF

#define SRM_ISP_GROC_2__ADDR                   0x1F040194
#define SRM_ISP_GROC_2__EMPTY       0x1F040194,0x00000000
#define SRM_ISP_GROC_2__FULL       0x1F040194,0xffffffff
#define SRM_ISP_GROC_2__CROC_GC5       0x1F040194,0x07FF0000
#define SRM_ISP_GROC_2__CROC_GC4       0x1F040194,0x000007FF

#define SRM_ISP_GROC_3__ADDR                   0x1F040198
#define SRM_ISP_GROC_3__EMPTY       0x1F040198,0x00000000
#define SRM_ISP_GROC_3__FULL       0x1F040198,0xffffffff
#define SRM_ISP_GROC_3__CROC_GC7       0x1F040198,0x07FF0000
#define SRM_ISP_GROC_3__CROC_GC6       0x1F040198,0x000007FF

#define SRM_ISP_GROC_4__ADDR                   0x1F04019C
#define SRM_ISP_GROC_4__EMPTY       0x1F04019C,0x00000000
#define SRM_ISP_GROC_4__FULL       0x1F04019C,0xffffffff
#define SRM_ISP_GROC_4__CROC_GC9       0x1F04019C,0x07FF0000
#define SRM_ISP_GROC_4__CROC_GC8       0x1F04019C,0x000007FF

#define SRM_ISP_GROC_5__ADDR                   0x1F0401A0
#define SRM_ISP_GROC_5__EMPTY       0x1F0401A0,0x00000000
#define SRM_ISP_GROC_5__FULL       0x1F0401A0,0xffffffff
#define SRM_ISP_GROC_5__CROC_GC11       0x1F0401A0,0x07FF0000
#define SRM_ISP_GROC_5__CROC_GC10       0x1F0401A0,0x000007FF

#define SRM_ISP_GROC_6__ADDR                   0x1F0401A4
#define SRM_ISP_GROC_6__EMPTY       0x1F0401A4,0x00000000
#define SRM_ISP_GROC_6__FULL       0x1F0401A4,0xffffffff
#define SRM_ISP_GROC_6__CROC_GC13       0x1F0401A4,0x07FF0000
#define SRM_ISP_GROC_6__CROC_GC12       0x1F0401A4,0x000007FF

#define SRM_ISP_GROC_7__ADDR                   0x1F0401A8
#define SRM_ISP_GROC_7__EMPTY       0x1F0401A8,0x00000000
#define SRM_ISP_GROC_7__FULL       0x1F0401A8,0xffffffff
#define SRM_ISP_GROC_7__CROC_GC15       0x1F0401A8,0x07FF0000
#define SRM_ISP_GROC_7__CROC_GC14       0x1F0401A8,0x000007FF

#define SRM_ISP_GROS_0__ADDR                   0x1F0401AC
#define SRM_ISP_GROS_0__EMPTY       0x1F0401AC,0x00000000
#define SRM_ISP_GROS_0__FULL       0x1F0401AC,0xffffffff
#define SRM_ISP_GROS_0__CROC_GS3       0x1F0401AC,0x7F000000
#define SRM_ISP_GROS_0__CROC_GS2       0x1F0401AC,0x007F0000
#define SRM_ISP_GROS_0__CROC_GS1       0x1F0401AC,0x00007F00
#define SRM_ISP_GROS_0__CROC_GS0       0x1F0401AC,0x0000007F

#define SRM_ISP_GROS_1__ADDR                   0x1F0401B0
#define SRM_ISP_GROS_1__EMPTY       0x1F0401B0,0x00000000
#define SRM_ISP_GROS_1__FULL       0x1F0401B0,0xffffffff
#define SRM_ISP_GROS_1__CROC_GS7       0x1F0401B0,0x7F000000
#define SRM_ISP_GROS_1__CROC_GS6       0x1F0401B0,0x007F0000
#define SRM_ISP_GROS_1__CROC_GS5       0x1F0401B0,0x00007F00
#define SRM_ISP_GROS_1__CROC_GS4       0x1F0401B0,0x0000007F

#define SRM_ISP_GROS_2__ADDR                   0x1F0401B4
#define SRM_ISP_GROS_2__EMPTY       0x1F0401B4,0x00000000
#define SRM_ISP_GROS_2__FULL       0x1F0401B4,0xffffffff
#define SRM_ISP_GROS_2__CROC_GS11       0x1F0401B4,0x7F000000
#define SRM_ISP_GROS_2__CROC_GS10       0x1F0401B4,0x007F0000
#define SRM_ISP_GROS_2__CROC_GS9       0x1F0401B4,0x00007F00
#define SRM_ISP_GROS_2__CROC_GS8       0x1F0401B4,0x0000007F

#define SRM_ISP_GROS_3__ADDR                   0x1F0401B8
#define SRM_ISP_GROS_3__EMPTY       0x1F0401B8,0x00000000
#define SRM_ISP_GROS_3__FULL       0x1F0401B8,0xffffffff
#define SRM_ISP_GROS_3__CROC_GS15       0x1F0401B8,0x7F000000
#define SRM_ISP_GROS_3__CROC_GS14       0x1F0401B8,0x007F0000
#define SRM_ISP_GROS_3__CROC_GS13       0x1F0401B8,0x00007F00
#define SRM_ISP_GROS_3__CROC_GS12       0x1F0401B8,0x0000007F

#define SRM_ISP_BROC_0__ADDR                   0x1F0401BC
#define SRM_ISP_BROC_0__EMPTY       0x1F0401BC,0x00000000
#define SRM_ISP_BROC_0__FULL       0x1F0401BC,0xffffffff
#define SRM_ISP_BROC_0__CROC_BC1       0x1F0401BC,0x07FF0000
#define SRM_ISP_BROC_0__CROC_BC0       0x1F0401BC,0x000007FF

#define SRM_ISP_BROC_1__ADDR                   0x1F0401C0
#define SRM_ISP_BROC_1__EMPTY       0x1F0401C0,0x00000000
#define SRM_ISP_BROC_1__FULL       0x1F0401C0,0xffffffff
#define SRM_ISP_BROC_1__CROC_BC3       0x1F0401C0,0x07FF0000
#define SRM_ISP_BROC_1__CROC_BC2       0x1F0401C0,0x000007FF

#define SRM_ISP_BROC_2__ADDR                   0x1F0401C4
#define SRM_ISP_BROC_2__EMPTY       0x1F0401C4,0x00000000
#define SRM_ISP_BROC_2__FULL       0x1F0401C4,0xffffffff
#define SRM_ISP_BROC_2__CROC_BC5       0x1F0401C4,0x07FF0000
#define SRM_ISP_BROC_2__CROC_BC4       0x1F0401C4,0x000007FF

#define SRM_ISP_BROC_3__ADDR                   0x1F0401C8
#define SRM_ISP_BROC_3__EMPTY       0x1F0401C8,0x00000000
#define SRM_ISP_BROC_3__FULL       0x1F0401C8,0xffffffff
#define SRM_ISP_BROC_3__CROC_BC7       0x1F0401C8,0x07FF0000
#define SRM_ISP_BROC_3__CROC_BC6       0x1F0401C8,0x000007FF

#define SRM_ISP_BROC_4__ADDR                   0x1F0401CC
#define SRM_ISP_BROC_4__EMPTY       0x1F0401CC,0x00000000
#define SRM_ISP_BROC_4__FULL       0x1F0401CC,0xffffffff
#define SRM_ISP_BROC_4__CROC_BC9       0x1F0401CC,0x07FF0000
#define SRM_ISP_BROC_4__CROC_BC8       0x1F0401CC,0x000007FF

#define SRM_ISP_BROC_5__ADDR                   0x1F0401D0
#define SRM_ISP_BROC_5__EMPTY       0x1F0401D0,0x00000000
#define SRM_ISP_BROC_5__FULL       0x1F0401D0,0xffffffff
#define SRM_ISP_BROC_5__CROC_BC11       0x1F0401D0,0x07FF0000
#define SRM_ISP_BROC_5__CROC_BC10       0x1F0401D0,0x000007FF

#define SRM_ISP_BROC_6__ADDR                   0x1F0401D4
#define SRM_ISP_BROC_6__EMPTY       0x1F0401D4,0x00000000
#define SRM_ISP_BROC_6__FULL       0x1F0401D4,0xffffffff
#define SRM_ISP_BROC_6__CROC_BC13       0x1F0401D4,0x07FF0000
#define SRM_ISP_BROC_6__CROC_BC12       0x1F0401D4,0x000007FF

#define SRM_ISP_BROC_7__ADDR                   0x1F0401D8
#define SRM_ISP_BROC_7__EMPTY       0x1F0401D8,0x00000000
#define SRM_ISP_BROC_7__FULL       0x1F0401D8,0xffffffff
#define SRM_ISP_BROC_7__CROC_BC15       0x1F0401D8,0x07FF0000
#define SRM_ISP_BROC_7__CROC_BC14       0x1F0401D8,0x000007FF

#define SRM_ISP_BROS_0__ADDR                   0x1F0401DC
#define SRM_ISP_BROS_0__EMPTY       0x1F0401DC,0x00000000
#define SRM_ISP_BROS_0__FULL       0x1F0401DC,0xffffffff
#define SRM_ISP_BROS_0__CROC_BS3       0x1F0401DC,0x7F000000
#define SRM_ISP_BROS_0__CROC_BS2       0x1F0401DC,0x007F0000
#define SRM_ISP_BROS_0__CROC_BS1       0x1F0401DC,0x00007F00
#define SRM_ISP_BROS_0__CROC_BS0       0x1F0401DC,0x0000007F

#define SRM_ISP_BROS_1__ADDR                   0x1F0401E0
#define SRM_ISP_BROS_1__EMPTY       0x1F0401E0,0x00000000
#define SRM_ISP_BROS_1__FULL       0x1F0401E0,0xffffffff
#define SRM_ISP_BROS_1__CROC_BS7       0x1F0401E0,0x7F000000
#define SRM_ISP_BROS_1__CROC_BS6       0x1F0401E0,0x007F0000
#define SRM_ISP_BROS_1__CROC_BS5       0x1F0401E0,0x00007F00
#define SRM_ISP_BROS_1__CROC_BS4       0x1F0401E0,0x0000007F

#define SRM_ISP_BROS_2__ADDR                   0x1F0401E4
#define SRM_ISP_BROS_2__EMPTY       0x1F0401E4,0x00000000
#define SRM_ISP_BROS_2__FULL       0x1F0401E4,0xffffffff
#define SRM_ISP_BROS_2__CROC_BS11       0x1F0401E4,0x7F000000
#define SRM_ISP_BROS_2__CROC_BS10       0x1F0401E4,0x007F0000
#define SRM_ISP_BROS_2__CROC_BS9       0x1F0401E4,0x00007F00
#define SRM_ISP_BROS_2__CROC_BS8       0x1F0401E4,0x0000007F

#define SRM_ISP_BROS_3__ADDR                   0x1F0401E8
#define SRM_ISP_BROS_3__EMPTY       0x1F0401E8,0x00000000
#define SRM_ISP_BROS_3__FULL       0x1F0401E8,0xffffffff
#define SRM_ISP_BROS_3__CROC_BS15       0x1F0401E8,0x7F000000
#define SRM_ISP_BROS_3__CROC_BS14       0x1F0401E8,0x007F0000
#define SRM_ISP_BROS_3__CROC_BS13       0x1F0401E8,0x00007F00
#define SRM_ISP_BROS_3__CROC_BS12       0x1F0401E8,0x0000007F

#define SRM_ISP_GAMMA_C_0__ADDR                   0x1F0401EC
#define SRM_ISP_GAMMA_C_0__EMPTY       0x1F0401EC,0x00000000
#define SRM_ISP_GAMMA_C_0__FULL       0x1F0401EC,0xffffffff
#define SRM_ISP_GAMMA_C_0__GAMMA_C1       0x1F0401EC,0x01FF0000
#define SRM_ISP_GAMMA_C_0__GAMMA_C0       0x1F0401EC,0x000001FF

#define SRM_ISP_GAMMA_C_1__ADDR                   0x1F0401F0
#define SRM_ISP_GAMMA_C_1__EMPTY       0x1F0401F0,0x00000000
#define SRM_ISP_GAMMA_C_1__FULL       0x1F0401F0,0xffffffff
#define SRM_ISP_GAMMA_C_1__GAMMA_C3       0x1F0401F0,0x01FF0000
#define SRM_ISP_GAMMA_C_1__GAMMA_C2       0x1F0401F0,0x000001FF

#define SRM_ISP_GAMMA_C_2__ADDR                   0x1F0401F4
#define SRM_ISP_GAMMA_C_2__EMPTY       0x1F0401F4,0x00000000
#define SRM_ISP_GAMMA_C_2__FULL       0x1F0401F4,0xffffffff
#define SRM_ISP_GAMMA_C_2__GAMMA_C5       0x1F0401F4,0x01FF0000
#define SRM_ISP_GAMMA_C_2__GAMMA_C4       0x1F0401F4,0x000001FF

#define SRM_ISP_GAMMA_C_3__ADDR                   0x1F0401F8
#define SRM_ISP_GAMMA_C_3__EMPTY       0x1F0401F8,0x00000000
#define SRM_ISP_GAMMA_C_3__FULL       0x1F0401F8,0xffffffff
#define SRM_ISP_GAMMA_C_3__GAMMA_C7       0x1F0401F8,0x01FF0000
#define SRM_ISP_GAMMA_C_3__GAMMA_C6       0x1F0401F8,0x000001FF

#define SRM_ISP_GAMMA_C_4__ADDR                   0x1F0401FC
#define SRM_ISP_GAMMA_C_4__EMPTY       0x1F0401FC,0x00000000
#define SRM_ISP_GAMMA_C_4__FULL       0x1F0401FC,0xffffffff
#define SRM_ISP_GAMMA_C_4__GAMMA_C9       0x1F0401FC,0x01FF0000
#define SRM_ISP_GAMMA_C_4__GAMMA_C8       0x1F0401FC,0x000001FF

#define SRM_ISP_GAMMA_C_5__ADDR                   0x1F040200
#define SRM_ISP_GAMMA_C_5__EMPTY       0x1F040200,0x00000000
#define SRM_ISP_GAMMA_C_5__FULL       0x1F040200,0xffffffff
#define SRM_ISP_GAMMA_C_5__GAMMA_C11       0x1F040200,0x01FF0000
#define SRM_ISP_GAMMA_C_5__GAMMA_C10       0x1F040200,0x000001FF

#define SRM_ISP_GAMMA_C_6__ADDR                   0x1F040204
#define SRM_ISP_GAMMA_C_6__EMPTY       0x1F040204,0x00000000
#define SRM_ISP_GAMMA_C_6__FULL       0x1F040204,0xffffffff
#define SRM_ISP_GAMMA_C_6__GAMMA_C13       0x1F040204,0x01FF0000
#define SRM_ISP_GAMMA_C_6__GAMMA_C12       0x1F040204,0x000001FF

#define SRM_ISP_GAMMA_C_7__ADDR                   0x1F040208
#define SRM_ISP_GAMMA_C_7__EMPTY       0x1F040208,0x00000000
#define SRM_ISP_GAMMA_C_7__FULL       0x1F040208,0xffffffff
#define SRM_ISP_GAMMA_C_7__GAMMA_C15       0x1F040208,0x01FF0000
#define SRM_ISP_GAMMA_C_7__GAMMA_C14       0x1F040208,0x000001FF

#define SRM_ISP_GAMMA_S_0__ADDR                   0x1F04020C
#define SRM_ISP_GAMMA_S_0__EMPTY       0x1F04020C,0x00000000
#define SRM_ISP_GAMMA_S_0__FULL       0x1F04020C,0xffffffff
#define SRM_ISP_GAMMA_S_0__GAMMA_S3       0x1F04020C,0xFF000000
#define SRM_ISP_GAMMA_S_0__GAMMA_S2       0x1F04020C,0x00FF0000
#define SRM_ISP_GAMMA_S_0__GAMMA_S1       0x1F04020C,0x0000FF00
#define SRM_ISP_GAMMA_S_0__GAMMA_S0       0x1F04020C,0x000000FF

#define SRM_ISP_GAMMA_S_1__ADDR                   0x1F040210
#define SRM_ISP_GAMMA_S_1__EMPTY       0x1F040210,0x00000000
#define SRM_ISP_GAMMA_S_1__FULL       0x1F040210,0xffffffff
#define SRM_ISP_GAMMA_S_1__GAMMA_S7       0x1F040210,0xFF000000
#define SRM_ISP_GAMMA_S_1__GAMMA_S6       0x1F040210,0x00FF0000
#define SRM_ISP_GAMMA_S_1__GAMMA_S5       0x1F040210,0x0000FF00
#define SRM_ISP_GAMMA_S_1__GAMMA_S4       0x1F040210,0x000000FF

#define SRM_ISP_GAMMA_S_2__ADDR                   0x1F040214
#define SRM_ISP_GAMMA_S_2__EMPTY       0x1F040214,0x00000000
#define SRM_ISP_GAMMA_S_2__FULL       0x1F040214,0xffffffff
#define SRM_ISP_GAMMA_S_2__GAMMA_S11       0x1F040214,0xFF000000
#define SRM_ISP_GAMMA_S_2__GAMMA_S10       0x1F040214,0x00FF0000
#define SRM_ISP_GAMMA_S_2__GAMMA_S9       0x1F040214,0x0000FF00
#define SRM_ISP_GAMMA_S_2__GAMMA_S8       0x1F040214,0x000000FF

#define SRM_ISP_GAMMA_S_3__ADDR                   0x1F040218
#define SRM_ISP_GAMMA_S_3__EMPTY       0x1F040218,0x00000000
#define SRM_ISP_GAMMA_S_3__FULL       0x1F040218,0xffffffff
#define SRM_ISP_GAMMA_S_3__GAMMA_S15       0x1F040218,0xFF000000
#define SRM_ISP_GAMMA_S_3__GAMMA_S14       0x1F040218,0x00FF0000
#define SRM_ISP_GAMMA_S_3__GAMMA_S13       0x1F040218,0x0000FF00
#define SRM_ISP_GAMMA_S_3__GAMMA_S12       0x1F040218,0x000000FF

#define SRM_ISP_CSCA_0__ADDR                   0x1F04021C
#define SRM_ISP_CSCA_0__EMPTY       0x1F04021C,0x00000000
#define SRM_ISP_CSCA_0__FULL       0x1F04021C,0xffffffff
#define SRM_ISP_CSCA_0__CSC_A1       0x1F04021C,0x03FF0000
#define SRM_ISP_CSCA_0__CSC_A0       0x1F04021C,0x000003FF

#define SRM_ISP_CSCA_1__ADDR                   0x1F040220
#define SRM_ISP_CSCA_1__EMPTY       0x1F040220,0x00000000
#define SRM_ISP_CSCA_1__FULL       0x1F040220,0xffffffff
#define SRM_ISP_CSCA_1__CSC_A3       0x1F040220,0x03FF0000
#define SRM_ISP_CSCA_1__CSC_A2       0x1F040220,0x000003FF

#define SRM_ISP_CSCA_2__ADDR                   0x1F040224
#define SRM_ISP_CSCA_2__EMPTY       0x1F040224,0x00000000
#define SRM_ISP_CSCA_2__FULL       0x1F040224,0xffffffff
#define SRM_ISP_CSCA_2__CSC_A5       0x1F040224,0x03FF0000
#define SRM_ISP_CSCA_2__CSC_A4       0x1F040224,0x000003FF

#define SRM_ISP_CSCA_3__ADDR                   0x1F040228
#define SRM_ISP_CSCA_3__EMPTY       0x1F040228,0x00000000
#define SRM_ISP_CSCA_3__FULL       0x1F040228,0xffffffff
#define SRM_ISP_CSCA_3__CSC_A7       0x1F040228,0x03FF0000
#define SRM_ISP_CSCA_3__CSC_A6       0x1F040228,0x000003FF

#define SRM_ISP_CSC_0__ADDR                   0x1F04022C
#define SRM_ISP_CSC_0__EMPTY       0x1F04022C,0x00000000
#define SRM_ISP_CSC_0__FULL       0x1F04022C,0xffffffff
#define SRM_ISP_CSC_0__CSC_S0       0x1F04022C,0xC0000000
#define SRM_ISP_CSC_0__CSC_B0       0x1F04022C,0x3FFF0000
#define SRM_ISP_CSC_0__CSC_A8       0x1F04022C,0x000003FF

#define SRM_ISP_CSC_1__ADDR                   0x1F040230
#define SRM_ISP_CSC_1__EMPTY       0x1F040230,0x00000000
#define SRM_ISP_CSC_1__FULL       0x1F040230,0xffffffff
#define SRM_ISP_CSC_1__CSC_S2       0x1F040230,0xC0000000
#define SRM_ISP_CSC_1__CSC_B2       0x1F040230,0x3FFF0000
#define SRM_ISP_CSC_1__CSC_S1       0x1F040230,0x0000C000
#define SRM_ISP_CSC_1__CSC_B1       0x1F040230,0x00003FFF

#define SRM_ISP_CNS_C_0__ADDR                   0x1F040234
#define SRM_ISP_CNS_C_0__EMPTY       0x1F040234,0x00000000
#define SRM_ISP_CNS_C_0__FULL       0x1F040234,0xffffffff
#define SRM_ISP_CNS_C_0__CNS_C1       0x1F040234,0x01FF0000
#define SRM_ISP_CNS_C_0__CNS_C0       0x1F040234,0x000001FF

#define SRM_ISP_CNS_C_1__ADDR                   0x1F040238
#define SRM_ISP_CNS_C_1__EMPTY       0x1F040238,0x00000000
#define SRM_ISP_CNS_C_1__FULL       0x1F040238,0xffffffff
#define SRM_ISP_CNS_C_1__CNS_C3       0x1F040238,0x01FF0000
#define SRM_ISP_CNS_C_1__CNS_C2       0x1F040238,0x000001FF

#define SRM_ISP_CNS_C_2__ADDR                   0x1F04023C
#define SRM_ISP_CNS_C_2__EMPTY       0x1F04023C,0x00000000
#define SRM_ISP_CNS_C_2__FULL       0x1F04023C,0xffffffff
#define SRM_ISP_CNS_C_2__CNS_C5       0x1F04023C,0x01FF0000
#define SRM_ISP_CNS_C_2__CNS_C4       0x1F04023C,0x000001FF

#define SRM_ISP_CNS_C_3__ADDR                   0x1F040240
#define SRM_ISP_CNS_C_3__EMPTY       0x1F040240,0x00000000
#define SRM_ISP_CNS_C_3__FULL       0x1F040240,0xffffffff
#define SRM_ISP_CNS_C_3__CNS_C7       0x1F040240,0x01FF0000
#define SRM_ISP_CNS_C_3__CNS_C6       0x1F040240,0x000001FF

#define SRM_ISP_CNS_C_4__ADDR                   0x1F040244
#define SRM_ISP_CNS_C_4__EMPTY       0x1F040244,0x00000000
#define SRM_ISP_CNS_C_4__FULL       0x1F040244,0xffffffff
#define SRM_ISP_CNS_C_4__CNS_C9       0x1F040244,0x01FF0000
#define SRM_ISP_CNS_C_4__CNS_C8       0x1F040244,0x000001FF

#define SRM_ISP_CNS_C_5__ADDR                   0x1F040248
#define SRM_ISP_CNS_C_5__EMPTY       0x1F040248,0x00000000
#define SRM_ISP_CNS_C_5__FULL       0x1F040248,0xffffffff
#define SRM_ISP_CNS_C_5__CNS_C11       0x1F040248,0x01FF0000
#define SRM_ISP_CNS_C_5__CNS_C10       0x1F040248,0x000001FF

#define SRM_ISP_CNS_C_6__ADDR                   0x1F04024C
#define SRM_ISP_CNS_C_6__EMPTY       0x1F04024C,0x00000000
#define SRM_ISP_CNS_C_6__FULL       0x1F04024C,0xffffffff
#define SRM_ISP_CNS_C_6__CNS_C13       0x1F04024C,0x01FF0000
#define SRM_ISP_CNS_C_6__CNS_C12       0x1F04024C,0x000001FF

#define SRM_ISP_CNS_C_7__ADDR                   0x1F040250
#define SRM_ISP_CNS_C_7__EMPTY       0x1F040250,0x00000000
#define SRM_ISP_CNS_C_7__FULL       0x1F040250,0xffffffff
#define SRM_ISP_CNS_C_7__CNS_C15       0x1F040250,0x01FF0000
#define SRM_ISP_CNS_C_7__CNS_C14       0x1F040250,0x000001FF

#define SRM_ISP_CNS_S_0__ADDR                   0x1F040254
#define SRM_ISP_CNS_S_0__EMPTY       0x1F040254,0x00000000
#define SRM_ISP_CNS_S_0__FULL       0x1F040254,0xffffffff
#define SRM_ISP_CNS_S_0__CNS_S3       0x1F040254,0xFF000000
#define SRM_ISP_CNS_S_0__CNS_S2       0x1F040254,0x00FF0000
#define SRM_ISP_CNS_S_0__CNS_S1       0x1F040254,0x0000FF00
#define SRM_ISP_CNS_S_0__CNS_S0       0x1F040254,0x000000FF

#define SRM_ISP_CNS_S_1__ADDR                   0x1F040258
#define SRM_ISP_CNS_S_1__EMPTY       0x1F040258,0x00000000
#define SRM_ISP_CNS_S_1__FULL       0x1F040258,0xffffffff
#define SRM_ISP_CNS_S_1__CNS_S7       0x1F040258,0xFF000000
#define SRM_ISP_CNS_S_1__CNS_S6       0x1F040258,0x00FF0000
#define SRM_ISP_CNS_S_1__CNS_S5       0x1F040258,0x0000FF00
#define SRM_ISP_CNS_S_1__CNS_S4       0x1F040258,0x000000FF

#define SRM_ISP_CNS_S_2__ADDR                   0x1F04025C
#define SRM_ISP_CNS_S_2__EMPTY       0x1F04025C,0x00000000
#define SRM_ISP_CNS_S_2__FULL       0x1F04025C,0xffffffff
#define SRM_ISP_CNS_S_2__CNS_S11       0x1F04025C,0xFF000000
#define SRM_ISP_CNS_S_2__CNS_S10       0x1F04025C,0x00FF0000
#define SRM_ISP_CNS_S_2__CNS_S9       0x1F04025C,0x0000FF00
#define SRM_ISP_CNS_S_2__CNS_S8       0x1F04025C,0x000000FF

#define SRM_ISP_CNS_S_3__ADDR                   0x1F040260
#define SRM_ISP_CNS_S_3__EMPTY       0x1F040260,0x00000000
#define SRM_ISP_CNS_S_3__FULL       0x1F040260,0xffffffff
#define SRM_ISP_CNS_S_3__CNS_S15       0x1F040260,0xFF000000
#define SRM_ISP_CNS_S_3__CNS_S14       0x1F040260,0x00FF0000
#define SRM_ISP_CNS_S_3__CNS_S13       0x1F040260,0x0000FF00
#define SRM_ISP_CNS_S_3__CNS_S12       0x1F040260,0x000000FF

#define SRM_ISP_MTF_ROC_C_0__ADDR                   0x1F040264
#define SRM_ISP_MTF_ROC_C_0__EMPTY       0x1F040264,0x00000000
#define SRM_ISP_MTF_ROC_C_0__FULL       0x1F040264,0xffffffff
#define SRM_ISP_MTF_ROC_C_0__MTF_ROC_C1       0x1F040264,0x01FF0000
#define SRM_ISP_MTF_ROC_C_0__MTF_ROC_C0       0x1F040264,0x000001FF

#define SRM_ISP_MTF_ROC_C_1__ADDR                   0x1F040268
#define SRM_ISP_MTF_ROC_C_1__EMPTY       0x1F040268,0x00000000
#define SRM_ISP_MTF_ROC_C_1__FULL       0x1F040268,0xffffffff
#define SRM_ISP_MTF_ROC_C_1__MTF_ROC_C3       0x1F040268,0x01FF0000
#define SRM_ISP_MTF_ROC_C_1__MTF_ROC_C2       0x1F040268,0x000001FF

#define SRM_ISP_MTF_ROC_C_2__ADDR                   0x1F04026C
#define SRM_ISP_MTF_ROC_C_2__EMPTY       0x1F04026C,0x00000000
#define SRM_ISP_MTF_ROC_C_2__FULL       0x1F04026C,0xffffffff
#define SRM_ISP_MTF_ROC_C_2__MTF_ROC_C5       0x1F04026C,0x01FF0000
#define SRM_ISP_MTF_ROC_C_2__MTF_ROC_C4       0x1F04026C,0x000001FF

#define SRM_ISP_MTF_ROC_C_3__ADDR                   0x1F040270
#define SRM_ISP_MTF_ROC_C_3__EMPTY       0x1F040270,0x00000000
#define SRM_ISP_MTF_ROC_C_3__FULL       0x1F040270,0xffffffff
#define SRM_ISP_MTF_ROC_C_3__MTF_ROC_C7       0x1F040270,0x01FF0000
#define SRM_ISP_MTF_ROC_C_3__MTF_ROC_C6       0x1F040270,0x000001FF

#define SRM_ISP_MTF_ROC_S_0__ADDR                   0x1F040274
#define SRM_ISP_MTF_ROC_S_0__EMPTY       0x1F040274,0x00000000
#define SRM_ISP_MTF_ROC_S_0__FULL       0x1F040274,0xffffffff
#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S3       0x1F040274,0xFF000000
#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S2       0x1F040274,0x00FF0000
#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S1       0x1F040274,0x0000FF00
#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S0       0x1F040274,0x000000FF

#define SRM_ISP_MTF_ROC_S_1__ADDR                   0x1F040278
#define SRM_ISP_MTF_ROC_S_1__EMPTY       0x1F040278,0x00000000
#define SRM_ISP_MTF_ROC_S_1__FULL       0x1F040278,0xffffffff
#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S7       0x1F040278,0xFF000000
#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S6       0x1F040278,0x00FF0000
#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S5       0x1F040278,0x0000FF00
#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S4       0x1F040278,0x000000FF

#define SRM_ISP_HFE_0__ADDR                   0x1F04027C
#define SRM_ISP_HFE_0__EMPTY       0x1F04027C,0x00000000
#define SRM_ISP_HFE_0__FULL       0x1F04027C,0xffffffff
#define SRM_ISP_HFE_0__HFE_LUT5       0x1F04027C,0x7C000000
#define SRM_ISP_HFE_0__HFE_LUT4       0x1F04027C,0x03E00000
#define SRM_ISP_HFE_0__HFE_LUT3       0x1F04027C,0x001F0000
#define SRM_ISP_HFE_0__HFE_LUT2       0x1F04027C,0x00007C00
#define SRM_ISP_HFE_0__HFE_LUT1       0x1F04027C,0x000003E0
#define SRM_ISP_HFE_0__HFE_LUT0       0x1F04027C,0x0000001F

#define SRM_ISP_HFE_1__ADDR                   0x1F040280
#define SRM_ISP_HFE_1__EMPTY       0x1F040280,0x00000000
#define SRM_ISP_HFE_1__FULL       0x1F040280,0xffffffff
#define SRM_ISP_HFE_1__HFE_LUT11       0x1F040280,0x7C000000
#define SRM_ISP_HFE_1__HFE_LUT10       0x1F040280,0x03E00000
#define SRM_ISP_HFE_1__HFE_LUT9       0x1F040280,0x001F0000
#define SRM_ISP_HFE_1__HFE_LUT8       0x1F040280,0x00007C00
#define SRM_ISP_HFE_1__HFE_LUT7       0x1F040280,0x000003E0
#define SRM_ISP_HFE_1__HFE_LUT6       0x1F040280,0x0000001F

#define SRM_ISP_HFE_2__ADDR                   0x1F040284
#define SRM_ISP_HFE_2__EMPTY       0x1F040284,0x00000000
#define SRM_ISP_HFE_2__FULL       0x1F040284,0xffffffff
#define SRM_ISP_HFE_2__HFE_LUT15       0x1F040284,0x001F0000
#define SRM_ISP_HFE_2__HFE_LUT14       0x1F040284,0x00007C00
#define SRM_ISP_HFE_2__HFE_LUT13       0x1F040284,0x000003E0
#define SRM_ISP_HFE_2__HFE_LUT12       0x1F040284,0x0000001F

#define SRM_ISP_HFE_S_0__ADDR                   0x1F040288
#define SRM_ISP_HFE_S_0__EMPTY       0x1F040288,0x00000000
#define SRM_ISP_HFE_S_0__FULL       0x1F040288,0xffffffff
#define SRM_ISP_HFE_S_0__HFE_S1       0x1F040288,0x01FF0000
#define SRM_ISP_HFE_S_0__HFE_S0       0x1F040288,0x000001FF

#define SRM_ISP_HFE_S_1__ADDR                   0x1F04028C
#define SRM_ISP_HFE_S_1__EMPTY       0x1F04028C,0x00000000
#define SRM_ISP_HFE_S_1__FULL       0x1F04028C,0xffffffff
#define SRM_ISP_HFE_S_1__HFE_S3       0x1F04028C,0x01FF0000
#define SRM_ISP_HFE_S_1__HFE_S2       0x1F04028C,0x000001FF

#define SRM_ISP_HFE_S_2__ADDR                   0x1F040290
#define SRM_ISP_HFE_S_2__EMPTY       0x1F040290,0x00000000
#define SRM_ISP_HFE_S_2__FULL       0x1F040290,0xffffffff
#define SRM_ISP_HFE_S_2__HFE_S5       0x1F040290,0x01FF0000
#define SRM_ISP_HFE_S_2__HFE_S4       0x1F040290,0x000001FF

#define SRM_ISP_HFE_S_3__ADDR                   0x1F040294
#define SRM_ISP_HFE_S_3__EMPTY       0x1F040294,0x00000000
#define SRM_ISP_HFE_S_3__FULL       0x1F040294,0xffffffff
#define SRM_ISP_HFE_S_3__HFE_S7       0x1F040294,0x01FF0000
#define SRM_ISP_HFE_S_3__HFE_S6       0x1F040294,0x000001FF

#define SRM_ISP_HFE_C_0__ADDR                   0x1F040298
#define SRM_ISP_HFE_C_0__EMPTY       0x1F040298,0x00000000
#define SRM_ISP_HFE_C_0__FULL       0x1F040298,0xffffffff
#define SRM_ISP_HFE_C_0__HFE_C1       0x1F040298,0x01FF0000
#define SRM_ISP_HFE_C_0__HFE_C0       0x1F040298,0x000001FF

#define SRM_ISP_HFE_C_1__ADDR                   0x1F04029C
#define SRM_ISP_HFE_C_1__EMPTY       0x1F04029C,0x00000000
#define SRM_ISP_HFE_C_1__FULL       0x1F04029C,0xffffffff
#define SRM_ISP_HFE_C_1__HFE_C3       0x1F04029C,0x01FF0000
#define SRM_ISP_HFE_C_1__HFE_C2       0x1F04029C,0x000001FF

#define SRM_ISP_HFE_C_2__ADDR                   0x1F0402A0
#define SRM_ISP_HFE_C_2__EMPTY       0x1F0402A0,0x00000000
#define SRM_ISP_HFE_C_2__FULL       0x1F0402A0,0xffffffff
#define SRM_ISP_HFE_C_2__HFE_C5       0x1F0402A0,0x01FF0000
#define SRM_ISP_HFE_C_2__HFE_C4       0x1F0402A0,0x000001FF

#define SRM_ISP_HFE_C_3__ADDR                   0x1F0402A4
#define SRM_ISP_HFE_C_3__EMPTY       0x1F0402A4,0x00000000
#define SRM_ISP_HFE_C_3__FULL       0x1F0402A4,0xffffffff
#define SRM_ISP_HFE_C_3__HFE_C7       0x1F0402A4,0x01FF0000
#define SRM_ISP_HFE_C_3__HFE_C6       0x1F0402A4,0x000001FF

#define SRM_ISP_STC_0__ADDR                   0x1F0402A8
#define SRM_ISP_STC_0__EMPTY       0x1F0402A8,0x00000000
#define SRM_ISP_STC_0__FULL       0x1F0402A8,0xffffffff
#define SRM_ISP_STC_0__VNMBR_BLKS       0x1F0402A8,0x03E00000
#define SRM_ISP_STC_0__HNMBR_BLKS       0x1F0402A8,0x001F0000
#define SRM_ISP_STC_0__PIX_SKIP       0x1F0402A8,0x00006000
#define SRM_ISP_STC_0__VBLK_EXP       0x1F0402A8,0x00001C00
#define SRM_ISP_STC_0__VBLK_MNTS       0x1F0402A8,0x00000300
#define SRM_ISP_STC_0__HBLK_EXP       0x1F0402A8,0x000000E0
#define SRM_ISP_STC_0__HBLK_MNTS       0x1F0402A8,0x00000018
#define SRM_ISP_STC_0__Y_HT_EN       0x1F0402A8,0x00000004
#define SRM_ISP_STC_0__RAW_HT_EN       0x1F0402A8,0x00000002
#define SRM_ISP_STC_0__ST_EN       0x1F0402A8,0x00000001

#define SRM_ISP_STC_1__ADDR                   0x1F0402AC
#define SRM_ISP_STC_1__EMPTY       0x1F0402AC,0x00000000
#define SRM_ISP_STC_1__FULL       0x1F0402AC,0xffffffff
#define SRM_ISP_STC_1__TOP_SKIP       0x1F0402AC,0x07FF0000
#define SRM_ISP_STC_1__LEFT_SKIP       0x1F0402AC,0x000007FF

#define SRM_ISP_FC_0__ADDR                   0x1F0402B0
#define SRM_ISP_FC_0__EMPTY       0x1F0402B0,0x00000000
#define SRM_ISP_FC_0__FULL       0x1F0402B0,0xffffffff
#define SRM_ISP_FC_0__FL_LAST_PHASE       0x1F0402B0,0x00007FE0
#define SRM_ISP_FC_0__FL_SHIFT       0x1F0402B0,0x0000001F

#define SRM_ISP_FC_1__ADDR                   0x1F0402B4
#define SRM_ISP_FC_1__EMPTY       0x1F0402B4,0x00000000
#define SRM_ISP_FC_1__FULL       0x1F0402B4,0xffffffff
#define SRM_ISP_FC_1__FL_PHASE       0x1F0402B4,0x000FFFFF

#define SRM_ISP_DC1__ADDR                   0x1F0402B8
#define SRM_ISP_DC1__EMPTY       0x1F0402B8,0x00000000
#define SRM_ISP_DC1__FULL       0x1F0402B8,0xffffffff
#define SRM_ISP_DC1__SMOOTH       0x1F0402B8,0x7C000000
#define SRM_ISP_DC1__NOSTEP       0x1F0402B8,0x03E00000
#define SRM_ISP_DC1__NOLINE       0x1F0402B8,0x001F0000
#define SRM_ISP_DC1__BOTHSTEP       0x1F0402B8,0x00003800
#define SRM_ISP_DC1__LNSHIFTN       0x1F0402B8,0x00000600
#define SRM_ISP_DC1__LNSHIFTM       0x1F0402B8,0x00000180
#define SRM_ISP_DC1__NOLINEINSTEP       0x1F0402B8,0x0000007C
#define SRM_ISP_DC1__ALIASSHIFT       0x1F0402B8,0x00000003

#define SRM_ISP_DC2__ADDR                   0x1F0402BC
#define SRM_ISP_DC2__EMPTY       0x1F0402BC,0x00000000
#define SRM_ISP_DC2__FULL       0x1F0402BC,0xffffffff
#define SRM_ISP_DC2__NOSTEPNOISE       0x1F0402BC,0x03E00000
#define SRM_ISP_DC2__NOLINENOISE       0x1F0402BC,0x001F0000
#define SRM_ISP_DC2__ACT       0x1F0402BC,0x00007C00
#define SRM_ISP_DC2__MSMOOTH       0x1F0402BC,0x00000180
#define SRM_ISP_DC2__MBRIGHT       0x1F0402BC,0x00000060
#define SRM_ISP_DC2__BRIGHT       0x1F0402BC,0x0000001F

#define SRM_ISP_DC3__ADDR                   0x1F0402C0
#define SRM_ISP_DC3__EMPTY       0x1F0402C0,0x00000000
#define SRM_ISP_DC3__FULL       0x1F0402C0,0xffffffff
#define SRM_ISP_DC3__NORIMNOISE       0x1F0402C0,0x000003FF

#define SRM_CSI0_CPD_CTRL__ADDR                   0x1F0402C4
#define SRM_CSI0_CPD_CTRL__EMPTY       0x1F0402C4,0x00000000
#define SRM_CSI0_CPD_CTRL__FULL       0x1F0402C4,0xffffffff
#define SRM_CSI0_CPD_CTRL__CSI0_CPD       0x1F0402C4,0x0000001C
#define SRM_CSI0_CPD_CTRL__CSI0_RED_ROW_BEGIN       0x1F0402C4,0x00000002
#define SRM_CSI0_CPD_CTRL__CSI0_GREEN_P_BEGIN       0x1F0402C4,0x00000001

#define SRM_CSI0_CPD_RC_0__ADDR                   0x1F0402C8
#define SRM_CSI0_CPD_RC_0__EMPTY       0x1F0402C8,0x00000000
#define SRM_CSI0_CPD_RC_0__FULL       0x1F0402C8,0xffffffff
#define SRM_CSI0_CPD_RC_0__CSI0_CPD_RC_1       0x1F0402C8,0x01FF0000
#define SRM_CSI0_CPD_RC_0__CSI0_CPD_RC_0       0x1F0402C8,0x000001FF

#define SRM_CSI0_CPD_RC_1__ADDR                   0x1F0402CC
#define SRM_CSI0_CPD_RC_1__EMPTY       0x1F0402CC,0x00000000
#define SRM_CSI0_CPD_RC_1__FULL       0x1F0402CC,0xffffffff
#define SRM_CSI0_CPD_RC_1__CSI0_CPD_RC_3       0x1F0402CC,0x01FF0000
#define SRM_CSI0_CPD_RC_1__CSI0_CPD_RC_2       0x1F0402CC,0x000001FF

#define SRM_CSI0_CPD_RC_2__ADDR                   0x1F0402D0
#define SRM_CSI0_CPD_RC_2__EMPTY       0x1F0402D0,0x00000000
#define SRM_CSI0_CPD_RC_2__FULL       0x1F0402D0,0xffffffff
#define SRM_CSI0_CPD_RC_2__CSI0_CPD_RC_5       0x1F0402D0,0x01FF0000
#define SRM_CSI0_CPD_RC_2__CSI0_CPD_RC_4       0x1F0402D0,0x000001FF

#define SRM_CSI0_CPD_RC_3__ADDR                   0x1F0402D4
#define SRM_CSI0_CPD_RC_3__EMPTY       0x1F0402D4,0x00000000
#define SRM_CSI0_CPD_RC_3__FULL       0x1F0402D4,0xffffffff
#define SRM_CSI0_CPD_RC_3__CSI0_CPD_RC_7       0x1F0402D4,0x01FF0000
#define SRM_CSI0_CPD_RC_3__CSI0_CPD_RC_6       0x1F0402D4,0x000001FF

#define SRM_CSI0_CPD_RC_4__ADDR                   0x1F0402D8
#define SRM_CSI0_CPD_RC_4__EMPTY       0x1F0402D8,0x00000000
#define SRM_CSI0_CPD_RC_4__FULL       0x1F0402D8,0xffffffff
#define SRM_CSI0_CPD_RC_4__CSI0_CPD_RC_9       0x1F0402D8,0x01FF0000
#define SRM_CSI0_CPD_RC_4__CSI0_CPD_RC_8       0x1F0402D8,0x000001FF

#define SRM_CSI0_CPD_RC_5__ADDR                   0x1F0402DC
#define SRM_CSI0_CPD_RC_5__EMPTY       0x1F0402DC,0x00000000
#define SRM_CSI0_CPD_RC_5__FULL       0x1F0402DC,0xffffffff
#define SRM_CSI0_CPD_RC_5__CSI0_CPD_RC_11       0x1F0402DC,0x01FF0000
#define SRM_CSI0_CPD_RC_5__CSI0_CPD_RC_10       0x1F0402DC,0x000001FF

#define SRM_CSI0_CPD_RC_6__ADDR                   0x1F0402E0
#define SRM_CSI0_CPD_RC_6__EMPTY       0x1F0402E0,0x00000000
#define SRM_CSI0_CPD_RC_6__FULL       0x1F0402E0,0xffffffff
#define SRM_CSI0_CPD_RC_6__CSI0_CPD_RC_13       0x1F0402E0,0x01FF0000
#define SRM_CSI0_CPD_RC_6__CSI0_CPD_RC_12       0x1F0402E0,0x000001FF

#define SRM_CSI0_CPD_RC_7__ADDR                   0x1F0402E4
#define SRM_CSI0_CPD_RC_7__EMPTY       0x1F0402E4,0x00000000
#define SRM_CSI0_CPD_RC_7__FULL       0x1F0402E4,0xffffffff
#define SRM_CSI0_CPD_RC_7__CSI0_CPD_RC_15       0x1F0402E4,0x01FF0000
#define SRM_CSI0_CPD_RC_7__CSI0_CPD_RC_14       0x1F0402E4,0x000001FF

#define SRM_CSI0_CPD_RS_0__ADDR                   0x1F0402E8
#define SRM_CSI0_CPD_RS_0__EMPTY       0x1F0402E8,0x00000000
#define SRM_CSI0_CPD_RS_0__FULL       0x1F0402E8,0xffffffff
#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS3       0x1F0402E8,0xFF000000
#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS2       0x1F0402E8,0x00FF0000
#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS1       0x1F0402E8,0x0000FF00
#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS0       0x1F0402E8,0x000000FF

#define SRM_CSI0_CPD_RS_1__ADDR                   0x1F0402EC
#define SRM_CSI0_CPD_RS_1__EMPTY       0x1F0402EC,0x00000000
#define SRM_CSI0_CPD_RS_1__FULL       0x1F0402EC,0xffffffff
#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS7       0x1F0402EC,0xFF000000
#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS6       0x1F0402EC,0x00FF0000
#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS5       0x1F0402EC,0x0000FF00
#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS4       0x1F0402EC,0x000000FF

#define SRM_CSI0_CPD_RS_2__ADDR                   0x1F0402F0
#define SRM_CSI0_CPD_RS_2__EMPTY       0x1F0402F0,0x00000000
#define SRM_CSI0_CPD_RS_2__FULL       0x1F0402F0,0xffffffff
#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS11       0x1F0402F0,0xFF000000
#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS10       0x1F0402F0,0x00FF0000
#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS9       0x1F0402F0,0x0000FF00
#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS8       0x1F0402F0,0x000000FF

#define SRM_CSI0_CPD_RS_3__ADDR                   0x1F0402F4
#define SRM_CSI0_CPD_RS_3__EMPTY       0x1F0402F4,0x00000000
#define SRM_CSI0_CPD_RS_3__FULL       0x1F0402F4,0xffffffff
#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS15       0x1F0402F4,0xFF000000
#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS14       0x1F0402F4,0x00FF0000
#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS13       0x1F0402F4,0x0000FF00
#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS12       0x1F0402F4,0x000000FF

#define SRM_CSI0_CPD_GRC_0__ADDR                   0x1F0402F8
#define SRM_CSI0_CPD_GRC_0__EMPTY       0x1F0402F8,0x00000000
#define SRM_CSI0_CPD_GRC_0__FULL       0x1F0402F8,0xffffffff
#define SRM_CSI0_CPD_GRC_0__CSI0_CPD_GRC1       0x1F0402F8,0x01FF0000
#define SRM_CSI0_CPD_GRC_0__CSI0_CPD_GRC0       0x1F0402F8,0x000001FF

#define SRM_CSI0_CPD_GRC_1__ADDR                   0x1F0402FC
#define SRM_CSI0_CPD_GRC_1__EMPTY       0x1F0402FC,0x00000000
#define SRM_CSI0_CPD_GRC_1__FULL       0x1F0402FC,0xffffffff
#define SRM_CSI0_CPD_GRC_1__CSI0_CPD_GRC3       0x1F0402FC,0x01FF0000
#define SRM_CSI0_CPD_GRC_1__CSI0_CPD_GRC2       0x1F0402FC,0x000001FF

#define SRM_CSI0_CPD_GRC_2__ADDR                   0x1F040300
#define SRM_CSI0_CPD_GRC_2__EMPTY       0x1F040300,0x00000000
#define SRM_CSI0_CPD_GRC_2__FULL       0x1F040300,0xffffffff
#define SRM_CSI0_CPD_GRC_2__CSI0_CPD_GRC5       0x1F040300,0x01FF0000
#define SRM_CSI0_CPD_GRC_2__CSI0_CPD_GRC4       0x1F040300,0x000001FF

#define SRM_CSI0_CPD_GRC_3__ADDR                   0x1F040304
#define SRM_CSI0_CPD_GRC_3__EMPTY       0x1F040304,0x00000000
#define SRM_CSI0_CPD_GRC_3__FULL       0x1F040304,0xffffffff
#define SRM_CSI0_CPD_GRC_3__CSI0_CPD_GRC7       0x1F040304,0x01FF0000
#define SRM_CSI0_CPD_GRC_3__CSI0_CPD_GRC6       0x1F040304,0x000001FF

#define SRM_CSI0_CPD_GRC_4__ADDR                   0x1F040308
#define SRM_CSI0_CPD_GRC_4__EMPTY       0x1F040308,0x00000000
#define SRM_CSI0_CPD_GRC_4__FULL       0x1F040308,0xffffffff
#define SRM_CSI0_CPD_GRC_4__CSI0_CPD_GRC9       0x1F040308,0x01FF0000
#define SRM_CSI0_CPD_GRC_4__CSI0_CPD_GRC8       0x1F040308,0x000001FF

#define SRM_CSI0_CPD_GRC_5__ADDR                   0x1F04030C
#define SRM_CSI0_CPD_GRC_5__EMPTY       0x1F04030C,0x00000000
#define SRM_CSI0_CPD_GRC_5__FULL       0x1F04030C,0xffffffff
#define SRM_CSI0_CPD_GRC_5__CSI0_CPD_GRC11       0x1F04030C,0x01FF0000
#define SRM_CSI0_CPD_GRC_5__CSI0_CPD_GRC10       0x1F04030C,0x000001FF

#define SRM_CSI0_CPD_GRC_6__ADDR                   0x1F040310
#define SRM_CSI0_CPD_GRC_6__EMPTY       0x1F040310,0x00000000
#define SRM_CSI0_CPD_GRC_6__FULL       0x1F040310,0xffffffff
#define SRM_CSI0_CPD_GRC_6__CSI0_CPD_GRC13       0x1F040310,0x01FF0000
#define SRM_CSI0_CPD_GRC_6__CSI0_CPD_GRC12       0x1F040310,0x000001FF

#define SRM_CSI0_CPD_GRC_7__ADDR                   0x1F040314
#define SRM_CSI0_CPD_GRC_7__EMPTY       0x1F040314,0x00000000
#define SRM_CSI0_CPD_GRC_7__FULL       0x1F040314,0xffffffff
#define SRM_CSI0_CPD_GRC_7__CSI0_CPD_GRC15       0x1F040314,0x01FF0000
#define SRM_CSI0_CPD_GRC_7__CSI0_CPD_GRC14       0x1F040314,0x000001FF

#define SRM_CSI0_CPD_GRS_0__ADDR                   0x1F040318
#define SRM_CSI0_CPD_GRS_0__EMPTY       0x1F040318,0x00000000
#define SRM_CSI0_CPD_GRS_0__FULL       0x1F040318,0xffffffff
#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS3       0x1F040318,0xFF000000
#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS2       0x1F040318,0x00FF0000
#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS1       0x1F040318,0x0000FF00
#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS0       0x1F040318,0x000000FF

#define SRM_CSI0_CPD_GRS_1__ADDR                   0x1F04031C
#define SRM_CSI0_CPD_GRS_1__EMPTY       0x1F04031C,0x00000000
#define SRM_CSI0_CPD_GRS_1__FULL       0x1F04031C,0xffffffff
#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS7       0x1F04031C,0xFF000000
#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS6       0x1F04031C,0x00FF0000
#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS5       0x1F04031C,0x0000FF00
#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS4       0x1F04031C,0x000000FF

#define SRM_CSI0_CPD_GRS_2__ADDR                   0x1F040320
#define SRM_CSI0_CPD_GRS_2__EMPTY       0x1F040320,0x00000000
#define SRM_CSI0_CPD_GRS_2__FULL       0x1F040320,0xffffffff
#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS11       0x1F040320,0xFF000000
#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS10       0x1F040320,0x00FF0000
#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS9       0x1F040320,0x0000FF00
#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS8       0x1F040320,0x000000FF

#define SRM_CSI0_CPD_GRS_3__ADDR                   0x1F040324
#define SRM_CSI0_CPD_GRS_3__EMPTY       0x1F040324,0x00000000
#define SRM_CSI0_CPD_GRS_3__FULL       0x1F040324,0xffffffff
#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS15       0x1F040324,0xFF000000
#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS14       0x1F040324,0x00FF0000
#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS13       0x1F040324,0x0000FF00
#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS12       0x1F040324,0x000000FF

#define SRM_CSI0_CPD_GBC_0__ADDR                   0x1F040328
#define SRM_CSI0_CPD_GBC_0__EMPTY       0x1F040328,0x00000000
#define SRM_CSI0_CPD_GBC_0__FULL       0x1F040328,0xffffffff
#define SRM_CSI0_CPD_GBC_0__CSI0_CPD_GBC1       0x1F040328,0x01FF0000
#define SRM_CSI0_CPD_GBC_0__CSI0_CPD_GBC0       0x1F040328,0x000001FF

#define SRM_CSI0_CPD_GBC_1__ADDR                   0x1F04032C
#define SRM_CSI0_CPD_GBC_1__EMPTY       0x1F04032C,0x00000000
#define SRM_CSI0_CPD_GBC_1__FULL       0x1F04032C,0xffffffff
#define SRM_CSI0_CPD_GBC_1__CSI0_CPD_GBC3       0x1F04032C,0x01FF0000
#define SRM_CSI0_CPD_GBC_1__CSI0_CPD_GBC2       0x1F04032C,0x000001FF

#define SRM_CSI0_CPD_GBC_2__ADDR                   0x1F040330
#define SRM_CSI0_CPD_GBC_2__EMPTY       0x1F040330,0x00000000
#define SRM_CSI0_CPD_GBC_2__FULL       0x1F040330,0xffffffff
#define SRM_CSI0_CPD_GBC_2__CSI0_CPD_GBC5       0x1F040330,0x01FF0000
#define SRM_CSI0_CPD_GBC_2__CSI0_CPD_GBC4       0x1F040330,0x000001FF

#define SRM_CSI0_CPD_GBC_3__ADDR                   0x1F040334
#define SRM_CSI0_CPD_GBC_3__EMPTY       0x1F040334,0x00000000
#define SRM_CSI0_CPD_GBC_3__FULL       0x1F040334,0xffffffff
#define SRM_CSI0_CPD_GBC_3__CSI0_CPD_GBC7       0x1F040334,0x01FF0000
#define SRM_CSI0_CPD_GBC_3__CSI0_CPD_GBC6       0x1F040334,0x000001FF

#define SRM_CSI0_CPD_GBC_4__ADDR                   0x1F040338
#define SRM_CSI0_CPD_GBC_4__EMPTY       0x1F040338,0x00000000
#define SRM_CSI0_CPD_GBC_4__FULL       0x1F040338,0xffffffff
#define SRM_CSI0_CPD_GBC_4__CSI0_CPD_GBC9       0x1F040338,0x01FF0000
#define SRM_CSI0_CPD_GBC_4__CSI0_CPD_GBC8       0x1F040338,0x000001FF

#define SRM_CSI0_CPD_GBC_5__ADDR                   0x1F04033C
#define SRM_CSI0_CPD_GBC_5__EMPTY       0x1F04033C,0x00000000
#define SRM_CSI0_CPD_GBC_5__FULL       0x1F04033C,0xffffffff
#define SRM_CSI0_CPD_GBC_5__CSI0_CPD_GBC11       0x1F04033C,0x01FF0000
#define SRM_CSI0_CPD_GBC_5__CSI0_CPD_GBC10       0x1F04033C,0x000001FF

#define SRM_CSI0_CPD_GBC_6__ADDR                   0x1F040340
#define SRM_CSI0_CPD_GBC_6__EMPTY       0x1F040340,0x00000000
#define SRM_CSI0_CPD_GBC_6__FULL       0x1F040340,0xffffffff
#define SRM_CSI0_CPD_GBC_6__CSI0_CPD_GBC13       0x1F040340,0x01FF0000
#define SRM_CSI0_CPD_GBC_6__CSI0_CPD_GBC12       0x1F040340,0x000001FF

#define SRM_CSI0_CPD_GBC_7__ADDR                   0x1F040344
#define SRM_CSI0_CPD_GBC_7__EMPTY       0x1F040344,0x00000000
#define SRM_CSI0_CPD_GBC_7__FULL       0x1F040344,0xffffffff
#define SRM_CSI0_CPD_GBC_7__CSI0_CPD_GBC15       0x1F040344,0x01FF0000
#define SRM_CSI0_CPD_GBC_7__CSI0_CPD_GBC14       0x1F040344,0x000001FF

#define SRM_CSI0_CPD_GBS_0__ADDR                   0x1F040348
#define SRM_CSI0_CPD_GBS_0__EMPTY       0x1F040348,0x00000000
#define SRM_CSI0_CPD_GBS_0__FULL       0x1F040348,0xffffffff
#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS3       0x1F040348,0xFF000000
#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS2       0x1F040348,0x00FF0000
#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS1       0x1F040348,0x0000FF00
#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS0       0x1F040348,0x000000FF

#define SRM_CSI0_CPD_GBS_1__ADDR                   0x1F04034C
#define SRM_CSI0_CPD_GBS_1__EMPTY       0x1F04034C,0x00000000
#define SRM_CSI0_CPD_GBS_1__FULL       0x1F04034C,0xffffffff
#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS7       0x1F04034C,0xFF000000
#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS6       0x1F04034C,0x00FF0000
#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS5       0x1F04034C,0x0000FF00
#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS4       0x1F04034C,0x000000FF

#define SRM_CSI0_CPD_GBS_2__ADDR                   0x1F040350
#define SRM_CSI0_CPD_GBS_2__EMPTY       0x1F040350,0x00000000
#define SRM_CSI0_CPD_GBS_2__FULL       0x1F040350,0xffffffff
#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS11       0x1F040350,0xFF000000
#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS10       0x1F040350,0x00FF0000
#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS9       0x1F040350,0x0000FF00
#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS8       0x1F040350,0x000000FF

#define SRM_CSI0_CPD_GBS_3__ADDR                   0x1F040354
#define SRM_CSI0_CPD_GBS_3__EMPTY       0x1F040354,0x00000000
#define SRM_CSI0_CPD_GBS_3__FULL       0x1F040354,0xffffffff
#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS15       0x1F040354,0xFF000000
#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS14       0x1F040354,0x00FF0000
#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS13       0x1F040354,0x0000FF00
#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS12       0x1F040354,0x000000FF

#define SRM_CSI0_CPD_BC_0__ADDR                   0x1F040358
#define SRM_CSI0_CPD_BC_0__EMPTY       0x1F040358,0x00000000
#define SRM_CSI0_CPD_BC_0__FULL       0x1F040358,0xffffffff
#define SRM_CSI0_CPD_BC_0__CSI0_CPD_BC1       0x1F040358,0x01FF0000
#define SRM_CSI0_CPD_BC_0__CSI0_CPD_BC0       0x1F040358,0x000001FF

#define SRM_CSI0_CPD_BC_1__ADDR                   0x1F04035C
#define SRM_CSI0_CPD_BC_1__EMPTY       0x1F04035C,0x00000000
#define SRM_CSI0_CPD_BC_1__FULL       0x1F04035C,0xffffffff
#define SRM_CSI0_CPD_BC_1__CSI0_CPD_BC3       0x1F04035C,0x01FF0000
#define SRM_CSI0_CPD_BC_1__CSI0_CPD_BC2       0x1F04035C,0x000001FF

#define SRM_CSI0_CPD_BC_2__ADDR                   0x1F040360
#define SRM_CSI0_CPD_BC_2__EMPTY       0x1F040360,0x00000000
#define SRM_CSI0_CPD_BC_2__FULL       0x1F040360,0xffffffff
#define SRM_CSI0_CPD_BC_2__CSI0_CPD_BC5       0x1F040360,0x01FF0000
#define SRM_CSI0_CPD_BC_2__CSI0_CPD_BC4       0x1F040360,0x000001FF

#define SRM_CSI0_CPD_BC_3__ADDR                   0x1F040364
#define SRM_CSI0_CPD_BC_3__EMPTY       0x1F040364,0x00000000
#define SRM_CSI0_CPD_BC_3__FULL       0x1F040364,0xffffffff
#define SRM_CSI0_CPD_BC_3__CSI0_CPD_BC7       0x1F040364,0x01FF0000
#define SRM_CSI0_CPD_BC_3__CSI0_CPD_BC6       0x1F040364,0x000001FF

#define SRM_CSI0_CPD_BC_4__ADDR                   0x1F040368
#define SRM_CSI0_CPD_BC_4__EMPTY       0x1F040368,0x00000000
#define SRM_CSI0_CPD_BC_4__FULL       0x1F040368,0xffffffff
#define SRM_CSI0_CPD_BC_4__CSI0_CPD_BC9       0x1F040368,0x01FF0000
#define SRM_CSI0_CPD_BC_4__CSI0_CPD_BC8       0x1F040368,0x000001FF

#define SRM_CSI0_CPD_BC_5__ADDR                   0x1F04036C
#define SRM_CSI0_CPD_BC_5__EMPTY       0x1F04036C,0x00000000
#define SRM_CSI0_CPD_BC_5__FULL       0x1F04036C,0xffffffff
#define SRM_CSI0_CPD_BC_5__CSI0_CPD_BC11       0x1F04036C,0x01FF0000
#define SRM_CSI0_CPD_BC_5__CSI0_CPD_BC10       0x1F04036C,0x000001FF

#define SRM_CSI0_CPD_BC_6__ADDR                   0x1F040370
#define SRM_CSI0_CPD_BC_6__EMPTY       0x1F040370,0x00000000
#define SRM_CSI0_CPD_BC_6__FULL       0x1F040370,0xffffffff
#define SRM_CSI0_CPD_BC_6__CSI0_CPD_BC13       0x1F040370,0x01FF0000
#define SRM_CSI0_CPD_BC_6__CSI0_CPD_BC12       0x1F040370,0x000001FF

#define SRM_CSI0_CPD_BC_7__ADDR                   0x1F040374
#define SRM_CSI0_CPD_BC_7__EMPTY       0x1F040374,0x00000000
#define SRM_CSI0_CPD_BC_7__FULL       0x1F040374,0xffffffff
#define SRM_CSI0_CPD_BC_7__CSI0_CPD_BC15       0x1F040374,0x01FF0000
#define SRM_CSI0_CPD_BC_7__CSI0_CPD_BC14       0x1F040374,0x000001FF

#define SRM_CSI0_CPD_BS_0__ADDR                   0x1F040378
#define SRM_CSI0_CPD_BS_0__EMPTY       0x1F040378,0x00000000
#define SRM_CSI0_CPD_BS_0__FULL       0x1F040378,0xffffffff
#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS3       0x1F040378,0xFF000000
#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS2       0x1F040378,0x00FF0000
#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS1       0x1F040378,0x0000FF00
#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS0       0x1F040378,0x000000FF

#define SRM_CSI0_CPD_BS_1__ADDR                   0x1F04037C
#define SRM_CSI0_CPD_BS_1__EMPTY       0x1F04037C,0x00000000
#define SRM_CSI0_CPD_BS_1__FULL       0x1F04037C,0xffffffff
#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS7       0x1F04037C,0xFF000000
#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS6       0x1F04037C,0x00FF0000
#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS5       0x1F04037C,0x0000FF00
#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS4       0x1F04037C,0x000000FF

#define SRM_CSI0_CPD_BS_2__ADDR                   0x1F040380
#define SRM_CSI0_CPD_BS_2__EMPTY       0x1F040380,0x00000000
#define SRM_CSI0_CPD_BS_2__FULL       0x1F040380,0xffffffff
#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS11       0x1F040380,0xFF000000
#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS10       0x1F040380,0x00FF0000
#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS9       0x1F040380,0x0000FF00
#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS8       0x1F040380,0x000000FF

#define SRM_CSI0_CPD_BS_3__ADDR                   0x1F040384
#define SRM_CSI0_CPD_BS_3__EMPTY       0x1F040384,0x00000000
#define SRM_CSI0_CPD_BS_3__FULL       0x1F040384,0xffffffff
#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS15       0x1F040384,0xFF000000
#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS14       0x1F040384,0x00FF0000
#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS13       0x1F040384,0x0000FF00
#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS12       0x1F040384,0x000000FF

#define SRM_CSI0_CPD_OFFSET1__ADDR                   0x1F040388
#define SRM_CSI0_CPD_OFFSET1__EMPTY       0x1F040388,0x00000000
#define SRM_CSI0_CPD_OFFSET1__FULL       0x1F040388,0xffffffff
#define SRM_CSI0_CPD_OFFSET1__CSI0_CPD_B_OFFSET       0x1F040388,0x3FF00000
#define SRM_CSI0_CPD_OFFSET1__CSI0_CPD_GB_OFFSET       0x1F040388,0x000FFC00
#define SRM_CSI0_CPD_OFFSET1__CSI0_CPD_GR_OFFSET       0x1F040388,0x000003FF

#define SRM_CSI0_CPD_OFFSET2__ADDR                   0x1F04038C
#define SRM_CSI0_CPD_OFFSET2__EMPTY       0x1F04038C,0x00000000
#define SRM_CSI0_CPD_OFFSET2__FULL       0x1F04038C,0xffffffff
#define SRM_CSI0_CPD_OFFSET2__CSI0_CPD_R_OFFSET       0x1F04038C,0x000003FF

#define SRM_CSI1_CPD_CTRL__ADDR                   0x1F040390
#define SRM_CSI1_CPD_CTRL__EMPTY       0x1F040390,0x00000000
#define SRM_CSI1_CPD_CTRL__FULL       0x1F040390,0xffffffff
#define SRM_CSI1_CPD_CTRL__CSI1_CPD       0x1F040390,0x0000001C
#define SRM_CSI1_CPD_CTRL__CSI1_RED_ROW_BEGIN       0x1F040390,0x00000002
#define SRM_CSI1_CPD_CTRL__CSI1_GREEN_P_BEGIN       0x1F040390,0x00000001

#define SRM_CSI1_CPD_RC_0__ADDR                   0x1F040394
#define SRM_CSI1_CPD_RC_0__EMPTY       0x1F040394,0x00000000
#define SRM_CSI1_CPD_RC_0__FULL       0x1F040394,0xffffffff
#define SRM_CSI1_CPD_RC_0__CSI1_CPD_RC_1       0x1F040394,0x01FF0000
#define SRM_CSI1_CPD_RC_0__CSI1_CPD_RC_0       0x1F040394,0x000001FF

#define SRM_CSI1_CPD_RC_1__ADDR                   0x1F040398
#define SRM_CSI1_CPD_RC_1__EMPTY       0x1F040398,0x00000000
#define SRM_CSI1_CPD_RC_1__FULL       0x1F040398,0xffffffff
#define SRM_CSI1_CPD_RC_1__CSI1_CPD_RC_3       0x1F040398,0x01FF0000
#define SRM_CSI1_CPD_RC_1__CSI1_CPD_RC_2       0x1F040398,0x000001FF

#define SRM_CSI1_CPD_RC_2__ADDR                   0x1F04039C
#define SRM_CSI1_CPD_RC_2__EMPTY       0x1F04039C,0x00000000
#define SRM_CSI1_CPD_RC_2__FULL       0x1F04039C,0xffffffff
#define SRM_CSI1_CPD_RC_2__CSI1_CPD_RC_5       0x1F04039C,0x01FF0000
#define SRM_CSI1_CPD_RC_2__CSI1_CPD_RC_4       0x1F04039C,0x000001FF

#define SRM_CSI1_CPD_RC_3__ADDR                   0x1F0403A0
#define SRM_CSI1_CPD_RC_3__EMPTY       0x1F0403A0,0x00000000
#define SRM_CSI1_CPD_RC_3__FULL       0x1F0403A0,0xffffffff
#define SRM_CSI1_CPD_RC_3__CSI1_CPD_RC_7       0x1F0403A0,0x01FF0000
#define SRM_CSI1_CPD_RC_3__CSI1_CPD_RC_6       0x1F0403A0,0x000001FF

#define SRM_CSI1_CPD_RC_4__ADDR                   0x1F0403A4
#define SRM_CSI1_CPD_RC_4__EMPTY       0x1F0403A4,0x00000000
#define SRM_CSI1_CPD_RC_4__FULL       0x1F0403A4,0xffffffff
#define SRM_CSI1_CPD_RC_4__CSI1_CPD_RC_9       0x1F0403A4,0x01FF0000
#define SRM_CSI1_CPD_RC_4__CSI1_CPD_RC_8       0x1F0403A4,0x000001FF

#define SRM_CSI1_CPD_RC_5__ADDR                   0x1F0403A8
#define SRM_CSI1_CPD_RC_5__EMPTY       0x1F0403A8,0x00000000
#define SRM_CSI1_CPD_RC_5__FULL       0x1F0403A8,0xffffffff
#define SRM_CSI1_CPD_RC_5__CSI1_CPD_RC_11       0x1F0403A8,0x01FF0000
#define SRM_CSI1_CPD_RC_5__CSI1_CPD_RC_10       0x1F0403A8,0x000001FF

#define SRM_CSI1_CPD_RC_6__ADDR                   0x1F0403AC
#define SRM_CSI1_CPD_RC_6__EMPTY       0x1F0403AC,0x00000000
#define SRM_CSI1_CPD_RC_6__FULL       0x1F0403AC,0xffffffff
#define SRM_CSI1_CPD_RC_6__CSI1_CPD_RC_13       0x1F0403AC,0x01FF0000
#define SRM_CSI1_CPD_RC_6__CSI1_CPD_RC_12       0x1F0403AC,0x000001FF

#define SRM_CSI1_CPD_RC_7__ADDR                   0x1F0403B0
#define SRM_CSI1_CPD_RC_7__EMPTY       0x1F0403B0,0x00000000
#define SRM_CSI1_CPD_RC_7__FULL       0x1F0403B0,0xffffffff
#define SRM_CSI1_CPD_RC_7__CSI1_CPD_RC_15       0x1F0403B0,0x01FF0000
#define SRM_CSI1_CPD_RC_7__CSI1_CPD_RC_14       0x1F0403B0,0x000001FF

#define SRM_CSI1_CPD_RS_0__ADDR                   0x1F0403B4
#define SRM_CSI1_CPD_RS_0__EMPTY       0x1F0403B4,0x00000000
#define SRM_CSI1_CPD_RS_0__FULL       0x1F0403B4,0xffffffff
#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS3       0x1F0403B4,0xFF000000
#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS2       0x1F0403B4,0x00FF0000
#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS1       0x1F0403B4,0x0000FF00
#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS0       0x1F0403B4,0x000000FF

#define SRM_CSI1_CPD_RS_1__ADDR                   0x1F0403B8
#define SRM_CSI1_CPD_RS_1__EMPTY       0x1F0403B8,0x00000000
#define SRM_CSI1_CPD_RS_1__FULL       0x1F0403B8,0xffffffff
#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS7       0x1F0403B8,0xFF000000
#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS6       0x1F0403B8,0x00FF0000
#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS5       0x1F0403B8,0x0000FF00
#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS4       0x1F0403B8,0x000000FF

#define SRM_CSI1_CPD_RS_2__ADDR                   0x1F0403BC
#define SRM_CSI1_CPD_RS_2__EMPTY       0x1F0403BC,0x00000000
#define SRM_CSI1_CPD_RS_2__FULL       0x1F0403BC,0xffffffff
#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS11       0x1F0403BC,0xFF000000
#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS10       0x1F0403BC,0x00FF0000
#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS9       0x1F0403BC,0x0000FF00
#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS8       0x1F0403BC,0x000000FF

#define SRM_CSI1_CPD_RS_3__ADDR                   0x1F0403C0
#define SRM_CSI1_CPD_RS_3__EMPTY       0x1F0403C0,0x00000000
#define SRM_CSI1_CPD_RS_3__FULL       0x1F0403C0,0xffffffff
#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS15       0x1F0403C0,0xFF000000
#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS14       0x1F0403C0,0x00FF0000
#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS13       0x1F0403C0,0x0000FF00
#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS12       0x1F0403C0,0x000000FF

#define SRM_CSI1_CPD_GRC_0__ADDR                   0x1F0403C4
#define SRM_CSI1_CPD_GRC_0__EMPTY       0x1F0403C4,0x00000000
#define SRM_CSI1_CPD_GRC_0__FULL       0x1F0403C4,0xffffffff
#define SRM_CSI1_CPD_GRC_0__CSI1_CPD_GRC1       0x1F0403C4,0x01FF0000
#define SRM_CSI1_CPD_GRC_0__CSI1_CPD_GRC0       0x1F0403C4,0x000001FF

#define SRM_CSI1_CPD_GRC_1__ADDR                   0x1F0403C8
#define SRM_CSI1_CPD_GRC_1__EMPTY       0x1F0403C8,0x00000000
#define SRM_CSI1_CPD_GRC_1__FULL       0x1F0403C8,0xffffffff
#define SRM_CSI1_CPD_GRC_1__CSI1_CPD_GRC3       0x1F0403C8,0x01FF0000
#define SRM_CSI1_CPD_GRC_1__CSI1_CPD_GRC2       0x1F0403C8,0x000001FF

#define SRM_CSI1_CPD_GRC_2__ADDR                   0x1F0403CC
#define SRM_CSI1_CPD_GRC_2__EMPTY       0x1F0403CC,0x00000000
#define SRM_CSI1_CPD_GRC_2__FULL       0x1F0403CC,0xffffffff
#define SRM_CSI1_CPD_GRC_2__CSI1_CPD_GRC5       0x1F0403CC,0x01FF0000
#define SRM_CSI1_CPD_GRC_2__CSI1_CPD_GRC4       0x1F0403CC,0x000001FF

#define SRM_CSI1_CPD_GRC_3__ADDR                   0x1F0403D0
#define SRM_CSI1_CPD_GRC_3__EMPTY       0x1F0403D0,0x00000000
#define SRM_CSI1_CPD_GRC_3__FULL       0x1F0403D0,0xffffffff
#define SRM_CSI1_CPD_GRC_3__CSI1_CPD_GRC7       0x1F0403D0,0x01FF0000
#define SRM_CSI1_CPD_GRC_3__CSI1_CPD_GRC6       0x1F0403D0,0x000001FF

#define SRM_CSI1_CPD_GRC_4__ADDR                   0x1F0403D4
#define SRM_CSI1_CPD_GRC_4__EMPTY       0x1F0403D4,0x00000000
#define SRM_CSI1_CPD_GRC_4__FULL       0x1F0403D4,0xffffffff
#define SRM_CSI1_CPD_GRC_4__CSI1_CPD_GRC9       0x1F0403D4,0x01FF0000
#define SRM_CSI1_CPD_GRC_4__CSI1_CPD_GRC8       0x1F0403D4,0x000001FF

#define SRM_CSI1_CPD_GRC_5__ADDR                   0x1F0403D8
#define SRM_CSI1_CPD_GRC_5__EMPTY       0x1F0403D8,0x00000000
#define SRM_CSI1_CPD_GRC_5__FULL       0x1F0403D8,0xffffffff
#define SRM_CSI1_CPD_GRC_5__CSI1_CPD_GRC11       0x1F0403D8,0x01FF0000
#define SRM_CSI1_CPD_GRC_5__CSI1_CPD_GRC10       0x1F0403D8,0x000001FF

#define SRM_CSI1_CPD_GRC_6__ADDR                   0x1F0403DC
#define SRM_CSI1_CPD_GRC_6__EMPTY       0x1F0403DC,0x00000000
#define SRM_CSI1_CPD_GRC_6__FULL       0x1F0403DC,0xffffffff
#define SRM_CSI1_CPD_GRC_6__CSI1_CPD_GRC13       0x1F0403DC,0x01FF0000
#define SRM_CSI1_CPD_GRC_6__CSI1_CPD_GRC12       0x1F0403DC,0x000001FF

#define SRM_CSI1_CPD_GRC_7__ADDR                   0x1F0403E0
#define SRM_CSI1_CPD_GRC_7__EMPTY       0x1F0403E0,0x00000000
#define SRM_CSI1_CPD_GRC_7__FULL       0x1F0403E0,0xffffffff
#define SRM_CSI1_CPD_GRC_7__CSI1_CPD_GRC15       0x1F0403E0,0x01FF0000
#define SRM_CSI1_CPD_GRC_7__CSI1_CPD_GRC14       0x1F0403E0,0x000001FF

#define SRM_CSI1_CPD_GRS_0__ADDR                   0x1F0403E4
#define SRM_CSI1_CPD_GRS_0__EMPTY       0x1F0403E4,0x00000000
#define SRM_CSI1_CPD_GRS_0__FULL       0x1F0403E4,0xffffffff
#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS3       0x1F0403E4,0xFF000000
#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS2       0x1F0403E4,0x00FF0000
#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS1       0x1F0403E4,0x0000FF00
#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS0       0x1F0403E4,0x000000FF

#define SRM_CSI1_CPD_GRS_1__ADDR                   0x1F0403E8
#define SRM_CSI1_CPD_GRS_1__EMPTY       0x1F0403E8,0x00000000
#define SRM_CSI1_CPD_GRS_1__FULL       0x1F0403E8,0xffffffff
#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS7       0x1F0403E8,0xFF000000
#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS6       0x1F0403E8,0x00FF0000
#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS5       0x1F0403E8,0x0000FF00
#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS4       0x1F0403E8,0x000000FF

#define SRM_CSI1_CPD_GRS_2__ADDR                   0x1F0403EC
#define SRM_CSI1_CPD_GRS_2__EMPTY       0x1F0403EC,0x00000000
#define SRM_CSI1_CPD_GRS_2__FULL       0x1F0403EC,0xffffffff
#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS11       0x1F0403EC,0xFF000000
#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS10       0x1F0403EC,0x00FF0000
#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS9       0x1F0403EC,0x0000FF00
#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS8       0x1F0403EC,0x000000FF

#define SRM_CSI1_CPD_GRS_3__ADDR                   0x1F0403F0
#define SRM_CSI1_CPD_GRS_3__EMPTY       0x1F0403F0,0x00000000
#define SRM_CSI1_CPD_GRS_3__FULL       0x1F0403F0,0xffffffff
#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS15       0x1F0403F0,0xFF000000
#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS14       0x1F0403F0,0x00FF0000
#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS13       0x1F0403F0,0x0000FF00
#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS12       0x1F0403F0,0x000000FF

#define SRM_CSI1_CPD_GBC_0__ADDR                   0x1F0403F4
#define SRM_CSI1_CPD_GBC_0__EMPTY       0x1F0403F4,0x00000000
#define SRM_CSI1_CPD_GBC_0__FULL       0x1F0403F4,0xffffffff
#define SRM_CSI1_CPD_GBC_0__CSI1_CPD_GBC1       0x1F0403F4,0x01FF0000
#define SRM_CSI1_CPD_GBC_0__CSI1_CPD_GBC0       0x1F0403F4,0x000001FF

#define SRM_CSI1_CPD_GBC_1__ADDR                   0x1F0403F8
#define SRM_CSI1_CPD_GBC_1__EMPTY       0x1F0403F8,0x00000000
#define SRM_CSI1_CPD_GBC_1__FULL       0x1F0403F8,0xffffffff
#define SRM_CSI1_CPD_GBC_1__CSI1_CPD_GBC3       0x1F0403F8,0x01FF0000
#define SRM_CSI1_CPD_GBC_1__CSI1_CPD_GBC2       0x1F0403F8,0x000001FF

#define SRM_CSI1_CPD_GBC_2__ADDR                   0x1F0403FC
#define SRM_CSI1_CPD_GBC_2__EMPTY       0x1F0403FC,0x00000000
#define SRM_CSI1_CPD_GBC_2__FULL       0x1F0403FC,0xffffffff
#define SRM_CSI1_CPD_GBC_2__CSI1_CPD_GBC5       0x1F0403FC,0x01FF0000
#define SRM_CSI1_CPD_GBC_2__CSI1_CPD_GBC4       0x1F0403FC,0x000001FF

#define SRM_CSI1_CPD_GBC_3__ADDR                   0x1F040400
#define SRM_CSI1_CPD_GBC_3__EMPTY       0x1F040400,0x00000000
#define SRM_CSI1_CPD_GBC_3__FULL       0x1F040400,0xffffffff
#define SRM_CSI1_CPD_GBC_3__CSI1_CPD_GBC7       0x1F040400,0x01FF0000
#define SRM_CSI1_CPD_GBC_3__CSI1_CPD_GBC6       0x1F040400,0x000001FF

#define SRM_CSI1_CPD_GBC_4__ADDR                   0x1F040404
#define SRM_CSI1_CPD_GBC_4__EMPTY       0x1F040404,0x00000000
#define SRM_CSI1_CPD_GBC_4__FULL       0x1F040404,0xffffffff
#define SRM_CSI1_CPD_GBC_4__CSI1_CPD_GBC9       0x1F040404,0x01FF0000
#define SRM_CSI1_CPD_GBC_4__CSI1_CPD_GBC8       0x1F040404,0x000001FF

#define SRM_CSI1_CPD_GBC_5__ADDR                   0x1F040408
#define SRM_CSI1_CPD_GBC_5__EMPTY       0x1F040408,0x00000000
#define SRM_CSI1_CPD_GBC_5__FULL       0x1F040408,0xffffffff
#define SRM_CSI1_CPD_GBC_5__CSI1_CPD_GBC11       0x1F040408,0x01FF0000
#define SRM_CSI1_CPD_GBC_5__CSI1_CPD_GBC10       0x1F040408,0x000001FF

#define SRM_CSI1_CPD_GBC_6__ADDR                   0x1F04040C
#define SRM_CSI1_CPD_GBC_6__EMPTY       0x1F04040C,0x00000000
#define SRM_CSI1_CPD_GBC_6__FULL       0x1F04040C,0xffffffff
#define SRM_CSI1_CPD_GBC_6__CSI1_CPD_GBC13       0x1F04040C,0x01FF0000
#define SRM_CSI1_CPD_GBC_6__CSI1_CPD_GBC12       0x1F04040C,0x000001FF

#define SRM_CSI1_CPD_GBC_7__ADDR                   0x1F040410
#define SRM_CSI1_CPD_GBC_7__EMPTY       0x1F040410,0x00000000
#define SRM_CSI1_CPD_GBC_7__FULL       0x1F040410,0xffffffff
#define SRM_CSI1_CPD_GBC_7__CSI1_CPD_GBC15       0x1F040410,0x01FF0000
#define SRM_CSI1_CPD_GBC_7__CSI1_CPD_GBC14       0x1F040410,0x000001FF

#define SRM_CSI1_CPD_GBS_0__ADDR                   0x1F040414
#define SRM_CSI1_CPD_GBS_0__EMPTY       0x1F040414,0x00000000
#define SRM_CSI1_CPD_GBS_0__FULL       0x1F040414,0xffffffff
#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS3       0x1F040414,0xFF000000
#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS2       0x1F040414,0x00FF0000
#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS1       0x1F040414,0x0000FF00
#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS0       0x1F040414,0x000000FF

#define SRM_CSI1_CPD_GBS_1__ADDR                   0x1F040418
#define SRM_CSI1_CPD_GBS_1__EMPTY       0x1F040418,0x00000000
#define SRM_CSI1_CPD_GBS_1__FULL       0x1F040418,0xffffffff
#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS7       0x1F040418,0xFF000000
#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS6       0x1F040418,0x00FF0000
#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS5       0x1F040418,0x0000FF00
#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS4       0x1F040418,0x000000FF

#define SRM_CSI1_CPD_GBS_2__ADDR                   0x1F04041C
#define SRM_CSI1_CPD_GBS_2__EMPTY       0x1F04041C,0x00000000
#define SRM_CSI1_CPD_GBS_2__FULL       0x1F04041C,0xffffffff
#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS11       0x1F04041C,0xFF000000
#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS10       0x1F04041C,0x00FF0000
#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS9       0x1F04041C,0x0000FF00
#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS8       0x1F04041C,0x000000FF

#define SRM_CSI1_CPD_GBS_3__ADDR                   0x1F040420
#define SRM_CSI1_CPD_GBS_3__EMPTY       0x1F040420,0x00000000
#define SRM_CSI1_CPD_GBS_3__FULL       0x1F040420,0xffffffff
#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS15       0x1F040420,0xFF000000
#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS14       0x1F040420,0x00FF0000
#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS13       0x1F040420,0x0000FF00
#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS12       0x1F040420,0x000000FF

#define SRM_CSI1_CPD_BC_0__ADDR                   0x1F040424
#define SRM_CSI1_CPD_BC_0__EMPTY       0x1F040424,0x00000000
#define SRM_CSI1_CPD_BC_0__FULL       0x1F040424,0xffffffff
#define SRM_CSI1_CPD_BC_0__CSI1_CPD_BC1       0x1F040424,0x01FF0000
#define SRM_CSI1_CPD_BC_0__CSI1_CPD_BC0       0x1F040424,0x000001FF

#define SRM_CSI1_CPD_BC_1__ADDR                   0x1F040428
#define SRM_CSI1_CPD_BC_1__EMPTY       0x1F040428,0x00000000
#define SRM_CSI1_CPD_BC_1__FULL       0x1F040428,0xffffffff
#define SRM_CSI1_CPD_BC_1__CSI1_CPD_BC3       0x1F040428,0x01FF0000
#define SRM_CSI1_CPD_BC_1__CSI1_CPD_BC2       0x1F040428,0x000001FF

#define SRM_CSI1_CPD_BC_2__ADDR                   0x1F04042C
#define SRM_CSI1_CPD_BC_2__EMPTY       0x1F04042C,0x00000000
#define SRM_CSI1_CPD_BC_2__FULL       0x1F04042C,0xffffffff
#define SRM_CSI1_CPD_BC_2__CSI1_CPD_BC5       0x1F04042C,0x01FF0000
#define SRM_CSI1_CPD_BC_2__CSI1_CPD_BC4       0x1F04042C,0x000001FF

#define SRM_CSI1_CPD_BC_3__ADDR                   0x1F040430
#define SRM_CSI1_CPD_BC_3__EMPTY       0x1F040430,0x00000000
#define SRM_CSI1_CPD_BC_3__FULL       0x1F040430,0xffffffff
#define SRM_CSI1_CPD_BC_3__CSI1_CPD_BC7       0x1F040430,0x01FF0000
#define SRM_CSI1_CPD_BC_3__CSI1_CPD_BC6       0x1F040430,0x000001FF

#define SRM_CSI1_CPD_BC_4__ADDR                   0x1F040434
#define SRM_CSI1_CPD_BC_4__EMPTY       0x1F040434,0x00000000
#define SRM_CSI1_CPD_BC_4__FULL       0x1F040434,0xffffffff
#define SRM_CSI1_CPD_BC_4__CSI1_CPD_BC9       0x1F040434,0x01FF0000
#define SRM_CSI1_CPD_BC_4__CSI1_CPD_BC8       0x1F040434,0x000001FF

#define SRM_CSI1_CPD_BC_5__ADDR                   0x1F040438
#define SRM_CSI1_CPD_BC_5__EMPTY       0x1F040438,0x00000000
#define SRM_CSI1_CPD_BC_5__FULL       0x1F040438,0xffffffff
#define SRM_CSI1_CPD_BC_5__CSI1_CPD_BC11       0x1F040438,0x01FF0000
#define SRM_CSI1_CPD_BC_5__CSI1_CPD_BC10       0x1F040438,0x000001FF

#define SRM_CSI1_CPD_BC_6__ADDR                   0x1F04043C
#define SRM_CSI1_CPD_BC_6__EMPTY       0x1F04043C,0x00000000
#define SRM_CSI1_CPD_BC_6__FULL       0x1F04043C,0xffffffff
#define SRM_CSI1_CPD_BC_6__CSI1_CPD_BC13       0x1F04043C,0x01FF0000
#define SRM_CSI1_CPD_BC_6__CSI1_CPD_BC12       0x1F04043C,0x000001FF

#define SRM_CSI1_CPD_BC_7__ADDR                   0x1F040440
#define SRM_CSI1_CPD_BC_7__EMPTY       0x1F040440,0x00000000
#define SRM_CSI1_CPD_BC_7__FULL       0x1F040440,0xffffffff
#define SRM_CSI1_CPD_BC_7__CSI1_CPD_BC15       0x1F040440,0x01FF0000
#define SRM_CSI1_CPD_BC_7__CSI1_CPD_BC14       0x1F040440,0x000001FF

#define SRM_CSI1_CPD_BS_0__ADDR                   0x1F040444
#define SRM_CSI1_CPD_BS_0__EMPTY       0x1F040444,0x00000000
#define SRM_CSI1_CPD_BS_0__FULL       0x1F040444,0xffffffff
#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS3       0x1F040444,0xFF000000
#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS2       0x1F040444,0x00FF0000
#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS1       0x1F040444,0x0000FF00
#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS0       0x1F040444,0x000000FF

#define SRM_CSI1_CPD_BS_1__ADDR                   0x1F040448
#define SRM_CSI1_CPD_BS_1__EMPTY       0x1F040448,0x00000000
#define SRM_CSI1_CPD_BS_1__FULL       0x1F040448,0xffffffff
#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS7       0x1F040448,0xFF000000
#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS6       0x1F040448,0x00FF0000
#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS5       0x1F040448,0x0000FF00
#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS4       0x1F040448,0x000000FF

#define SRM_CSI1_CPD_BS_2__ADDR                   0x1F04044C
#define SRM_CSI1_CPD_BS_2__EMPTY       0x1F04044C,0x00000000
#define SRM_CSI1_CPD_BS_2__FULL       0x1F04044C,0xffffffff
#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS11       0x1F04044C,0xFF000000
#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS10       0x1F04044C,0x00FF0000
#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS9       0x1F04044C,0x0000FF00
#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS8       0x1F04044C,0x000000FF

#define SRM_CSI1_CPD_BS_3__ADDR                   0x1F040450
#define SRM_CSI1_CPD_BS_3__EMPTY       0x1F040450,0x00000000
#define SRM_CSI1_CPD_BS_3__FULL       0x1F040450,0xffffffff
#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS15       0x1F040450,0xFF000000
#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS14       0x1F040450,0x00FF0000
#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS13       0x1F040450,0x0000FF00
#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS12       0x1F040450,0x000000FF

#define SRM_CSI1_CPD_OFFSET1__ADDR                   0x1F040454
#define SRM_CSI1_CPD_OFFSET1__EMPTY       0x1F040454,0x00000000
#define SRM_CSI1_CPD_OFFSET1__FULL       0x1F040454,0xffffffff
#define SRM_CSI1_CPD_OFFSET1__CSI1_CPD_B_OFFSET       0x1F040454,0x3FF00000
#define SRM_CSI1_CPD_OFFSET1__CSI1_CPD_GB_OFFSET       0x1F040454,0x000FFC00
#define SRM_CSI1_CPD_OFFSET1__CSI1_CPD_GR_OFFSET       0x1F040454,0x000003FF

#define SRM_CSI1_CPD_OFFSET2__ADDR                   0x1F040458
#define SRM_CSI1_CPD_OFFSET2__EMPTY       0x1F040458,0x00000000
#define SRM_CSI1_CPD_OFFSET2__FULL       0x1F040458,0xffffffff
#define SRM_CSI1_CPD_OFFSET2__CSI1_CPD_R_OFFSET       0x1F040458,0x000003FF

#define SRM_DI0_GENERAL__ADDR                   0x1F040494
#define SRM_DI0_GENERAL__EMPTY       0x1F040494,0x00000000
#define SRM_DI0_GENERAL__FULL       0x1F040494,0xffffffff
#define SRM_DI0_GENERAL__DI0_DISP_Y_SEL       0x1F040494,0x70000000
#define SRM_DI0_GENERAL__DI0_CLOCK_STOP_MODE       0x1F040494,0x0F000000
#define SRM_DI0_GENERAL__DI0_DISP_CLOCK_INIT   0x1F040494,0x00800000
#define SRM_DI0_GENERAL__DI0_MASK_SEL       0x1F040494,0x00400000
#define SRM_DI0_GENERAL__DI0_VSYNC_EXT       0x1F040494,0x00200000
#define SRM_DI0_GENERAL__DI0_CLK_EXT       0x1F040494,0x00100000
#define SRM_DI0_GENERAL__DI0_WATCHDOG_MODE     0x1F040494,0x000C0000
#define SRM_DI0_GENERAL__DI0_POLARITY_DISP_CLK       0x1F040494,0x00020000
#define SRM_DI0_GENERAL__DI0_SYNC_COUNT_SEL       0x1F040494,0x0000F000
#define SRM_DI0_GENERAL__DI0_ERR_TREATMENT       0x1F040494,0x00000800
#define SRM_DI0_GENERAL__DI0_ERM_VSYNC_SEL     0x1F040494,0x00000400
#define SRM_DI0_GENERAL__DI0_POLARITY_CS1       0x1F040494,0x00000200
#define SRM_DI0_GENERAL__DI0_POLARITY_CS0       0x1F040494,0x00000100
#define SRM_DI0_GENERAL__DI0_POLARITY_8       0x1F040494,0x00000080
#define SRM_DI0_GENERAL__DI0_POLARITY_7       0x1F040494,0x00000040
#define SRM_DI0_GENERAL__DI0_POLARITY_6       0x1F040494,0x00000020
#define SRM_DI0_GENERAL__DI0_POLARITY_5       0x1F040494,0x00000010
#define SRM_DI0_GENERAL__DI0_POLARITY_4       0x1F040494,0x00000008
#define SRM_DI0_GENERAL__DI0_POLARITY_3       0x1F040494,0x00000004
#define SRM_DI0_GENERAL__DI0_POLARITY_2       0x1F040494,0x00000002
#define SRM_DI0_GENERAL__DI0_POLARITY_1       0x1F040494,0x00000001

#define SRM_DI0_BS_CLKGEN0__ADDR                   0x1F040498
#define SRM_DI0_BS_CLKGEN0__EMPTY       0x1F040498,0x00000000
#define SRM_DI0_BS_CLKGEN0__FULL       0x1F040498,0xffffffff
#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET       0x1F040498,0x01FF0000
#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD       0x1F040498,0x00000FFF

#define SRM_DI0_BS_CLKGEN1__ADDR                   0x1F04049C
#define SRM_DI0_BS_CLKGEN1__EMPTY       0x1F04049C,0x00000000
#define SRM_DI0_BS_CLKGEN1__FULL       0x1F04049C,0xffffffff
#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN       0x1F04049C,0x01FF0000
#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP       0x1F04049C,0x000001FF

#define SRM_DI0_SW_GEN0_1__ADDR                   0x1F0404A0
#define SRM_DI0_SW_GEN0_1__EMPTY       0x1F0404A0,0x00000000
#define SRM_DI0_SW_GEN0_1__FULL       0x1F0404A0,0xffffffff
#define SRM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1       0x1F0404A0,0x7FF80000
#define SRM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1       0x1F0404A0,0x00070000
#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1       0x1F0404A0,0x00007FF8
#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1       0x1F0404A0,0x00000007

#define SRM_DI0_SW_GEN0_2__ADDR                   0x1F0404A4
#define SRM_DI0_SW_GEN0_2__EMPTY       0x1F0404A4,0x00000000
#define SRM_DI0_SW_GEN0_2__FULL       0x1F0404A4,0xffffffff
#define SRM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2       0x1F0404A4,0x7FF80000
#define SRM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2       0x1F0404A4,0x00070000
#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2       0x1F0404A4,0x00007FF8
#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2       0x1F0404A4,0x00000007

#define SRM_DI0_SW_GEN0_3__ADDR                   0x1F0404A8
#define SRM_DI0_SW_GEN0_3__EMPTY       0x1F0404A8,0x00000000
#define SRM_DI0_SW_GEN0_3__FULL       0x1F0404A8,0xffffffff
#define SRM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3       0x1F0404A8,0x7FF80000
#define SRM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3       0x1F0404A8,0x00070000
#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3       0x1F0404A8,0x00007FF8
#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3       0x1F0404A8,0x00000007

#define SRM_DI0_SW_GEN0_4__ADDR                   0x1F0404AC
#define SRM_DI0_SW_GEN0_4__EMPTY       0x1F0404AC,0x00000000
#define SRM_DI0_SW_GEN0_4__FULL       0x1F0404AC,0xffffffff
#define SRM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4       0x1F0404AC,0x7FF80000
#define SRM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4       0x1F0404AC,0x00070000
#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4       0x1F0404AC,0x00007FF8
#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4       0x1F0404AC,0x00000007

#define SRM_DI0_SW_GEN0_5__ADDR                   0x1F0404B0
#define SRM_DI0_SW_GEN0_5__EMPTY       0x1F0404B0,0x00000000
#define SRM_DI0_SW_GEN0_5__FULL       0x1F0404B0,0xffffffff
#define SRM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5       0x1F0404B0,0x7FF80000
#define SRM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5       0x1F0404B0,0x00070000
#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5       0x1F0404B0,0x00007FF8
#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5       0x1F0404B0,0x00000007

#define SRM_DI0_SW_GEN0_6__ADDR                   0x1F0404B4
#define SRM_DI0_SW_GEN0_6__EMPTY       0x1F0404B4,0x00000000
#define SRM_DI0_SW_GEN0_6__FULL       0x1F0404B4,0xffffffff
#define SRM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6       0x1F0404B4,0x7FF80000
#define SRM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6       0x1F0404B4,0x00070000
#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6       0x1F0404B4,0x00007FF8
#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6       0x1F0404B4,0x00000007

#define SRM_DI0_SW_GEN0_7__ADDR                   0x1F0404B8
#define SRM_DI0_SW_GEN0_7__EMPTY       0x1F0404B8,0x00000000
#define SRM_DI0_SW_GEN0_7__FULL       0x1F0404B8,0xffffffff
#define SRM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7       0x1F0404B8,0x7FF80000
#define SRM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7       0x1F0404B8,0x00070000
#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7       0x1F0404B8,0x00007FF8
#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7       0x1F0404B8,0x00000007

#define SRM_DI0_SW_GEN0_8__ADDR                   0x1F0404BC
#define SRM_DI0_SW_GEN0_8__EMPTY       0x1F0404BC,0x00000000
#define SRM_DI0_SW_GEN0_8__FULL       0x1F0404BC,0xffffffff
#define SRM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8       0x1F0404BC,0x7FF80000
#define SRM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8       0x1F0404BC,0x00070000
#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8       0x1F0404BC,0x00007FF8
#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8       0x1F0404BC,0x00000007

#define SRM_DI0_SW_GEN0_9__ADDR                   0x1F0404C0
#define SRM_DI0_SW_GEN0_9__EMPTY       0x1F0404C0,0x00000000
#define SRM_DI0_SW_GEN0_9__FULL       0x1F0404C0,0xffffffff
#define SRM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9       0x1F0404C0,0x7FF80000
#define SRM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9       0x1F0404C0,0x00070000
#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9       0x1F0404C0,0x00007FF8
#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9       0x1F0404C0,0x00000007

#define SRM_DI0_SW_GEN1_1__ADDR                   0x1F0404C4
#define SRM_DI0_SW_GEN1_1__EMPTY       0x1F0404C4,0x00000000
#define SRM_DI0_SW_GEN1_1__FULL       0x1F0404C4,0xffffffff
#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1       0x1F0404C4,0x60000000
#define SRM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1       0x1F0404C4,0x10000000
#define SRM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1       0x1F0404C4,0x0E000000
#define SRM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1       0x1F0404C4,0x01FF0000
#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1       0x1F0404C4,0x00007000
#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1       0x1F0404C4,0x00000E00
#define SRM_DI0_SW_GEN1_1__DI0_CNT_UP_1       0x1F0404C4,0x000001FF

#define SRM_DI0_SW_GEN1_2__ADDR                   0x1F0404C8
#define SRM_DI0_SW_GEN1_2__EMPTY       0x1F0404C8,0x00000000
#define SRM_DI0_SW_GEN1_2__FULL       0x1F0404C8,0xffffffff
#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2       0x1F0404C8,0x60000000
#define SRM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2       0x1F0404C8,0x10000000
#define SRM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2       0x1F0404C8,0x0E000000
#define SRM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2       0x1F0404C8,0x01FF0000
#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2       0x1F0404C8,0x00007000
#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2       0x1F0404C8,0x00000E00
#define SRM_DI0_SW_GEN1_2__DI0_CNT_UP_2       0x1F0404C8,0x000001FF

#define SRM_DI0_SW_GEN1_3__ADDR                   0x1F0404CC
#define SRM_DI0_SW_GEN1_3__EMPTY       0x1F0404CC,0x00000000
#define SRM_DI0_SW_GEN1_3__FULL       0x1F0404CC,0xffffffff
#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3       0x1F0404CC,0x60000000
#define SRM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3       0x1F0404CC,0x10000000
#define SRM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3       0x1F0404CC,0x0E000000
#define SRM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3       0x1F0404CC,0x01FF0000
#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3       0x1F0404CC,0x00007000
#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3       0x1F0404CC,0x00000E00
#define SRM_DI0_SW_GEN1_3__DI0_CNT_UP_3       0x1F0404CC,0x000001FF

#define SRM_DI0_SW_GEN1_4__ADDR                   0x1F0404D0
#define SRM_DI0_SW_GEN1_4__EMPTY       0x1F0404D0,0x00000000
#define SRM_DI0_SW_GEN1_4__FULL       0x1F0404D0,0xffffffff
#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4       0x1F0404D0,0x60000000
#define SRM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4       0x1F0404D0,0x10000000
#define SRM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4       0x1F0404D0,0x0E000000
#define SRM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4       0x1F0404D0,0x01FF0000
#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4       0x1F0404D0,0x00007000
#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4       0x1F0404D0,0x00000E00
#define SRM_DI0_SW_GEN1_4__DI0_CNT_UP_4       0x1F0404D0,0x000001FF

#define SRM_DI0_SW_GEN1_5__ADDR                   0x1F0404D4
#define SRM_DI0_SW_GEN1_5__EMPTY       0x1F0404D4,0x00000000
#define SRM_DI0_SW_GEN1_5__FULL       0x1F0404D4,0xffffffff
#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5       0x1F0404D4,0x60000000
#define SRM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5       0x1F0404D4,0x10000000
#define SRM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5       0x1F0404D4,0x0E000000
#define SRM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5       0x1F0404D4,0x01FF0000
#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5       0x1F0404D4,0x00007000
#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5       0x1F0404D4,0x00000E00
#define SRM_DI0_SW_GEN1_5__DI0_CNT_UP_5       0x1F0404D4,0x000001FF

#define SRM_DI0_SW_GEN1_6__ADDR                   0x1F0404D8
#define SRM_DI0_SW_GEN1_6__EMPTY       0x1F0404D8,0x00000000
#define SRM_DI0_SW_GEN1_6__FULL       0x1F0404D8,0xffffffff
#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6       0x1F0404D8,0x60000000
#define SRM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6       0x1F0404D8,0x10000000
#define SRM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6       0x1F0404D8,0x0E000000
#define SRM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6       0x1F0404D8,0x01FF0000
#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6       0x1F0404D8,0x00007000
#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6       0x1F0404D8,0x00000E00
#define SRM_DI0_SW_GEN1_6__DI0_CNT_UP_6       0x1F0404D8,0x000001FF

#define SRM_DI0_SW_GEN1_7__ADDR                   0x1F0404DC
#define SRM_DI0_SW_GEN1_7__EMPTY       0x1F0404DC,0x00000000
#define SRM_DI0_SW_GEN1_7__FULL       0x1F0404DC,0xffffffff
#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7       0x1F0404DC,0x60000000
#define SRM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7       0x1F0404DC,0x10000000
#define SRM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7       0x1F0404DC,0x0E000000
#define SRM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7       0x1F0404DC,0x01FF0000
#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7       0x1F0404DC,0x00007000
#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7       0x1F0404DC,0x00000E00
#define SRM_DI0_SW_GEN1_7__DI0_CNT_UP_7       0x1F0404DC,0x000001FF

#define SRM_DI0_SW_GEN1_8__ADDR                   0x1F0404E0
#define SRM_DI0_SW_GEN1_8__EMPTY       0x1F0404E0,0x00000000
#define SRM_DI0_SW_GEN1_8__FULL       0x1F0404E0,0xffffffff
#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8       0x1F0404E0,0x60000000
#define SRM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8       0x1F0404E0,0x10000000
#define SRM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8       0x1F0404E0,0x0E000000
#define SRM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8       0x1F0404E0,0x01FF0000
#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8       0x1F0404E0,0x00007000
#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8       0x1F0404E0,0x00000E00
#define SRM_DI0_SW_GEN1_8__DI0_CNT_UP_8       0x1F0404E0,0x000001FF

#define SRM_DI0_SW_GEN1_9__ADDR                   0x1F0404E4
#define SRM_DI0_SW_GEN1_9__EMPTY       0x1F0404E4,0x00000000
#define SRM_DI0_SW_GEN1_9__FULL       0x1F0404E4,0xffffffff
#define SRM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9       0x1F0404E4,0xE0000000
#define SRM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9       0x1F0404E4,0x10000000
#define SRM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9       0x1F0404E4,0x0E000000
#define SRM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9       0x1F0404E4,0x01FF0000
#define SRM_DI0_SW_GEN1_9__DI0_TAG_SEL_9       0x1F0404E4,0x00008000
#define SRM_DI0_SW_GEN1_9__DI0_CNT_UP_9       0x1F0404E4,0x000001FF

#define SRM_DI0_SYNC_AS_GEN__ADDR                   0x1F0404E8
#define SRM_DI0_SYNC_AS_GEN__EMPTY       0x1F0404E8,0x00000000
#define SRM_DI0_SYNC_AS_GEN__FULL       0x1F0404E8,0xffffffff
#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN       0x1F0404E8,0x10000000
#define SRM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL       0x1F0404E8,0x0000E000
#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START       0x1F0404E8,0x00000FFF

#define SRM_DI0_DW_GEN_0__ADDR                  0x1F0404EC
#define SRM_DI0_DW_GEN_0__EMPTY                 0x1F0404EC,0x00000000
#define SRM_DI0_DW_GEN_0__FULL                  0x1F0404EC,0xffffffff
#define SRM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0     0x1F0404EC,0xFF000000
#define SRM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1F0404EC,0x00FF0000
#define SRM_DI0_DW_GEN_0__DI0_CST_0             0x1F0404EC,0x0000C000
#define SRM_DI0_DW_GEN_0__DI0_PT_6_0            0x1F0404EC,0x00003000
#define SRM_DI0_DW_GEN_0__DI0_PT_5_0            0x1F0404EC,0x00000C00
#define SRM_DI0_DW_GEN_0__DI0_PT_4_0            0x1F0404EC,0x00000300
#define SRM_DI0_DW_GEN_0__DI0_PT_3_0            0x1F0404EC,0x000000C0
#define SRM_DI0_DW_GEN_0__DI0_PT_2_0            0x1F0404EC,0x00000030
#define SRM_DI0_DW_GEN_0__DI0_PT_1_0            0x1F0404EC,0x0000000C
#define SRM_DI0_DW_GEN_0__DI0_PT_0_0            0x1F0404EC,0x00000003

#define SRM_DI0_DW_GEN_0__ADDR                    0x1F0404EC
#define SRM_DI0_DW_GEN_0__EMPTY                   0x1F0404EC,0x00000000
#define SRM_DI0_DW_GEN_0__FULL                    0x1F0404EC,0xffffffff
#define SRM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0     0x1F0404EC,0xFF000000
#define SRM_DI0_DW_GEN_0__DI0_START_PERIOD_0      0x1F0404EC,0x00FF0000
#define SRM_DI0_DW_GEN_0__DI0_CST_0               0x1F0404EC,0x0000C000
#define SRM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1F0404EC,0x000001F0
#define SRM_DI0_DW_GEN_0__DI0_SERIAL_RS_0         0x1F0404EC,0x0000000C
#define SRM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0        0x1F0404EC,0x00000003

#define SRM_DI0_DW_GEN_1__ADDR                  0x1F0404F0
#define SRM_DI0_DW_GEN_1__EMPTY                 0x1F0404F0,0x00000000
#define SRM_DI0_DW_GEN_1__FULL                  0x1F0404F0,0xffffffff
#define SRM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1     0x1F0404F0,0xFF000000
#define SRM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1F0404F0,0x00FF0000
#define SRM_DI0_DW_GEN_1__DI0_CST_1             0x1F0404F0,0x0000C000
#define SRM_DI0_DW_GEN_1__DI0_PT_6_1            0x1F0404F0,0x00003000
#define SRM_DI0_DW_GEN_1__DI0_PT_5_1            0x1F0404F0,0x00000C00
#define SRM_DI0_DW_GEN_1__DI0_PT_4_1            0x1F0404F0,0x00000300
#define SRM_DI0_DW_GEN_1__DI0_PT_3_1            0x1F0404F0,0x000000C0
#define SRM_DI0_DW_GEN_1__DI0_PT_2_1            0x1F0404F0,0x00000030
#define SRM_DI0_DW_GEN_1__DI0_PT_1_1            0x1F0404F0,0x0000000C
#define SRM_DI0_DW_GEN_1__DI0_PT_0_1            0x1F0404F0,0x00000003

#define SRM_DI0_DW_GEN_1__ADDR                    0x1F0404F0
#define SRM_DI0_DW_GEN_1__EMPTY                   0x1F0404F0,0x00000000
#define SRM_DI0_DW_GEN_1__FULL                    0x1F0404F0,0xffffffff
#define SRM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1     0x1F0404F0,0xFF000000
#define SRM_DI0_DW_GEN_1__DI0_START_PERIOD_1      0x1F0404F0,0x00FF0000
#define SRM_DI0_DW_GEN_1__DI0_CST_1               0x1F0404F0,0x0000C000
#define SRM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1F0404F0,0x000001F0
#define SRM_DI0_DW_GEN_1__DI0_SERIAL_RS_1         0x1F0404F0,0x0000000C
#define SRM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1        0x1F0404F0,0x00000003

#define SRM_DI0_DW_GEN_2__ADDR                  0x1F0404F4
#define SRM_DI0_DW_GEN_2__EMPTY                 0x1F0404F4,0x00000000
#define SRM_DI0_DW_GEN_2__FULL                  0x1F0404F4,0xffffffff
#define SRM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2     0x1F0404F4,0xFF000000
#define SRM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1F0404F4,0x00FF0000
#define SRM_DI0_DW_GEN_2__DI0_CST_2             0x1F0404F4,0x0000C000
#define SRM_DI0_DW_GEN_2__DI0_PT_6_2            0x1F0404F4,0x00003000
#define SRM_DI0_DW_GEN_2__DI0_PT_5_2            0x1F0404F4,0x00000C00
#define SRM_DI0_DW_GEN_2__DI0_PT_4_2            0x1F0404F4,0x00000300
#define SRM_DI0_DW_GEN_2__DI0_PT_3_2            0x1F0404F4,0x000000C0
#define SRM_DI0_DW_GEN_2__DI0_PT_2_2            0x1F0404F4,0x00000030
#define SRM_DI0_DW_GEN_2__DI0_PT_1_2            0x1F0404F4,0x0000000C
#define SRM_DI0_DW_GEN_2__DI0_PT_0_2            0x1F0404F4,0x00000003

#define SRM_DI0_DW_GEN_2__ADDR                    0x1F0404F4
#define SRM_DI0_DW_GEN_2__EMPTY                   0x1F0404F4,0x00000000
#define SRM_DI0_DW_GEN_2__FULL                    0x1F0404F4,0xffffffff
#define SRM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2     0x1F0404F4,0xFF000000
#define SRM_DI0_DW_GEN_2__DI0_START_PERIOD_2      0x1F0404F4,0x00FF0000
#define SRM_DI0_DW_GEN_2__DI0_CST_2               0x1F0404F4,0x0000C000
#define SRM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1F0404F4,0x000001F0
#define SRM_DI0_DW_GEN_2__DI0_SERIAL_RS_2         0x1F0404F4,0x0000000C
#define SRM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2        0x1F0404F4,0x00000003

#define SRM_DI0_DW_GEN_3__ADDR                  0x1F0404F8
#define SRM_DI0_DW_GEN_3__EMPTY                 0x1F0404F8,0x00000000
#define SRM_DI0_DW_GEN_3__FULL                  0x1F0404F8,0xffffffff
#define SRM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3     0x1F0404F8,0xFF000000
#define SRM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1F0404F8,0x00FF0000
#define SRM_DI0_DW_GEN_3__DI0_CST_3             0x1F0404F8,0x0000C000
#define SRM_DI0_DW_GEN_3__DI0_PT_6_3            0x1F0404F8,0x00003000
#define SRM_DI0_DW_GEN_3__DI0_PT_5_3            0x1F0404F8,0x00000C00
#define SRM_DI0_DW_GEN_3__DI0_PT_4_3            0x1F0404F8,0x00000300
#define SRM_DI0_DW_GEN_3__DI0_PT_3_3            0x1F0404F8,0x000000C0
#define SRM_DI0_DW_GEN_3__DI0_PT_2_3            0x1F0404F8,0x00000030
#define SRM_DI0_DW_GEN_3__DI0_PT_1_3            0x1F0404F8,0x0000000C
#define SRM_DI0_DW_GEN_3__DI0_PT_0_3            0x1F0404F8,0x00000003

#define SRM_DI0_DW_GEN_3__ADDR                    0x1F0404F8
#define SRM_DI0_DW_GEN_3__EMPTY                   0x1F0404F8,0x00000000
#define SRM_DI0_DW_GEN_3__FULL                    0x1F0404F8,0xffffffff
#define SRM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3     0x1F0404F8,0xFF000000
#define SRM_DI0_DW_GEN_3__DI0_START_PERIOD_3      0x1F0404F8,0x00FF0000
#define SRM_DI0_DW_GEN_3__DI0_CST_3               0x1F0404F8,0x0000C000
#define SRM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1F0404F8,0x000001F0
#define SRM_DI0_DW_GEN_3__DI0_SERIAL_RS_3         0x1F0404F8,0x0000000C
#define SRM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3        0x1F0404F8,0x00000003

#define SRM_DI0_DW_GEN_4__ADDR                  0x1F0404FC
#define SRM_DI0_DW_GEN_4__EMPTY                 0x1F0404FC,0x00000000
#define SRM_DI0_DW_GEN_4__FULL                  0x1F0404FC,0xffffffff
#define SRM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4     0x1F0404FC,0xFF000000
#define SRM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1F0404FC,0x00FF0000
#define SRM_DI0_DW_GEN_4__DI0_CST_4             0x1F0404FC,0x0000C000
#define SRM_DI0_DW_GEN_4__DI0_PT_6_4            0x1F0404FC,0x00003000
#define SRM_DI0_DW_GEN_4__DI0_PT_5_4            0x1F0404FC,0x00000C00
#define SRM_DI0_DW_GEN_4__DI0_PT_4_4            0x1F0404FC,0x00000300
#define SRM_DI0_DW_GEN_4__DI0_PT_3_4            0x1F0404FC,0x000000C0
#define SRM_DI0_DW_GEN_4__DI0_PT_2_4            0x1F0404FC,0x00000030
#define SRM_DI0_DW_GEN_4__DI0_PT_1_4            0x1F0404FC,0x0000000C
#define SRM_DI0_DW_GEN_4__DI0_PT_0_4            0x1F0404FC,0x00000003

#define SRM_DI0_DW_GEN_4__ADDR                    0x1F0404FC
#define SRM_DI0_DW_GEN_4__EMPTY                   0x1F0404FC,0x00000000
#define SRM_DI0_DW_GEN_4__FULL                    0x1F0404FC,0xffffffff
#define SRM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4     0x1F0404FC,0xFF000000
#define SRM_DI0_DW_GEN_4__DI0_START_PERIOD_4      0x1F0404FC,0x00FF0000
#define SRM_DI0_DW_GEN_4__DI0_CST_4               0x1F0404FC,0x0000C000
#define SRM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1F0404FC,0x000001F0
#define SRM_DI0_DW_GEN_4__DI0_SERIAL_RS_4         0x1F0404FC,0x0000000C
#define SRM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4        0x1F0404FC,0x00000003

#define SRM_DI0_DW_GEN_5__ADDR                  0x1F040500
#define SRM_DI0_DW_GEN_5__EMPTY                 0x1F040500,0x00000000
#define SRM_DI0_DW_GEN_5__FULL                  0x1F040500,0xffffffff
#define SRM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5     0x1F040500,0xFF000000
#define SRM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1F040500,0x00FF0000
#define SRM_DI0_DW_GEN_5__DI0_CST_5             0x1F040500,0x0000C000
#define SRM_DI0_DW_GEN_5__DI0_PT_6_5            0x1F040500,0x00003000
#define SRM_DI0_DW_GEN_5__DI0_PT_5_5            0x1F040500,0x00000C00
#define SRM_DI0_DW_GEN_5__DI0_PT_4_5            0x1F040500,0x00000300
#define SRM_DI0_DW_GEN_5__DI0_PT_3_5            0x1F040500,0x000000C0
#define SRM_DI0_DW_GEN_5__DI0_PT_2_5            0x1F040500,0x00000030
#define SRM_DI0_DW_GEN_5__DI0_PT_1_5            0x1F040500,0x0000000C
#define SRM_DI0_DW_GEN_5__DI0_PT_0_5            0x1F040500,0x00000003

#define SRM_DI0_DW_GEN_5__ADDR                    0x1F040500
#define SRM_DI0_DW_GEN_5__EMPTY                   0x1F040500,0x00000000
#define SRM_DI0_DW_GEN_5__FULL                    0x1F040500,0xffffffff
#define SRM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5     0x1F040500,0xFF000000
#define SRM_DI0_DW_GEN_5__DI0_START_PERIOD_5      0x1F040500,0x00FF0000
#define SRM_DI0_DW_GEN_5__DI0_CST_5               0x1F040500,0x0000C000
#define SRM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1F040500,0x000001F0
#define SRM_DI0_DW_GEN_5__DI0_SERIAL_RS_5         0x1F040500,0x0000000C
#define SRM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5        0x1F040500,0x00000003

#define SRM_DI0_DW_GEN_6__ADDR                  0x1F040504
#define SRM_DI0_DW_GEN_6__EMPTY                 0x1F040504,0x00000000
#define SRM_DI0_DW_GEN_6__FULL                  0x1F040504,0xffffffff
#define SRM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6     0x1F040504,0xFF000000
#define SRM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1F040504,0x00FF0000
#define SRM_DI0_DW_GEN_6__DI0_CST_6             0x1F040504,0x0000C000
#define SRM_DI0_DW_GEN_6__DI0_PT_6_6            0x1F040504,0x00003000
#define SRM_DI0_DW_GEN_6__DI0_PT_5_6            0x1F040504,0x00000C00
#define SRM_DI0_DW_GEN_6__DI0_PT_4_6            0x1F040504,0x00000300
#define SRM_DI0_DW_GEN_6__DI0_PT_3_6            0x1F040504,0x000000C0
#define SRM_DI0_DW_GEN_6__DI0_PT_2_6            0x1F040504,0x00000030
#define SRM_DI0_DW_GEN_6__DI0_PT_1_6            0x1F040504,0x0000000C
#define SRM_DI0_DW_GEN_6__DI0_PT_0_6            0x1F040504,0x00000003

#define SRM_DI0_DW_GEN_6__ADDR                    0x1F040504
#define SRM_DI0_DW_GEN_6__EMPTY                   0x1F040504,0x00000000
#define SRM_DI0_DW_GEN_6__FULL                    0x1F040504,0xffffffff
#define SRM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6     0x1F040504,0xFF000000
#define SRM_DI0_DW_GEN_6__DI0_START_PERIOD_6      0x1F040504,0x00FF0000
#define SRM_DI0_DW_GEN_6__DI0_CST_6               0x1F040504,0x0000C000
#define SRM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1F040504,0x000001F0
#define SRM_DI0_DW_GEN_6__DI0_SERIAL_RS_6         0x1F040504,0x0000000C
#define SRM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6        0x1F040504,0x00000003

#define SRM_DI0_DW_GEN_7__ADDR                  0x1F040508
#define SRM_DI0_DW_GEN_7__EMPTY                 0x1F040508,0x00000000
#define SRM_DI0_DW_GEN_7__FULL                  0x1F040508,0xffffffff
#define SRM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7     0x1F040508,0xFF000000
#define SRM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1F040508,0x00FF0000
#define SRM_DI0_DW_GEN_7__DI0_CST_7             0x1F040508,0x0000C000
#define SRM_DI0_DW_GEN_7__DI0_PT_6_7            0x1F040508,0x00003000
#define SRM_DI0_DW_GEN_7__DI0_PT_5_7            0x1F040508,0x00000C00
#define SRM_DI0_DW_GEN_7__DI0_PT_4_7            0x1F040508,0x00000300
#define SRM_DI0_DW_GEN_7__DI0_PT_3_7            0x1F040508,0x000000C0
#define SRM_DI0_DW_GEN_7__DI0_PT_2_7            0x1F040508,0x00000030
#define SRM_DI0_DW_GEN_7__DI0_PT_1_7            0x1F040508,0x0000000C
#define SRM_DI0_DW_GEN_7__DI0_PT_0_7            0x1F040508,0x00000003

#define SRM_DI0_DW_GEN_7__ADDR                    0x1F040508
#define SRM_DI0_DW_GEN_7__EMPTY                   0x1F040508,0x00000000
#define SRM_DI0_DW_GEN_7__FULL                    0x1F040508,0xffffffff
#define SRM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7     0x1F040508,0xFF000000
#define SRM_DI0_DW_GEN_7__DI0_START_PERIOD_7      0x1F040508,0x00FF0000
#define SRM_DI0_DW_GEN_7__DI0_CST_7               0x1F040508,0x0000C000
#define SRM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1F040508,0x000001F0
#define SRM_DI0_DW_GEN_7__DI0_SERIAL_RS_7         0x1F040508,0x0000000C
#define SRM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7        0x1F040508,0x00000003

#define SRM_DI0_DW_GEN_8__ADDR                  0x1F04050C
#define SRM_DI0_DW_GEN_8__EMPTY                 0x1F04050C,0x00000000
#define SRM_DI0_DW_GEN_8__FULL                  0x1F04050C,0xffffffff
#define SRM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8     0x1F04050C,0xFF000000
#define SRM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1F04050C,0x00FF0000
#define SRM_DI0_DW_GEN_8__DI0_CST_8             0x1F04050C,0x0000C000
#define SRM_DI0_DW_GEN_8__DI0_PT_6_8            0x1F04050C,0x00003000
#define SRM_DI0_DW_GEN_8__DI0_PT_5_8            0x1F04050C,0x00000C00
#define SRM_DI0_DW_GEN_8__DI0_PT_4_8            0x1F04050C,0x00000300
#define SRM_DI0_DW_GEN_8__DI0_PT_3_8            0x1F04050C,0x000000C0
#define SRM_DI0_DW_GEN_8__DI0_PT_2_8            0x1F04050C,0x00000030
#define SRM_DI0_DW_GEN_8__DI0_PT_1_8            0x1F04050C,0x0000000C
#define SRM_DI0_DW_GEN_8__DI0_PT_0_8            0x1F04050C,0x00000003

#define SRM_DI0_DW_GEN_8__ADDR                    0x1F04050C
#define SRM_DI0_DW_GEN_8__EMPTY                   0x1F04050C,0x00000000
#define SRM_DI0_DW_GEN_8__FULL                    0x1F04050C,0xffffffff
#define SRM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8     0x1F04050C,0xFF000000
#define SRM_DI0_DW_GEN_8__DI0_START_PERIOD_8      0x1F04050C,0x00FF0000
#define SRM_DI0_DW_GEN_8__DI0_CST_8               0x1F04050C,0x0000C000
#define SRM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1F04050C,0x000001F0
#define SRM_DI0_DW_GEN_8__DI0_SERIAL_RS_8         0x1F04050C,0x0000000C
#define SRM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8        0x1F04050C,0x00000003

#define SRM_DI0_DW_GEN_9__ADDR                  0x1F040510
#define SRM_DI0_DW_GEN_9__EMPTY                 0x1F040510,0x00000000
#define SRM_DI0_DW_GEN_9__FULL                  0x1F040510,0xffffffff
#define SRM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9     0x1F040510,0xFF000000
#define SRM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1F040510,0x00FF0000
#define SRM_DI0_DW_GEN_9__DI0_CST_9             0x1F040510,0x0000C000
#define SRM_DI0_DW_GEN_9__DI0_PT_6_9            0x1F040510,0x00003000
#define SRM_DI0_DW_GEN_9__DI0_PT_5_9            0x1F040510,0x00000C00
#define SRM_DI0_DW_GEN_9__DI0_PT_4_9            0x1F040510,0x00000300
#define SRM_DI0_DW_GEN_9__DI0_PT_3_9            0x1F040510,0x000000C0
#define SRM_DI0_DW_GEN_9__DI0_PT_2_9            0x1F040510,0x00000030
#define SRM_DI0_DW_GEN_9__DI0_PT_1_9            0x1F040510,0x0000000C
#define SRM_DI0_DW_GEN_9__DI0_PT_0_9            0x1F040510,0x00000003

#define SRM_DI0_DW_GEN_9__ADDR                    0x1F040510
#define SRM_DI0_DW_GEN_9__EMPTY                   0x1F040510,0x00000000
#define SRM_DI0_DW_GEN_9__FULL                    0x1F040510,0xffffffff
#define SRM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9     0x1F040510,0xFF000000
#define SRM_DI0_DW_GEN_9__DI0_START_PERIOD_9      0x1F040510,0x00FF0000
#define SRM_DI0_DW_GEN_9__DI0_CST_9               0x1F040510,0x0000C000
#define SRM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1F040510,0x000001F0
#define SRM_DI0_DW_GEN_9__DI0_SERIAL_RS_9         0x1F040510,0x0000000C
#define SRM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9        0x1F040510,0x00000003

#define SRM_DI0_DW_GEN_10__ADDR                   0x1F040514
#define SRM_DI0_DW_GEN_10__EMPTY                  0x1F040514,0x00000000
#define SRM_DI0_DW_GEN_10__FULL                   0x1F040514,0xffffffff
#define SRM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10     0x1F040514,0xFF000000
#define SRM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1F040514,0x00FF0000
#define SRM_DI0_DW_GEN_10__DI0_CST_10             0x1F040514,0x0000C000
#define SRM_DI0_DW_GEN_10__DI0_PT_6_10            0x1F040514,0x00003000
#define SRM_DI0_DW_GEN_10__DI0_PT_5_10            0x1F040514,0x00000C00
#define SRM_DI0_DW_GEN_10__DI0_PT_4_10            0x1F040514,0x00000300
#define SRM_DI0_DW_GEN_10__DI0_PT_3_10            0x1F040514,0x000000C0
#define SRM_DI0_DW_GEN_10__DI0_PT_2_10            0x1F040514,0x00000030
#define SRM_DI0_DW_GEN_10__DI0_PT_1_10            0x1F040514,0x0000000C
#define SRM_DI0_DW_GEN_10__DI0_PT_0_10            0x1F040514,0x00000003

#define SRM_DI0_DW_GEN_10__ADDR                     0x1F040514
#define SRM_DI0_DW_GEN_10__EMPTY                    0x1F040514,0x00000000
#define SRM_DI0_DW_GEN_10__FULL                     0x1F040514,0xffffffff
#define SRM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10     0x1F040514,0xFF000000
#define SRM_DI0_DW_GEN_10__DI0_START_PERIOD_10      0x1F040514,0x00FF0000
#define SRM_DI0_DW_GEN_10__DI0_CST_10               0x1F040514,0x0000C000
#define SRM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F040514,0x000001F0
#define SRM_DI0_DW_GEN_10__DI0_SERIAL_RS_10         0x1F040514,0x0000000C
#define SRM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10        0x1F040514,0x00000003

#define SRM_DI0_DW_GEN_11__ADDR                   0x1F040518
#define SRM_DI0_DW_GEN_11__EMPTY                  0x1F040518,0x00000000
#define SRM_DI0_DW_GEN_11__FULL                   0x1F040518,0xffffffff
#define SRM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11     0x1F040518,0xFF000000
#define SRM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1F040518,0x00FF0000
#define SRM_DI0_DW_GEN_11__DI0_CST_11             0x1F040518,0x0000C000
#define SRM_DI0_DW_GEN_11__DI0_PT_6_11            0x1F040518,0x00003000
#define SRM_DI0_DW_GEN_11__DI0_PT_5_11            0x1F040518,0x00000C00
#define SRM_DI0_DW_GEN_11__DI0_PT_4_11            0x1F040518,0x00000300
#define SRM_DI0_DW_GEN_11__DI0_PT_3_11            0x1F040518,0x000000C0
#define SRM_DI0_DW_GEN_11__DI0_PT_2_11            0x1F040518,0x00000030
#define SRM_DI0_DW_GEN_11__DI0_PT_1_11            0x1F040518,0x0000000C
#define SRM_DI0_DW_GEN_11__DI0_PT_0_11            0x1F040518,0x00000003

#define SRM_DI0_DW_GEN_11__ADDR                     0x1F040518
#define SRM_DI0_DW_GEN_11__EMPTY                    0x1F040518,0x00000000
#define SRM_DI0_DW_GEN_11__FULL                     0x1F040518,0xffffffff
#define SRM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11     0x1F040518,0xFF000000
#define SRM_DI0_DW_GEN_11__DI0_START_PERIOD_11      0x1F040518,0x00FF0000
#define SRM_DI0_DW_GEN_11__DI0_CST_11               0x1F040518,0x0000C000
#define SRM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F040518,0x000001F0
#define SRM_DI0_DW_GEN_11__DI0_SERIAL_RS_11         0x1F040518,0x0000000C
#define SRM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11        0x1F040518,0x00000003

#define SRM_DI0_DW_SET0_0__ADDR                   0x1F04051C
#define SRM_DI0_DW_SET0_0__EMPTY       0x1F04051C,0x00000000
#define SRM_DI0_DW_SET0_0__FULL       0x1F04051C,0xffffffff
#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0       0x1F04051C,0x01FF0000
#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0       0x1F04051C,0x000001FF

#define SRM_DI0_DW_SET0_1__ADDR                   0x1F040520
#define SRM_DI0_DW_SET0_1__EMPTY       0x1F040520,0x00000000
#define SRM_DI0_DW_SET0_1__FULL       0x1F040520,0xffffffff
#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1       0x1F040520,0x01FF0000
#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1       0x1F040520,0x000001FF

#define SRM_DI0_DW_SET0_2__ADDR                   0x1F040524
#define SRM_DI0_DW_SET0_2__EMPTY       0x1F040524,0x00000000
#define SRM_DI0_DW_SET0_2__FULL       0x1F040524,0xffffffff
#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2       0x1F040524,0x01FF0000
#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2       0x1F040524,0x000001FF

#define SRM_DI0_DW_SET0_3__ADDR                   0x1F040528
#define SRM_DI0_DW_SET0_3__EMPTY       0x1F040528,0x00000000
#define SRM_DI0_DW_SET0_3__FULL       0x1F040528,0xffffffff
#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3       0x1F040528,0x01FF0000
#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3       0x1F040528,0x000001FF

#define SRM_DI0_DW_SET0_4__ADDR                   0x1F04052C
#define SRM_DI0_DW_SET0_4__EMPTY       0x1F04052C,0x00000000
#define SRM_DI0_DW_SET0_4__FULL       0x1F04052C,0xffffffff
#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4       0x1F04052C,0x01FF0000
#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4       0x1F04052C,0x000001FF

#define SRM_DI0_DW_SET0_5__ADDR                   0x1F040530
#define SRM_DI0_DW_SET0_5__EMPTY       0x1F040530,0x00000000
#define SRM_DI0_DW_SET0_5__FULL       0x1F040530,0xffffffff
#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5       0x1F040530,0x01FF0000
#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5       0x1F040530,0x000001FF

#define SRM_DI0_DW_SET0_6__ADDR                   0x1F040534
#define SRM_DI0_DW_SET0_6__EMPTY       0x1F040534,0x00000000
#define SRM_DI0_DW_SET0_6__FULL       0x1F040534,0xffffffff
#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6       0x1F040534,0x01FF0000
#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6       0x1F040534,0x000001FF

#define SRM_DI0_DW_SET0_7__ADDR                   0x1F040538
#define SRM_DI0_DW_SET0_7__EMPTY       0x1F040538,0x00000000
#define SRM_DI0_DW_SET0_7__FULL       0x1F040538,0xffffffff
#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7       0x1F040538,0x01FF0000
#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7       0x1F040538,0x000001FF

#define SRM_DI0_DW_SET0_8__ADDR                   0x1F04053C
#define SRM_DI0_DW_SET0_8__EMPTY       0x1F04053C,0x00000000
#define SRM_DI0_DW_SET0_8__FULL       0x1F04053C,0xffffffff
#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8       0x1F04053C,0x01FF0000
#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8       0x1F04053C,0x000001FF

#define SRM_DI0_DW_SET0_9__ADDR                   0x1F040540
#define SRM_DI0_DW_SET0_9__EMPTY       0x1F040540,0x00000000
#define SRM_DI0_DW_SET0_9__FULL       0x1F040540,0xffffffff
#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9       0x1F040540,0x01FF0000
#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9       0x1F040540,0x000001FF

#define SRM_DI0_DW_SET0_10__ADDR                   0x1F040544
#define SRM_DI0_DW_SET0_10__EMPTY       0x1F040544,0x00000000
#define SRM_DI0_DW_SET0_10__FULL       0x1F040544,0xffffffff
#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10       0x1F040544,0x01FF0000
#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10       0x1F040544,0x000001FF

#define SRM_DI0_DW_SET0_11__ADDR                   0x1F040548
#define SRM_DI0_DW_SET0_11__EMPTY       0x1F040548,0x00000000
#define SRM_DI0_DW_SET0_11__FULL       0x1F040548,0xffffffff
#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11       0x1F040548,0x01FF0000
#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11       0x1F040548,0x000001FF

#define SRM_DI0_DW_SET1_0__ADDR                   0x1F04054C
#define SRM_DI0_DW_SET1_0__EMPTY       0x1F04054C,0x00000000
#define SRM_DI0_DW_SET1_0__FULL       0x1F04054C,0xffffffff
#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0       0x1F04054C,0x01FF0000
#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0       0x1F04054C,0x000001FF

#define SRM_DI0_DW_SET1_1__ADDR                   0x1F040550
#define SRM_DI0_DW_SET1_1__EMPTY       0x1F040550,0x00000000
#define SRM_DI0_DW_SET1_1__FULL       0x1F040550,0xffffffff
#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1       0x1F040550,0x01FF0000
#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1       0x1F040550,0x000001FF

#define SRM_DI0_DW_SET1_2__ADDR                   0x1F040554
#define SRM_DI0_DW_SET1_2__EMPTY       0x1F040554,0x00000000
#define SRM_DI0_DW_SET1_2__FULL       0x1F040554,0xffffffff
#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2       0x1F040554,0x01FF0000
#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2       0x1F040554,0x000001FF

#define SRM_DI0_DW_SET1_3__ADDR                   0x1F040558
#define SRM_DI0_DW_SET1_3__EMPTY       0x1F040558,0x00000000
#define SRM_DI0_DW_SET1_3__FULL       0x1F040558,0xffffffff
#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3       0x1F040558,0x01FF0000
#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3       0x1F040558,0x000001FF

#define SRM_DI0_DW_SET1_4__ADDR                   0x1F04055C
#define SRM_DI0_DW_SET1_4__EMPTY       0x1F04055C,0x00000000
#define SRM_DI0_DW_SET1_4__FULL       0x1F04055C,0xffffffff
#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4       0x1F04055C,0x01FF0000
#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4       0x1F04055C,0x000001FF

#define SRM_DI0_DW_SET1_5__ADDR                   0x1F040560
#define SRM_DI0_DW_SET1_5__EMPTY       0x1F040560,0x00000000
#define SRM_DI0_DW_SET1_5__FULL       0x1F040560,0xffffffff
#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5       0x1F040560,0x01FF0000
#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5       0x1F040560,0x000001FF

#define SRM_DI0_DW_SET1_6__ADDR                   0x1F040564
#define SRM_DI0_DW_SET1_6__EMPTY       0x1F040564,0x00000000
#define SRM_DI0_DW_SET1_6__FULL       0x1F040564,0xffffffff
#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6       0x1F040564,0x01FF0000
#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6       0x1F040564,0x000001FF

#define SRM_DI0_DW_SET1_7__ADDR                   0x1F040568
#define SRM_DI0_DW_SET1_7__EMPTY       0x1F040568,0x00000000
#define SRM_DI0_DW_SET1_7__FULL       0x1F040568,0xffffffff
#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7       0x1F040568,0x01FF0000
#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7       0x1F040568,0x000001FF

#define SRM_DI0_DW_SET1_8__ADDR                   0x1F04056C
#define SRM_DI0_DW_SET1_8__EMPTY       0x1F04056C,0x00000000
#define SRM_DI0_DW_SET1_8__FULL       0x1F04056C,0xffffffff
#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8       0x1F04056C,0x01FF0000
#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8       0x1F04056C,0x000001FF

#define SRM_DI0_DW_SET1_9__ADDR                   0x1F040570
#define SRM_DI0_DW_SET1_9__EMPTY       0x1F040570,0x00000000
#define SRM_DI0_DW_SET1_9__FULL       0x1F040570,0xffffffff
#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9       0x1F040570,0x01FF0000
#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9       0x1F040570,0x000001FF

#define SRM_DI0_DW_SET1_10__ADDR                   0x1F040574
#define SRM_DI0_DW_SET1_10__EMPTY       0x1F040574,0x00000000
#define SRM_DI0_DW_SET1_10__FULL       0x1F040574,0xffffffff
#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10       0x1F040574,0x01FF0000
#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10       0x1F040574,0x000001FF

#define SRM_DI0_DW_SET1_11__ADDR                   0x1F040578
#define SRM_DI0_DW_SET1_11__EMPTY       0x1F040578,0x00000000
#define SRM_DI0_DW_SET1_11__FULL       0x1F040578,0xffffffff
#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11       0x1F040578,0x01FF0000
#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11       0x1F040578,0x000001FF

#define SRM_DI0_DW_SET2_0__ADDR                   0x1F04057C
#define SRM_DI0_DW_SET2_0__EMPTY       0x1F04057C,0x00000000
#define SRM_DI0_DW_SET2_0__FULL       0x1F04057C,0xffffffff
#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0       0x1F04057C,0x01FF0000
#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0       0x1F04057C,0x000001FF

#define SRM_DI0_DW_SET2_1__ADDR                   0x1F040580
#define SRM_DI0_DW_SET2_1__EMPTY       0x1F040580,0x00000000
#define SRM_DI0_DW_SET2_1__FULL       0x1F040580,0xffffffff
#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1       0x1F040580,0x01FF0000
#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1       0x1F040580,0x000001FF

#define SRM_DI0_DW_SET2_2__ADDR                   0x1F040584
#define SRM_DI0_DW_SET2_2__EMPTY       0x1F040584,0x00000000
#define SRM_DI0_DW_SET2_2__FULL       0x1F040584,0xffffffff
#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2       0x1F040584,0x01FF0000
#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2       0x1F040584,0x000001FF

#define SRM_DI0_DW_SET2_3__ADDR                   0x1F040588
#define SRM_DI0_DW_SET2_3__EMPTY       0x1F040588,0x00000000
#define SRM_DI0_DW_SET2_3__FULL       0x1F040588,0xffffffff
#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3       0x1F040588,0x01FF0000
#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3       0x1F040588,0x000001FF

#define SRM_DI0_DW_SET2_4__ADDR                   0x1F04058C
#define SRM_DI0_DW_SET2_4__EMPTY       0x1F04058C,0x00000000
#define SRM_DI0_DW_SET2_4__FULL       0x1F04058C,0xffffffff
#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4       0x1F04058C,0x01FF0000
#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4       0x1F04058C,0x000001FF

#define SRM_DI0_DW_SET2_5__ADDR                   0x1F040590
#define SRM_DI0_DW_SET2_5__EMPTY       0x1F040590,0x00000000
#define SRM_DI0_DW_SET2_5__FULL       0x1F040590,0xffffffff
#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5       0x1F040590,0x01FF0000
#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5       0x1F040590,0x000001FF

#define SRM_DI0_DW_SET2_6__ADDR                   0x1F040594
#define SRM_DI0_DW_SET2_6__EMPTY       0x1F040594,0x00000000
#define SRM_DI0_DW_SET2_6__FULL       0x1F040594,0xffffffff
#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6       0x1F040594,0x01FF0000
#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6       0x1F040594,0x000001FF

#define SRM_DI0_DW_SET2_7__ADDR                   0x1F040598
#define SRM_DI0_DW_SET2_7__EMPTY       0x1F040598,0x00000000
#define SRM_DI0_DW_SET2_7__FULL       0x1F040598,0xffffffff
#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7       0x1F040598,0x01FF0000
#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7       0x1F040598,0x000001FF

#define SRM_DI0_DW_SET2_8__ADDR                   0x1F04059C
#define SRM_DI0_DW_SET2_8__EMPTY       0x1F04059C,0x00000000
#define SRM_DI0_DW_SET2_8__FULL       0x1F04059C,0xffffffff
#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8       0x1F04059C,0x01FF0000
#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8       0x1F04059C,0x000001FF

#define SRM_DI0_DW_SET2_9__ADDR                   0x1F0405A0
#define SRM_DI0_DW_SET2_9__EMPTY       0x1F0405A0,0x00000000
#define SRM_DI0_DW_SET2_9__FULL       0x1F0405A0,0xffffffff
#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9       0x1F0405A0,0x01FF0000
#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9       0x1F0405A0,0x000001FF

#define SRM_DI0_DW_SET2_10__ADDR                   0x1F0405A4
#define SRM_DI0_DW_SET2_10__EMPTY       0x1F0405A4,0x00000000
#define SRM_DI0_DW_SET2_10__FULL       0x1F0405A4,0xffffffff
#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10       0x1F0405A4,0x01FF0000
#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10       0x1F0405A4,0x000001FF

#define SRM_DI0_DW_SET2_11__ADDR                   0x1F0405A8
#define SRM_DI0_DW_SET2_11__EMPTY       0x1F0405A8,0x00000000
#define SRM_DI0_DW_SET2_11__FULL       0x1F0405A8,0xffffffff
#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11       0x1F0405A8,0x01FF0000
#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11       0x1F0405A8,0x000001FF

#define SRM_DI0_DW_SET3_0__ADDR                   0x1F0405AC
#define SRM_DI0_DW_SET3_0__EMPTY       0x1F0405AC,0x00000000
#define SRM_DI0_DW_SET3_0__FULL       0x1F0405AC,0xffffffff
#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0       0x1F0405AC,0x01FF0000
#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0       0x1F0405AC,0x000001FF

#define SRM_DI0_DW_SET3_1__ADDR                   0x1F0405B0
#define SRM_DI0_DW_SET3_1__EMPTY       0x1F0405B0,0x00000000
#define SRM_DI0_DW_SET3_1__FULL       0x1F0405B0,0xffffffff
#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1       0x1F0405B0,0x01FF0000
#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1       0x1F0405B0,0x000001FF

#define SRM_DI0_DW_SET3_2__ADDR                   0x1F0405B4
#define SRM_DI0_DW_SET3_2__EMPTY       0x1F0405B4,0x00000000
#define SRM_DI0_DW_SET3_2__FULL       0x1F0405B4,0xffffffff
#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2       0x1F0405B4,0x01FF0000
#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2       0x1F0405B4,0x000001FF

#define SRM_DI0_DW_SET3_3__ADDR                   0x1F0405B8
#define SRM_DI0_DW_SET3_3__EMPTY       0x1F0405B8,0x00000000
#define SRM_DI0_DW_SET3_3__FULL       0x1F0405B8,0xffffffff
#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3       0x1F0405B8,0x01FF0000
#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3       0x1F0405B8,0x000001FF

#define SRM_DI0_DW_SET3_4__ADDR                   0x1F0405BC
#define SRM_DI0_DW_SET3_4__EMPTY       0x1F0405BC,0x00000000
#define SRM_DI0_DW_SET3_4__FULL       0x1F0405BC,0xffffffff
#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4       0x1F0405BC,0x01FF0000
#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4       0x1F0405BC,0x000001FF

#define SRM_DI0_DW_SET3_5__ADDR                   0x1F0405C0
#define SRM_DI0_DW_SET3_5__EMPTY       0x1F0405C0,0x00000000
#define SRM_DI0_DW_SET3_5__FULL       0x1F0405C0,0xffffffff
#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5       0x1F0405C0,0x01FF0000
#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5       0x1F0405C0,0x000001FF

#define SRM_DI0_DW_SET3_6__ADDR                   0x1F0405C4
#define SRM_DI0_DW_SET3_6__EMPTY       0x1F0405C4,0x00000000
#define SRM_DI0_DW_SET3_6__FULL       0x1F0405C4,0xffffffff
#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6       0x1F0405C4,0x01FF0000
#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6       0x1F0405C4,0x000001FF

#define SRM_DI0_DW_SET3_7__ADDR                   0x1F0405C8
#define SRM_DI0_DW_SET3_7__EMPTY       0x1F0405C8,0x00000000
#define SRM_DI0_DW_SET3_7__FULL       0x1F0405C8,0xffffffff
#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7       0x1F0405C8,0x01FF0000
#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7       0x1F0405C8,0x000001FF

#define SRM_DI0_DW_SET3_8__ADDR                   0x1F0405CC
#define SRM_DI0_DW_SET3_8__EMPTY       0x1F0405CC,0x00000000
#define SRM_DI0_DW_SET3_8__FULL       0x1F0405CC,0xffffffff
#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8       0x1F0405CC,0x01FF0000
#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8       0x1F0405CC,0x000001FF

#define SRM_DI0_DW_SET3_9__ADDR                   0x1F0405D0
#define SRM_DI0_DW_SET3_9__EMPTY       0x1F0405D0,0x00000000
#define SRM_DI0_DW_SET3_9__FULL       0x1F0405D0,0xffffffff
#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9       0x1F0405D0,0x01FF0000
#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9       0x1F0405D0,0x000001FF

#define SRM_DI0_DW_SET3_10__ADDR                   0x1F0405D4
#define SRM_DI0_DW_SET3_10__EMPTY       0x1F0405D4,0x00000000
#define SRM_DI0_DW_SET3_10__FULL       0x1F0405D4,0xffffffff
#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10       0x1F0405D4,0x01FF0000
#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10       0x1F0405D4,0x000001FF

#define SRM_DI0_DW_SET3_11__ADDR                   0x1F0405D8
#define SRM_DI0_DW_SET3_11__EMPTY       0x1F0405D8,0x00000000
#define SRM_DI0_DW_SET3_11__FULL       0x1F0405D8,0xffffffff
#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11       0x1F0405D8,0x01FF0000
#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11       0x1F0405D8,0x000001FF

#define SRM_DI0_STP_REP_1__ADDR                   0x1F0405DC
#define SRM_DI0_STP_REP_1__EMPTY       0x1F0405DC,0x00000000
#define SRM_DI0_STP_REP_1__FULL       0x1F0405DC,0xffffffff
#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_2       0x1F0405DC,0x0FFF0000
#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_1       0x1F0405DC,0x00000FFF

#define SRM_DI0_STP_REP_2__ADDR                   0x1F0405E0
#define SRM_DI0_STP_REP_2__EMPTY       0x1F0405E0,0x00000000
#define SRM_DI0_STP_REP_2__FULL       0x1F0405E0,0xffffffff
#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_4       0x1F0405E0,0x0FFF0000
#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_3       0x1F0405E0,0x00000FFF

#define SRM_DI0_STP_REP_3__ADDR                   0x1F0405E4
#define SRM_DI0_STP_REP_3__EMPTY       0x1F0405E4,0x00000000
#define SRM_DI0_STP_REP_3__FULL       0x1F0405E4,0xffffffff
#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_6       0x1F0405E4,0x0FFF0000
#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_5       0x1F0405E4,0x00000FFF

#define SRM_DI0_STP_REP_4__ADDR                   0x1F0405E8
#define SRM_DI0_STP_REP_4__EMPTY       0x1F0405E8,0x00000000
#define SRM_DI0_STP_REP_4__FULL       0x1F0405E8,0xffffffff
#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_8       0x1F0405E8,0x0FFF0000
#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_7       0x1F0405E8,0x00000FFF

#define SRM_DI0_STP_REP_9__ADDR                   0x1F0405EC
#define SRM_DI0_STP_REP_9__EMPTY       0x1F0405EC,0x00000000
#define SRM_DI0_STP_REP_9__FULL       0x1F0405EC,0xffffffff
#define SRM_DI0_STP_REP_9__DI0_STEP_REPEAT_9       0x1F0405EC,0x00000FFF

#define SRM_DI0_SER_CONF__ADDR                   0x1F0405F0
#define SRM_DI0_SER_CONF__EMPTY       0x1F0405F0,0x00000000
#define SRM_DI0_SER_CONF__FULL       0x1F0405F0,0xffffffff
#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1       0x1F0405F0,0xF0000000
#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0       0x1F0405F0,0x0F000000
#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1       0x1F0405F0,0x00F00000
#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0       0x1F0405F0,0x000F0000
#define SRM_DI0_SER_CONF__DI0_SERIAL_LATCH       0x1F0405F0,0x0000FF00
#define SRM_DI0_SER_CONF__DI0_LLA_SER_ACCESS       0x1F0405F0,0x00000020
#define SRM_DI0_SER_CONF__DI0_SER_CLK_POLARITY       0x1F0405F0,0x00000010
#define SRM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY       0x1F0405F0,0x00000008
#define SRM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY       0x1F0405F0,0x00000004
#define SRM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY       0x1F0405F0,0x00000002
#define SRM_DI0_SER_CONF__DI0_WAIT4SERIAL       0x1F0405F0,0x00000001

#define SRM_DI0_SSC__ADDR                   0x1F0405F4
#define SRM_DI0_SSC__EMPTY       0x1F0405F4,0x00000000
#define SRM_DI0_SSC__FULL       0x1F0405F4,0xffffffff
#define SRM_DI0_SSC__DI0_PIN17_ERM     0x1F0405F4,0x00800000
#define SRM_DI0_SSC__DI0_PIN16_ERM     0x1F0405F4,0x00400000
#define SRM_DI0_SSC__DI0_PIN15_ERM     0x1F0405F4,0x00200000
#define SRM_DI0_SSC__DI0_PIN14_ERM     0x1F0405F4,0x00100000
#define SRM_DI0_SSC__DI0_PIN13_ERM     0x1F0405F4,0x00080000
#define SRM_DI0_SSC__DI0_PIN12_ERM     0x1F0405F4,0x00040000
#define SRM_DI0_SSC__DI0_PIN11_ERM     0x1F0405F4,0x00020000
#define SRM_DI0_SSC__DI0_CS_ERM        0x1F0405F4,0x00010000
#define SRM_DI0_SSC__DI0_WAIT_ON       0x1F0405F4,0x00000020
#define SRM_DI0_SSC__DI0_BYTE_EN_RD_IN       0x1F0405F4,0x00000008
#define SRM_DI0_SSC__DI0_BYTE_EN_PNTR       0x1F0405F4,0x00000007

#define SRM_DI0_POL__ADDR                   0x1F0405F8
#define SRM_DI0_POL__EMPTY       0x1F0405F8,0x00000000
#define SRM_DI0_POL__FULL       0x1F0405F8,0xffffffff
#define SRM_DI0_POL__DI0_WAIT_POLARITY       0x1F0405F8,0x04000000
#define SRM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY       0x1F0405F8,0x02000000
#define SRM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY       0x1F0405F8,0x01000000
#define SRM_DI0_POL__DI0_CS1_DATA_POLARITY       0x1F0405F8,0x00800000
#define SRM_DI0_POL__DI0_CS1_POLARITY_17       0x1F0405F8,0x00400000
#define SRM_DI0_POL__DI0_CS1_POLARITY_16       0x1F0405F8,0x00200000
#define SRM_DI0_POL__DI0_CS1_POLARITY_15       0x1F0405F8,0x00100000
#define SRM_DI0_POL__DI0_CS1_POLARITY_14       0x1F0405F8,0x00080000
#define SRM_DI0_POL__DI0_CS1_POLARITY_13       0x1F0405F8,0x00040000
#define SRM_DI0_POL__DI0_CS1_POLARITY_12       0x1F0405F8,0x00020000
#define SRM_DI0_POL__DI0_CS1_POLARITY_11       0x1F0405F8,0x00010000
#define SRM_DI0_POL__DI0_CS0_DATA_POLARITY       0x1F0405F8,0x00008000
#define SRM_DI0_POL__DI0_CS0_POLARITY_17       0x1F0405F8,0x00004000
#define SRM_DI0_POL__DI0_CS0_POLARITY_16       0x1F0405F8,0x00002000
#define SRM_DI0_POL__DI0_CS0_POLARITY_15       0x1F0405F8,0x00001000
#define SRM_DI0_POL__DI0_CS0_POLARITY_14       0x1F0405F8,0x00000800
#define SRM_DI0_POL__DI0_CS0_POLARITY_13       0x1F0405F8,0x00000400
#define SRM_DI0_POL__DI0_CS0_POLARITY_12       0x1F0405F8,0x00000200
#define SRM_DI0_POL__DI0_CS0_POLARITY_11       0x1F0405F8,0x00000100
#define SRM_DI0_POL__DI0_DRDY_DATA_POLARITY       0x1F0405F8,0x00000080
#define SRM_DI0_POL__DI0_DRDY_POLARITY_17       0x1F0405F8,0x00000040
#define SRM_DI0_POL__DI0_DRDY_POLARITY_16       0x1F0405F8,0x00000020
#define SRM_DI0_POL__DI0_DRDY_POLARITY_15       0x1F0405F8,0x00000010
#define SRM_DI0_POL__DI0_DRDY_POLARITY_14       0x1F0405F8,0x00000008
#define SRM_DI0_POL__DI0_DRDY_POLARITY_13       0x1F0405F8,0x00000004
#define SRM_DI0_POL__DI0_DRDY_POLARITY_12       0x1F0405F8,0x00000002
#define SRM_DI0_POL__DI0_DRDY_POLARITY_11       0x1F0405F8,0x00000001

#define SRM_DI0_AW0__ADDR                   0x1F0405FC
#define SRM_DI0_AW0__EMPTY       0x1F0405FC,0x00000000
#define SRM_DI0_AW0__FULL       0x1F0405FC,0xffffffff
#define SRM_DI0_AW0__DI0_AW_TRIG_SEL       0x1F0405FC,0xF0000000
#define SRM_DI0_AW0__DI0_AW_HEND       0x1F0405FC,0x0FFF0000
#define SRM_DI0_AW0__DI0_AW_HCOUNT_SEL       0x1F0405FC,0x0000F000
#define SRM_DI0_AW0__DI0_AW_HSTART       0x1F0405FC,0x00000FFF

#define SRM_DI0_AW1__ADDR                   0x1F040600
#define SRM_DI0_AW1__EMPTY       0x1F040600,0x00000000
#define SRM_DI0_AW1__FULL       0x1F040600,0xffffffff
#define SRM_DI0_AW1__DI0_AW_VEND       0x1F040600,0x0FFF0000
#define SRM_DI0_AW1__DI0_AW_VCOUNT_SEL       0x1F040600,0x0000F000
#define SRM_DI0_AW1__DI0_AW_VSTART       0x1F040600,0x00000FFF

#define SRM_DI0_SCR_CONF__ADDR                   0x1F040604
#define SRM_DI0_SCR_CONF__EMPTY       0x1F040604,0x00000000
#define SRM_DI0_SCR_CONF__FULL       0x1F040604,0xffffffff
#define SRM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT       0x1F040604,0x00000FFF

#define SRM_DI1_GENERAL__ADDR                   0x1F040608
#define SRM_DI1_GENERAL__EMPTY       0x1F040608,0x00000000
#define SRM_DI1_GENERAL__FULL       0x1F040608,0xffffffff
#define SRM_DI1_GENERAL__DI1_DISP_Y_SEL       0x1F040608,0x70000000
#define SRM_DI1_GENERAL__DI1_CLOCK_STOP_MODE       0x1F040608,0x0F000000
#define SRM_DI1_GENERAL__DI1_DISP_CLOCK_INIT   0x1F040608,0x00800000
#define SRM_DI1_GENERAL__DI1_MASK_SEL       0x1F040608,0x00400000
#define SRM_DI1_GENERAL__DI1_VSYNC_EXT       0x1F040608,0x00200000
#define SRM_DI1_GENERAL__DI1_CLK_EXT       0x1F040608,0x00100000
#define SRN_DI1_GENERAL__DI1_WATCHDOG_MODE     0x1F040608,0x000C0000
#define SRM_DI1_GENERAL__DI1_POLARITY_DISP_CLK       0x1F040608,0x00020000
#define SRM_DI1_GENERAL__DI1_SYNC_COUNT_SEL       0x1F040608,0x0000F000
#define SRM_DI1_GENERAL__DI1_ERR_TREATMENT       0x1F040608,0x00000800
#define SRM_DI1_GENERAL__DI1_ERM_VSYNC_SEL     0x1F040608,0x00000400
#define SRM_DI1_GENERAL__DI1_POLARITY_CS1       0x1F040608,0x00000200
#define SRM_DI1_GENERAL__DI1_POLARITY_CS0       0x1F040608,0x00000100
#define SRM_DI1_GENERAL__DI1_POLARITY_8       0x1F040608,0x00000080
#define SRM_DI1_GENERAL__DI1_POLARITY_7       0x1F040608,0x00000040
#define SRM_DI1_GENERAL__DI1_POLARITY_6       0x1F040608,0x00000020
#define SRM_DI1_GENERAL__DI1_POLARITY_5       0x1F040608,0x00000010
#define SRM_DI1_GENERAL__DI1_POLARITY_4       0x1F040608,0x00000008
#define SRM_DI1_GENERAL__DI1_POLARITY_3       0x1F040608,0x00000004
#define SRM_DI1_GENERAL__DI1_POLARITY_2       0x1F040608,0x00000002
#define SRM_DI1_GENERAL__DI1_POLARITY_1       0x1F040608,0x00000001

#define SRM_DI1_BS_CLKGEN0__ADDR                   0x1F04060C
#define SRM_DI1_BS_CLKGEN0__EMPTY       0x1F04060C,0x00000000
#define SRM_DI1_BS_CLKGEN0__FULL       0x1F04060C,0xffffffff
#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET       0x1F04060C,0x01FF0000
#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD       0x1F04060C,0x00000FFF

#define SRM_DI1_BS_CLKGEN1__ADDR                   0x1F040610
#define SRM_DI1_BS_CLKGEN1__EMPTY       0x1F040610,0x00000000
#define SRM_DI1_BS_CLKGEN1__FULL       0x1F040610,0xffffffff
#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN       0x1F040610,0x01FF0000
#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP       0x1F040610,0x000001FF

#define SRM_DI1_SW_GEN0_1__ADDR                   0x1F040614
#define SRM_DI1_SW_GEN0_1__EMPTY       0x1F040614,0x00000000
#define SRM_DI1_SW_GEN0_1__FULL       0x1F040614,0xffffffff
#define SRM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1       0x1F040614,0x7FF80000
#define SRM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1       0x1F040614,0x00070000
#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1       0x1F040614,0x00007FF8
#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1       0x1F040614,0x00000007

#define SRM_DI1_SW_GEN0_2__ADDR                   0x1F040618
#define SRM_DI1_SW_GEN0_2__EMPTY       0x1F040618,0x00000000
#define SRM_DI1_SW_GEN0_2__FULL       0x1F040618,0xffffffff
#define SRM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2       0x1F040618,0x7FF80000
#define SRM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2       0x1F040618,0x00070000
#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2       0x1F040618,0x00007FF8
#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2       0x1F040618,0x00000007

#define SRM_DI1_SW_GEN0_3__ADDR                   0x1F04061C
#define SRM_DI1_SW_GEN0_3__EMPTY       0x1F04061C,0x00000000
#define SRM_DI1_SW_GEN0_3__FULL       0x1F04061C,0xffffffff
#define SRM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3       0x1F04061C,0x7FF80000
#define SRM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3       0x1F04061C,0x00070000
#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3       0x1F04061C,0x00007FF8
#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3       0x1F04061C,0x00000007

#define SRM_DI1_SW_GEN0_4__ADDR                   0x1F040620
#define SRM_DI1_SW_GEN0_4__EMPTY       0x1F040620,0x00000000
#define SRM_DI1_SW_GEN0_4__FULL       0x1F040620,0xffffffff
#define SRM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4       0x1F040620,0x7FF80000
#define SRM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4       0x1F040620,0x00070000
#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4       0x1F040620,0x00007FF8
#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4       0x1F040620,0x00000007

#define SRM_DI1_SW_GEN0_5__ADDR                   0x1F040624
#define SRM_DI1_SW_GEN0_5__EMPTY       0x1F040624,0x00000000
#define SRM_DI1_SW_GEN0_5__FULL       0x1F040624,0xffffffff
#define SRM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5       0x1F040624,0x7FF80000
#define SRM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5       0x1F040624,0x00070000
#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5       0x1F040624,0x00007FF8
#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5       0x1F040624,0x00000007

#define SRM_DI1_SW_GEN0_6__ADDR                   0x1F040628
#define SRM_DI1_SW_GEN0_6__EMPTY       0x1F040628,0x00000000
#define SRM_DI1_SW_GEN0_6__FULL       0x1F040628,0xffffffff
#define SRM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6       0x1F040628,0x7FF80000
#define SRM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6       0x1F040628,0x00070000
#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6       0x1F040628,0x00007FF8
#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6       0x1F040628,0x00000007

#define SRM_DI1_SW_GEN0_7__ADDR                   0x1F04062C
#define SRM_DI1_SW_GEN0_7__EMPTY       0x1F04062C,0x00000000
#define SRM_DI1_SW_GEN0_7__FULL       0x1F04062C,0xffffffff
#define SRM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7       0x1F04062C,0x7FF80000
#define SRM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7       0x1F04062C,0x00070000
#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7       0x1F04062C,0x00007FF8
#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7       0x1F04062C,0x00000007

#define SRM_DI1_SW_GEN0_8__ADDR                   0x1F040630
#define SRM_DI1_SW_GEN0_8__EMPTY       0x1F040630,0x00000000
#define SRM_DI1_SW_GEN0_8__FULL       0x1F040630,0xffffffff
#define SRM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8       0x1F040630,0x7FF80000
#define SRM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8       0x1F040630,0x00070000
#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8       0x1F040630,0x00007FF8
#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8       0x1F040630,0x00000007

#define SRM_DI1_SW_GEN0_9__ADDR                   0x1F040634
#define SRM_DI1_SW_GEN0_9__EMPTY       0x1F040634,0x00000000
#define SRM_DI1_SW_GEN0_9__FULL       0x1F040634,0xffffffff
#define SRM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9       0x1F040634,0x7FF80000
#define SRM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9       0x1F040634,0x00070000
#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9       0x1F040634,0x00007FF8
#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9       0x1F040634,0x00000007

#define SRM_DI1_SW_GEN1_1__ADDR                   0x1F040638
#define SRM_DI1_SW_GEN1_1__EMPTY       0x1F040638,0x00000000
#define SRM_DI1_SW_GEN1_1__FULL       0x1F040638,0xffffffff
#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1       0x1F040638,0x60000000
#define SRM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1       0x1F040638,0x10000000
#define SRM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1       0x1F040638,0x0E000000
#define SRM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1       0x1F040638,0x01FF0000
#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1       0x1F040638,0x00007000
#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1       0x1F040638,0x00000E00
#define SRM_DI1_SW_GEN1_1__DI1_CNT_UP_1       0x1F040638,0x000001FF

#define SRM_DI1_SW_GEN1_2__ADDR                   0x1F04063C
#define SRM_DI1_SW_GEN1_2__EMPTY       0x1F04063C,0x00000000
#define SRM_DI1_SW_GEN1_2__FULL       0x1F04063C,0xffffffff
#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2       0x1F04063C,0x60000000
#define SRM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2       0x1F04063C,0x10000000
#define SRM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2       0x1F04063C,0x0E000000
#define SRM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2       0x1F04063C,0x01FF0000
#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2       0x1F04063C,0x00007000
#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2       0x1F04063C,0x00000E00
#define SRM_DI1_SW_GEN1_2__DI1_CNT_UP_2       0x1F04063C,0x000001FF

#define SRM_DI1_SW_GEN1_3__ADDR                   0x1F040640
#define SRM_DI1_SW_GEN1_3__EMPTY       0x1F040640,0x00000000
#define SRM_DI1_SW_GEN1_3__FULL       0x1F040640,0xffffffff
#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3       0x1F040640,0x60000000
#define SRM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3       0x1F040640,0x10000000
#define SRM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3       0x1F040640,0x0E000000
#define SRM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3       0x1F040640,0x01FF0000
#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3       0x1F040640,0x00007000
#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3       0x1F040640,0x00000E00
#define SRM_DI1_SW_GEN1_3__DI1_CNT_UP_3       0x1F040640,0x000001FF

#define SRM_DI1_SW_GEN1_4__ADDR                   0x1F040644
#define SRM_DI1_SW_GEN1_4__EMPTY       0x1F040644,0x00000000
#define SRM_DI1_SW_GEN1_4__FULL       0x1F040644,0xffffffff
#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4       0x1F040644,0x60000000
#define SRM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4       0x1F040644,0x10000000
#define SRM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4       0x1F040644,0x0E000000
#define SRM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4       0x1F040644,0x01FF0000
#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4       0x1F040644,0x00007000
#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4       0x1F040644,0x00000E00
#define SRM_DI1_SW_GEN1_4__DI1_CNT_UP_4       0x1F040644,0x000001FF

#define SRM_DI1_SW_GEN1_5__ADDR                   0x1F040648
#define SRM_DI1_SW_GEN1_5__EMPTY       0x1F040648,0x00000000
#define SRM_DI1_SW_GEN1_5__FULL       0x1F040648,0xffffffff
#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5       0x1F040648,0x60000000
#define SRM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5       0x1F040648,0x10000000
#define SRM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5       0x1F040648,0x0E000000
#define SRM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5       0x1F040648,0x01FF0000
#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5       0x1F040648,0x00007000
#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5       0x1F040648,0x00000E00
#define SRM_DI1_SW_GEN1_5__DI1_CNT_UP_5       0x1F040648,0x000001FF

#define SRM_DI1_SW_GEN1_6__ADDR                   0x1F04064C
#define SRM_DI1_SW_GEN1_6__EMPTY       0x1F04064C,0x00000000
#define SRM_DI1_SW_GEN1_6__FULL       0x1F04064C,0xffffffff
#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6       0x1F04064C,0x60000000
#define SRM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6       0x1F04064C,0x10000000
#define SRM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6       0x1F04064C,0x0E000000
#define SRM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6       0x1F04064C,0x01FF0000
#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6       0x1F04064C,0x00007000
#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6       0x1F04064C,0x00000E00
#define SRM_DI1_SW_GEN1_6__DI1_CNT_UP_6       0x1F04064C,0x000001FF

#define SRM_DI1_SW_GEN1_7__ADDR                   0x1F040650
#define SRM_DI1_SW_GEN1_7__EMPTY       0x1F040650,0x00000000
#define SRM_DI1_SW_GEN1_7__FULL       0x1F040650,0xffffffff
#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7       0x1F040650,0x60000000
#define SRM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7       0x1F040650,0x10000000
#define SRM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7       0x1F040650,0x0E000000
#define SRM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7       0x1F040650,0x01FF0000
#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7       0x1F040650,0x00007000
#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7       0x1F040650,0x00000E00
#define SRM_DI1_SW_GEN1_7__DI1_CNT_UP_7       0x1F040650,0x000001FF

#define SRM_DI1_SW_GEN1_8__ADDR                   0x1F040654
#define SRM_DI1_SW_GEN1_8__EMPTY       0x1F040654,0x00000000
#define SRM_DI1_SW_GEN1_8__FULL       0x1F040654,0xffffffff
#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8       0x1F040654,0x60000000
#define SRM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8       0x1F040654,0x10000000
#define SRM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8       0x1F040654,0x0E000000
#define SRM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8       0x1F040654,0x01FF0000
#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8       0x1F040654,0x00007000
#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8       0x1F040654,0x00000E00
#define SRM_DI1_SW_GEN1_8__DI1_CNT_UP_8       0x1F040654,0x000001FF

#define SRM_DI1_SW_GEN1_9__ADDR                   0x1F040658
#define SRM_DI1_SW_GEN1_9__EMPTY       0x1F040658,0x00000000
#define SRM_DI1_SW_GEN1_9__FULL       0x1F040658,0xffffffff
#define SRM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9       0x1F040658,0xE0000000
#define SRM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9       0x1F040658,0x10000000
#define SRM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9       0x1F040658,0x0E000000
#define SRM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9       0x1F040658,0x01FF0000
#define SRM_DI1_SW_GEN1_9__DI1_TAG_SEL_9       0x1F040658,0x00008000
#define SRM_DI1_SW_GEN1_9__DI1_CNT_UP_9       0x1F040658,0x000001FF

#define SRM_DI1_SYNC_AS_GEN__ADDR                   0x1F04065C
#define SRM_DI1_SYNC_AS_GEN__EMPTY       0x1F04065C,0x00000000
#define SRM_DI1_SYNC_AS_GEN__FULL       0x1F04065C,0xffffffff
#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN       0x1F04065C,0x10000000
#define SRM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL       0x1F04065C,0x0000E000
#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START       0x1F04065C,0x00000FFF

#define SRM_DI1_DW_GEN_0__ADDR                  0x1F040660
#define SRM_DI1_DW_GEN_0__EMPTY                 0x1F040660,0x00000000
#define SRM_DI1_DW_GEN_0__FULL                  0x1F040660,0xffffffff
#define SRM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0     0x1F040660,0xFF000000
#define SRM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1F040660,0x00FF0000
#define SRM_DI1_DW_GEN_0__DI1_CST_0             0x1F040660,0x0000C000
#define SRM_DI1_DW_GEN_0__DI1_PT_6_0            0x1F040660,0x00003000
#define SRM_DI1_DW_GEN_0__DI1_PT_5_0            0x1F040660,0x00000C00
#define SRM_DI1_DW_GEN_0__DI1_PT_4_0            0x1F040660,0x00000300
#define SRM_DI1_DW_GEN_0__DI1_PT_3_0            0x1F040660,0x000000C0
#define SRM_DI1_DW_GEN_0__DI1_PT_2_0            0x1F040660,0x00000030
#define SRM_DI1_DW_GEN_0__DI1_PT_1_0            0x1F040660,0x0000000C
#define SRM_DI1_DW_GEN_0__DI1_PT_0_0            0x1F040660,0x00000003

#define SRM_DI1_DW_GEN_0__ADDR                    0x1F040660
#define SRM_DI1_DW_GEN_0__EMPTY                   0x1F040660,0x00000000
#define SRM_DI1_DW_GEN_0__FULL                    0x1F040660,0xffffffff
#define SRM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0     0x1F040660,0xFF000000
#define SRM_DI1_DW_GEN_0__DI1_START_PERIOD_0      0x1F040660,0x00FF0000
#define SRM_DI1_DW_GEN_0__DI1_CST_0               0x1F040660,0x0000C000
#define SRM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1F040660,0x000001F0
#define SRM_DI1_DW_GEN_0__DI1_SERIAL_RS_0         0x1F040660,0x0000000C
#define SRM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0        0x1F040660,0x00000003

#define SRM_DI1_DW_GEN_1__ADDR                  0x1F040664
#define SRM_DI1_DW_GEN_1__EMPTY                 0x1F040664,0x00000000
#define SRM_DI1_DW_GEN_1__FULL                  0x1F040664,0xffffffff
#define SRM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1     0x1F040664,0xFF000000
#define SRM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1F040664,0x00FF0000
#define SRM_DI1_DW_GEN_1__DI1_CST_1             0x1F040664,0x0000C000
#define SRM_DI1_DW_GEN_1__DI1_PT_6_1            0x1F040664,0x00003000
#define SRM_DI1_DW_GEN_1__DI1_PT_5_1            0x1F040664,0x00000C00
#define SRM_DI1_DW_GEN_1__DI1_PT_4_1            0x1F040664,0x00000300
#define SRM_DI1_DW_GEN_1__DI1_PT_3_1            0x1F040664,0x000000C0
#define SRM_DI1_DW_GEN_1__DI1_PT_2_1            0x1F040664,0x00000030
#define SRM_DI1_DW_GEN_1__DI1_PT_1_1            0x1F040664,0x0000000C
#define SRM_DI1_DW_GEN_1__DI1_PT_0_1            0x1F040664,0x00000003

#define SRM_DI1_DW_GEN_1__ADDR                    0x1F040664
#define SRM_DI1_DW_GEN_1__EMPTY                   0x1F040664,0x00000000
#define SRM_DI1_DW_GEN_1__FULL                    0x1F040664,0xffffffff
#define SRM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1     0x1F040664,0xFF000000
#define SRM_DI1_DW_GEN_1__DI1_START_PERIOD_1      0x1F040664,0x00FF0000
#define SRM_DI1_DW_GEN_1__DI1_CST_1               0x1F040664,0x0000C000
#define SRM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1F040664,0x000001F0
#define SRM_DI1_DW_GEN_1__DI1_SERIAL_RS_1         0x1F040664,0x0000000C
#define SRM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1        0x1F040664,0x00000003

#define SRM_DI1_DW_GEN_2__ADDR                  0x1F040668
#define SRM_DI1_DW_GEN_2__EMPTY                 0x1F040668,0x00000000
#define SRM_DI1_DW_GEN_2__FULL                  0x1F040668,0xffffffff
#define SRM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2     0x1F040668,0xFF000000
#define SRM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1F040668,0x00FF0000
#define SRM_DI1_DW_GEN_2__DI1_CST_2             0x1F040668,0x0000C000
#define SRM_DI1_DW_GEN_2__DI1_PT_6_2            0x1F040668,0x00003000
#define SRM_DI1_DW_GEN_2__DI1_PT_5_2            0x1F040668,0x00000C00
#define SRM_DI1_DW_GEN_2__DI1_PT_4_2            0x1F040668,0x00000300
#define SRM_DI1_DW_GEN_2__DI1_PT_3_2            0x1F040668,0x000000C0
#define SRM_DI1_DW_GEN_2__DI1_PT_2_2            0x1F040668,0x00000030
#define SRM_DI1_DW_GEN_2__DI1_PT_1_2            0x1F040668,0x0000000C
#define SRM_DI1_DW_GEN_2__DI1_PT_0_2            0x1F040668,0x00000003

#define SRM_DI1_DW_GEN_2__ADDR                    0x1F040668
#define SRM_DI1_DW_GEN_2__EMPTY                   0x1F040668,0x00000000
#define SRM_DI1_DW_GEN_2__FULL                    0x1F040668,0xffffffff
#define SRM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2     0x1F040668,0xFF000000
#define SRM_DI1_DW_GEN_2__DI1_START_PERIOD_2      0x1F040668,0x00FF0000
#define SRM_DI1_DW_GEN_2__DI1_CST_2               0x1F040668,0x0000C000
#define SRM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1F040668,0x000001F0
#define SRM_DI1_DW_GEN_2__DI1_SERIAL_RS_2         0x1F040668,0x0000000C
#define SRM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2        0x1F040668,0x00000003

#define SRM_DI1_DW_GEN_3__ADDR                  0x1F04066C
#define SRM_DI1_DW_GEN_3__EMPTY                 0x1F04066C,0x00000000
#define SRM_DI1_DW_GEN_3__FULL                  0x1F04066C,0xffffffff
#define SRM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3     0x1F04066C,0xFF000000
#define SRM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1F04066C,0x00FF0000
#define SRM_DI1_DW_GEN_3__DI1_CST_3             0x1F04066C,0x0000C000
#define SRM_DI1_DW_GEN_3__DI1_PT_6_3            0x1F04066C,0x00003000
#define SRM_DI1_DW_GEN_3__DI1_PT_5_3            0x1F04066C,0x00000C00
#define SRM_DI1_DW_GEN_3__DI1_PT_4_3            0x1F04066C,0x00000300
#define SRM_DI1_DW_GEN_3__DI1_PT_3_3            0x1F04066C,0x000000C0
#define SRM_DI1_DW_GEN_3__DI1_PT_2_3            0x1F04066C,0x00000030
#define SRM_DI1_DW_GEN_3__DI1_PT_1_3            0x1F04066C,0x0000000C
#define SRM_DI1_DW_GEN_3__DI1_PT_0_3            0x1F04066C,0x00000003

#define SRM_DI1_DW_GEN_3__ADDR                    0x1F04066C
#define SRM_DI1_DW_GEN_3__EMPTY                   0x1F04066C,0x00000000
#define SRM_DI1_DW_GEN_3__FULL                    0x1F04066C,0xffffffff
#define SRM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3     0x1F04066C,0xFF000000
#define SRM_DI1_DW_GEN_3__DI1_START_PERIOD_3      0x1F04066C,0x00FF0000
#define SRM_DI1_DW_GEN_3__DI1_CST_3               0x1F04066C,0x0000C000
#define SRM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1F04066C,0x000001F0
#define SRM_DI1_DW_GEN_3__DI1_SERIAL_RS_3         0x1F04066C,0x0000000C
#define SRM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3        0x1F04066C,0x00000003

#define SRM_DI1_DW_GEN_4__ADDR                  0x1F040670
#define SRM_DI1_DW_GEN_4__EMPTY                 0x1F040670,0x00000000
#define SRM_DI1_DW_GEN_4__FULL                  0x1F040670,0xffffffff
#define SRM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4     0x1F040670,0xFF000000
#define SRM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1F040670,0x00FF0000
#define SRM_DI1_DW_GEN_4__DI1_CST_4             0x1F040670,0x0000C000
#define SRM_DI1_DW_GEN_4__DI1_PT_6_4            0x1F040670,0x00003000
#define SRM_DI1_DW_GEN_4__DI1_PT_5_4            0x1F040670,0x00000C00
#define SRM_DI1_DW_GEN_4__DI1_PT_4_4            0x1F040670,0x00000300
#define SRM_DI1_DW_GEN_4__DI1_PT_3_4            0x1F040670,0x000000C0
#define SRM_DI1_DW_GEN_4__DI1_PT_2_4            0x1F040670,0x00000030
#define SRM_DI1_DW_GEN_4__DI1_PT_1_4            0x1F040670,0x0000000C
#define SRM_DI1_DW_GEN_4__DI1_PT_0_4            0x1F040670,0x00000003

#define SRM_DI1_DW_GEN_4__ADDR                    0x1F040670
#define SRM_DI1_DW_GEN_4__EMPTY                   0x1F040670,0x00000000
#define SRM_DI1_DW_GEN_4__FULL                    0x1F040670,0xffffffff
#define SRM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4     0x1F040670,0xFF000000
#define SRM_DI1_DW_GEN_4__DI1_START_PERIOD_4      0x1F040670,0x00FF0000
#define SRM_DI1_DW_GEN_4__DI1_CST_4               0x1F040670,0x0000C000
#define SRM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1F040670,0x000001F0
#define SRM_DI1_DW_GEN_4__DI1_SERIAL_RS_4         0x1F040670,0x0000000C
#define SRM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4        0x1F040670,0x00000003

#define SRM_DI1_DW_GEN_5__ADDR                  0x1F040674
#define SRM_DI1_DW_GEN_5__EMPTY                 0x1F040674,0x00000000
#define SRM_DI1_DW_GEN_5__FULL                  0x1F040674,0xffffffff
#define SRM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5     0x1F040674,0xFF000000
#define SRM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1F040674,0x00FF0000
#define SRM_DI1_DW_GEN_5__DI1_CST_5             0x1F040674,0x0000C000
#define SRM_DI1_DW_GEN_5__DI1_PT_6_5            0x1F040674,0x00003000
#define SRM_DI1_DW_GEN_5__DI1_PT_5_5            0x1F040674,0x00000C00
#define SRM_DI1_DW_GEN_5__DI1_PT_4_5            0x1F040674,0x00000300
#define SRM_DI1_DW_GEN_5__DI1_PT_3_5            0x1F040674,0x000000C0
#define SRM_DI1_DW_GEN_5__DI1_PT_2_5            0x1F040674,0x00000030
#define SRM_DI1_DW_GEN_5__DI1_PT_1_5            0x1F040674,0x0000000C
#define SRM_DI1_DW_GEN_5__DI1_PT_0_5            0x1F040674,0x00000003

#define SRM_DI1_DW_GEN_5__ADDR                    0x1F040674
#define SRM_DI1_DW_GEN_5__EMPTY                   0x1F040674,0x00000000
#define SRM_DI1_DW_GEN_5__FULL                    0x1F040674,0xffffffff
#define SRM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5     0x1F040674,0xFF000000
#define SRM_DI1_DW_GEN_5__DI1_START_PERIOD_5      0x1F040674,0x00FF0000
#define SRM_DI1_DW_GEN_5__DI1_CST_5               0x1F040674,0x0000C000
#define SRM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1F040674,0x000001F0
#define SRM_DI1_DW_GEN_5__DI1_SERIAL_RS_5         0x1F040674,0x0000000C
#define SRM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5        0x1F040674,0x00000003

#define SRM_DI1_DW_GEN_6__ADDR                  0x1F040678
#define SRM_DI1_DW_GEN_6__EMPTY                 0x1F040678,0x00000000
#define SRM_DI1_DW_GEN_6__FULL                  0x1F040678,0xffffffff
#define SRM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6     0x1F040678,0xFF000000
#define SRM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1F040678,0x00FF0000
#define SRM_DI1_DW_GEN_6__DI1_CST_6             0x1F040678,0x0000C000
#define SRM_DI1_DW_GEN_6__DI1_PT_6_6            0x1F040678,0x00003000
#define SRM_DI1_DW_GEN_6__DI1_PT_5_6            0x1F040678,0x00000C00
#define SRM_DI1_DW_GEN_6__DI1_PT_4_6            0x1F040678,0x00000300
#define SRM_DI1_DW_GEN_6__DI1_PT_3_6            0x1F040678,0x000000C0
#define SRM_DI1_DW_GEN_6__DI1_PT_2_6            0x1F040678,0x00000030
#define SRM_DI1_DW_GEN_6__DI1_PT_1_6            0x1F040678,0x0000000C
#define SRM_DI1_DW_GEN_6__DI1_PT_0_6            0x1F040678,0x00000003

#define SRM_DI1_DW_GEN_6__ADDR                    0x1F040678
#define SRM_DI1_DW_GEN_6__EMPTY                   0x1F040678,0x00000000
#define SRM_DI1_DW_GEN_6__FULL                    0x1F040678,0xffffffff
#define SRM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6     0x1F040678,0xFF000000
#define SRM_DI1_DW_GEN_6__DI1_START_PERIOD_6      0x1F040678,0x00FF0000
#define SRM_DI1_DW_GEN_6__DI1_CST_6               0x1F040678,0x0000C000
#define SRM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1F040678,0x000001F0
#define SRM_DI1_DW_GEN_6__DI1_SERIAL_RS_6         0x1F040678,0x0000000C
#define SRM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6        0x1F040678,0x00000003

#define SRM_DI1_DW_GEN_7__ADDR                  0x1F04067C
#define SRM_DI1_DW_GEN_7__EMPTY                 0x1F04067C,0x00000000
#define SRM_DI1_DW_GEN_7__FULL                  0x1F04067C,0xffffffff
#define SRM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7     0x1F04067C,0xFF000000
#define SRM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1F04067C,0x00FF0000
#define SRM_DI1_DW_GEN_7__DI1_CST_7             0x1F04067C,0x0000C000
#define SRM_DI1_DW_GEN_7__DI1_PT_6_7            0x1F04067C,0x00003000
#define SRM_DI1_DW_GEN_7__DI1_PT_5_7            0x1F04067C,0x00000C00
#define SRM_DI1_DW_GEN_7__DI1_PT_4_7            0x1F04067C,0x00000300
#define SRM_DI1_DW_GEN_7__DI1_PT_3_7            0x1F04067C,0x000000C0
#define SRM_DI1_DW_GEN_7__DI1_PT_2_7            0x1F04067C,0x00000030
#define SRM_DI1_DW_GEN_7__DI1_PT_1_7            0x1F04067C,0x0000000C
#define SRM_DI1_DW_GEN_7__DI1_PT_0_7            0x1F04067C,0x00000003

#define SRM_DI1_DW_GEN_7__ADDR                    0x1F04067C
#define SRM_DI1_DW_GEN_7__EMPTY                   0x1F04067C,0x00000000
#define SRM_DI1_DW_GEN_7__FULL                    0x1F04067C,0xffffffff
#define SRM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7     0x1F04067C,0xFF000000
#define SRM_DI1_DW_GEN_7__DI1_START_PERIOD_7      0x1F04067C,0x00FF0000
#define SRM_DI1_DW_GEN_7__DI1_CST_7               0x1F04067C,0x0000C000
#define SRM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1F04067C,0x000001F0
#define SRM_DI1_DW_GEN_7__DI1_SERIAL_RS_7         0x1F04067C,0x0000000C
#define SRM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7        0x1F04067C,0x00000003

#define SRM_DI1_DW_GEN_8__ADDR                  0x1F040680
#define SRM_DI1_DW_GEN_8__EMPTY                 0x1F040680,0x00000000
#define SRM_DI1_DW_GEN_8__FULL                  0x1F040680,0xffffffff
#define SRM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8     0x1F040680,0xFF000000
#define SRM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1F040680,0x00FF0000
#define SRM_DI1_DW_GEN_8__DI1_CST_8             0x1F040680,0x0000C000
#define SRM_DI1_DW_GEN_8__DI1_PT_6_8            0x1F040680,0x00003000
#define SRM_DI1_DW_GEN_8__DI1_PT_5_8            0x1F040680,0x00000C00
#define SRM_DI1_DW_GEN_8__DI1_PT_4_8            0x1F040680,0x00000300
#define SRM_DI1_DW_GEN_8__DI1_PT_3_8            0x1F040680,0x000000C0
#define SRM_DI1_DW_GEN_8__DI1_PT_2_8            0x1F040680,0x00000030
#define SRM_DI1_DW_GEN_8__DI1_PT_1_8            0x1F040680,0x0000000C
#define SRM_DI1_DW_GEN_8__DI1_PT_0_8            0x1F040680,0x00000003

#define SRM_DI1_DW_GEN_8__ADDR                    0x1F040680
#define SRM_DI1_DW_GEN_8__EMPTY                   0x1F040680,0x00000000
#define SRM_DI1_DW_GEN_8__FULL                    0x1F040680,0xffffffff
#define SRM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8     0x1F040680,0xFF000000
#define SRM_DI1_DW_GEN_8__DI1_START_PERIOD_8      0x1F040680,0x00FF0000
#define SRM_DI1_DW_GEN_8__DI1_CST_8               0x1F040680,0x0000C000
#define SRM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1F040680,0x000001F0
#define SRM_DI1_DW_GEN_8__DI1_SERIAL_RS_8         0x1F040680,0x0000000C
#define SRM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8        0x1F040680,0x00000003

#define SRM_DI1_DW_GEN_9__ADDR                  0x1F040684
#define SRM_DI1_DW_GEN_9__EMPTY                 0x1F040684,0x00000000
#define SRM_DI1_DW_GEN_9__FULL                  0x1F040684,0xffffffff
#define SRM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9     0x1F040684,0xFF000000
#define SRM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1F040684,0x00FF0000
#define SRM_DI1_DW_GEN_9__DI1_CST_9             0x1F040684,0x0000C000
#define SRM_DI1_DW_GEN_9__DI1_PT_6_9            0x1F040684,0x00003000
#define SRM_DI1_DW_GEN_9__DI1_PT_5_9            0x1F040684,0x00000C00
#define SRM_DI1_DW_GEN_9__DI1_PT_4_9            0x1F040684,0x00000300
#define SRM_DI1_DW_GEN_9__DI1_PT_3_9            0x1F040684,0x000000C0
#define SRM_DI1_DW_GEN_9__DI1_PT_2_9            0x1F040684,0x00000030
#define SRM_DI1_DW_GEN_9__DI1_PT_1_9            0x1F040684,0x0000000C
#define SRM_DI1_DW_GEN_9__DI1_PT_0_9            0x1F040684,0x00000003

#define SRM_DI1_DW_GEN_9__ADDR                    0x1F040684
#define SRM_DI1_DW_GEN_9__EMPTY                   0x1F040684,0x00000000
#define SRM_DI1_DW_GEN_9__FULL                    0x1F040684,0xffffffff
#define SRM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9     0x1F040684,0xFF000000
#define SRM_DI1_DW_GEN_9__DI1_START_PERIOD_9      0x1F040684,0x00FF0000
#define SRM_DI1_DW_GEN_9__DI1_CST_9               0x1F040684,0x0000C000
#define SRM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1F040684,0x000001F0
#define SRM_DI1_DW_GEN_9__DI1_SERIAL_RS_9         0x1F040684,0x0000000C
#define SRM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9        0x1F040684,0x00000003

#define SRM_DI1_DW_GEN_10__ADDR                   0x1F040688
#define SRM_DI1_DW_GEN_10__EMPTY                  0x1F040688,0x00000000
#define SRM_DI1_DW_GEN_10__FULL                   0x1F040688,0xffffffff
#define SRM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10     0x1F040688,0xFF000000
#define SRM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1F040688,0x00FF0000
#define SRM_DI1_DW_GEN_10__DI1_CST_10             0x1F040688,0x0000C000
#define SRM_DI1_DW_GEN_10__DI1_PT_6_10            0x1F040688,0x00003000
#define SRM_DI1_DW_GEN_10__DI1_PT_5_10            0x1F040688,0x00000C00
#define SRM_DI1_DW_GEN_10__DI1_PT_4_10            0x1F040688,0x00000300
#define SRM_DI1_DW_GEN_10__DI1_PT_3_10            0x1F040688,0x000000C0
#define SRM_DI1_DW_GEN_10__DI1_PT_2_10            0x1F040688,0x00000030
#define SRM_DI1_DW_GEN_10__DI1_PT_1_10            0x1F040688,0x0000000C
#define SRM_DI1_DW_GEN_10__DI1_PT_0_10            0x1F040688,0x00000003

#define SRM_DI1_DW_GEN_10__ADDR                     0x1F040688
#define SRM_DI1_DW_GEN_10__EMPTY                    0x1F040688,0x00000000
#define SRM_DI1_DW_GEN_10__FULL                     0x1F040688,0xffffffff
#define SRM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10     0x1F040688,0xFF000000
#define SRM_DI1_DW_GEN_10__DI1_START_PERIOD_10      0x1F040688,0x00FF0000
#define SRM_DI1_DW_GEN_10__DI1_CST_10               0x1F040688,0x0000C000
#define SRM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F040688,0x000001F0
#define SRM_DI1_DW_GEN_10__DI1_SERIAL_RS_10         0x1F040688,0x0000000C
#define SRM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10        0x1F040688,0x00000003

#define SRM_DI1_DW_GEN_11__ADDR                   0x1F04068C
#define SRM_DI1_DW_GEN_11__EMPTY                  0x1F04068C,0x00000000
#define SRM_DI1_DW_GEN_11__FULL                   0x1F04068C,0xffffffff
#define SRM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11     0x1F04068C,0xFF000000
#define SRM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1F04068C,0x00FF0000
#define SRM_DI1_DW_GEN_11__DI1_CST_11             0x1F04068C,0x0000C000
#define SRM_DI1_DW_GEN_11__DI1_PT_6_11            0x1F04068C,0x00003000
#define SRM_DI1_DW_GEN_11__DI1_PT_5_11            0x1F04068C,0x00000C00
#define SRM_DI1_DW_GEN_11__DI1_PT_4_11            0x1F04068C,0x00000300
#define SRM_DI1_DW_GEN_11__DI1_PT_3_11            0x1F04068C,0x000000C0
#define SRM_DI1_DW_GEN_11__DI1_PT_2_11            0x1F04068C,0x00000030
#define SRM_DI1_DW_GEN_11__DI1_PT_1_11            0x1F04068C,0x0000000C
#define SRM_DI1_DW_GEN_11__DI1_PT_0_11            0x1F04068C,0x00000003

#define SRM_DI1_DW_GEN_11__ADDR                     0x1F04068C
#define SRM_DI1_DW_GEN_11__EMPTY                    0x1F04068C,0x00000000
#define SRM_DI1_DW_GEN_11__FULL                     0x1F04068C,0xffffffff
#define SRM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11     0x1F04068C,0xFF000000
#define SRM_DI1_DW_GEN_11__DI1_START_PERIOD_11      0x1F04068C,0x00FF0000
#define SRM_DI1_DW_GEN_11__DI1_CST_11               0x1F04068C,0x0000C000
#define SRM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F04068C,0x000001F0
#define SRM_DI1_DW_GEN_11__DI1_SERIAL_RS_11         0x1F04068C,0x0000000C
#define SRM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11        0x1F04068C,0x00000003

#define SRM_DI1_DW_SET0_0__ADDR                   0x1F040690
#define SRM_DI1_DW_SET0_0__EMPTY       0x1F040690,0x00000000
#define SRM_DI1_DW_SET0_0__FULL       0x1F040690,0xffffffff
#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0       0x1F040690,0x01FF0000
#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0       0x1F040690,0x000001FF

#define SRM_DI1_DW_SET0_1__ADDR                   0x1F040694
#define SRM_DI1_DW_SET0_1__EMPTY       0x1F040694,0x00000000
#define SRM_DI1_DW_SET0_1__FULL       0x1F040694,0xffffffff
#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1       0x1F040694,0x01FF0000
#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1       0x1F040694,0x000001FF

#define SRM_DI1_DW_SET0_2__ADDR                   0x1F040698
#define SRM_DI1_DW_SET0_2__EMPTY       0x1F040698,0x00000000
#define SRM_DI1_DW_SET0_2__FULL       0x1F040698,0xffffffff
#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2       0x1F040698,0x01FF0000
#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2       0x1F040698,0x000001FF

#define SRM_DI1_DW_SET0_3__ADDR                   0x1F04069C
#define SRM_DI1_DW_SET0_3__EMPTY       0x1F04069C,0x00000000
#define SRM_DI1_DW_SET0_3__FULL       0x1F04069C,0xffffffff
#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3       0x1F04069C,0x01FF0000
#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3       0x1F04069C,0x000001FF

#define SRM_DI1_DW_SET0_4__ADDR                   0x1F0406A0
#define SRM_DI1_DW_SET0_4__EMPTY       0x1F0406A0,0x00000000
#define SRM_DI1_DW_SET0_4__FULL       0x1F0406A0,0xffffffff
#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4       0x1F0406A0,0x01FF0000
#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4       0x1F0406A0,0x000001FF

#define SRM_DI1_DW_SET0_5__ADDR                   0x1F0406A4
#define SRM_DI1_DW_SET0_5__EMPTY       0x1F0406A4,0x00000000
#define SRM_DI1_DW_SET0_5__FULL       0x1F0406A4,0xffffffff
#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5       0x1F0406A4,0x01FF0000
#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5       0x1F0406A4,0x000001FF

#define SRM_DI1_DW_SET0_6__ADDR                   0x1F0406A8
#define SRM_DI1_DW_SET0_6__EMPTY       0x1F0406A8,0x00000000
#define SRM_DI1_DW_SET0_6__FULL       0x1F0406A8,0xffffffff
#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6       0x1F0406A8,0x01FF0000
#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6       0x1F0406A8,0x000001FF

#define SRM_DI1_DW_SET0_7__ADDR                   0x1F0406AC
#define SRM_DI1_DW_SET0_7__EMPTY       0x1F0406AC,0x00000000
#define SRM_DI1_DW_SET0_7__FULL       0x1F0406AC,0xffffffff
#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7       0x1F0406AC,0x01FF0000
#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7       0x1F0406AC,0x000001FF

#define SRM_DI1_DW_SET0_8__ADDR                   0x1F0406B0
#define SRM_DI1_DW_SET0_8__EMPTY       0x1F0406B0,0x00000000
#define SRM_DI1_DW_SET0_8__FULL       0x1F0406B0,0xffffffff
#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8       0x1F0406B0,0x01FF0000
#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8       0x1F0406B0,0x000001FF

#define SRM_DI1_DW_SET0_9__ADDR                   0x1F0406B4
#define SRM_DI1_DW_SET0_9__EMPTY       0x1F0406B4,0x00000000
#define SRM_DI1_DW_SET0_9__FULL       0x1F0406B4,0xffffffff
#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9       0x1F0406B4,0x01FF0000
#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9       0x1F0406B4,0x000001FF

#define SRM_DI1_DW_SET0_10__ADDR                   0x1F0406B8
#define SRM_DI1_DW_SET0_10__EMPTY       0x1F0406B8,0x00000000
#define SRM_DI1_DW_SET0_10__FULL       0x1F0406B8,0xffffffff
#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10       0x1F0406B8,0x01FF0000
#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10       0x1F0406B8,0x000001FF

#define SRM_DI1_DW_SET0_11__ADDR                   0x1F0406BC
#define SRM_DI1_DW_SET0_11__EMPTY       0x1F0406BC,0x00000000
#define SRM_DI1_DW_SET0_11__FULL       0x1F0406BC,0xffffffff
#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11       0x1F0406BC,0x01FF0000
#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11       0x1F0406BC,0x000001FF

#define SRM_DI1_DW_SET1_0__ADDR                   0x1F0406C0
#define SRM_DI1_DW_SET1_0__EMPTY       0x1F0406C0,0x00000000
#define SRM_DI1_DW_SET1_0__FULL       0x1F0406C0,0xffffffff
#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0       0x1F0406C0,0x01FF0000
#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0       0x1F0406C0,0x000001FF

#define SRM_DI1_DW_SET1_1__ADDR                   0x1F0406C4
#define SRM_DI1_DW_SET1_1__EMPTY       0x1F0406C4,0x00000000
#define SRM_DI1_DW_SET1_1__FULL       0x1F0406C4,0xffffffff
#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1       0x1F0406C4,0x01FF0000
#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1       0x1F0406C4,0x000001FF

#define SRM_DI1_DW_SET1_2__ADDR                   0x1F0406C8
#define SRM_DI1_DW_SET1_2__EMPTY       0x1F0406C8,0x00000000
#define SRM_DI1_DW_SET1_2__FULL       0x1F0406C8,0xffffffff
#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2       0x1F0406C8,0x01FF0000
#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2       0x1F0406C8,0x000001FF

#define SRM_DI1_DW_SET1_3__ADDR                   0x1F0406CC
#define SRM_DI1_DW_SET1_3__EMPTY       0x1F0406CC,0x00000000
#define SRM_DI1_DW_SET1_3__FULL       0x1F0406CC,0xffffffff
#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3       0x1F0406CC,0x01FF0000
#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3       0x1F0406CC,0x000001FF

#define SRM_DI1_DW_SET1_4__ADDR                   0x1F0406D0
#define SRM_DI1_DW_SET1_4__EMPTY       0x1F0406D0,0x00000000
#define SRM_DI1_DW_SET1_4__FULL       0x1F0406D0,0xffffffff
#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4       0x1F0406D0,0x01FF0000
#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4       0x1F0406D0,0x000001FF

#define SRM_DI1_DW_SET1_5__ADDR                   0x1F0406D4
#define SRM_DI1_DW_SET1_5__EMPTY       0x1F0406D4,0x00000000
#define SRM_DI1_DW_SET1_5__FULL       0x1F0406D4,0xffffffff
#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5       0x1F0406D4,0x01FF0000
#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5       0x1F0406D4,0x000001FF

#define SRM_DI1_DW_SET1_6__ADDR                   0x1F0406D8
#define SRM_DI1_DW_SET1_6__EMPTY       0x1F0406D8,0x00000000
#define SRM_DI1_DW_SET1_6__FULL       0x1F0406D8,0xffffffff
#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6       0x1F0406D8,0x01FF0000
#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6       0x1F0406D8,0x000001FF

#define SRM_DI1_DW_SET1_7__ADDR                   0x1F0406DC
#define SRM_DI1_DW_SET1_7__EMPTY       0x1F0406DC,0x00000000
#define SRM_DI1_DW_SET1_7__FULL       0x1F0406DC,0xffffffff
#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7       0x1F0406DC,0x01FF0000
#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7       0x1F0406DC,0x000001FF

#define SRM_DI1_DW_SET1_8__ADDR                   0x1F0406E0
#define SRM_DI1_DW_SET1_8__EMPTY       0x1F0406E0,0x00000000
#define SRM_DI1_DW_SET1_8__FULL       0x1F0406E0,0xffffffff
#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8       0x1F0406E0,0x01FF0000
#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8       0x1F0406E0,0x000001FF

#define SRM_DI1_DW_SET1_9__ADDR                   0x1F0406E4
#define SRM_DI1_DW_SET1_9__EMPTY       0x1F0406E4,0x00000000
#define SRM_DI1_DW_SET1_9__FULL       0x1F0406E4,0xffffffff
#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9       0x1F0406E4,0x01FF0000
#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9       0x1F0406E4,0x000001FF

#define SRM_DI1_DW_SET1_10__ADDR                   0x1F0406E8
#define SRM_DI1_DW_SET1_10__EMPTY       0x1F0406E8,0x00000000
#define SRM_DI1_DW_SET1_10__FULL       0x1F0406E8,0xffffffff
#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10       0x1F0406E8,0x01FF0000
#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10       0x1F0406E8,0x000001FF

#define SRM_DI1_DW_SET1_11__ADDR                   0x1F0406EC
#define SRM_DI1_DW_SET1_11__EMPTY       0x1F0406EC,0x00000000
#define SRM_DI1_DW_SET1_11__FULL       0x1F0406EC,0xffffffff
#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11       0x1F0406EC,0x01FF0000
#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11       0x1F0406EC,0x000001FF

#define SRM_DI1_DW_SET2_0__ADDR                   0x1F0406F0
#define SRM_DI1_DW_SET2_0__EMPTY       0x1F0406F0,0x00000000
#define SRM_DI1_DW_SET2_0__FULL       0x1F0406F0,0xffffffff
#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0       0x1F0406F0,0x01FF0000
#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0       0x1F0406F0,0x000001FF

#define SRM_DI1_DW_SET2_1__ADDR                   0x1F0406F4
#define SRM_DI1_DW_SET2_1__EMPTY       0x1F0406F4,0x00000000
#define SRM_DI1_DW_SET2_1__FULL       0x1F0406F4,0xffffffff
#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1       0x1F0406F4,0x01FF0000
#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1       0x1F0406F4,0x000001FF

#define SRM_DI1_DW_SET2_2__ADDR                   0x1F0406F8
#define SRM_DI1_DW_SET2_2__EMPTY       0x1F0406F8,0x00000000
#define SRM_DI1_DW_SET2_2__FULL       0x1F0406F8,0xffffffff
#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2       0x1F0406F8,0x01FF0000
#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2       0x1F0406F8,0x000001FF

#define SRM_DI1_DW_SET2_3__ADDR                   0x1F0406FC
#define SRM_DI1_DW_SET2_3__EMPTY       0x1F0406FC,0x00000000
#define SRM_DI1_DW_SET2_3__FULL       0x1F0406FC,0xffffffff
#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3       0x1F0406FC,0x01FF0000
#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3       0x1F0406FC,0x000001FF

#define SRM_DI1_DW_SET2_4__ADDR                   0x1F040700
#define SRM_DI1_DW_SET2_4__EMPTY       0x1F040700,0x00000000
#define SRM_DI1_DW_SET2_4__FULL       0x1F040700,0xffffffff
#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4       0x1F040700,0x01FF0000
#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4       0x1F040700,0x000001FF

#define SRM_DI1_DW_SET2_5__ADDR                   0x1F040704
#define SRM_DI1_DW_SET2_5__EMPTY       0x1F040704,0x00000000
#define SRM_DI1_DW_SET2_5__FULL       0x1F040704,0xffffffff
#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5       0x1F040704,0x01FF0000
#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5       0x1F040704,0x000001FF

#define SRM_DI1_DW_SET2_6__ADDR                   0x1F040708
#define SRM_DI1_DW_SET2_6__EMPTY       0x1F040708,0x00000000
#define SRM_DI1_DW_SET2_6__FULL       0x1F040708,0xffffffff
#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6       0x1F040708,0x01FF0000
#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6       0x1F040708,0x000001FF

#define SRM_DI1_DW_SET2_7__ADDR                   0x1F04070C
#define SRM_DI1_DW_SET2_7__EMPTY       0x1F04070C,0x00000000
#define SRM_DI1_DW_SET2_7__FULL       0x1F04070C,0xffffffff
#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7       0x1F04070C,0x01FF0000
#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7       0x1F04070C,0x000001FF

#define SRM_DI1_DW_SET2_8__ADDR                   0x1F040710
#define SRM_DI1_DW_SET2_8__EMPTY       0x1F040710,0x00000000
#define SRM_DI1_DW_SET2_8__FULL       0x1F040710,0xffffffff
#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8       0x1F040710,0x01FF0000
#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8       0x1F040710,0x000001FF

#define SRM_DI1_DW_SET2_9__ADDR                   0x1F040714
#define SRM_DI1_DW_SET2_9__EMPTY       0x1F040714,0x00000000
#define SRM_DI1_DW_SET2_9__FULL       0x1F040714,0xffffffff
#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9       0x1F040714,0x01FF0000
#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9       0x1F040714,0x000001FF

#define SRM_DI1_DW_SET2_10__ADDR                   0x1F040718
#define SRM_DI1_DW_SET2_10__EMPTY       0x1F040718,0x00000000
#define SRM_DI1_DW_SET2_10__FULL       0x1F040718,0xffffffff
#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10       0x1F040718,0x01FF0000
#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10       0x1F040718,0x000001FF

#define SRM_DI1_DW_SET2_11__ADDR                   0x1F04071C
#define SRM_DI1_DW_SET2_11__EMPTY       0x1F04071C,0x00000000
#define SRM_DI1_DW_SET2_11__FULL       0x1F04071C,0xffffffff
#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11       0x1F04071C,0x01FF0000
#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11       0x1F04071C,0x000001FF

#define SRM_DI1_DW_SET3_0__ADDR                   0x1F040720
#define SRM_DI1_DW_SET3_0__EMPTY       0x1F040720,0x00000000
#define SRM_DI1_DW_SET3_0__FULL       0x1F040720,0xffffffff
#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0       0x1F040720,0x01FF0000
#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0       0x1F040720,0x000001FF

#define SRM_DI1_DW_SET3_1__ADDR                   0x1F040724
#define SRM_DI1_DW_SET3_1__EMPTY       0x1F040724,0x00000000
#define SRM_DI1_DW_SET3_1__FULL       0x1F040724,0xffffffff
#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1       0x1F040724,0x01FF0000
#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1       0x1F040724,0x000001FF

#define SRM_DI1_DW_SET3_2__ADDR                   0x1F040728
#define SRM_DI1_DW_SET3_2__EMPTY       0x1F040728,0x00000000
#define SRM_DI1_DW_SET3_2__FULL       0x1F040728,0xffffffff
#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2       0x1F040728,0x01FF0000
#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2       0x1F040728,0x000001FF

#define SRM_DI1_DW_SET3_3__ADDR                   0x1F04072C
#define SRM_DI1_DW_SET3_3__EMPTY       0x1F04072C,0x00000000
#define SRM_DI1_DW_SET3_3__FULL       0x1F04072C,0xffffffff
#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3       0x1F04072C,0x01FF0000
#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3       0x1F04072C,0x000001FF

#define SRM_DI1_DW_SET3_4__ADDR                   0x1F040730
#define SRM_DI1_DW_SET3_4__EMPTY       0x1F040730,0x00000000
#define SRM_DI1_DW_SET3_4__FULL       0x1F040730,0xffffffff
#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4       0x1F040730,0x01FF0000
#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4       0x1F040730,0x000001FF

#define SRM_DI1_DW_SET3_5__ADDR                   0x1F040734
#define SRM_DI1_DW_SET3_5__EMPTY       0x1F040734,0x00000000
#define SRM_DI1_DW_SET3_5__FULL       0x1F040734,0xffffffff
#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5       0x1F040734,0x01FF0000
#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5       0x1F040734,0x000001FF

#define SRM_DI1_DW_SET3_6__ADDR                   0x1F040738
#define SRM_DI1_DW_SET3_6__EMPTY       0x1F040738,0x00000000
#define SRM_DI1_DW_SET3_6__FULL       0x1F040738,0xffffffff
#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6       0x1F040738,0x01FF0000
#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6       0x1F040738,0x000001FF

#define SRM_DI1_DW_SET3_7__ADDR                   0x1F04073C
#define SRM_DI1_DW_SET3_7__EMPTY       0x1F04073C,0x00000000
#define SRM_DI1_DW_SET3_7__FULL       0x1F04073C,0xffffffff
#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7       0x1F04073C,0x01FF0000
#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7       0x1F04073C,0x000001FF

#define SRM_DI1_DW_SET3_8__ADDR                   0x1F040740
#define SRM_DI1_DW_SET3_8__EMPTY       0x1F040740,0x00000000
#define SRM_DI1_DW_SET3_8__FULL       0x1F040740,0xffffffff
#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8       0x1F040740,0x01FF0000
#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8       0x1F040740,0x000001FF

#define SRM_DI1_DW_SET3_9__ADDR                   0x1F040744
#define SRM_DI1_DW_SET3_9__EMPTY       0x1F040744,0x00000000
#define SRM_DI1_DW_SET3_9__FULL       0x1F040744,0xffffffff
#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9       0x1F040744,0x01FF0000
#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9       0x1F040744,0x000001FF

#define SRM_DI1_DW_SET3_10__ADDR                   0x1F040748
#define SRM_DI1_DW_SET3_10__EMPTY       0x1F040748,0x00000000
#define SRM_DI1_DW_SET3_10__FULL       0x1F040748,0xffffffff
#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10       0x1F040748,0x01FF0000
#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10       0x1F040748,0x000001FF

#define SRM_DI1_DW_SET3_11__ADDR                   0x1F04074C
#define SRM_DI1_DW_SET3_11__EMPTY       0x1F04074C,0x00000000
#define SRM_DI1_DW_SET3_11__FULL       0x1F04074C,0xffffffff
#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11       0x1F04074C,0x01FF0000
#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11       0x1F04074C,0x000001FF

#define SRM_DI1_STP_REP_1__ADDR                   0x1F040750
#define SRM_DI1_STP_REP_1__EMPTY       0x1F040750,0x00000000
#define SRM_DI1_STP_REP_1__FULL       0x1F040750,0xffffffff
#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_2       0x1F040750,0x0FFF0000
#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_1       0x1F040750,0x00000FFF

#define SRM_DI1_STP_REP_2__ADDR                   0x1F040754
#define SRM_DI1_STP_REP_2__EMPTY       0x1F040754,0x00000000
#define SRM_DI1_STP_REP_2__FULL       0x1F040754,0xffffffff
#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_4       0x1F040754,0x0FFF0000
#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_3       0x1F040754,0x00000FFF

#define SRM_DI1_STP_REP_3__ADDR                   0x1F040758
#define SRM_DI1_STP_REP_3__EMPTY       0x1F040758,0x00000000
#define SRM_DI1_STP_REP_3__FULL       0x1F040758,0xffffffff
#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_6       0x1F040758,0x0FFF0000
#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_5       0x1F040758,0x00000FFF

#define SRM_DI1_STP_REP_4__ADDR                   0x1F04075C
#define SRM_DI1_STP_REP_4__EMPTY       0x1F04075C,0x00000000
#define SRM_DI1_STP_REP_4__FULL       0x1F04075C,0xffffffff
#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_8       0x1F04075C,0x0FFF0000
#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_7       0x1F04075C,0x00000FFF

#define SRM_DI1_STP_REP_9__ADDR                   0x1F040760
#define SRM_DI1_STP_REP_9__EMPTY       0x1F040760,0x00000000
#define SRM_DI1_STP_REP_9__FULL       0x1F040760,0xffffffff
#define SRM_DI1_STP_REP_9__DI1_STEP_REPEAT_9       0x1F040760,0x00000FFF

#define SRM_DI1_SER_CONF__ADDR                   0x1F040764
#define SRM_DI1_SER_CONF__EMPTY       0x1F040764,0x00000000
#define SRM_DI1_SER_CONF__FULL       0x1F040764,0xffffffff
#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1       0x1F040764,0xF0000000
#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0       0x1F040764,0x0F000000
#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1       0x1F040764,0x00F00000
#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0       0x1F040764,0x000F0000
#define SRM_DI1_SER_CONF__DI1_SERIAL_LATCH       0x1F040764,0x0000FF00
#define SRM_DI1_SER_CONF__DI1_LLA_SER_ACCESS       0x1F040764,0x00000020
#define SRM_DI1_SER_CONF__DI1_SER_CLK_POLARITY       0x1F040764,0x00000010
#define SRM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY       0x1F040764,0x00000008
#define SRM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY       0x1F040764,0x00000004
#define SRM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY       0x1F040764,0x00000002
#define SRM_DI1_SER_CONF__DI1_WAIT4SERIAL       0x1F040764,0x00000001

#define SRM_DI1_SSC__ADDR                   0x1F040768
#define SRM_DI1_SSC__EMPTY       0x1F040768,0x00000000
#define SRM_DI1_SSC__FULL       0x1F040768,0xffffffff
#define SRM_DI1_SSC__DI1_PIN17_ERM     0x1F040768,0x00800000
#define SRM_DI1_SSC__DI1_PIN16_ERM     0x1F040768,0x00400000
#define SRM_DI1_SSC__DI1_PIN15_ERM     0x1F040768,0x00200000
#define SRM_DI1_SSC__DI1_PIN14_ERM     0x1F040768,0x00100000
#define SRM_DI1_SSC__DI1_PIN13_ERM     0x1F040768,0x00080000
#define SRM_DI1_SSC__DI1_PIN12_ERM     0x1F040768,0x00040000
#define SRM_DI1_SSC__DI1_PIN11_ERM     0x1F040768,0x00020000
#define SRM_DI1_SSC__DI1_CS_ERM        0x1F040768,0x00010000
#define SRM_DI1_SSC__DI1_WAIT_ON       0x1F040768,0x00000020
#define SRM_DI1_SSC__DI1_BYTE_EN_RD_IN       0x1F040768,0x00000008
#define SRM_DI1_SSC__DI1_BYTE_EN_PNTR       0x1F040768,0x00000007

#define SRM_DI1_POL__ADDR                   0x1F04076C
#define SRM_DI1_POL__EMPTY       0x1F04076C,0x00000000
#define SRM_DI1_POL__FULL       0x1F04076C,0xffffffff
#define SRM_DI1_POL__DI1_WAIT_POLARITY       0x1F04076C,0x04000000
#define SRM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY       0x1F04076C,0x02000000
#define SRM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY       0x1F04076C,0x01000000
#define SRM_DI1_POL__DI1_CS1_DATA_POLARITY       0x1F04076C,0x00800000
#define SRM_DI1_POL__DI1_CS1_POLARITY_17       0x1F04076C,0x00400000
#define SRM_DI1_POL__DI1_CS1_POLARITY_16       0x1F04076C,0x00200000
#define SRM_DI1_POL__DI1_CS1_POLARITY_15       0x1F04076C,0x00100000
#define SRM_DI1_POL__DI1_CS1_POLARITY_14       0x1F04076C,0x00080000
#define SRM_DI1_POL__DI1_CS1_POLARITY_13       0x1F04076C,0x00040000
#define SRM_DI1_POL__DI1_CS1_POLARITY_12       0x1F04076C,0x00020000
#define SRM_DI1_POL__DI1_CS1_POLARITY_11       0x1F04076C,0x00010000
#define SRM_DI1_POL__DI1_CS0_DATA_POLARITY       0x1F04076C,0x00008000
#define SRM_DI1_POL__DI1_CS0_POLARITY_17       0x1F04076C,0x00004000
#define SRM_DI1_POL__DI1_CS0_POLARITY_16       0x1F04076C,0x00002000
#define SRM_DI1_POL__DI1_CS0_POLARITY_15       0x1F04076C,0x00001000
#define SRM_DI1_POL__DI1_CS0_POLARITY_14       0x1F04076C,0x00000800
#define SRM_DI1_POL__DI1_CS0_POLARITY_13       0x1F04076C,0x00000400
#define SRM_DI1_POL__DI1_CS0_POLARITY_12       0x1F04076C,0x00000200
#define SRM_DI1_POL__DI1_CS0_POLARITY_11       0x1F04076C,0x00000100
#define SRM_DI1_POL__DI1_DRDY_DATA_POLARITY       0x1F04076C,0x00000080
#define SRM_DI1_POL__DI1_DRDY_POLARITY_17       0x1F04076C,0x00000040
#define SRM_DI1_POL__DI1_DRDY_POLARITY_16       0x1F04076C,0x00000020
#define SRM_DI1_POL__DI1_DRDY_POLARITY_15       0x1F04076C,0x00000010
#define SRM_DI1_POL__DI1_DRDY_POLARITY_14       0x1F04076C,0x00000008
#define SRM_DI1_POL__DI1_DRDY_POLARITY_13       0x1F04076C,0x00000004
#define SRM_DI1_POL__DI1_DRDY_POLARITY_12       0x1F04076C,0x00000002
#define SRM_DI1_POL__DI1_DRDY_POLARITY_11       0x1F04076C,0x00000001

#define SRM_DI1_AW0__ADDR                   0x1F040770
#define SRM_DI1_AW0__EMPTY       0x1F040770,0x00000000
#define SRM_DI1_AW0__FULL       0x1F040770,0xffffffff
#define SRM_DI1_AW0__DI1_AW_TRIG_SEL       0x1F040770,0xF0000000
#define SRM_DI1_AW0__DI1_AW_HEND       0x1F040770,0x0FFF0000
#define SRM_DI1_AW0__DI1_AW_HCOUNT_SEL       0x1F040770,0x0000F000
#define SRM_DI1_AW0__DI1_AW_HSTART       0x1F040770,0x00000FFF

#define SRM_DI1_AW1__ADDR                   0x1F040774
#define SRM_DI1_AW1__EMPTY       0x1F040774,0x00000000
#define SRM_DI1_AW1__FULL       0x1F040774,0xffffffff
#define SRM_DI1_AW1__DI1_AW_VEND       0x1F040774,0x0FFF0000
#define SRM_DI1_AW1__DI1_AW_VCOUNT_SEL       0x1F040774,0x0000F000
#define SRM_DI1_AW1__DI1_AW_VSTART       0x1F040774,0x00000FFF

#define SRM_DI1_SCR_CONF__ADDR                   0x1F040778
#define SRM_DI1_SCR_CONF__EMPTY       0x1F040778,0x00000000
#define SRM_DI1_SCR_CONF__FULL       0x1F040778,0xffffffff
#define SRM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT       0x1F040778,0x00000FFF

#define SRM_DC_WR_CH_CONF_2__ADDR                   0x1F04045C
#define SRM_DC_WR_CH_CONF_2__EMPTY       0x1F04045C,0x00000000
#define SRM_DC_WR_CH_CONF_2__FULL       0x1F04045C,0xffffffff
#define SRM_DC_WR_CH_CONF_2__PROG_START_TIME_2       0x1F04045C,0x07FF0000
#define SRM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2       0x1F04045C,0x00000100
#define SRM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2       0x1F04045C,0x000000E0
#define SRM_DC_WR_CH_CONF_2__PROG_DISP_ID_2       0x1F04045C,0x00000018
#define SRM_DC_WR_CH_CONF_2__PROG_DI_ID_2       0x1F04045C,0x00000004
#define SRM_DC_WR_CH_CONF_2__W_SIZE_2       0x1F04045C,0x00000003

#define SRM_DC_WR_CH_ADDR_2__ADDR                   0x1F040460
#define SRM_DC_WR_CH_ADDR_2__EMPTY       0x1F040460,0x00000000
#define SRM_DC_WR_CH_ADDR_2__FULL       0x1F040460,0xffffffff
#define SRM_DC_WR_CH_ADDR_2__ST_ADDR_2       0x1F040460,0x1FFFFFFF

#define SRM_DC_RL0_CH_2__ADDR                   0x1F040464
#define SRM_DC_RL0_CH_2__EMPTY       0x1F040464,0x00000000
#define SRM_DC_RL0_CH_2__FULL       0x1F040464,0xffffffff
#define SRM_DC_RL0_CH_2__COD_NL_START_CHAN_2       0x1F040464,0xFF000000
#define SRM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2       0x1F040464,0x000F0000
#define SRM_DC_RL0_CH_2__COD_NF_START_CHAN_2       0x1F040464,0x0000FF00
#define SRM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2       0x1F040464,0x0000000F

#define SRM_DC_RL1_CH_2__ADDR                   0x1F040468
#define SRM_DC_RL1_CH_2__EMPTY       0x1F040468,0x00000000
#define SRM_DC_RL1_CH_2__FULL       0x1F040468,0xffffffff
#define SRM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2       0x1F040468,0xFF000000
#define SRM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2       0x1F040468,0x000F0000
#define SRM_DC_RL1_CH_2__COD_EOF_START_CHAN_2       0x1F040468,0x0000FF00
#define SRM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2       0x1F040468,0x0000000F

#define SRM_DC_RL2_CH_2__ADDR                   0x1F04046C
#define SRM_DC_RL2_CH_2__EMPTY       0x1F04046C,0x00000000
#define SRM_DC_RL2_CH_2__FULL       0x1F04046C,0xffffffff
#define SRM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2       0x1F04046C,0xFF000000
#define SRM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2       0x1F04046C,0x000F0000
#define SRM_DC_RL2_CH_2__COD_EOL_START_CHAN_2       0x1F04046C,0x0000FF00
#define SRM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2       0x1F04046C,0x0000000F

#define SRM_DC_RL3_CH_2__ADDR                   0x1F040470
#define SRM_DC_RL3_CH_2__EMPTY       0x1F040470,0x00000000
#define SRM_DC_RL3_CH_2__FULL       0x1F040470,0xffffffff
#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2       0x1F040470,0xFF000000
#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2       0x1F040470,0x000F0000
#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2       0x1F040470,0x0000FF00
#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2       0x1F040470,0x0000000F

#define SRM_DC_RL4_CH_2__ADDR                   0x1F040474
#define SRM_DC_RL4_CH_2__EMPTY       0x1F040474,0x00000000
#define SRM_DC_RL4_CH_2__FULL       0x1F040474,0xffffffff
#define SRM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2       0x1F040474,0x0000FF00
#define SRM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2       0x1F040474,0x0000000F

#define SRM_DC_WR_CH_CONF_6__ADDR                   0x1F040478
#define SRM_DC_WR_CH_CONF_6__EMPTY       0x1F040478,0x00000000
#define SRM_DC_WR_CH_CONF_6__FULL       0x1F040478,0xffffffff
#define SRM_DC_WR_CH_CONF_6__PROG_START_TIME_6       0x1F040478,0x07FF0000
#define SRM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6       0x1F040478,0x00000100
#define SRM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6       0x1F040478,0x000000E0
#define SRM_DC_WR_CH_CONF_6__PROG_DISP_ID_6       0x1F040478,0x00000018
#define SRM_DC_WR_CH_CONF_6__PROG_DI_ID_6       0x1F040478,0x00000004
#define SRM_DC_WR_CH_CONF_6__W_SIZE_6       0x1F040478,0x00000003

#define SRM_DC_WR_CH_ADDR_6__ADDR                   0x1F04047C
#define SRM_DC_WR_CH_ADDR_6__EMPTY       0x1F04047C,0x00000000
#define SRM_DC_WR_CH_ADDR_6__FULL       0x1F04047C,0xffffffff
#define SRM_DC_WR_CH_ADDR_6__ST_ADDR_6       0x1F04047C,0x1FFFFFFF

#define SRM_DC_RL0_CH_6__ADDR                   0x1F040480
#define SRM_DC_RL0_CH_6__EMPTY       0x1F040480,0x00000000
#define SRM_DC_RL0_CH_6__FULL       0x1F040480,0xffffffff
#define SRM_DC_RL0_CH_6__COD_NL_START_CHAN_6       0x1F040480,0xFF000000
#define SRM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6       0x1F040480,0x000F0000
#define SRM_DC_RL0_CH_6__COD_NF_START_CHAN_6       0x1F040480,0x0000FF00
#define SRM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6       0x1F040480,0x0000000F

#define SRM_DC_RL1_CH_6__ADDR                   0x1F040484
#define SRM_DC_RL1_CH_6__EMPTY       0x1F040484,0x00000000
#define SRM_DC_RL1_CH_6__FULL       0x1F040484,0xffffffff
#define SRM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6       0x1F040484,0xFF000000
#define SRM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6       0x1F040484,0x000F0000
#define SRM_DC_RL1_CH_6__COD_EOF_START_CHAN_6       0x1F040484,0x0000FF00
#define SRM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6       0x1F040484,0x0000000F

#define SRM_DC_RL2_CH_6__ADDR                   0x1F040488
#define SRM_DC_RL2_CH_6__EMPTY       0x1F040488,0x00000000
#define SRM_DC_RL2_CH_6__FULL       0x1F040488,0xffffffff
#define SRM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6       0x1F040488,0xFF000000
#define SRM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6       0x1F040488,0x000F0000
#define SRM_DC_RL2_CH_6__COD_EOL_START_CHAN_6       0x1F040488,0x0000FF00
#define SRM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6       0x1F040488,0x0000000F

#define SRM_DC_RL3_CH_6__ADDR                   0x1F04048C
#define SRM_DC_RL3_CH_6__EMPTY       0x1F04048C,0x00000000
#define SRM_DC_RL3_CH_6__FULL       0x1F04048C,0xffffffff
#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6       0x1F04048C,0xFF000000
#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6       0x1F04048C,0x000F0000
#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6       0x1F04048C,0x0000FF00
#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6       0x1F04048C,0x0000000F

#define SRM_DC_RL4_CH_6__ADDR                   0x1F040490
#define SRM_DC_RL4_CH_6__EMPTY       0x1F040490,0x00000000
#define SRM_DC_RL4_CH_6__FULL       0x1F040490,0xffffffff
#define SRM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6       0x1F040490,0x0000FF00
#define SRM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6       0x1F040490,0x0000000F

#define IPU_MEM_DC_MICROCODE_BASE_ADDR 0x1F080000

#define IPU_ISP_TBPR_0__ADDR                   0x1F0C0000
#define IPU_ISP_TBPR_0__EMPTY       0x1F0C0000,0x00000000
#define IPU_ISP_TBPR_0__FULL        0x1F0C0000,0xffffffff
#define IPU_ISP_TBPR_0__HCB_0       0x1F0C0000,0x0FFF0000
#define IPU_ISP_TBPR_0__VCB_0       0x1F0C0000,0x00000FFF

#define IPU_ISP_TBPR_1__ADDR                   0x1F0C0004
#define IPU_ISP_TBPR_1__EMPTY       0x1F0C0004,0x00000000
#define IPU_ISP_TBPR_1__FULL        0x1F0C0004,0xffffffff
#define IPU_ISP_TBPR_1__HCB_1       0x1F0C0004,0x0FFF0000
#define IPU_ISP_TBPR_1__VCB_1       0x1F0C0004,0x00000FFF

#define IPU_ISP_TBPR_2__ADDR                   0x1F0C0008
#define IPU_ISP_TBPR_2__EMPTY       0x1F0C0008,0x00000000
#define IPU_ISP_TBPR_2__FULL        0x1F0C0008,0xffffffff
#define IPU_ISP_TBPR_2__HCB_2       0x1F0C0008,0x0FFF0000
#define IPU_ISP_TBPR_2__VCB_2       0x1F0C0008,0x00000FFF

#define IPU_ISP_TBPR_3__ADDR                   0x1F0C000C
#define IPU_ISP_TBPR_3__EMPTY       0x1F0C000C,0x00000000
#define IPU_ISP_TBPR_3__FULL        0x1F0C000C,0xffffffff
#define IPU_ISP_TBPR_3__HCB_3       0x1F0C000C,0x0FFF0000
#define IPU_ISP_TBPR_3__VCB_3       0x1F0C000C,0x00000FFF

#define IPU_ISP_TBPR_4__ADDR                   0x1F0C0010
#define IPU_ISP_TBPR_4__EMPTY       0x1F0C0010,0x00000000
#define IPU_ISP_TBPR_4__FULL        0x1F0C0010,0xffffffff
#define IPU_ISP_TBPR_4__HCB_4       0x1F0C0010,0x0FFF0000
#define IPU_ISP_TBPR_4__VCB_4       0x1F0C0010,0x00000FFF

#define IPU_ISP_TBPR_5__ADDR                   0x1F0C0014
#define IPU_ISP_TBPR_5__EMPTY       0x1F0C0014,0x00000000
#define IPU_ISP_TBPR_5__FULL        0x1F0C0014,0xffffffff
#define IPU_ISP_TBPR_5__HCB_5       0x1F0C0014,0x0FFF0000
#define IPU_ISP_TBPR_5__VCB_5       0x1F0C0014,0x00000FFF

#define IPU_ISP_TBPR_6__ADDR                   0x1F0C0018
#define IPU_ISP_TBPR_6__EMPTY       0x1F0C0018,0x00000000
#define IPU_ISP_TBPR_6__FULL        0x1F0C0018,0xffffffff
#define IPU_ISP_TBPR_6__HCB_6       0x1F0C0018,0x0FFF0000
#define IPU_ISP_TBPR_6__VCB_6       0x1F0C0018,0x00000FFF

#define IPU_ISP_TBPR_7__ADDR                   0x1F0C001C
#define IPU_ISP_TBPR_7__EMPTY       0x1F0C001C,0x00000000
#define IPU_ISP_TBPR_7__FULL        0x1F0C001C,0xffffffff
#define IPU_ISP_TBPR_7__HCB_7       0x1F0C001C,0x0FFF0000
#define IPU_ISP_TBPR_7__VCB_7       0x1F0C001C,0x00000FFF

#define IPU_ISP_TBPR_8__ADDR                   0x1F0C0020
#define IPU_ISP_TBPR_8__EMPTY       0x1F0C0020,0x00000000
#define IPU_ISP_TBPR_8__FULL        0x1F0C0020,0xffffffff
#define IPU_ISP_TBPR_8__HCB_8       0x1F0C0020,0x0FFF0000
#define IPU_ISP_TBPR_8__VCB_8       0x1F0C0020,0x00000FFF

#define IPU_ISP_TBPR_9__ADDR                   0x1F0C0024
#define IPU_ISP_TBPR_9__EMPTY       0x1F0C0024,0x00000000
#define IPU_ISP_TBPR_9__FULL        0x1F0C0024,0xffffffff
#define IPU_ISP_TBPR_9__HCB_9       0x1F0C0024,0x0FFF0000
#define IPU_ISP_TBPR_9__VCB_9       0x1F0C0024,0x00000FFF

#define IPU_ISP_TBPR_10__ADDR                   0x1F0C0028
#define IPU_ISP_TBPR_10__EMPTY       0x1F0C0028,0x00000000
#define IPU_ISP_TBPR_10__FULL        0x1F0C0028,0xffffffff
#define IPU_ISP_TBPR_10__HCB_10       0x1F0C0028,0x0FFF0000
#define IPU_ISP_TBPR_10__VCB_10       0x1F0C0028,0x00000FFF

#define IPU_ISP_TBPR_11__ADDR                   0x1F0C002C
#define IPU_ISP_TBPR_11__EMPTY       0x1F0C002C,0x00000000
#define IPU_ISP_TBPR_11__FULL        0x1F0C002C,0xffffffff
#define IPU_ISP_TBPR_11__HCB_11       0x1F0C002C,0x0FFF0000
#define IPU_ISP_TBPR_11__VCB_11       0x1F0C002C,0x00000FFF

#define IPU_ISP_TBPR_12__ADDR                   0x1F0C0030
#define IPU_ISP_TBPR_12__EMPTY       0x1F0C0030,0x00000000
#define IPU_ISP_TBPR_12__FULL        0x1F0C0030,0xffffffff
#define IPU_ISP_TBPR_12__HCB_12       0x1F0C0030,0x0FFF0000
#define IPU_ISP_TBPR_12__VCB_12       0x1F0C0030,0x00000FFF

#define IPU_ISP_TBPR_13__ADDR                   0x1F0C0034
#define IPU_ISP_TBPR_13__EMPTY       0x1F0C0034,0x00000000
#define IPU_ISP_TBPR_13__FULL        0x1F0C0034,0xffffffff
#define IPU_ISP_TBPR_13__HCB_13       0x1F0C0034,0x0FFF0000
#define IPU_ISP_TBPR_13__VCB_13       0x1F0C0034,0x00000FFF

#define IPU_ISP_TBPR_14__ADDR                   0x1F0C0038
#define IPU_ISP_TBPR_14__EMPTY       0x1F0C0038,0x00000000
#define IPU_ISP_TBPR_14__FULL        0x1F0C0038,0xffffffff
#define IPU_ISP_TBPR_14__HCB_14       0x1F0C0038,0x0FFF0000
#define IPU_ISP_TBPR_14__VCB_14       0x1F0C0038,0x00000FFF

#define IPU_ISP_TBPR_15__ADDR                   0x1F0C003C
#define IPU_ISP_TBPR_15__EMPTY       0x1F0C003C,0x00000000
#define IPU_ISP_TBPR_15__FULL        0x1F0C003C,0xffffffff
#define IPU_ISP_TBPR_15__HCB_15       0x1F0C003C,0x0FFF0000
#define IPU_ISP_TBPR_15__VCB_15       0x1F0C003C,0x00000FFF

#define IPU_ISP_TBPR_16__ADDR                   0x1F0C0040
#define IPU_ISP_TBPR_16__EMPTY       0x1F0C0040,0x00000000
#define IPU_ISP_TBPR_16__FULL        0x1F0C0040,0xffffffff
#define IPU_ISP_TBPR_16__HCB_16       0x1F0C0040,0x0FFF0000
#define IPU_ISP_TBPR_16__VCB_16       0x1F0C0040,0x00000FFF

#define IPU_ISP_TBPR_17__ADDR                   0x1F0C0044
#define IPU_ISP_TBPR_17__EMPTY       0x1F0C0044,0x00000000
#define IPU_ISP_TBPR_17__FULL        0x1F0C0044,0xffffffff
#define IPU_ISP_TBPR_17__HCB_17       0x1F0C0044,0x0FFF0000
#define IPU_ISP_TBPR_17__VCB_17       0x1F0C0044,0x00000FFF

#define IPU_ISP_TBPR_18__ADDR                   0x1F0C0048
#define IPU_ISP_TBPR_18__EMPTY       0x1F0C0048,0x00000000
#define IPU_ISP_TBPR_18__FULL        0x1F0C0048,0xffffffff
#define IPU_ISP_TBPR_18__HCB_18       0x1F0C0048,0x0FFF0000
#define IPU_ISP_TBPR_18__VCB_18       0x1F0C0048,0x00000FFF

#define IPU_ISP_TBPR_19__ADDR                   0x1F0C004C
#define IPU_ISP_TBPR_19__EMPTY       0x1F0C004C,0x00000000
#define IPU_ISP_TBPR_19__FULL        0x1F0C004C,0xffffffff
#define IPU_ISP_TBPR_19__HCB_19       0x1F0C004C,0x0FFF0000
#define IPU_ISP_TBPR_19__VCB_19       0x1F0C004C,0x00000FFF

#define IPU_ISP_TBPR_20__ADDR                   0x1F0C0050
#define IPU_ISP_TBPR_20__EMPTY       0x1F0C0050,0x00000000
#define IPU_ISP_TBPR_20__FULL        0x1F0C0050,0xffffffff
#define IPU_ISP_TBPR_20__HCB_20       0x1F0C0050,0x0FFF0000
#define IPU_ISP_TBPR_20__VCB_20       0x1F0C0050,0x00000FFF

#define IPU_ISP_TBPR_21__ADDR                   0x1F0C0054
#define IPU_ISP_TBPR_21__EMPTY       0x1F0C0054,0x00000000
#define IPU_ISP_TBPR_21__FULL        0x1F0C0054,0xffffffff
#define IPU_ISP_TBPR_21__HCB_21       0x1F0C0054,0x0FFF0000
#define IPU_ISP_TBPR_21__VCB_21       0x1F0C0054,0x00000FFF

#define IPU_ISP_TBPR_22__ADDR                   0x1F0C0058
#define IPU_ISP_TBPR_22__EMPTY       0x1F0C0058,0x00000000
#define IPU_ISP_TBPR_22__FULL        0x1F0C0058,0xffffffff
#define IPU_ISP_TBPR_22__HCB_22       0x1F0C0058,0x0FFF0000
#define IPU_ISP_TBPR_22__VCB_22       0x1F0C0058,0x00000FFF

#define IPU_ISP_TBPR_23__ADDR                   0x1F0C005C
#define IPU_ISP_TBPR_23__EMPTY       0x1F0C005C,0x00000000
#define IPU_ISP_TBPR_23__FULL        0x1F0C005C,0xffffffff
#define IPU_ISP_TBPR_23__HCB_23       0x1F0C005C,0x0FFF0000
#define IPU_ISP_TBPR_23__VCB_23       0x1F0C005C,0x00000FFF

#define IPU_ISP_TBPR_24__ADDR                   0x1F0C0060
#define IPU_ISP_TBPR_24__EMPTY       0x1F0C0060,0x00000000
#define IPU_ISP_TBPR_24__FULL        0x1F0C0060,0xffffffff
#define IPU_ISP_TBPR_24__HCB_24       0x1F0C0060,0x0FFF0000
#define IPU_ISP_TBPR_24__VCB_24       0x1F0C0060,0x00000FFF

#define IPU_ISP_TBPR_25__ADDR                   0x1F0C0064
#define IPU_ISP_TBPR_25__EMPTY       0x1F0C0064,0x00000000
#define IPU_ISP_TBPR_25__FULL        0x1F0C0064,0xffffffff
#define IPU_ISP_TBPR_25__HCB_25       0x1F0C0064,0x0FFF0000
#define IPU_ISP_TBPR_25__VCB_25       0x1F0C0064,0x00000FFF

#define IPU_ISP_TBPR_26__ADDR                   0x1F0C0068
#define IPU_ISP_TBPR_26__EMPTY       0x1F0C0068,0x00000000
#define IPU_ISP_TBPR_26__FULL        0x1F0C0068,0xffffffff
#define IPU_ISP_TBPR_26__HCB_26       0x1F0C0068,0x0FFF0000
#define IPU_ISP_TBPR_26__VCB_26       0x1F0C0068,0x00000FFF

#define IPU_ISP_TBPR_27__ADDR                   0x1F0C006C
#define IPU_ISP_TBPR_27__EMPTY       0x1F0C006C,0x00000000
#define IPU_ISP_TBPR_27__FULL        0x1F0C006C,0xffffffff
#define IPU_ISP_TBPR_27__HCB_27       0x1F0C006C,0x0FFF0000
#define IPU_ISP_TBPR_27__VCB_27       0x1F0C006C,0x00000FFF

#define IPU_ISP_TBPR_28__ADDR                   0x1F0C0070
#define IPU_ISP_TBPR_28__EMPTY       0x1F0C0070,0x00000000
#define IPU_ISP_TBPR_28__FULL        0x1F0C0070,0xffffffff
#define IPU_ISP_TBPR_28__HCB_28       0x1F0C0070,0x0FFF0000
#define IPU_ISP_TBPR_28__VCB_28       0x1F0C0070,0x00000FFF

#define IPU_ISP_TBPR_29__ADDR                   0x1F0C0074
#define IPU_ISP_TBPR_29__EMPTY       0x1F0C0074,0x00000000
#define IPU_ISP_TBPR_29__FULL        0x1F0C0074,0xffffffff
#define IPU_ISP_TBPR_29__HCB_29       0x1F0C0074,0x0FFF0000
#define IPU_ISP_TBPR_29__VCB_29       0x1F0C0074,0x00000FFF

#define IPU_ISP_TBPR_30__ADDR                   0x1F0C0078
#define IPU_ISP_TBPR_30__EMPTY       0x1F0C0078,0x00000000
#define IPU_ISP_TBPR_30__FULL        0x1F0C0078,0xffffffff
#define IPU_ISP_TBPR_30__HCB_30       0x1F0C0078,0x0FFF0000
#define IPU_ISP_TBPR_30__VCB_30       0x1F0C0078,0x00000FFF

#define IPU_ISP_TBPR_31__ADDR                   0x1F0C007C
#define IPU_ISP_TBPR_31__EMPTY       0x1F0C007C,0x00000000
#define IPU_ISP_TBPR_31__FULL        0x1F0C007C,0xffffffff
#define IPU_ISP_TBPR_31__HCB_31       0x1F0C007C,0x0FFF0000
#define IPU_ISP_TBPR_31__VCB_31       0x1F0C007C,0x00000FFF

#define IPU_ISP_TBPR_32__ADDR                   0x1F0C0080
#define IPU_ISP_TBPR_32__EMPTY       0x1F0C0080,0x00000000
#define IPU_ISP_TBPR_32__FULL        0x1F0C0080,0xffffffff
#define IPU_ISP_TBPR_32__HCB_32       0x1F0C0080,0x0FFF0000
#define IPU_ISP_TBPR_32__VCB_32       0x1F0C0080,0x00000FFF

#define IPU_ISP_TBPR_33__ADDR                   0x1F0C0084
#define IPU_ISP_TBPR_33__EMPTY       0x1F0C0084,0x00000000
#define IPU_ISP_TBPR_33__FULL        0x1F0C0084,0xffffffff
#define IPU_ISP_TBPR_33__HCB_33       0x1F0C0084,0x0FFF0000
#define IPU_ISP_TBPR_33__VCB_33       0x1F0C0084,0x00000FFF

#define IPU_ISP_TBPR_34__ADDR                   0x1F0C0088
#define IPU_ISP_TBPR_34__EMPTY       0x1F0C0088,0x00000000
#define IPU_ISP_TBPR_34__FULL        0x1F0C0088,0xffffffff
#define IPU_ISP_TBPR_34__HCB_34       0x1F0C0088,0x0FFF0000
#define IPU_ISP_TBPR_34__VCB_34       0x1F0C0088,0x00000FFF

#define IPU_ISP_TBPR_35__ADDR                   0x1F0C008C
#define IPU_ISP_TBPR_35__EMPTY       0x1F0C008C,0x00000000
#define IPU_ISP_TBPR_35__FULL        0x1F0C008C,0xffffffff
#define IPU_ISP_TBPR_35__HCB_35       0x1F0C008C,0x0FFF0000
#define IPU_ISP_TBPR_35__VCB_35       0x1F0C008C,0x00000FFF

#define IPU_ISP_TBPR_36__ADDR                   0x1F0C0090
#define IPU_ISP_TBPR_36__EMPTY       0x1F0C0090,0x00000000
#define IPU_ISP_TBPR_36__FULL        0x1F0C0090,0xffffffff
#define IPU_ISP_TBPR_36__HCB_36       0x1F0C0090,0x0FFF0000
#define IPU_ISP_TBPR_36__VCB_36       0x1F0C0090,0x00000FFF

#define IPU_ISP_TBPR_37__ADDR                   0x1F0C0094
#define IPU_ISP_TBPR_37__EMPTY       0x1F0C0094,0x00000000
#define IPU_ISP_TBPR_37__FULL        0x1F0C0094,0xffffffff
#define IPU_ISP_TBPR_37__HCB_37       0x1F0C0094,0x0FFF0000
#define IPU_ISP_TBPR_37__VCB_37       0x1F0C0094,0x00000FFF

#define IPU_ISP_TBPR_38__ADDR                   0x1F0C0098
#define IPU_ISP_TBPR_38__EMPTY       0x1F0C0098,0x00000000
#define IPU_ISP_TBPR_38__FULL        0x1F0C0098,0xffffffff
#define IPU_ISP_TBPR_38__HCB_38       0x1F0C0098,0x0FFF0000
#define IPU_ISP_TBPR_38__VCB_38       0x1F0C0098,0x00000FFF

#define IPU_ISP_TBPR_39__ADDR                   0x1F0C009C
#define IPU_ISP_TBPR_39__EMPTY       0x1F0C009C,0x00000000
#define IPU_ISP_TBPR_39__FULL        0x1F0C009C,0xffffffff
#define IPU_ISP_TBPR_39__HCB_39       0x1F0C009C,0x0FFF0000
#define IPU_ISP_TBPR_39__VCB_39       0x1F0C009C,0x00000FFF

#define IPU_ISP_TBPR_40__ADDR                   0x1F0C00A0
#define IPU_ISP_TBPR_40__EMPTY       0x1F0C00A0,0x00000000
#define IPU_ISP_TBPR_40__FULL        0x1F0C00A0,0xffffffff
#define IPU_ISP_TBPR_40__HCB_40       0x1F0C00A0,0x0FFF0000
#define IPU_ISP_TBPR_40__VCB_40       0x1F0C00A0,0x00000FFF

#define IPU_ISP_TBPR_41__ADDR                   0x1F0C00A4
#define IPU_ISP_TBPR_41__EMPTY       0x1F0C00A4,0x00000000
#define IPU_ISP_TBPR_41__FULL        0x1F0C00A4,0xffffffff
#define IPU_ISP_TBPR_41__HCB_41       0x1F0C00A4,0x0FFF0000
#define IPU_ISP_TBPR_41__VCB_41       0x1F0C00A4,0x00000FFF

#define IPU_ISP_TBPR_42__ADDR                   0x1F0C00A8
#define IPU_ISP_TBPR_42__EMPTY       0x1F0C00A8,0x00000000
#define IPU_ISP_TBPR_42__FULL        0x1F0C00A8,0xffffffff
#define IPU_ISP_TBPR_42__HCB_42       0x1F0C00A8,0x0FFF0000
#define IPU_ISP_TBPR_42__VCB_42       0x1F0C00A8,0x00000FFF

#define IPU_ISP_TBPR_43__ADDR                   0x1F0C00AC
#define IPU_ISP_TBPR_43__EMPTY       0x1F0C00AC,0x00000000
#define IPU_ISP_TBPR_43__FULL        0x1F0C00AC,0xffffffff
#define IPU_ISP_TBPR_43__HCB_43       0x1F0C00AC,0x0FFF0000
#define IPU_ISP_TBPR_43__VCB_43       0x1F0C00AC,0x00000FFF

#define IPU_ISP_TBPR_44__ADDR                   0x1F0C00B0
#define IPU_ISP_TBPR_44__EMPTY       0x1F0C00B0,0x00000000
#define IPU_ISP_TBPR_44__FULL        0x1F0C00B0,0xffffffff
#define IPU_ISP_TBPR_44__HCB_44       0x1F0C00B0,0x0FFF0000
#define IPU_ISP_TBPR_44__VCB_44       0x1F0C00B0,0x00000FFF

#define IPU_ISP_TBPR_45__ADDR                   0x1F0C00B4
#define IPU_ISP_TBPR_45__EMPTY       0x1F0C00B4,0x00000000
#define IPU_ISP_TBPR_45__FULL        0x1F0C00B4,0xffffffff
#define IPU_ISP_TBPR_45__HCB_45       0x1F0C00B4,0x0FFF0000
#define IPU_ISP_TBPR_45__VCB_45       0x1F0C00B4,0x00000FFF

#define IPU_ISP_TBPR_46__ADDR                   0x1F0C00B8
#define IPU_ISP_TBPR_46__EMPTY       0x1F0C00B8,0x00000000
#define IPU_ISP_TBPR_46__FULL        0x1F0C00B8,0xffffffff
#define IPU_ISP_TBPR_46__HCB_46       0x1F0C00B8,0x0FFF0000
#define IPU_ISP_TBPR_46__VCB_46       0x1F0C00B8,0x00000FFF

#define IPU_ISP_TBPR_47__ADDR                   0x1F0C00BC
#define IPU_ISP_TBPR_47__EMPTY       0x1F0C00BC,0x00000000
#define IPU_ISP_TBPR_47__FULL        0x1F0C00BC,0xffffffff
#define IPU_ISP_TBPR_47__HCB_47       0x1F0C00BC,0x0FFF0000
#define IPU_ISP_TBPR_47__VCB_47       0x1F0C00BC,0x00000FFF

#define IPU_ISP_TBPR_48__ADDR                   0x1F0C00C0
#define IPU_ISP_TBPR_48__EMPTY       0x1F0C00C0,0x00000000
#define IPU_ISP_TBPR_48__FULL        0x1F0C00C0,0xffffffff
#define IPU_ISP_TBPR_48__HCB_48       0x1F0C00C0,0x0FFF0000
#define IPU_ISP_TBPR_48__VCB_48       0x1F0C00C0,0x00000FFF

#define IPU_ISP_TBPR_49__ADDR                   0x1F0C00C4
#define IPU_ISP_TBPR_49__EMPTY       0x1F0C00C4,0x00000000
#define IPU_ISP_TBPR_49__FULL        0x1F0C00C4,0xffffffff
#define IPU_ISP_TBPR_49__HCB_49       0x1F0C00C4,0x0FFF0000
#define IPU_ISP_TBPR_49__VCB_49       0x1F0C00C4,0x00000FFF

#define IPU_ISP_TBPR_50__ADDR                   0x1F0C00C8
#define IPU_ISP_TBPR_50__EMPTY       0x1F0C00C8,0x00000000
#define IPU_ISP_TBPR_50__FULL        0x1F0C00C8,0xffffffff
#define IPU_ISP_TBPR_50__HCB_50       0x1F0C00C8,0x0FFF0000
#define IPU_ISP_TBPR_50__VCB_50       0x1F0C00C8,0x00000FFF

#define IPU_ISP_TBPR_51__ADDR                   0x1F0C00CC
#define IPU_ISP_TBPR_51__EMPTY       0x1F0C00CC,0x00000000
#define IPU_ISP_TBPR_51__FULL        0x1F0C00CC,0xffffffff
#define IPU_ISP_TBPR_51__HCB_51       0x1F0C00CC,0x0FFF0000
#define IPU_ISP_TBPR_51__VCB_51       0x1F0C00CC,0x00000FFF

#define IPU_ISP_TBPR_52__ADDR                   0x1F0C00D0
#define IPU_ISP_TBPR_52__EMPTY       0x1F0C00D0,0x00000000
#define IPU_ISP_TBPR_52__FULL        0x1F0C00D0,0xffffffff
#define IPU_ISP_TBPR_52__HCB_52       0x1F0C00D0,0x0FFF0000
#define IPU_ISP_TBPR_52__VCB_52       0x1F0C00D0,0x00000FFF

#define IPU_ISP_TBPR_53__ADDR                   0x1F0C00D4
#define IPU_ISP_TBPR_53__EMPTY       0x1F0C00D4,0x00000000
#define IPU_ISP_TBPR_53__FULL        0x1F0C00D4,0xffffffff
#define IPU_ISP_TBPR_53__HCB_53       0x1F0C00D4,0x0FFF0000
#define IPU_ISP_TBPR_53__VCB_53       0x1F0C00D4,0x00000FFF

#define IPU_ISP_TBPR_54__ADDR                   0x1F0C00D8
#define IPU_ISP_TBPR_54__EMPTY       0x1F0C00D8,0x00000000
#define IPU_ISP_TBPR_54__FULL        0x1F0C00D8,0xffffffff
#define IPU_ISP_TBPR_54__HCB_54       0x1F0C00D8,0x0FFF0000
#define IPU_ISP_TBPR_54__VCB_54       0x1F0C00D8,0x00000FFF

#define IPU_ISP_TBPR_55__ADDR                   0x1F0C00DC
#define IPU_ISP_TBPR_55__EMPTY       0x1F0C00DC,0x00000000
#define IPU_ISP_TBPR_55__FULL        0x1F0C00DC,0xffffffff
#define IPU_ISP_TBPR_55__HCB_55       0x1F0C00DC,0x0FFF0000
#define IPU_ISP_TBPR_55__VCB_55       0x1F0C00DC,0x00000FFF

#define IPU_ISP_TBPR_56__ADDR                   0x1F0C00E0
#define IPU_ISP_TBPR_56__EMPTY       0x1F0C00E0,0x00000000
#define IPU_ISP_TBPR_56__FULL        0x1F0C00E0,0xffffffff
#define IPU_ISP_TBPR_56__HCB_56       0x1F0C00E0,0x0FFF0000
#define IPU_ISP_TBPR_56__VCB_56       0x1F0C00E0,0x00000FFF

#define IPU_ISP_TBPR_57__ADDR                   0x1F0C00E4
#define IPU_ISP_TBPR_57__EMPTY       0x1F0C00E4,0x00000000
#define IPU_ISP_TBPR_57__FULL        0x1F0C00E4,0xffffffff
#define IPU_ISP_TBPR_57__HCB_57       0x1F0C00E4,0x0FFF0000
#define IPU_ISP_TBPR_57__VCB_57       0x1F0C00E4,0x00000FFF

#define IPU_ISP_TBPR_58__ADDR                   0x1F0C00E8
#define IPU_ISP_TBPR_58__EMPTY       0x1F0C00E8,0x00000000
#define IPU_ISP_TBPR_58__FULL        0x1F0C00E8,0xffffffff
#define IPU_ISP_TBPR_58__HCB_58       0x1F0C00E8,0x0FFF0000
#define IPU_ISP_TBPR_58__VCB_58       0x1F0C00E8,0x00000FFF

#define IPU_ISP_TBPR_59__ADDR                   0x1F0C00EC
#define IPU_ISP_TBPR_59__EMPTY       0x1F0C00EC,0x00000000
#define IPU_ISP_TBPR_59__FULL        0x1F0C00EC,0xffffffff
#define IPU_ISP_TBPR_59__HCB_59       0x1F0C00EC,0x0FFF0000
#define IPU_ISP_TBPR_59__VCB_59       0x1F0C00EC,0x00000FFF

#define IPU_ISP_TBPR_60__ADDR                   0x1F0C00F0
#define IPU_ISP_TBPR_60__EMPTY       0x1F0C00F0,0x00000000
#define IPU_ISP_TBPR_60__FULL        0x1F0C00F0,0xffffffff
#define IPU_ISP_TBPR_60__HCB_60       0x1F0C00F0,0x0FFF0000
#define IPU_ISP_TBPR_60__VCB_60       0x1F0C00F0,0x00000FFF

#define IPU_ISP_TBPR_61__ADDR                   0x1F0C00F4
#define IPU_ISP_TBPR_61__EMPTY       0x1F0C00F4,0x00000000
#define IPU_ISP_TBPR_61__FULL        0x1F0C00F4,0xffffffff
#define IPU_ISP_TBPR_61__HCB_61       0x1F0C00F4,0x0FFF0000
#define IPU_ISP_TBPR_61__VCB_61       0x1F0C00F4,0x00000FFF

#define IPU_ISP_TBPR_62__ADDR                   0x1F0C00F8
#define IPU_ISP_TBPR_62__EMPTY       0x1F0C00F8,0x00000000
#define IPU_ISP_TBPR_62__FULL        0x1F0C00F8,0xffffffff
#define IPU_ISP_TBPR_62__HCB_62       0x1F0C00F8,0x0FFF0000
#define IPU_ISP_TBPR_62__VCB_62       0x1F0C00F8,0x00000FFF

#define IPU_ISP_TBPR_63__ADDR                   0x1F0C00FC
#define IPU_ISP_TBPR_63__EMPTY       0x1F0C00FC,0x00000000
#define IPU_ISP_TBPR_63__FULL        0x1F0C00FC,0xffffffff
#define IPU_ISP_TBPR_63__HCB_63       0x1F0C00FC,0x0FFF0000
#define IPU_ISP_TBPR_63__VCB_63       0x1F0C00FC,0x00000FFF

#define SRM_ISP_TBPR_0__ADDR                   0x1F0C0100
#define SRM_ISP_TBPR_0__EMPTY       0x1F0C0100,0x00000000
#define SRM_ISP_TBPR_0__FULL        0x1F0C0100,0xffffffff
#define SRM_ISP_TBPR_0__HCB_0       0x1F0C0100,0x0FFF0000
#define SRM_ISP_TBPR_0__VCB_0       0x1F0C0100,0x00000FFF

#define SRM_ISP_TBPR_1__ADDR                   0x1F0C0104
#define SRM_ISP_TBPR_1__EMPTY       0x1F0C0104,0x00000000
#define SRM_ISP_TBPR_1__FULL        0x1F0C0104,0xffffffff
#define SRM_ISP_TBPR_1__HCB_1       0x1F0C0104,0x0FFF0000
#define SRM_ISP_TBPR_1__VCB_1       0x1F0C0104,0x00000FFF

#define SRM_ISP_TBPR_2__ADDR                   0x1F0C0108
#define SRM_ISP_TBPR_2__EMPTY       0x1F0C0108,0x00000000
#define SRM_ISP_TBPR_2__FULL        0x1F0C0108,0xffffffff
#define SRM_ISP_TBPR_2__HCB_2       0x1F0C0108,0x0FFF0000
#define SRM_ISP_TBPR_2__VCB_2       0x1F0C0108,0x00000FFF

#define SRM_ISP_TBPR_3__ADDR                   0x1F0C010C
#define SRM_ISP_TBPR_3__EMPTY       0x1F0C010C,0x00000000
#define SRM_ISP_TBPR_3__FULL        0x1F0C010C,0xffffffff
#define SRM_ISP_TBPR_3__HCB_3       0x1F0C010C,0x0FFF0000
#define SRM_ISP_TBPR_3__VCB_3       0x1F0C010C,0x00000FFF

#define SRM_ISP_TBPR_4__ADDR                   0x1F0C0110
#define SRM_ISP_TBPR_4__EMPTY       0x1F0C0110,0x00000000
#define SRM_ISP_TBPR_4__FULL        0x1F0C0110,0xffffffff
#define SRM_ISP_TBPR_4__HCB_4       0x1F0C0110,0x0FFF0000
#define SRM_ISP_TBPR_4__VCB_4       0x1F0C0110,0x00000FFF

#define SRM_ISP_TBPR_5__ADDR                   0x1F0C0114
#define SRM_ISP_TBPR_5__EMPTY       0x1F0C0114,0x00000000
#define SRM_ISP_TBPR_5__FULL        0x1F0C0114,0xffffffff
#define SRM_ISP_TBPR_5__HCB_5       0x1F0C0114,0x0FFF0000
#define SRM_ISP_TBPR_5__VCB_5       0x1F0C0114,0x00000FFF

#define SRM_ISP_TBPR_6__ADDR                   0x1F0C0118
#define SRM_ISP_TBPR_6__EMPTY       0x1F0C0118,0x00000000
#define SRM_ISP_TBPR_6__FULL        0x1F0C0118,0xffffffff
#define SRM_ISP_TBPR_6__HCB_6       0x1F0C0118,0x0FFF0000
#define SRM_ISP_TBPR_6__VCB_6       0x1F0C0118,0x00000FFF

#define SRM_ISP_TBPR_7__ADDR                   0x1F0C011C
#define SRM_ISP_TBPR_7__EMPTY       0x1F0C011C,0x00000000
#define SRM_ISP_TBPR_7__FULL        0x1F0C011C,0xffffffff
#define SRM_ISP_TBPR_7__HCB_7       0x1F0C011C,0x0FFF0000
#define SRM_ISP_TBPR_7__VCB_7       0x1F0C011C,0x00000FFF

#define SRM_ISP_TBPR_8__ADDR                   0x1F0C0120
#define SRM_ISP_TBPR_8__EMPTY       0x1F0C0120,0x00000000
#define SRM_ISP_TBPR_8__FULL        0x1F0C0120,0xffffffff
#define SRM_ISP_TBPR_8__HCB_8       0x1F0C0120,0x0FFF0000
#define SRM_ISP_TBPR_8__VCB_8       0x1F0C0120,0x00000FFF

#define SRM_ISP_TBPR_9__ADDR                   0x1F0C0124
#define SRM_ISP_TBPR_9__EMPTY       0x1F0C0124,0x00000000
#define SRM_ISP_TBPR_9__FULL        0x1F0C0124,0xffffffff
#define SRM_ISP_TBPR_9__HCB_9       0x1F0C0124,0x0FFF0000
#define SRM_ISP_TBPR_9__VCB_9       0x1F0C0124,0x00000FFF

#define SRM_ISP_TBPR_10__ADDR                   0x1F0C0128
#define SRM_ISP_TBPR_10__EMPTY       0x1F0C0128,0x00000000
#define SRM_ISP_TBPR_10__FULL        0x1F0C0128,0xffffffff
#define SRM_ISP_TBPR_10__HCB_10       0x1F0C0128,0x0FFF0000
#define SRM_ISP_TBPR_10__VCB_10       0x1F0C0128,0x00000FFF

#define SRM_ISP_TBPR_11__ADDR                   0x1F0C012C
#define SRM_ISP_TBPR_11__EMPTY       0x1F0C012C,0x00000000
#define SRM_ISP_TBPR_11__FULL        0x1F0C012C,0xffffffff
#define SRM_ISP_TBPR_11__HCB_11       0x1F0C012C,0x0FFF0000
#define SRM_ISP_TBPR_11__VCB_11       0x1F0C012C,0x00000FFF

#define SRM_ISP_TBPR_12__ADDR                   0x1F0C0130
#define SRM_ISP_TBPR_12__EMPTY       0x1F0C0130,0x00000000
#define SRM_ISP_TBPR_12__FULL        0x1F0C0130,0xffffffff
#define SRM_ISP_TBPR_12__HCB_12       0x1F0C0130,0x0FFF0000
#define SRM_ISP_TBPR_12__VCB_12       0x1F0C0130,0x00000FFF

#define SRM_ISP_TBPR_13__ADDR                   0x1F0C0134
#define SRM_ISP_TBPR_13__EMPTY       0x1F0C0134,0x00000000
#define SRM_ISP_TBPR_13__FULL        0x1F0C0134,0xffffffff
#define SRM_ISP_TBPR_13__HCB_13       0x1F0C0134,0x0FFF0000
#define SRM_ISP_TBPR_13__VCB_13       0x1F0C0134,0x00000FFF

#define SRM_ISP_TBPR_14__ADDR                   0x1F0C0138
#define SRM_ISP_TBPR_14__EMPTY       0x1F0C0138,0x00000000
#define SRM_ISP_TBPR_14__FULL        0x1F0C0138,0xffffffff
#define SRM_ISP_TBPR_14__HCB_14       0x1F0C0138,0x0FFF0000
#define SRM_ISP_TBPR_14__VCB_14       0x1F0C0138,0x00000FFF

#define SRM_ISP_TBPR_15__ADDR                   0x1F0C013C
#define SRM_ISP_TBPR_15__EMPTY       0x1F0C013C,0x00000000
#define SRM_ISP_TBPR_15__FULL        0x1F0C013C,0xffffffff
#define SRM_ISP_TBPR_15__HCB_15       0x1F0C013C,0x0FFF0000
#define SRM_ISP_TBPR_15__VCB_15       0x1F0C013C,0x00000FFF

#define SRM_ISP_TBPR_16__ADDR                   0x1F0C0140
#define SRM_ISP_TBPR_16__EMPTY       0x1F0C0140,0x00000000
#define SRM_ISP_TBPR_16__FULL        0x1F0C0140,0xffffffff
#define SRM_ISP_TBPR_16__HCB_16       0x1F0C0140,0x0FFF0000
#define SRM_ISP_TBPR_16__VCB_16       0x1F0C0140,0x00000FFF

#define SRM_ISP_TBPR_17__ADDR                   0x1F0C0144
#define SRM_ISP_TBPR_17__EMPTY       0x1F0C0144,0x00000000
#define SRM_ISP_TBPR_17__FULL        0x1F0C0144,0xffffffff
#define SRM_ISP_TBPR_17__HCB_17       0x1F0C0144,0x0FFF0000
#define SRM_ISP_TBPR_17__VCB_17       0x1F0C0144,0x00000FFF

#define SRM_ISP_TBPR_18__ADDR                   0x1F0C0148
#define SRM_ISP_TBPR_18__EMPTY       0x1F0C0148,0x00000000
#define SRM_ISP_TBPR_18__FULL        0x1F0C0148,0xffffffff
#define SRM_ISP_TBPR_18__HCB_18       0x1F0C0148,0x0FFF0000
#define SRM_ISP_TBPR_18__VCB_18       0x1F0C0148,0x00000FFF

#define SRM_ISP_TBPR_19__ADDR                   0x1F0C014C
#define SRM_ISP_TBPR_19__EMPTY       0x1F0C014C,0x00000000
#define SRM_ISP_TBPR_19__FULL        0x1F0C014C,0xffffffff
#define SRM_ISP_TBPR_19__HCB_19       0x1F0C014C,0x0FFF0000
#define SRM_ISP_TBPR_19__VCB_19       0x1F0C014C,0x00000FFF

#define SRM_ISP_TBPR_20__ADDR                   0x1F0C0150
#define SRM_ISP_TBPR_20__EMPTY       0x1F0C0150,0x00000000
#define SRM_ISP_TBPR_20__FULL        0x1F0C0150,0xffffffff
#define SRM_ISP_TBPR_20__HCB_20       0x1F0C0150,0x0FFF0000
#define SRM_ISP_TBPR_20__VCB_20       0x1F0C0150,0x00000FFF

#define SRM_ISP_TBPR_21__ADDR                   0x1F0C0154
#define SRM_ISP_TBPR_21__EMPTY       0x1F0C0154,0x00000000
#define SRM_ISP_TBPR_21__FULL        0x1F0C0154,0xffffffff
#define SRM_ISP_TBPR_21__HCB_21       0x1F0C0154,0x0FFF0000
#define SRM_ISP_TBPR_21__VCB_21       0x1F0C0154,0x00000FFF

#define SRM_ISP_TBPR_22__ADDR                   0x1F0C0158
#define SRM_ISP_TBPR_22__EMPTY       0x1F0C0158,0x00000000
#define SRM_ISP_TBPR_22__FULL        0x1F0C0158,0xffffffff
#define SRM_ISP_TBPR_22__HCB_22       0x1F0C0158,0x0FFF0000
#define SRM_ISP_TBPR_22__VCB_22       0x1F0C0158,0x00000FFF

#define SRM_ISP_TBPR_23__ADDR                   0x1F0C015C
#define SRM_ISP_TBPR_23__EMPTY       0x1F0C015C,0x00000000
#define SRM_ISP_TBPR_23__FULL        0x1F0C015C,0xffffffff
#define SRM_ISP_TBPR_23__HCB_23       0x1F0C015C,0x0FFF0000
#define SRM_ISP_TBPR_23__VCB_23       0x1F0C015C,0x00000FFF

#define SRM_ISP_TBPR_24__ADDR                   0x1F0C0160
#define SRM_ISP_TBPR_24__EMPTY       0x1F0C0160,0x00000000
#define SRM_ISP_TBPR_24__FULL        0x1F0C0160,0xffffffff
#define SRM_ISP_TBPR_24__HCB_24       0x1F0C0160,0x0FFF0000
#define SRM_ISP_TBPR_24__VCB_24       0x1F0C0160,0x00000FFF

#define SRM_ISP_TBPR_25__ADDR                   0x1F0C0164
#define SRM_ISP_TBPR_25__EMPTY       0x1F0C0164,0x00000000
#define SRM_ISP_TBPR_25__FULL        0x1F0C0164,0xffffffff
#define SRM_ISP_TBPR_25__HCB_25       0x1F0C0164,0x0FFF0000
#define SRM_ISP_TBPR_25__VCB_25       0x1F0C0164,0x00000FFF

#define SRM_ISP_TBPR_26__ADDR                   0x1F0C0168
#define SRM_ISP_TBPR_26__EMPTY       0x1F0C0168,0x00000000
#define SRM_ISP_TBPR_26__FULL        0x1F0C0168,0xffffffff
#define SRM_ISP_TBPR_26__HCB_26       0x1F0C0168,0x0FFF0000
#define SRM_ISP_TBPR_26__VCB_26       0x1F0C0168,0x00000FFF

#define SRM_ISP_TBPR_27__ADDR                   0x1F0C016C
#define SRM_ISP_TBPR_27__EMPTY       0x1F0C016C,0x00000000
#define SRM_ISP_TBPR_27__FULL        0x1F0C016C,0xffffffff
#define SRM_ISP_TBPR_27__HCB_27       0x1F0C016C,0x0FFF0000
#define SRM_ISP_TBPR_27__VCB_27       0x1F0C016C,0x00000FFF

#define SRM_ISP_TBPR_28__ADDR                   0x1F0C0170
#define SRM_ISP_TBPR_28__EMPTY       0x1F0C0170,0x00000000
#define SRM_ISP_TBPR_28__FULL        0x1F0C0170,0xffffffff
#define SRM_ISP_TBPR_28__HCB_28       0x1F0C0170,0x0FFF0000
#define SRM_ISP_TBPR_28__VCB_28       0x1F0C0170,0x00000FFF

#define SRM_ISP_TBPR_29__ADDR                   0x1F0C0174
#define SRM_ISP_TBPR_29__EMPTY       0x1F0C0174,0x00000000
#define SRM_ISP_TBPR_29__FULL        0x1F0C0174,0xffffffff
#define SRM_ISP_TBPR_29__HCB_29       0x1F0C0174,0x0FFF0000
#define SRM_ISP_TBPR_29__VCB_29       0x1F0C0174,0x00000FFF

#define SRM_ISP_TBPR_30__ADDR                   0x1F0C0178
#define SRM_ISP_TBPR_30__EMPTY       0x1F0C0178,0x00000000
#define SRM_ISP_TBPR_30__FULL        0x1F0C0178,0xffffffff
#define SRM_ISP_TBPR_30__HCB_30       0x1F0C0178,0x0FFF0000
#define SRM_ISP_TBPR_30__VCB_30       0x1F0C0178,0x00000FFF

#define SRM_ISP_TBPR_31__ADDR                   0x1F0C017C
#define SRM_ISP_TBPR_31__EMPTY       0x1F0C017C,0x00000000
#define SRM_ISP_TBPR_31__FULL        0x1F0C017C,0xffffffff
#define SRM_ISP_TBPR_31__HCB_31       0x1F0C017C,0x0FFF0000
#define SRM_ISP_TBPR_31__VCB_31       0x1F0C017C,0x00000FFF

#define SRM_ISP_TBPR_32__ADDR                   0x1F0C0180
#define SRM_ISP_TBPR_32__EMPTY       0x1F0C0180,0x00000000
#define SRM_ISP_TBPR_32__FULL        0x1F0C0180,0xffffffff
#define SRM_ISP_TBPR_32__HCB_32       0x1F0C0180,0x0FFF0000
#define SRM_ISP_TBPR_32__VCB_32       0x1F0C0180,0x00000FFF

#define SRM_ISP_TBPR_33__ADDR                   0x1F0C0184
#define SRM_ISP_TBPR_33__EMPTY       0x1F0C0184,0x00000000
#define SRM_ISP_TBPR_33__FULL        0x1F0C0184,0xffffffff
#define SRM_ISP_TBPR_33__HCB_33       0x1F0C0184,0x0FFF0000
#define SRM_ISP_TBPR_33__VCB_33       0x1F0C0184,0x00000FFF

#define SRM_ISP_TBPR_34__ADDR                   0x1F0C0188
#define SRM_ISP_TBPR_34__EMPTY       0x1F0C0188,0x00000000
#define SRM_ISP_TBPR_34__FULL        0x1F0C0188,0xffffffff
#define SRM_ISP_TBPR_34__HCB_34       0x1F0C0188,0x0FFF0000
#define SRM_ISP_TBPR_34__VCB_34       0x1F0C0188,0x00000FFF

#define SRM_ISP_TBPR_35__ADDR                   0x1F0C018C
#define SRM_ISP_TBPR_35__EMPTY       0x1F0C018C,0x00000000
#define SRM_ISP_TBPR_35__FULL        0x1F0C018C,0xffffffff
#define SRM_ISP_TBPR_35__HCB_35       0x1F0C018C,0x0FFF0000
#define SRM_ISP_TBPR_35__VCB_35       0x1F0C018C,0x00000FFF

#define SRM_ISP_TBPR_36__ADDR                   0x1F0C0190
#define SRM_ISP_TBPR_36__EMPTY       0x1F0C0190,0x00000000
#define SRM_ISP_TBPR_36__FULL        0x1F0C0190,0xffffffff
#define SRM_ISP_TBPR_36__HCB_36       0x1F0C0190,0x0FFF0000
#define SRM_ISP_TBPR_36__VCB_36       0x1F0C0190,0x00000FFF

#define SRM_ISP_TBPR_37__ADDR                   0x1F0C0194
#define SRM_ISP_TBPR_37__EMPTY       0x1F0C0194,0x00000000
#define SRM_ISP_TBPR_37__FULL        0x1F0C0194,0xffffffff
#define SRM_ISP_TBPR_37__HCB_37       0x1F0C0194,0x0FFF0000
#define SRM_ISP_TBPR_37__VCB_37       0x1F0C0194,0x00000FFF

#define SRM_ISP_TBPR_38__ADDR                   0x1F0C0198
#define SRM_ISP_TBPR_38__EMPTY       0x1F0C0198,0x00000000
#define SRM_ISP_TBPR_38__FULL        0x1F0C0198,0xffffffff
#define SRM_ISP_TBPR_38__HCB_38       0x1F0C0198,0x0FFF0000
#define SRM_ISP_TBPR_38__VCB_38       0x1F0C0198,0x00000FFF

#define SRM_ISP_TBPR_39__ADDR                   0x1F0C019C
#define SRM_ISP_TBPR_39__EMPTY       0x1F0C019C,0x00000000
#define SRM_ISP_TBPR_39__FULL        0x1F0C019C,0xffffffff
#define SRM_ISP_TBPR_39__HCB_39       0x1F0C019C,0x0FFF0000
#define SRM_ISP_TBPR_39__VCB_39       0x1F0C019C,0x00000FFF

#define SRM_ISP_TBPR_40__ADDR                   0x1F0C01A0
#define SRM_ISP_TBPR_40__EMPTY       0x1F0C01A0,0x00000000
#define SRM_ISP_TBPR_40__FULL        0x1F0C01A0,0xffffffff
#define SRM_ISP_TBPR_40__HCB_40       0x1F0C01A0,0x0FFF0000
#define SRM_ISP_TBPR_40__VCB_40       0x1F0C01A0,0x00000FFF

#define SRM_ISP_TBPR_41__ADDR                   0x1F0C01A4
#define SRM_ISP_TBPR_41__EMPTY       0x1F0C01A4,0x00000000
#define SRM_ISP_TBPR_41__FULL        0x1F0C01A4,0xffffffff
#define SRM_ISP_TBPR_41__HCB_41       0x1F0C01A4,0x0FFF0000
#define SRM_ISP_TBPR_41__VCB_41       0x1F0C01A4,0x00000FFF

#define SRM_ISP_TBPR_42__ADDR                   0x1F0C01A8
#define SRM_ISP_TBPR_42__EMPTY       0x1F0C01A8,0x00000000
#define SRM_ISP_TBPR_42__FULL        0x1F0C01A8,0xffffffff
#define SRM_ISP_TBPR_42__HCB_42       0x1F0C01A8,0x0FFF0000
#define SRM_ISP_TBPR_42__VCB_42       0x1F0C01A8,0x00000FFF

#define SRM_ISP_TBPR_43__ADDR                   0x1F0C01AC
#define SRM_ISP_TBPR_43__EMPTY       0x1F0C01AC,0x00000000
#define SRM_ISP_TBPR_43__FULL        0x1F0C01AC,0xffffffff
#define SRM_ISP_TBPR_43__HCB_43       0x1F0C01AC,0x0FFF0000
#define SRM_ISP_TBPR_43__VCB_43       0x1F0C01AC,0x00000FFF

#define SRM_ISP_TBPR_44__ADDR                   0x1F0C01B0
#define SRM_ISP_TBPR_44__EMPTY       0x1F0C01B0,0x00000000
#define SRM_ISP_TBPR_44__FULL        0x1F0C01B0,0xffffffff
#define SRM_ISP_TBPR_44__HCB_44       0x1F0C01B0,0x0FFF0000
#define SRM_ISP_TBPR_44__VCB_44       0x1F0C01B0,0x00000FFF

#define SRM_ISP_TBPR_45__ADDR                   0x1F0C01B4
#define SRM_ISP_TBPR_45__EMPTY       0x1F0C01B4,0x00000000
#define SRM_ISP_TBPR_45__FULL        0x1F0C01B4,0xffffffff
#define SRM_ISP_TBPR_45__HCB_45       0x1F0C01B4,0x0FFF0000
#define SRM_ISP_TBPR_45__VCB_45       0x1F0C01B4,0x00000FFF

#define SRM_ISP_TBPR_46__ADDR                   0x1F0C01B8
#define SRM_ISP_TBPR_46__EMPTY       0x1F0C01B8,0x00000000
#define SRM_ISP_TBPR_46__FULL        0x1F0C01B8,0xffffffff
#define SRM_ISP_TBPR_46__HCB_46       0x1F0C01B8,0x0FFF0000
#define SRM_ISP_TBPR_46__VCB_46       0x1F0C01B8,0x00000FFF

#define SRM_ISP_TBPR_47__ADDR                   0x1F0C01BC
#define SRM_ISP_TBPR_47__EMPTY       0x1F0C01BC,0x00000000
#define SRM_ISP_TBPR_47__FULL        0x1F0C01BC,0xffffffff
#define SRM_ISP_TBPR_47__HCB_47       0x1F0C01BC,0x0FFF0000
#define SRM_ISP_TBPR_47__VCB_47       0x1F0C01BC,0x00000FFF

#define SRM_ISP_TBPR_48__ADDR                   0x1F0C01C0
#define SRM_ISP_TBPR_48__EMPTY       0x1F0C01C0,0x00000000
#define SRM_ISP_TBPR_48__FULL        0x1F0C01C0,0xffffffff
#define SRM_ISP_TBPR_48__HCB_48       0x1F0C01C0,0x0FFF0000
#define SRM_ISP_TBPR_48__VCB_48       0x1F0C01C0,0x00000FFF

#define SRM_ISP_TBPR_49__ADDR                   0x1F0C01C4
#define SRM_ISP_TBPR_49__EMPTY       0x1F0C01C4,0x00000000
#define SRM_ISP_TBPR_49__FULL        0x1F0C01C4,0xffffffff
#define SRM_ISP_TBPR_49__HCB_49       0x1F0C01C4,0x0FFF0000
#define SRM_ISP_TBPR_49__VCB_49       0x1F0C01C4,0x00000FFF

#define SRM_ISP_TBPR_50__ADDR                   0x1F0C01C8
#define SRM_ISP_TBPR_50__EMPTY       0x1F0C01C8,0x00000000
#define SRM_ISP_TBPR_50__FULL        0x1F0C01C8,0xffffffff
#define SRM_ISP_TBPR_50__HCB_50       0x1F0C01C8,0x0FFF0000
#define SRM_ISP_TBPR_50__VCB_50       0x1F0C01C8,0x00000FFF

#define SRM_ISP_TBPR_51__ADDR                   0x1F0C01CC
#define SRM_ISP_TBPR_51__EMPTY       0x1F0C01CC,0x00000000
#define SRM_ISP_TBPR_51__FULL        0x1F0C01CC,0xffffffff
#define SRM_ISP_TBPR_51__HCB_51       0x1F0C01CC,0x0FFF0000
#define SRM_ISP_TBPR_51__VCB_51       0x1F0C01CC,0x00000FFF

#define SRM_ISP_TBPR_52__ADDR                   0x1F0C01D0
#define SRM_ISP_TBPR_52__EMPTY       0x1F0C01D0,0x00000000
#define SRM_ISP_TBPR_52__FULL        0x1F0C01D0,0xffffffff
#define SRM_ISP_TBPR_52__HCB_52       0x1F0C01D0,0x0FFF0000
#define SRM_ISP_TBPR_52__VCB_52       0x1F0C01D0,0x00000FFF

#define SRM_ISP_TBPR_53__ADDR                   0x1F0C01D4
#define SRM_ISP_TBPR_53__EMPTY       0x1F0C01D4,0x00000000
#define SRM_ISP_TBPR_53__FULL        0x1F0C01D4,0xffffffff
#define SRM_ISP_TBPR_53__HCB_53       0x1F0C01D4,0x0FFF0000
#define SRM_ISP_TBPR_53__VCB_53       0x1F0C01D4,0x00000FFF

#define SRM_ISP_TBPR_54__ADDR                   0x1F0C01D8
#define SRM_ISP_TBPR_54__EMPTY       0x1F0C01D8,0x00000000
#define SRM_ISP_TBPR_54__FULL        0x1F0C01D8,0xffffffff
#define SRM_ISP_TBPR_54__HCB_54       0x1F0C01D8,0x0FFF0000
#define SRM_ISP_TBPR_54__VCB_54       0x1F0C01D8,0x00000FFF

#define SRM_ISP_TBPR_55__ADDR                   0x1F0C01DC
#define SRM_ISP_TBPR_55__EMPTY       0x1F0C01DC,0x00000000
#define SRM_ISP_TBPR_55__FULL        0x1F0C01DC,0xffffffff
#define SRM_ISP_TBPR_55__HCB_55       0x1F0C01DC,0x0FFF0000
#define SRM_ISP_TBPR_55__VCB_55       0x1F0C01DC,0x00000FFF

#define SRM_ISP_TBPR_56__ADDR                   0x1F0C01E0
#define SRM_ISP_TBPR_56__EMPTY       0x1F0C01E0,0x00000000
#define SRM_ISP_TBPR_56__FULL        0x1F0C01E0,0xffffffff
#define SRM_ISP_TBPR_56__HCB_56       0x1F0C01E0,0x0FFF0000
#define SRM_ISP_TBPR_56__VCB_56       0x1F0C01E0,0x00000FFF

#define SRM_ISP_TBPR_57__ADDR                   0x1F0C01E4
#define SRM_ISP_TBPR_57__EMPTY       0x1F0C01E4,0x00000000
#define SRM_ISP_TBPR_57__FULL        0x1F0C01E4,0xffffffff
#define SRM_ISP_TBPR_57__HCB_57       0x1F0C01E4,0x0FFF0000
#define SRM_ISP_TBPR_57__VCB_57       0x1F0C01E4,0x00000FFF

#define SRM_ISP_TBPR_58__ADDR                   0x1F0C01E8
#define SRM_ISP_TBPR_58__EMPTY       0x1F0C01E8,0x00000000
#define SRM_ISP_TBPR_58__FULL        0x1F0C01E8,0xffffffff
#define SRM_ISP_TBPR_58__HCB_58       0x1F0C01E8,0x0FFF0000
#define SRM_ISP_TBPR_58__VCB_58       0x1F0C01E8,0x00000FFF

#define SRM_ISP_TBPR_59__ADDR                   0x1F0C01EC
#define SRM_ISP_TBPR_59__EMPTY       0x1F0C01EC,0x00000000
#define SRM_ISP_TBPR_59__FULL        0x1F0C01EC,0xffffffff
#define SRM_ISP_TBPR_59__HCB_59       0x1F0C01EC,0x0FFF0000
#define SRM_ISP_TBPR_59__VCB_59       0x1F0C01EC,0x00000FFF

#define SRM_ISP_TBPR_60__ADDR                   0x1F0C01F0
#define SRM_ISP_TBPR_60__EMPTY       0x1F0C01F0,0x00000000
#define SRM_ISP_TBPR_60__FULL        0x1F0C01F0,0xffffffff
#define SRM_ISP_TBPR_60__HCB_60       0x1F0C01F0,0x0FFF0000
#define SRM_ISP_TBPR_60__VCB_60       0x1F0C01F0,0x00000FFF

#define SRM_ISP_TBPR_61__ADDR                   0x1F0C01F4
#define SRM_ISP_TBPR_61__EMPTY       0x1F0C01F4,0x00000000
#define SRM_ISP_TBPR_61__FULL        0x1F0C01F4,0xffffffff
#define SRM_ISP_TBPR_61__HCB_61       0x1F0C01F4,0x0FFF0000
#define SRM_ISP_TBPR_61__VCB_61       0x1F0C01F4,0x00000FFF

#define SRM_ISP_TBPR_62__ADDR                   0x1F0C01F8
#define SRM_ISP_TBPR_62__EMPTY       0x1F0C01F8,0x00000000
#define SRM_ISP_TBPR_62__FULL        0x1F0C01F8,0xffffffff
#define SRM_ISP_TBPR_62__HCB_62       0x1F0C01F8,0x0FFF0000
#define SRM_ISP_TBPR_62__VCB_62       0x1F0C01F8,0x00000FFF

#define SRM_ISP_TBPR_63__ADDR                   0x1F0C01FC
#define SRM_ISP_TBPR_63__EMPTY       0x1F0C01FC,0x00000000
#define SRM_ISP_TBPR_63__FULL        0x1F0C01FC,0xffffffff
#define SRM_ISP_TBPR_63__HCB_63       0x1F0C01FC,0x0FFF0000
#define SRM_ISP_TBPR_63__VCB_63       0x1F0C01FC,0x00000FFF

#define LPM_MEM_DI0_GENERAL__ADDR                   0x1F0402C4
#define LPM_MEM_DI0_GENERAL__EMPTY       0x1F0402C4,0x00000000
#define LPM_MEM_DI0_GENERAL__FULL       0x1F0402C4,0xffffffff
#define LPM_MEM_DI0_GENERAL__DI0_DISP_Y_SEL       0x1F0402C4,0x70000000
#define LPM_MEM_DI0_GENERAL__DI0_CLOCK_STOP_MODE       0x1F0402C4,0x0F000000
#define LPM_MEM_DI0_GENERAL__DI0_DISP_CLOCK_INIT       0x1F0402C4,0x00800000
#define LPM_MEM_DI0_GENERAL__DI0_MASK_SEL       0x1F0402C4,0x00400000
#define LPM_MEM_DI0_GENERAL__DI0_VSYNC_EXT       0x1F0402C4,0x00200000
#define LPM_MEM_DI0_GENERAL__DI0_CLK_EXT       0x1F0402C4,0x00100000
#define LPM_MEM_DI0_GENERAL__DI0_WATCHDOG_MODE       0x1F0402C4,0x000C0000
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_DISP_CLK       0x1F0402C4,0x00020000
#define LPM_MEM_DI0_GENERAL__DI0_SYNC_COUNT_SEL       0x1F0402C4,0x0000F000
#define LPM_MEM_DI0_GENERAL__DI0_ERR_TREATMENT       0x1F0402C4,0x00000800
#define LPM_MEM_DI0_GENERAL__DI0_ERM_VSYNC_SEL     0x1F0402C4,0x00000400
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS1       0x1F0402C4,0x00000200
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS0       0x1F0402C4,0x00000100
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_8       0x1F0402C4,0x00000080
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_7       0x1F0402C4,0x00000040
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_6       0x1F0402C4,0x00000020
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_5       0x1F0402C4,0x00000010
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_4       0x1F0402C4,0x00000008
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_3       0x1F0402C4,0x00000004
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_2       0x1F0402C4,0x00000002
#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_1       0x1F0402C4,0x00000001

#define LPM_MEM_DI0_BS_CLKGEN0__ADDR                   0x1F0402C8
#define LPM_MEM_DI0_BS_CLKGEN0__EMPTY       0x1F0402C8,0x00000000
#define LPM_MEM_DI0_BS_CLKGEN0__FULL       0x1F0402C8,0xffffffff
#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET       0x1F0402C8,0x01FF0000
#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD       0x1F0402C8,0x00000FFF

#define LPM_MEM_DI0_BS_CLKGEN1__ADDR                   0x1F0402CC
#define LPM_MEM_DI0_BS_CLKGEN1__EMPTY       0x1F0402CC,0x00000000
#define LPM_MEM_DI0_BS_CLKGEN1__FULL       0x1F0402CC,0xffffffff
#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN       0x1F0402CC,0x01FF0000
#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP       0x1F0402CC,0x000001FF

#define LPM_MEM_DI0_SW_GEN0_1__ADDR                   0x1F0402D0
#define LPM_MEM_DI0_SW_GEN0_1__EMPTY       0x1F0402D0,0x00000000
#define LPM_MEM_DI0_SW_GEN0_1__FULL       0x1F0402D0,0xffffffff
#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1       0x1F0402D0,0x7FF80000
#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1       0x1F0402D0,0x00070000
#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1       0x1F0402D0,0x00007FF8
#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1       0x1F0402D0,0x00000007

#define LPM_MEM_DI0_SW_GEN0_2__ADDR                   0x1F0402D4
#define LPM_MEM_DI0_SW_GEN0_2__EMPTY       0x1F0402D4,0x00000000
#define LPM_MEM_DI0_SW_GEN0_2__FULL       0x1F0402D4,0xffffffff
#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2       0x1F0402D4,0x7FF80000
#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2       0x1F0402D4,0x00070000
#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2       0x1F0402D4,0x00007FF8
#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2       0x1F0402D4,0x00000007

#define LPM_MEM_DI0_SW_GEN0_3__ADDR                   0x1F0402D8
#define LPM_MEM_DI0_SW_GEN0_3__EMPTY       0x1F0402D8,0x00000000
#define LPM_MEM_DI0_SW_GEN0_3__FULL       0x1F0402D8,0xffffffff
#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3       0x1F0402D8,0x7FF80000
#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3       0x1F0402D8,0x00070000
#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3       0x1F0402D8,0x00007FF8
#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3       0x1F0402D8,0x00000007

#define LPM_MEM_DI0_SW_GEN0_4__ADDR                   0x1F0402DC
#define LPM_MEM_DI0_SW_GEN0_4__EMPTY       0x1F0402DC,0x00000000
#define LPM_MEM_DI0_SW_GEN0_4__FULL       0x1F0402DC,0xffffffff
#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4       0x1F0402DC,0x7FF80000
#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4       0x1F0402DC,0x00070000
#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4       0x1F0402DC,0x00007FF8
#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4       0x1F0402DC,0x00000007

#define LPM_MEM_DI0_SW_GEN0_5__ADDR                   0x1F0402E0
#define LPM_MEM_DI0_SW_GEN0_5__EMPTY       0x1F0402E0,0x00000000
#define LPM_MEM_DI0_SW_GEN0_5__FULL       0x1F0402E0,0xffffffff
#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5       0x1F0402E0,0x7FF80000
#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5       0x1F0402E0,0x00070000
#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5       0x1F0402E0,0x00007FF8
#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5       0x1F0402E0,0x00000007

#define LPM_MEM_DI0_SW_GEN0_6__ADDR                   0x1F0402E4
#define LPM_MEM_DI0_SW_GEN0_6__EMPTY       0x1F0402E4,0x00000000
#define LPM_MEM_DI0_SW_GEN0_6__FULL       0x1F0402E4,0xffffffff
#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6       0x1F0402E4,0x7FF80000
#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6       0x1F0402E4,0x00070000
#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6       0x1F0402E4,0x00007FF8
#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6       0x1F0402E4,0x00000007

#define LPM_MEM_DI0_SW_GEN0_7__ADDR                   0x1F0402E8
#define LPM_MEM_DI0_SW_GEN0_7__EMPTY       0x1F0402E8,0x00000000
#define LPM_MEM_DI0_SW_GEN0_7__FULL       0x1F0402E8,0xffffffff
#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7       0x1F0402E8,0x7FF80000
#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7       0x1F0402E8,0x00070000
#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7       0x1F0402E8,0x00007FF8
#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7       0x1F0402E8,0x00000007

#define LPM_MEM_DI0_SW_GEN0_8__ADDR                   0x1F0402EC
#define LPM_MEM_DI0_SW_GEN0_8__EMPTY       0x1F0402EC,0x00000000
#define LPM_MEM_DI0_SW_GEN0_8__FULL       0x1F0402EC,0xffffffff
#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8       0x1F0402EC,0x7FF80000
#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8       0x1F0402EC,0x00070000
#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8       0x1F0402EC,0x00007FF8
#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8       0x1F0402EC,0x00000007

#define LPM_MEM_DI0_SW_GEN0_9__ADDR                   0x1F0402F0
#define LPM_MEM_DI0_SW_GEN0_9__EMPTY       0x1F0402F0,0x00000000
#define LPM_MEM_DI0_SW_GEN0_9__FULL       0x1F0402F0,0xffffffff
#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9       0x1F0402F0,0x7FF80000
#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9       0x1F0402F0,0x00070000
#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9       0x1F0402F0,0x00007FF8
#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9       0x1F0402F0,0x00000007

#define LPM_MEM_DI0_SW_GEN1_1__ADDR                   0x1F0402F4
#define LPM_MEM_DI0_SW_GEN1_1__EMPTY       0x1F0402F4,0x00000000
#define LPM_MEM_DI0_SW_GEN1_1__FULL       0x1F0402F4,0xffffffff
#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1       0x1F0402F4,0x60000000
#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1       0x1F0402F4,0x10000000
#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1       0x1F0402F4,0x0E000000
#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1       0x1F0402F4,0x01FF0000
#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1       0x1F0402F4,0x00007000
#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1       0x1F0402F4,0x00000E00
#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_UP_1       0x1F0402F4,0x000001FF

#define LPM_MEM_DI0_SW_GEN1_2__ADDR                   0x1F0402F8
#define LPM_MEM_DI0_SW_GEN1_2__EMPTY       0x1F0402F8,0x00000000
#define LPM_MEM_DI0_SW_GEN1_2__FULL       0x1F0402F8,0xffffffff
#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2       0x1F0402F8,0x60000000
#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2       0x1F0402F8,0x10000000
#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2       0x1F0402F8,0x0E000000
#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2       0x1F0402F8,0x01FF0000
#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2       0x1F0402F8,0x00007000
#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2       0x1F0402F8,0x00000E00
#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_UP_2       0x1F0402F8,0x000001FF

#define LPM_MEM_DI0_SW_GEN1_3__ADDR                   0x1F0402FC
#define LPM_MEM_DI0_SW_GEN1_3__EMPTY       0x1F0402FC,0x00000000
#define LPM_MEM_DI0_SW_GEN1_3__FULL       0x1F0402FC,0xffffffff
#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3       0x1F0402FC,0x60000000
#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3       0x1F0402FC,0x10000000
#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3       0x1F0402FC,0x0E000000
#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3       0x1F0402FC,0x01FF0000
#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3       0x1F0402FC,0x00007000
#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3       0x1F0402FC,0x00000E00
#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_UP_3       0x1F0402FC,0x000001FF

#define LPM_MEM_DI0_SW_GEN1_4__ADDR                   0x1F040300
#define LPM_MEM_DI0_SW_GEN1_4__EMPTY       0x1F040300,0x00000000
#define LPM_MEM_DI0_SW_GEN1_4__FULL       0x1F040300,0xffffffff
#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4       0x1F040300,0x60000000
#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4       0x1F040300,0x10000000
#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4       0x1F040300,0x0E000000
#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4       0x1F040300,0x01FF0000
#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4       0x1F040300,0x00007000
#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4       0x1F040300,0x00000E00
#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_UP_4       0x1F040300,0x000001FF

#define LPM_MEM_DI0_SW_GEN1_5__ADDR                   0x1F040304
#define LPM_MEM_DI0_SW_GEN1_5__EMPTY       0x1F040304,0x00000000
#define LPM_MEM_DI0_SW_GEN1_5__FULL       0x1F040304,0xffffffff
#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5       0x1F040304,0x60000000
#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5       0x1F040304,0x10000000
#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5       0x1F040304,0x0E000000
#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5       0x1F040304,0x01FF0000
#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5       0x1F040304,0x00007000
#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5       0x1F040304,0x00000E00
#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_UP_5       0x1F040304,0x000001FF

#define LPM_MEM_DI0_SW_GEN1_6__ADDR                   0x1F040308
#define LPM_MEM_DI0_SW_GEN1_6__EMPTY       0x1F040308,0x00000000
#define LPM_MEM_DI0_SW_GEN1_6__FULL       0x1F040308,0xffffffff
#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6       0x1F040308,0x60000000
#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6       0x1F040308,0x10000000
#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6       0x1F040308,0x0E000000
#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6       0x1F040308,0x01FF0000
#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6       0x1F040308,0x00007000
#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6       0x1F040308,0x00000E00
#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_UP_6       0x1F040308,0x000001FF

#define LPM_MEM_DI0_SW_GEN1_7__ADDR                   0x1F04030C
#define LPM_MEM_DI0_SW_GEN1_7__EMPTY       0x1F04030C,0x00000000
#define LPM_MEM_DI0_SW_GEN1_7__FULL       0x1F04030C,0xffffffff
#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7       0x1F04030C,0x60000000
#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7       0x1F04030C,0x10000000
#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7       0x1F04030C,0x0E000000
#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7       0x1F04030C,0x01FF0000
#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7       0x1F04030C,0x00007000
#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7       0x1F04030C,0x00000E00
#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_UP_7       0x1F04030C,0x000001FF

#define LPM_MEM_DI0_SW_GEN1_8__ADDR                   0x1F040310
#define LPM_MEM_DI0_SW_GEN1_8__EMPTY       0x1F040310,0x00000000
#define LPM_MEM_DI0_SW_GEN1_8__FULL       0x1F040310,0xffffffff
#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8       0x1F040310,0x60000000
#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8       0x1F040310,0x10000000
#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8       0x1F040310,0x0E000000
#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8       0x1F040310,0x01FF0000
#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8       0x1F040310,0x00007000
#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8       0x1F040310,0x00000E00
#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_UP_8       0x1F040310,0x000001FF

#define LPM_MEM_DI0_SW_GEN1_9__ADDR                   0x1F040314
#define LPM_MEM_DI0_SW_GEN1_9__EMPTY       0x1F040314,0x00000000
#define LPM_MEM_DI0_SW_GEN1_9__FULL       0x1F040314,0xffffffff
#define LPM_MEM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9       0x1F040314,0xE0000000
#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9       0x1F040314,0x10000000
#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9       0x1F040314,0x0E000000
#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9       0x1F040314,0x01FF0000
#define LPM_MEM_DI0_SW_GEN1_9__DI0_TAG_SEL_9       0x1F040314,0x00008000
#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_UP_9       0x1F040314,0x000001FF

#define LPM_MEM_DI0_SYNC_AS_GEN__ADDR                   0x1F040318
#define LPM_MEM_DI0_SYNC_AS_GEN__EMPTY       0x1F040318,0x00000000
#define LPM_MEM_DI0_SYNC_AS_GEN__FULL       0x1F040318,0xffffffff
#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN       0x1F040318,0x10000000
#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL       0x1F040318,0x0000E000
#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START       0x1F040318,0x00000FFF

#define LPM_MEM_DI0_DW_GEN_0__ADDR                   0x1F04031C
#define LPM_MEM_DI0_DW_GEN_0__EMPTY       0x1F04031C,0x00000000
#define LPM_MEM_DI0_DW_GEN_0__FULL       0x1F04031C,0xffffffff
#define LPM_MEM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0       0x1F04031C,0xFF000000
#define LPM_MEM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0       0x1F04031C,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0       0x1F04031C,0x0000C000
#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_6_0       0x1F04031C,0x00003000
#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_5_0       0x1F04031C,0x00000C00
#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_4_0       0x1F04031C,0x00000300
#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_3_0       0x1F04031C,0x000000C0
#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_2_0       0x1F04031C,0x00000030
#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_1_0       0x1F04031C,0x0000000C
#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_0_0       0x1F04031C,0x00000003

#define LPM_MEM_DI0_DW_GEN_0__ADDR                   0x1F04031C
#define LPM_MEM_DI0_DW_GEN_0__EMPTY       0x1F04031C,0x00000000
#define LPM_MEM_DI0_DW_GEN_0__FULL       0x1F04031C,0xffffffff
#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0       0x1F04031C,0xFF000000
#define LPM_MEM_DI0_DW_GEN_0__DI0_START_PERIOD_0       0x1F04031C,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0       0x1F04031C,0x0000C000
#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0       0x1F04031C,0x000001F0
#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_RS_0       0x1F04031C,0x0000000C
#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0       0x1F04031C,0x00000003

#define LPM_MEM_DI0_DW_GEN_1__ADDR                   0x1F040320
#define LPM_MEM_DI0_DW_GEN_1__EMPTY       0x1F040320,0x00000000
#define LPM_MEM_DI0_DW_GEN_1__FULL       0x1F040320,0xffffffff
#define LPM_MEM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1       0x1F040320,0xFF000000
#define LPM_MEM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1       0x1F040320,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1       0x1F040320,0x0000C000
#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_6_1       0x1F040320,0x00003000
#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_5_1       0x1F040320,0x00000C00
#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_4_1       0x1F040320,0x00000300
#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_3_1       0x1F040320,0x000000C0
#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_2_1       0x1F040320,0x00000030
#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_1_1       0x1F040320,0x0000000C
#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_0_1       0x1F040320,0x00000003

#define LPM_MEM_DI0_DW_GEN_1__ADDR                   0x1F040320
#define LPM_MEM_DI0_DW_GEN_1__EMPTY       0x1F040320,0x00000000
#define LPM_MEM_DI0_DW_GEN_1__FULL       0x1F040320,0xffffffff
#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1       0x1F040320,0xFF000000
#define LPM_MEM_DI0_DW_GEN_1__DI0_START_PERIOD_1       0x1F040320,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1       0x1F040320,0x0000C000
#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1       0x1F040320,0x000001F0
#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_RS_1       0x1F040320,0x0000000C
#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1       0x1F040320,0x00000003

#define LPM_MEM_DI0_DW_GEN_2__ADDR                   0x1F040324
#define LPM_MEM_DI0_DW_GEN_2__EMPTY       0x1F040324,0x00000000
#define LPM_MEM_DI0_DW_GEN_2__FULL       0x1F040324,0xffffffff
#define LPM_MEM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2       0x1F040324,0xFF000000
#define LPM_MEM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2       0x1F040324,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2       0x1F040324,0x0000C000
#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_6_2       0x1F040324,0x00003000
#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_5_2       0x1F040324,0x00000C00
#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_4_2       0x1F040324,0x00000300
#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_3_2       0x1F040324,0x000000C0
#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_2_2       0x1F040324,0x00000030
#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_1_2       0x1F040324,0x0000000C
#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_0_2       0x1F040324,0x00000003

#define LPM_MEM_DI0_DW_GEN_2__ADDR                   0x1F040324
#define LPM_MEM_DI0_DW_GEN_2__EMPTY       0x1F040324,0x00000000
#define LPM_MEM_DI0_DW_GEN_2__FULL       0x1F040324,0xffffffff
#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2       0x1F040324,0xFF000000
#define LPM_MEM_DI0_DW_GEN_2__DI0_START_PERIOD_2       0x1F040324,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2       0x1F040324,0x0000C000
#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2       0x1F040324,0x000001F0
#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_RS_2       0x1F040324,0x0000000C
#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2       0x1F040324,0x00000003

#define LPM_MEM_DI0_DW_GEN_3__ADDR                   0x1F040328
#define LPM_MEM_DI0_DW_GEN_3__EMPTY       0x1F040328,0x00000000
#define LPM_MEM_DI0_DW_GEN_3__FULL       0x1F040328,0xffffffff
#define LPM_MEM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3       0x1F040328,0xFF000000
#define LPM_MEM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3       0x1F040328,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3       0x1F040328,0x0000C000
#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_6_3       0x1F040328,0x00003000
#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_5_3       0x1F040328,0x00000C00
#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_4_3       0x1F040328,0x00000300
#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_3_3       0x1F040328,0x000000C0
#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_2_3       0x1F040328,0x00000030
#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_1_3       0x1F040328,0x0000000C
#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_0_3       0x1F040328,0x00000003

#define LPM_MEM_DI0_DW_GEN_3__ADDR                   0x1F040328
#define LPM_MEM_DI0_DW_GEN_3__EMPTY       0x1F040328,0x00000000
#define LPM_MEM_DI0_DW_GEN_3__FULL       0x1F040328,0xffffffff
#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3       0x1F040328,0xFF000000
#define LPM_MEM_DI0_DW_GEN_3__DI0_START_PERIOD_3       0x1F040328,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3       0x1F040328,0x0000C000
#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3       0x1F040328,0x000001F0
#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_RS_3       0x1F040328,0x0000000C
#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3       0x1F040328,0x00000003

#define LPM_MEM_DI0_DW_GEN_4__ADDR                   0x1F04032C
#define LPM_MEM_DI0_DW_GEN_4__EMPTY       0x1F04032C,0x00000000
#define LPM_MEM_DI0_DW_GEN_4__FULL       0x1F04032C,0xffffffff
#define LPM_MEM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4       0x1F04032C,0xFF000000
#define LPM_MEM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4       0x1F04032C,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4       0x1F04032C,0x0000C000
#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_6_4       0x1F04032C,0x00003000
#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_5_4       0x1F04032C,0x00000C00
#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_4_4       0x1F04032C,0x00000300
#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_3_4       0x1F04032C,0x000000C0
#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_2_4       0x1F04032C,0x00000030
#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_1_4       0x1F04032C,0x0000000C
#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_0_4       0x1F04032C,0x00000003

#define LPM_MEM_DI0_DW_GEN_4__ADDR                   0x1F04032C
#define LPM_MEM_DI0_DW_GEN_4__EMPTY       0x1F04032C,0x00000000
#define LPM_MEM_DI0_DW_GEN_4__FULL       0x1F04032C,0xffffffff
#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4       0x1F04032C,0xFF000000
#define LPM_MEM_DI0_DW_GEN_4__DI0_START_PERIOD_4       0x1F04032C,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4       0x1F04032C,0x0000C000
#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4       0x1F04032C,0x000001F0
#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_RS_4       0x1F04032C,0x0000000C
#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4       0x1F04032C,0x00000003

#define LPM_MEM_DI0_DW_GEN_5__ADDR                   0x1F040330
#define LPM_MEM_DI0_DW_GEN_5__EMPTY       0x1F040330,0x00000000
#define LPM_MEM_DI0_DW_GEN_5__FULL       0x1F040330,0xffffffff
#define LPM_MEM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5       0x1F040330,0xFF000000
#define LPM_MEM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5       0x1F040330,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5       0x1F040330,0x0000C000
#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_6_5       0x1F040330,0x00003000
#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_5_5       0x1F040330,0x00000C00
#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_4_5       0x1F040330,0x00000300
#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_3_5       0x1F040330,0x000000C0
#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_2_5       0x1F040330,0x00000030
#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_1_5       0x1F040330,0x0000000C
#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_0_5       0x1F040330,0x00000003

#define LPM_MEM_DI0_DW_GEN_5__ADDR                   0x1F040330
#define LPM_MEM_DI0_DW_GEN_5__EMPTY       0x1F040330,0x00000000
#define LPM_MEM_DI0_DW_GEN_5__FULL       0x1F040330,0xffffffff
#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5       0x1F040330,0xFF000000
#define LPM_MEM_DI0_DW_GEN_5__DI0_START_PERIOD_5       0x1F040330,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5       0x1F040330,0x0000C000
#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5       0x1F040330,0x000001F0
#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_RS_5       0x1F040330,0x0000000C
#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5       0x1F040330,0x00000003

#define LPM_MEM_DI0_DW_GEN_6__ADDR                   0x1F040334
#define LPM_MEM_DI0_DW_GEN_6__EMPTY       0x1F040334,0x00000000
#define LPM_MEM_DI0_DW_GEN_6__FULL       0x1F040334,0xffffffff
#define LPM_MEM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6       0x1F040334,0xFF000000
#define LPM_MEM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6       0x1F040334,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6       0x1F040334,0x0000C000
#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_6_6       0x1F040334,0x00003000
#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_5_6       0x1F040334,0x00000C00
#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_4_6       0x1F040334,0x00000300
#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_3_6       0x1F040334,0x000000C0
#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_2_6       0x1F040334,0x00000030
#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_1_6       0x1F040334,0x0000000C
#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_0_6       0x1F040334,0x00000003

#define LPM_MEM_DI0_DW_GEN_6__ADDR                   0x1F040334
#define LPM_MEM_DI0_DW_GEN_6__EMPTY       0x1F040334,0x00000000
#define LPM_MEM_DI0_DW_GEN_6__FULL       0x1F040334,0xffffffff
#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6       0x1F040334,0xFF000000
#define LPM_MEM_DI0_DW_GEN_6__DI0_START_PERIOD_6       0x1F040334,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6       0x1F040334,0x0000C000
#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6       0x1F040334,0x000001F0
#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_RS_6       0x1F040334,0x0000000C
#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6       0x1F040334,0x00000003

#define LPM_MEM_DI0_DW_GEN_7__ADDR                   0x1F040338
#define LPM_MEM_DI0_DW_GEN_7__EMPTY       0x1F040338,0x00000000
#define LPM_MEM_DI0_DW_GEN_7__FULL       0x1F040338,0xffffffff
#define LPM_MEM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7       0x1F040338,0xFF000000
#define LPM_MEM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7       0x1F040338,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7       0x1F040338,0x0000C000
#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_6_7       0x1F040338,0x00003000
#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_5_7       0x1F040338,0x00000C00
#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_4_7       0x1F040338,0x00000300
#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_3_7       0x1F040338,0x000000C0
#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_2_7       0x1F040338,0x00000030
#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_1_7       0x1F040338,0x0000000C
#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_0_7       0x1F040338,0x00000003

#define LPM_MEM_DI0_DW_GEN_7__ADDR                   0x1F040338
#define LPM_MEM_DI0_DW_GEN_7__EMPTY       0x1F040338,0x00000000
#define LPM_MEM_DI0_DW_GEN_7__FULL       0x1F040338,0xffffffff
#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7       0x1F040338,0xFF000000
#define LPM_MEM_DI0_DW_GEN_7__DI0_START_PERIOD_7       0x1F040338,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7       0x1F040338,0x0000C000
#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7       0x1F040338,0x000001F0
#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_RS_7       0x1F040338,0x0000000C
#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7       0x1F040338,0x00000003

#define LPM_MEM_DI0_DW_GEN_8__ADDR                   0x1F04033C
#define LPM_MEM_DI0_DW_GEN_8__EMPTY       0x1F04033C,0x00000000
#define LPM_MEM_DI0_DW_GEN_8__FULL       0x1F04033C,0xffffffff
#define LPM_MEM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8       0x1F04033C,0xFF000000
#define LPM_MEM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8       0x1F04033C,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8       0x1F04033C,0x0000C000
#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_6_8       0x1F04033C,0x00003000
#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_5_8       0x1F04033C,0x00000C00
#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_4_8       0x1F04033C,0x00000300
#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_3_8       0x1F04033C,0x000000C0
#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_2_8       0x1F04033C,0x00000030
#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_1_8       0x1F04033C,0x0000000C
#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_0_8       0x1F04033C,0x00000003

#define LPM_MEM_DI0_DW_GEN_8__ADDR                   0x1F04033C
#define LPM_MEM_DI0_DW_GEN_8__EMPTY       0x1F04033C,0x00000000
#define LPM_MEM_DI0_DW_GEN_8__FULL       0x1F04033C,0xffffffff
#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8       0x1F04033C,0xFF000000
#define LPM_MEM_DI0_DW_GEN_8__DI0_START_PERIOD_8       0x1F04033C,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8       0x1F04033C,0x0000C000
#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8       0x1F04033C,0x000001F0
#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_RS_8       0x1F04033C,0x0000000C
#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8       0x1F04033C,0x00000003

#define LPM_MEM_DI0_DW_GEN_9__ADDR                   0x1F040340
#define LPM_MEM_DI0_DW_GEN_9__EMPTY       0x1F040340,0x00000000
#define LPM_MEM_DI0_DW_GEN_9__FULL       0x1F040340,0xffffffff
#define LPM_MEM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9       0x1F040340,0xFF000000
#define LPM_MEM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9       0x1F040340,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9       0x1F040340,0x0000C000
#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_6_9       0x1F040340,0x00003000
#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_5_9       0x1F040340,0x00000C00
#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_4_9       0x1F040340,0x00000300
#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_3_9       0x1F040340,0x000000C0
#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_2_9       0x1F040340,0x00000030
#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_1_9       0x1F040340,0x0000000C
#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_0_9       0x1F040340,0x00000003

#define LPM_MEM_DI0_DW_GEN_9__ADDR                   0x1F040340
#define LPM_MEM_DI0_DW_GEN_9__EMPTY       0x1F040340,0x00000000
#define LPM_MEM_DI0_DW_GEN_9__FULL       0x1F040340,0xffffffff
#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9       0x1F040340,0xFF000000
#define LPM_MEM_DI0_DW_GEN_9__DI0_START_PERIOD_9       0x1F040340,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9       0x1F040340,0x0000C000
#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9       0x1F040340,0x000001F0
#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_RS_9       0x1F040340,0x0000000C
#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9       0x1F040340,0x00000003

#define LPM_MEM_DI0_DW_GEN_10__ADDR                   0x1F040344
#define LPM_MEM_DI0_DW_GEN_10__EMPTY       0x1F040344,0x00000000
#define LPM_MEM_DI0_DW_GEN_10__FULL       0x1F040344,0xffffffff
#define LPM_MEM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10       0x1F040344,0xFF000000
#define LPM_MEM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10       0x1F040344,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10       0x1F040344,0x0000C000
#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_6_10       0x1F040344,0x00003000
#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_5_10       0x1F040344,0x00000C00
#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_4_10       0x1F040344,0x00000300
#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_3_10       0x1F040344,0x000000C0
#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_2_10       0x1F040344,0x00000030
#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_1_10       0x1F040344,0x0000000C
#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_0_10       0x1F040344,0x00000003

#define LPM_MEM_DI0_DW_GEN_10__ADDR                   0x1F040344
#define LPM_MEM_DI0_DW_GEN_10__EMPTY       0x1F040344,0x00000000
#define LPM_MEM_DI0_DW_GEN_10__FULL       0x1F040344,0xffffffff
#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10       0x1F040344,0xFF000000
#define LPM_MEM_DI0_DW_GEN_10__DI0_START_PERIOD_10       0x1F040344,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10       0x1F040344,0x0000C000
#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10       0x1F040344,0x000001F0
#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_RS_10       0x1F040344,0x0000000C
#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10       0x1F040344,0x00000003

#define LPM_MEM_DI0_DW_GEN_11__ADDR                   0x1F040348
#define LPM_MEM_DI0_DW_GEN_11__EMPTY       0x1F040348,0x00000000
#define LPM_MEM_DI0_DW_GEN_11__FULL       0x1F040348,0xffffffff
#define LPM_MEM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11       0x1F040348,0xFF000000
#define LPM_MEM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11       0x1F040348,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11       0x1F040348,0x0000C000
#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_6_11       0x1F040348,0x00003000
#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_5_11       0x1F040348,0x00000C00
#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_4_11       0x1F040348,0x00000300
#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_3_11       0x1F040348,0x000000C0
#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_2_11       0x1F040348,0x00000030
#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_1_11       0x1F040348,0x0000000C
#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_0_11       0x1F040348,0x00000003

#define LPM_MEM_DI0_DW_GEN_11__ADDR                   0x1F040348
#define LPM_MEM_DI0_DW_GEN_11__EMPTY       0x1F040348,0x00000000
#define LPM_MEM_DI0_DW_GEN_11__FULL       0x1F040348,0xffffffff
#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11       0x1F040348,0xFF000000
#define LPM_MEM_DI0_DW_GEN_11__DI0_START_PERIOD_11       0x1F040348,0x00FF0000
#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11       0x1F040348,0x0000C000
#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11       0x1F040348,0x000001F0
#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_RS_11       0x1F040348,0x0000000C
#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11       0x1F040348,0x00000003

#define LPM_MEM_DI0_DW_SET0_0__ADDR                   0x1F04034C
#define LPM_MEM_DI0_DW_SET0_0__EMPTY       0x1F04034C,0x00000000
#define LPM_MEM_DI0_DW_SET0_0__FULL       0x1F04034C,0xffffffff
#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0       0x1F04034C,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0       0x1F04034C,0x000001FF

#define LPM_MEM_DI0_DW_SET0_1__ADDR                   0x1F040350
#define LPM_MEM_DI0_DW_SET0_1__EMPTY       0x1F040350,0x00000000
#define LPM_MEM_DI0_DW_SET0_1__FULL       0x1F040350,0xffffffff
#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1       0x1F040350,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1       0x1F040350,0x000001FF

#define LPM_MEM_DI0_DW_SET0_2__ADDR                   0x1F040354
#define LPM_MEM_DI0_DW_SET0_2__EMPTY       0x1F040354,0x00000000
#define LPM_MEM_DI0_DW_SET0_2__FULL       0x1F040354,0xffffffff
#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2       0x1F040354,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2       0x1F040354,0x000001FF

#define LPM_MEM_DI0_DW_SET0_3__ADDR                   0x1F040358
#define LPM_MEM_DI0_DW_SET0_3__EMPTY       0x1F040358,0x00000000
#define LPM_MEM_DI0_DW_SET0_3__FULL       0x1F040358,0xffffffff
#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3       0x1F040358,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3       0x1F040358,0x000001FF

#define LPM_MEM_DI0_DW_SET0_4__ADDR                   0x1F04035C
#define LPM_MEM_DI0_DW_SET0_4__EMPTY       0x1F04035C,0x00000000
#define LPM_MEM_DI0_DW_SET0_4__FULL       0x1F04035C,0xffffffff
#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4       0x1F04035C,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4       0x1F04035C,0x000001FF

#define LPM_MEM_DI0_DW_SET0_5__ADDR                   0x1F040360
#define LPM_MEM_DI0_DW_SET0_5__EMPTY       0x1F040360,0x00000000
#define LPM_MEM_DI0_DW_SET0_5__FULL       0x1F040360,0xffffffff
#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5       0x1F040360,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5       0x1F040360,0x000001FF

#define LPM_MEM_DI0_DW_SET0_6__ADDR                   0x1F040364
#define LPM_MEM_DI0_DW_SET0_6__EMPTY       0x1F040364,0x00000000
#define LPM_MEM_DI0_DW_SET0_6__FULL       0x1F040364,0xffffffff
#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6       0x1F040364,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6       0x1F040364,0x000001FF

#define LPM_MEM_DI0_DW_SET0_7__ADDR                   0x1F040368
#define LPM_MEM_DI0_DW_SET0_7__EMPTY       0x1F040368,0x00000000
#define LPM_MEM_DI0_DW_SET0_7__FULL       0x1F040368,0xffffffff
#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7       0x1F040368,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7       0x1F040368,0x000001FF

#define LPM_MEM_DI0_DW_SET0_8__ADDR                   0x1F04036C
#define LPM_MEM_DI0_DW_SET0_8__EMPTY       0x1F04036C,0x00000000
#define LPM_MEM_DI0_DW_SET0_8__FULL       0x1F04036C,0xffffffff
#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8       0x1F04036C,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8       0x1F04036C,0x000001FF

#define LPM_MEM_DI0_DW_SET0_9__ADDR                   0x1F040370
#define LPM_MEM_DI0_DW_SET0_9__EMPTY       0x1F040370,0x00000000
#define LPM_MEM_DI0_DW_SET0_9__FULL       0x1F040370,0xffffffff
#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9       0x1F040370,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9       0x1F040370,0x000001FF

#define LPM_MEM_DI0_DW_SET0_10__ADDR                   0x1F040374
#define LPM_MEM_DI0_DW_SET0_10__EMPTY       0x1F040374,0x00000000
#define LPM_MEM_DI0_DW_SET0_10__FULL       0x1F040374,0xffffffff
#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10       0x1F040374,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10       0x1F040374,0x000001FF

#define LPM_MEM_DI0_DW_SET0_11__ADDR                   0x1F040378
#define LPM_MEM_DI0_DW_SET0_11__EMPTY       0x1F040378,0x00000000
#define LPM_MEM_DI0_DW_SET0_11__FULL       0x1F040378,0xffffffff
#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11       0x1F040378,0x01FF0000
#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11       0x1F040378,0x000001FF

#define LPM_MEM_DI0_DW_SET1_0__ADDR                   0x1F04037C
#define LPM_MEM_DI0_DW_SET1_0__EMPTY       0x1F04037C,0x00000000
#define LPM_MEM_DI0_DW_SET1_0__FULL       0x1F04037C,0xffffffff
#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0       0x1F04037C,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0       0x1F04037C,0x000001FF

#define LPM_MEM_DI0_DW_SET1_1__ADDR                   0x1F040380
#define LPM_MEM_DI0_DW_SET1_1__EMPTY       0x1F040380,0x00000000
#define LPM_MEM_DI0_DW_SET1_1__FULL       0x1F040380,0xffffffff
#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1       0x1F040380,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1       0x1F040380,0x000001FF

#define LPM_MEM_DI0_DW_SET1_2__ADDR                   0x1F040384
#define LPM_MEM_DI0_DW_SET1_2__EMPTY       0x1F040384,0x00000000
#define LPM_MEM_DI0_DW_SET1_2__FULL       0x1F040384,0xffffffff
#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2       0x1F040384,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2       0x1F040384,0x000001FF

#define LPM_MEM_DI0_DW_SET1_3__ADDR                   0x1F040388
#define LPM_MEM_DI0_DW_SET1_3__EMPTY       0x1F040388,0x00000000
#define LPM_MEM_DI0_DW_SET1_3__FULL       0x1F040388,0xffffffff
#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3       0x1F040388,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3       0x1F040388,0x000001FF

#define LPM_MEM_DI0_DW_SET1_4__ADDR                   0x1F04038C
#define LPM_MEM_DI0_DW_SET1_4__EMPTY       0x1F04038C,0x00000000
#define LPM_MEM_DI0_DW_SET1_4__FULL       0x1F04038C,0xffffffff
#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4       0x1F04038C,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4       0x1F04038C,0x000001FF

#define LPM_MEM_DI0_DW_SET1_5__ADDR                   0x1F040390
#define LPM_MEM_DI0_DW_SET1_5__EMPTY       0x1F040390,0x00000000
#define LPM_MEM_DI0_DW_SET1_5__FULL       0x1F040390,0xffffffff
#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5       0x1F040390,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5       0x1F040390,0x000001FF

#define LPM_MEM_DI0_DW_SET1_6__ADDR                   0x1F040394
#define LPM_MEM_DI0_DW_SET1_6__EMPTY       0x1F040394,0x00000000
#define LPM_MEM_DI0_DW_SET1_6__FULL       0x1F040394,0xffffffff
#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6       0x1F040394,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6       0x1F040394,0x000001FF

#define LPM_MEM_DI0_DW_SET1_7__ADDR                   0x1F040398
#define LPM_MEM_DI0_DW_SET1_7__EMPTY       0x1F040398,0x00000000
#define LPM_MEM_DI0_DW_SET1_7__FULL       0x1F040398,0xffffffff
#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7       0x1F040398,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7       0x1F040398,0x000001FF

#define LPM_MEM_DI0_DW_SET1_8__ADDR                   0x1F04039C
#define LPM_MEM_DI0_DW_SET1_8__EMPTY       0x1F04039C,0x00000000
#define LPM_MEM_DI0_DW_SET1_8__FULL       0x1F04039C,0xffffffff
#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8       0x1F04039C,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8       0x1F04039C,0x000001FF

#define LPM_MEM_DI0_DW_SET1_9__ADDR                   0x1F0403A0
#define LPM_MEM_DI0_DW_SET1_9__EMPTY       0x1F0403A0,0x00000000
#define LPM_MEM_DI0_DW_SET1_9__FULL       0x1F0403A0,0xffffffff
#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9       0x1F0403A0,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9       0x1F0403A0,0x000001FF

#define LPM_MEM_DI0_DW_SET1_10__ADDR                   0x1F0403A4
#define LPM_MEM_DI0_DW_SET1_10__EMPTY       0x1F0403A4,0x00000000
#define LPM_MEM_DI0_DW_SET1_10__FULL       0x1F0403A4,0xffffffff
#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10       0x1F0403A4,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10       0x1F0403A4,0x000001FF

#define LPM_MEM_DI0_DW_SET1_11__ADDR                   0x1F0403A8
#define LPM_MEM_DI0_DW_SET1_11__EMPTY       0x1F0403A8,0x00000000
#define LPM_MEM_DI0_DW_SET1_11__FULL       0x1F0403A8,0xffffffff
#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11       0x1F0403A8,0x01FF0000
#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11       0x1F0403A8,0x000001FF

#define LPM_MEM_DI0_DW_SET2_0__ADDR                   0x1F0403AC
#define LPM_MEM_DI0_DW_SET2_0__EMPTY       0x1F0403AC,0x00000000
#define LPM_MEM_DI0_DW_SET2_0__FULL       0x1F0403AC,0xffffffff
#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0       0x1F0403AC,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0       0x1F0403AC,0x000001FF

#define LPM_MEM_DI0_DW_SET2_1__ADDR                   0x1F0403B0
#define LPM_MEM_DI0_DW_SET2_1__EMPTY       0x1F0403B0,0x00000000
#define LPM_MEM_DI0_DW_SET2_1__FULL       0x1F0403B0,0xffffffff
#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1       0x1F0403B0,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1       0x1F0403B0,0x000001FF

#define LPM_MEM_DI0_DW_SET2_2__ADDR                   0x1F0403B4
#define LPM_MEM_DI0_DW_SET2_2__EMPTY       0x1F0403B4,0x00000000
#define LPM_MEM_DI0_DW_SET2_2__FULL       0x1F0403B4,0xffffffff
#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2       0x1F0403B4,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2       0x1F0403B4,0x000001FF

#define LPM_MEM_DI0_DW_SET2_3__ADDR                   0x1F0403B8
#define LPM_MEM_DI0_DW_SET2_3__EMPTY       0x1F0403B8,0x00000000
#define LPM_MEM_DI0_DW_SET2_3__FULL       0x1F0403B8,0xffffffff
#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3       0x1F0403B8,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3       0x1F0403B8,0x000001FF

#define LPM_MEM_DI0_DW_SET2_4__ADDR                   0x1F0403BC
#define LPM_MEM_DI0_DW_SET2_4__EMPTY       0x1F0403BC,0x00000000
#define LPM_MEM_DI0_DW_SET2_4__FULL       0x1F0403BC,0xffffffff
#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4       0x1F0403BC,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4       0x1F0403BC,0x000001FF

#define LPM_MEM_DI0_DW_SET2_5__ADDR                   0x1F0403C0
#define LPM_MEM_DI0_DW_SET2_5__EMPTY       0x1F0403C0,0x00000000
#define LPM_MEM_DI0_DW_SET2_5__FULL       0x1F0403C0,0xffffffff
#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5       0x1F0403C0,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5       0x1F0403C0,0x000001FF

#define LPM_MEM_DI0_DW_SET2_6__ADDR                   0x1F0403C4
#define LPM_MEM_DI0_DW_SET2_6__EMPTY       0x1F0403C4,0x00000000
#define LPM_MEM_DI0_DW_SET2_6__FULL       0x1F0403C4,0xffffffff
#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6       0x1F0403C4,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6       0x1F0403C4,0x000001FF

#define LPM_MEM_DI0_DW_SET2_7__ADDR                   0x1F0403C8
#define LPM_MEM_DI0_DW_SET2_7__EMPTY       0x1F0403C8,0x00000000
#define LPM_MEM_DI0_DW_SET2_7__FULL       0x1F0403C8,0xffffffff
#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7       0x1F0403C8,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7       0x1F0403C8,0x000001FF

#define LPM_MEM_DI0_DW_SET2_8__ADDR                   0x1F0403CC
#define LPM_MEM_DI0_DW_SET2_8__EMPTY       0x1F0403CC,0x00000000
#define LPM_MEM_DI0_DW_SET2_8__FULL       0x1F0403CC,0xffffffff
#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8       0x1F0403CC,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8       0x1F0403CC,0x000001FF

#define LPM_MEM_DI0_DW_SET2_9__ADDR                   0x1F0403D0
#define LPM_MEM_DI0_DW_SET2_9__EMPTY       0x1F0403D0,0x00000000
#define LPM_MEM_DI0_DW_SET2_9__FULL       0x1F0403D0,0xffffffff
#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9       0x1F0403D0,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9       0x1F0403D0,0x000001FF

#define LPM_MEM_DI0_DW_SET2_10__ADDR                   0x1F0403D4
#define LPM_MEM_DI0_DW_SET2_10__EMPTY       0x1F0403D4,0x00000000
#define LPM_MEM_DI0_DW_SET2_10__FULL       0x1F0403D4,0xffffffff
#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10       0x1F0403D4,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10       0x1F0403D4,0x000001FF

#define LPM_MEM_DI0_DW_SET2_11__ADDR                   0x1F0403D8
#define LPM_MEM_DI0_DW_SET2_11__EMPTY       0x1F0403D8,0x00000000
#define LPM_MEM_DI0_DW_SET2_11__FULL       0x1F0403D8,0xffffffff
#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11       0x1F0403D8,0x01FF0000
#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11       0x1F0403D8,0x000001FF

#define LPM_MEM_DI0_DW_SET3_0__ADDR                   0x1F0403DC
#define LPM_MEM_DI0_DW_SET3_0__EMPTY       0x1F0403DC,0x00000000
#define LPM_MEM_DI0_DW_SET3_0__FULL       0x1F0403DC,0xffffffff
#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0       0x1F0403DC,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0       0x1F0403DC,0x000001FF

#define LPM_MEM_DI0_DW_SET3_1__ADDR                   0x1F0403E0
#define LPM_MEM_DI0_DW_SET3_1__EMPTY       0x1F0403E0,0x00000000
#define LPM_MEM_DI0_DW_SET3_1__FULL       0x1F0403E0,0xffffffff
#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1       0x1F0403E0,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1       0x1F0403E0,0x000001FF

#define LPM_MEM_DI0_DW_SET3_2__ADDR                   0x1F0403E4
#define LPM_MEM_DI0_DW_SET3_2__EMPTY       0x1F0403E4,0x00000000
#define LPM_MEM_DI0_DW_SET3_2__FULL       0x1F0403E4,0xffffffff
#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2       0x1F0403E4,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2       0x1F0403E4,0x000001FF

#define LPM_MEM_DI0_DW_SET3_3__ADDR                   0x1F0403E8
#define LPM_MEM_DI0_DW_SET3_3__EMPTY       0x1F0403E8,0x00000000
#define LPM_MEM_DI0_DW_SET3_3__FULL       0x1F0403E8,0xffffffff
#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3       0x1F0403E8,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3       0x1F0403E8,0x000001FF

#define LPM_MEM_DI0_DW_SET3_4__ADDR                   0x1F0403EC
#define LPM_MEM_DI0_DW_SET3_4__EMPTY       0x1F0403EC,0x00000000
#define LPM_MEM_DI0_DW_SET3_4__FULL       0x1F0403EC,0xffffffff
#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4       0x1F0403EC,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4       0x1F0403EC,0x000001FF

#define LPM_MEM_DI0_DW_SET3_5__ADDR                   0x1F0403F0
#define LPM_MEM_DI0_DW_SET3_5__EMPTY       0x1F0403F0,0x00000000
#define LPM_MEM_DI0_DW_SET3_5__FULL       0x1F0403F0,0xffffffff
#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5       0x1F0403F0,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5       0x1F0403F0,0x000001FF

#define LPM_MEM_DI0_DW_SET3_6__ADDR                   0x1F0403F4
#define LPM_MEM_DI0_DW_SET3_6__EMPTY       0x1F0403F4,0x00000000
#define LPM_MEM_DI0_DW_SET3_6__FULL       0x1F0403F4,0xffffffff
#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6       0x1F0403F4,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6       0x1F0403F4,0x000001FF

#define LPM_MEM_DI0_DW_SET3_7__ADDR                   0x1F0403F8
#define LPM_MEM_DI0_DW_SET3_7__EMPTY       0x1F0403F8,0x00000000
#define LPM_MEM_DI0_DW_SET3_7__FULL       0x1F0403F8,0xffffffff
#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7       0x1F0403F8,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7       0x1F0403F8,0x000001FF

#define LPM_MEM_DI0_DW_SET3_8__ADDR                   0x1F0403FC
#define LPM_MEM_DI0_DW_SET3_8__EMPTY       0x1F0403FC,0x00000000
#define LPM_MEM_DI0_DW_SET3_8__FULL       0x1F0403FC,0xffffffff
#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8       0x1F0403FC,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8       0x1F0403FC,0x000001FF

#define LPM_MEM_DI0_DW_SET3_9__ADDR                   0x1F040400
#define LPM_MEM_DI0_DW_SET3_9__EMPTY       0x1F040400,0x00000000
#define LPM_MEM_DI0_DW_SET3_9__FULL       0x1F040400,0xffffffff
#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9       0x1F040400,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9       0x1F040400,0x000001FF

#define LPM_MEM_DI0_DW_SET3_10__ADDR                   0x1F040404
#define LPM_MEM_DI0_DW_SET3_10__EMPTY       0x1F040404,0x00000000
#define LPM_MEM_DI0_DW_SET3_10__FULL       0x1F040404,0xffffffff
#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10       0x1F040404,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10       0x1F040404,0x000001FF

#define LPM_MEM_DI0_DW_SET3_11__ADDR                   0x1F040408
#define LPM_MEM_DI0_DW_SET3_11__EMPTY       0x1F040408,0x00000000
#define LPM_MEM_DI0_DW_SET3_11__FULL       0x1F040408,0xffffffff
#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11       0x1F040408,0x01FF0000
#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11       0x1F040408,0x000001FF

#define LPM_MEM_DI0_STP_REP_1__ADDR                   0x1F04040C
#define LPM_MEM_DI0_STP_REP_1__EMPTY       0x1F04040C,0x00000000
#define LPM_MEM_DI0_STP_REP_1__FULL       0x1F04040C,0xffffffff
#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_2       0x1F04040C,0x0FFF0000
#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_1       0x1F04040C,0x00000FFF

#define LPM_MEM_DI0_STP_REP_2__ADDR                   0x1F040410
#define LPM_MEM_DI0_STP_REP_2__EMPTY       0x1F040410,0x00000000
#define LPM_MEM_DI0_STP_REP_2__FULL       0x1F040410,0xffffffff
#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_4       0x1F040410,0x0FFF0000
#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_3       0x1F040410,0x00000FFF

#define LPM_MEM_DI0_STP_REP_3__ADDR                   0x1F040414
#define LPM_MEM_DI0_STP_REP_3__EMPTY       0x1F040414,0x00000000
#define LPM_MEM_DI0_STP_REP_3__FULL       0x1F040414,0xffffffff
#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_6       0x1F040414,0x0FFF0000
#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_5       0x1F040414,0x00000FFF

#define LPM_MEM_DI0_STP_REP_4__ADDR                   0x1F040418
#define LPM_MEM_DI0_STP_REP_4__EMPTY       0x1F040418,0x00000000
#define LPM_MEM_DI0_STP_REP_4__FULL       0x1F040418,0xffffffff
#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_8       0x1F040418,0x0FFF0000
#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_7       0x1F040418,0x00000FFF

#define LPM_MEM_DI0_STP_REP_9__ADDR                   0x1F04041C
#define LPM_MEM_DI0_STP_REP_9__EMPTY       0x1F04041C,0x00000000
#define LPM_MEM_DI0_STP_REP_9__FULL       0x1F04041C,0xffffffff
#define LPM_MEM_DI0_STP_REP_9__DI0_STEP_REPEAT_9       0x1F04041C,0x00000FFF

#define LPM_MEM_DI0_SER_CONF__ADDR                   0x1F040420
#define LPM_MEM_DI0_SER_CONF__EMPTY       0x1F040420,0x00000000
#define LPM_MEM_DI0_SER_CONF__FULL       0x1F040420,0xffffffff
#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1       0x1F040420,0xF0000000
#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0       0x1F040420,0x0F000000
#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1       0x1F040420,0x00F00000
#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0       0x1F040420,0x000F0000
#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LATCH       0x1F040420,0x0000FF00
#define LPM_MEM_DI0_SER_CONF__DI0_LLA_SER_ACCESS       0x1F040420,0x00000020
#define LPM_MEM_DI0_SER_CONF__DI0_SER_CLK_POLARITY       0x1F040420,0x00000010
#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY       0x1F040420,0x00000008
#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY       0x1F040420,0x00000004
#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY       0x1F040420,0x00000002
#define LPM_MEM_DI0_SER_CONF__DI0_WAIT4SERIAL       0x1F040420,0x00000001

#define LPM_MEM_DI0_SSC__ADDR                   0x1F040424
#define LPM_MEM_DI0_SSC__EMPTY       0x1F040424,0x00000000
#define LPM_MEM_DI0_SSC__FULL       0x1F040424,0xffffffff
#define LPM_MEM_DI0_SSC__DI0_PIN17_ERM       0x1F040424,0x00800000
#define LPM_MEM_DI0_SSC__DI0_PIN16_ERM       0x1F040424,0x00400000
#define LPM_MEM_DI0_SSC__DI0_PIN15_ERM       0x1F040424,0x00200000
#define LPM_MEM_DI0_SSC__DI0_PIN14_ERM       0x1F040424,0x00100000
#define LPM_MEM_DI0_SSC__DI0_PIN13_ERM       0x1F040424,0x00080000
#define LPM_MEM_DI0_SSC__DI0_PIN12_ERM       0x1F040424,0x00040000
#define LPM_MEM_DI0_SSC__DI0_PIN11_ERM       0x1F040424,0x00020000
#define LPM_MEM_DI0_SSC__DI0_CS_ERM       0x1F040424,0x00010000
#define LPM_MEM_DI0_SSC__DI0_WAIT_ON       0x1F040424,0x00000020
#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_RD_IN       0x1F040424,0x00000008
#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_PNTR       0x1F040424,0x00000007

#define LPM_MEM_DI0_POL__ADDR                   0x1F040428
#define LPM_MEM_DI0_POL__EMPTY       0x1F040428,0x00000000
#define LPM_MEM_DI0_POL__FULL       0x1F040428,0xffffffff
#define LPM_MEM_DI0_POL__DI0_WAIT_POLARITY       0x1F040428,0x04000000
#define LPM_MEM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY       0x1F040428,0x02000000
#define LPM_MEM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY       0x1F040428,0x01000000
#define LPM_MEM_DI0_POL__DI0_CS1_DATA_POLARITY       0x1F040428,0x00800000
#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_17       0x1F040428,0x00400000
#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_16       0x1F040428,0x00200000
#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_15       0x1F040428,0x00100000
#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_14       0x1F040428,0x00080000
#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_13       0x1F040428,0x00040000
#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_12       0x1F040428,0x00020000
#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_11       0x1F040428,0x00010000
#define LPM_MEM_DI0_POL__DI0_CS0_DATA_POLARITY       0x1F040428,0x00008000
#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_17       0x1F040428,0x00004000
#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_16       0x1F040428,0x00002000
#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_15       0x1F040428,0x00001000
#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_14       0x1F040428,0x00000800
#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_13       0x1F040428,0x00000400
#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_12       0x1F040428,0x00000200
#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_11       0x1F040428,0x00000100
#define LPM_MEM_DI0_POL__DI0_DRDY_DATA_POLARITY       0x1F040428,0x00000080
#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_17       0x1F040428,0x00000040
#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_16       0x1F040428,0x00000020
#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_15       0x1F040428,0x00000010
#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_14       0x1F040428,0x00000008
#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_13       0x1F040428,0x00000004
#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_12       0x1F040428,0x00000002
#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_11       0x1F040428,0x00000001

#define LPM_MEM_DI0_AW0__ADDR                   0x1F04042C
#define LPM_MEM_DI0_AW0__EMPTY       0x1F04042C,0x00000000
#define LPM_MEM_DI0_AW0__FULL       0x1F04042C,0xffffffff
#define LPM_MEM_DI0_AW0__DI0_AW_TRIG_SEL       0x1F04042C,0xF0000000
#define LPM_MEM_DI0_AW0__DI0_AW_HEND       0x1F04042C,0x0FFF0000
#define LPM_MEM_DI0_AW0__DI0_AW_HCOUNT_SEL       0x1F04042C,0x0000F000
#define LPM_MEM_DI0_AW0__DI0_AW_HSTART       0x1F04042C,0x00000FFF

#define LPM_MEM_DI0_AW1__ADDR                   0x1F040430
#define LPM_MEM_DI0_AW1__EMPTY       0x1F040430,0x00000000
#define LPM_MEM_DI0_AW1__FULL       0x1F040430,0xffffffff
#define LPM_MEM_DI0_AW1__DI0_AW_VEND       0x1F040430,0x0FFF0000
#define LPM_MEM_DI0_AW1__DI0_AW_VCOUNT_SEL       0x1F040430,0x0000F000
#define LPM_MEM_DI0_AW1__DI0_AW_VSTART       0x1F040430,0x00000FFF

#define LPM_MEM_DI0_SCR_CONF__ADDR                   0x1F040434
#define LPM_MEM_DI0_SCR_CONF__EMPTY       0x1F040434,0x00000000
#define LPM_MEM_DI0_SCR_CONF__FULL       0x1F040434,0xffffffff
#define LPM_MEM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT       0x1F040434,0x00000FFF

#define LPM_MEM_DI1_GENERAL__ADDR                   0x1F040438
#define LPM_MEM_DI1_GENERAL__EMPTY       0x1F040438,0x00000000
#define LPM_MEM_DI1_GENERAL__FULL       0x1F040438,0xffffffff
#define LPM_MEM_DI1_GENERAL__DI1_DISP_Y_SEL       0x1F040438,0x70000000
#define LPM_MEM_DI1_GENERAL__DI1_CLOCK_STOP_MODE       0x1F040438,0x0F000000
#define LPM_MEM_DI1_GENERAL__DI1_DISP_CLOCK_INIT       0x1F040438,0x00800000
#define LPM_MEM_DI1_GENERAL__DI1_MASK_SEL       0x1F040438,0x00400000
#define LPM_MEM_DI1_GENERAL__DI1_VSYNC_EXT       0x1F040438,0x00200000
#define LPM_MEM_DI1_GENERAL__DI1_CLK_EXT       0x1F040438,0x00100000
#define LPM_MEM_DI1_GENERAL__DI1_WATCHDOG_MODE       0x1F040438,0x000C0000
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_DISP_CLK       0x1F040438,0x00020000
#define LPM_MEM_DI1_GENERAL__DI1_SYNC_COUNT_SEL       0x1F040438,0x0000F000
#define LPM_MEM_DI1_GENERAL__DI1_ERR_TREATMENT       0x1F040438,0x00000800
#define LPM_MEM_DI1_GENERAL__DI1_ERM_VSYNC_SEL     0x1F040438,0x00000400
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS1       0x1F040438,0x00000200
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS0       0x1F040438,0x00000100
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_8       0x1F040438,0x00000080
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_7       0x1F040438,0x00000040
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_6       0x1F040438,0x00000020
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_5       0x1F040438,0x00000010
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_4       0x1F040438,0x00000008
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_3       0x1F040438,0x00000004
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_2       0x1F040438,0x00000002
#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_1       0x1F040438,0x00000001

#define LPM_MEM_DI1_BS_CLKGEN0__ADDR                   0x1F04043C
#define LPM_MEM_DI1_BS_CLKGEN0__EMPTY       0x1F04043C,0x00000000
#define LPM_MEM_DI1_BS_CLKGEN0__FULL       0x1F04043C,0xffffffff
#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET       0x1F04043C,0x01FF0000
#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD       0x1F04043C,0x00000FFF

#define LPM_MEM_DI1_BS_CLKGEN1__ADDR                   0x1F040440
#define LPM_MEM_DI1_BS_CLKGEN1__EMPTY       0x1F040440,0x00000000
#define LPM_MEM_DI1_BS_CLKGEN1__FULL       0x1F040440,0xffffffff
#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN       0x1F040440,0x01FF0000
#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP       0x1F040440,0x000001FF

#define LPM_MEM_DI1_SW_GEN0_1__ADDR                   0x1F040444
#define LPM_MEM_DI1_SW_GEN0_1__EMPTY       0x1F040444,0x00000000
#define LPM_MEM_DI1_SW_GEN0_1__FULL       0x1F040444,0xffffffff
#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1       0x1F040444,0x7FF80000
#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1       0x1F040444,0x00070000
#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1       0x1F040444,0x00007FF8
#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1       0x1F040444,0x00000007

#define LPM_MEM_DI1_SW_GEN0_2__ADDR                   0x1F040448
#define LPM_MEM_DI1_SW_GEN0_2__EMPTY       0x1F040448,0x00000000
#define LPM_MEM_DI1_SW_GEN0_2__FULL       0x1F040448,0xffffffff
#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2       0x1F040448,0x7FF80000
#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2       0x1F040448,0x00070000
#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2       0x1F040448,0x00007FF8
#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2       0x1F040448,0x00000007

#define LPM_MEM_DI1_SW_GEN0_3__ADDR                   0x1F04044C
#define LPM_MEM_DI1_SW_GEN0_3__EMPTY       0x1F04044C,0x00000000
#define LPM_MEM_DI1_SW_GEN0_3__FULL       0x1F04044C,0xffffffff
#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3       0x1F04044C,0x7FF80000
#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3       0x1F04044C,0x00070000
#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3       0x1F04044C,0x00007FF8
#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3       0x1F04044C,0x00000007

#define LPM_MEM_DI1_SW_GEN0_4__ADDR                   0x1F040450
#define LPM_MEM_DI1_SW_GEN0_4__EMPTY       0x1F040450,0x00000000
#define LPM_MEM_DI1_SW_GEN0_4__FULL       0x1F040450,0xffffffff
#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4       0x1F040450,0x7FF80000
#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4       0x1F040450,0x00070000
#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4       0x1F040450,0x00007FF8
#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4       0x1F040450,0x00000007

#define LPM_MEM_DI1_SW_GEN0_5__ADDR                   0x1F040454
#define LPM_MEM_DI1_SW_GEN0_5__EMPTY       0x1F040454,0x00000000
#define LPM_MEM_DI1_SW_GEN0_5__FULL       0x1F040454,0xffffffff
#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5       0x1F040454,0x7FF80000
#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5       0x1F040454,0x00070000
#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5       0x1F040454,0x00007FF8
#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5       0x1F040454,0x00000007

#define LPM_MEM_DI1_SW_GEN0_6__ADDR                   0x1F040458
#define LPM_MEM_DI1_SW_GEN0_6__EMPTY       0x1F040458,0x00000000
#define LPM_MEM_DI1_SW_GEN0_6__FULL       0x1F040458,0xffffffff
#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6       0x1F040458,0x7FF80000
#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6       0x1F040458,0x00070000
#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6       0x1F040458,0x00007FF8
#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6       0x1F040458,0x00000007

#define LPM_MEM_DI1_SW_GEN0_7__ADDR                   0x1F04045C
#define LPM_MEM_DI1_SW_GEN0_7__EMPTY       0x1F04045C,0x00000000
#define LPM_MEM_DI1_SW_GEN0_7__FULL       0x1F04045C,0xffffffff
#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7       0x1F04045C,0x7FF80000
#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7       0x1F04045C,0x00070000
#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7       0x1F04045C,0x00007FF8
#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7       0x1F04045C,0x00000007

#define LPM_MEM_DI1_SW_GEN0_8__ADDR                   0x1F040460
#define LPM_MEM_DI1_SW_GEN0_8__EMPTY       0x1F040460,0x00000000
#define LPM_MEM_DI1_SW_GEN0_8__FULL       0x1F040460,0xffffffff
#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8       0x1F040460,0x7FF80000
#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8       0x1F040460,0x00070000
#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8       0x1F040460,0x00007FF8
#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8       0x1F040460,0x00000007

#define LPM_MEM_DI1_SW_GEN0_9__ADDR                   0x1F040464
#define LPM_MEM_DI1_SW_GEN0_9__EMPTY       0x1F040464,0x00000000
#define LPM_MEM_DI1_SW_GEN0_9__FULL       0x1F040464,0xffffffff
#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9       0x1F040464,0x7FF80000
#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9       0x1F040464,0x00070000
#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9       0x1F040464,0x00007FF8
#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9       0x1F040464,0x00000007

#define LPM_MEM_DI1_SW_GEN1_1__ADDR                   0x1F040468
#define LPM_MEM_DI1_SW_GEN1_1__EMPTY       0x1F040468,0x00000000
#define LPM_MEM_DI1_SW_GEN1_1__FULL       0x1F040468,0xffffffff
#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1       0x1F040468,0x60000000
#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1       0x1F040468,0x10000000
#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1       0x1F040468,0x0E000000
#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1       0x1F040468,0x01FF0000
#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1       0x1F040468,0x00007000
#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1       0x1F040468,0x00000E00
#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_UP_1       0x1F040468,0x000001FF

#define LPM_MEM_DI1_SW_GEN1_2__ADDR                   0x1F04046C
#define LPM_MEM_DI1_SW_GEN1_2__EMPTY       0x1F04046C,0x00000000
#define LPM_MEM_DI1_SW_GEN1_2__FULL       0x1F04046C,0xffffffff
#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2       0x1F04046C,0x60000000
#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2       0x1F04046C,0x10000000
#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2       0x1F04046C,0x0E000000
#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2       0x1F04046C,0x01FF0000
#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2       0x1F04046C,0x00007000
#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2       0x1F04046C,0x00000E00
#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_UP_2       0x1F04046C,0x000001FF

#define LPM_MEM_DI1_SW_GEN1_3__ADDR                   0x1F040470
#define LPM_MEM_DI1_SW_GEN1_3__EMPTY       0x1F040470,0x00000000
#define LPM_MEM_DI1_SW_GEN1_3__FULL       0x1F040470,0xffffffff
#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3       0x1F040470,0x60000000
#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3       0x1F040470,0x10000000
#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3       0x1F040470,0x0E000000
#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3       0x1F040470,0x01FF0000
#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3       0x1F040470,0x00007000
#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3       0x1F040470,0x00000E00
#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_UP_3       0x1F040470,0x000001FF

#define LPM_MEM_DI1_SW_GEN1_4__ADDR                   0x1F040474
#define LPM_MEM_DI1_SW_GEN1_4__EMPTY       0x1F040474,0x00000000
#define LPM_MEM_DI1_SW_GEN1_4__FULL       0x1F040474,0xffffffff
#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4       0x1F040474,0x60000000
#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4       0x1F040474,0x10000000
#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4       0x1F040474,0x0E000000
#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4       0x1F040474,0x01FF0000
#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4       0x1F040474,0x00007000
#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4       0x1F040474,0x00000E00
#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_UP_4       0x1F040474,0x000001FF

#define LPM_MEM_DI1_SW_GEN1_5__ADDR                   0x1F040478
#define LPM_MEM_DI1_SW_GEN1_5__EMPTY       0x1F040478,0x00000000
#define LPM_MEM_DI1_SW_GEN1_5__FULL       0x1F040478,0xffffffff
#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5       0x1F040478,0x60000000
#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5       0x1F040478,0x10000000
#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5       0x1F040478,0x0E000000
#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5       0x1F040478,0x01FF0000
#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5       0x1F040478,0x00007000
#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5       0x1F040478,0x00000E00
#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_UP_5       0x1F040478,0x000001FF

#define LPM_MEM_DI1_SW_GEN1_6__ADDR                   0x1F04047C
#define LPM_MEM_DI1_SW_GEN1_6__EMPTY       0x1F04047C,0x00000000
#define LPM_MEM_DI1_SW_GEN1_6__FULL       0x1F04047C,0xffffffff
#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6       0x1F04047C,0x60000000
#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6       0x1F04047C,0x10000000
#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6       0x1F04047C,0x0E000000
#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6       0x1F04047C,0x01FF0000
#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6       0x1F04047C,0x00007000
#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6       0x1F04047C,0x00000E00
#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_UP_6       0x1F04047C,0x000001FF

#define LPM_MEM_DI1_SW_GEN1_7__ADDR                   0x1F040480
#define LPM_MEM_DI1_SW_GEN1_7__EMPTY       0x1F040480,0x00000000
#define LPM_MEM_DI1_SW_GEN1_7__FULL       0x1F040480,0xffffffff
#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7       0x1F040480,0x60000000
#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7       0x1F040480,0x10000000
#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7       0x1F040480,0x0E000000
#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7       0x1F040480,0x01FF0000
#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7       0x1F040480,0x00007000
#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7       0x1F040480,0x00000E00
#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_UP_7       0x1F040480,0x000001FF

#define LPM_MEM_DI1_SW_GEN1_8__ADDR                   0x1F040484
#define LPM_MEM_DI1_SW_GEN1_8__EMPTY       0x1F040484,0x00000000
#define LPM_MEM_DI1_SW_GEN1_8__FULL       0x1F040484,0xffffffff
#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8       0x1F040484,0x60000000
#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8       0x1F040484,0x10000000
#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8       0x1F040484,0x0E000000
#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8       0x1F040484,0x01FF0000
#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8       0x1F040484,0x00007000
#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8       0x1F040484,0x00000E00
#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_UP_8       0x1F040484,0x000001FF

#define LPM_MEM_DI1_SW_GEN1_9__ADDR                   0x1F040488
#define LPM_MEM_DI1_SW_GEN1_9__EMPTY       0x1F040488,0x00000000
#define LPM_MEM_DI1_SW_GEN1_9__FULL       0x1F040488,0xffffffff
#define LPM_MEM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9       0x1F040488,0xE0000000
#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9       0x1F040488,0x10000000
#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9       0x1F040488,0x0E000000
#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9       0x1F040488,0x01FF0000
#define LPM_MEM_DI1_SW_GEN1_9__DI1_TAG_SEL_9       0x1F040488,0x00008000
#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_UP_9       0x1F040488,0x000001FF

#define LPM_MEM_DI1_SYNC_AS_GEN__ADDR                   0x1F04048C
#define LPM_MEM_DI1_SYNC_AS_GEN__EMPTY       0x1F04048C,0x00000000
#define LPM_MEM_DI1_SYNC_AS_GEN__FULL       0x1F04048C,0xffffffff
#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN       0x1F04048C,0x10000000
#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL       0x1F04048C,0x0000E000
#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START       0x1F04048C,0x00000FFF

#define LPM_MEM_DI1_DW_GEN_0__ADDR                   0x1F040490
#define LPM_MEM_DI1_DW_GEN_0__EMPTY       0x1F040490,0x00000000
#define LPM_MEM_DI1_DW_GEN_0__FULL       0x1F040490,0xffffffff
#define LPM_MEM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0       0x1F040490,0xFF000000
#define LPM_MEM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0       0x1F040490,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0       0x1F040490,0x0000C000
#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_6_0       0x1F040490,0x00003000
#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_5_0       0x1F040490,0x00000C00
#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_4_0       0x1F040490,0x00000300
#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_3_0       0x1F040490,0x000000C0
#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_2_0       0x1F040490,0x00000030
#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_1_0       0x1F040490,0x0000000C
#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_0_0       0x1F040490,0x00000003

#define LPM_MEM_DI1_DW_GEN_0__ADDR                   0x1F040490
#define LPM_MEM_DI1_DW_GEN_0__EMPTY       0x1F040490,0x00000000
#define LPM_MEM_DI1_DW_GEN_0__FULL       0x1F040490,0xffffffff
#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0       0x1F040490,0xFF000000
#define LPM_MEM_DI1_DW_GEN_0__DI1_START_PERIOD_0       0x1F040490,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0       0x1F040490,0x0000C000
#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0       0x1F040490,0x000001F0
#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_RS_0       0x1F040490,0x0000000C
#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0       0x1F040490,0x00000003

#define LPM_MEM_DI1_DW_GEN_1__ADDR                   0x1F040494
#define LPM_MEM_DI1_DW_GEN_1__EMPTY       0x1F040494,0x00000000
#define LPM_MEM_DI1_DW_GEN_1__FULL       0x1F040494,0xffffffff
#define LPM_MEM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1       0x1F040494,0xFF000000
#define LPM_MEM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1       0x1F040494,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1       0x1F040494,0x0000C000
#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_6_1       0x1F040494,0x00003000
#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_5_1       0x1F040494,0x00000C00
#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_4_1       0x1F040494,0x00000300
#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_3_1       0x1F040494,0x000000C0
#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_2_1       0x1F040494,0x00000030
#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_1_1       0x1F040494,0x0000000C
#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_0_1       0x1F040494,0x00000003

#define LPM_MEM_DI1_DW_GEN_1__ADDR                   0x1F040494
#define LPM_MEM_DI1_DW_GEN_1__EMPTY       0x1F040494,0x00000000
#define LPM_MEM_DI1_DW_GEN_1__FULL       0x1F040494,0xffffffff
#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1       0x1F040494,0xFF000000
#define LPM_MEM_DI1_DW_GEN_1__DI1_START_PERIOD_1       0x1F040494,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1       0x1F040494,0x0000C000
#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1       0x1F040494,0x000001F0
#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_RS_1       0x1F040494,0x0000000C
#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1       0x1F040494,0x00000003

#define LPM_MEM_DI1_DW_GEN_2__ADDR                   0x1F040498
#define LPM_MEM_DI1_DW_GEN_2__EMPTY       0x1F040498,0x00000000
#define LPM_MEM_DI1_DW_GEN_2__FULL       0x1F040498,0xffffffff
#define LPM_MEM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2       0x1F040498,0xFF000000
#define LPM_MEM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2       0x1F040498,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2       0x1F040498,0x0000C000
#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_6_2       0x1F040498,0x00003000
#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_5_2       0x1F040498,0x00000C00
#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_4_2       0x1F040498,0x00000300
#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_3_2       0x1F040498,0x000000C0
#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_2_2       0x1F040498,0x00000030
#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_1_2       0x1F040498,0x0000000C
#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_0_2       0x1F040498,0x00000003

#define LPM_MEM_DI1_DW_GEN_2__ADDR                   0x1F040498
#define LPM_MEM_DI1_DW_GEN_2__EMPTY       0x1F040498,0x00000000
#define LPM_MEM_DI1_DW_GEN_2__FULL       0x1F040498,0xffffffff
#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2       0x1F040498,0xFF000000
#define LPM_MEM_DI1_DW_GEN_2__DI1_START_PERIOD_2       0x1F040498,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2       0x1F040498,0x0000C000
#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2       0x1F040498,0x000001F0
#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_RS_2       0x1F040498,0x0000000C
#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2       0x1F040498,0x00000003

#define LPM_MEM_DI1_DW_GEN_3__ADDR                   0x1F04049C
#define LPM_MEM_DI1_DW_GEN_3__EMPTY       0x1F04049C,0x00000000
#define LPM_MEM_DI1_DW_GEN_3__FULL       0x1F04049C,0xffffffff
#define LPM_MEM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3       0x1F04049C,0xFF000000
#define LPM_MEM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3       0x1F04049C,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3       0x1F04049C,0x0000C000
#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_6_3       0x1F04049C,0x00003000
#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_5_3       0x1F04049C,0x00000C00
#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_4_3       0x1F04049C,0x00000300
#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_3_3       0x1F04049C,0x000000C0
#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_2_3       0x1F04049C,0x00000030
#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_1_3       0x1F04049C,0x0000000C
#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_0_3       0x1F04049C,0x00000003

#define LPM_MEM_DI1_DW_GEN_3__ADDR                   0x1F04049C
#define LPM_MEM_DI1_DW_GEN_3__EMPTY       0x1F04049C,0x00000000
#define LPM_MEM_DI1_DW_GEN_3__FULL       0x1F04049C,0xffffffff
#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3       0x1F04049C,0xFF000000
#define LPM_MEM_DI1_DW_GEN_3__DI1_START_PERIOD_3       0x1F04049C,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3       0x1F04049C,0x0000C000
#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3       0x1F04049C,0x000001F0
#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_RS_3       0x1F04049C,0x0000000C
#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3       0x1F04049C,0x00000003

#define LPM_MEM_DI1_DW_GEN_4__ADDR                   0x1F0404A0
#define LPM_MEM_DI1_DW_GEN_4__EMPTY       0x1F0404A0,0x00000000
#define LPM_MEM_DI1_DW_GEN_4__FULL       0x1F0404A0,0xffffffff
#define LPM_MEM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4       0x1F0404A0,0xFF000000
#define LPM_MEM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4       0x1F0404A0,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4       0x1F0404A0,0x0000C000
#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_6_4       0x1F0404A0,0x00003000
#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_5_4       0x1F0404A0,0x00000C00
#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_4_4       0x1F0404A0,0x00000300
#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_3_4       0x1F0404A0,0x000000C0
#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_2_4       0x1F0404A0,0x00000030
#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_1_4       0x1F0404A0,0x0000000C
#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_0_4       0x1F0404A0,0x00000003

#define LPM_MEM_DI1_DW_GEN_4__ADDR                   0x1F0404A0
#define LPM_MEM_DI1_DW_GEN_4__EMPTY       0x1F0404A0,0x00000000
#define LPM_MEM_DI1_DW_GEN_4__FULL       0x1F0404A0,0xffffffff
#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4       0x1F0404A0,0xFF000000
#define LPM_MEM_DI1_DW_GEN_4__DI1_START_PERIOD_4       0x1F0404A0,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4       0x1F0404A0,0x0000C000
#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4       0x1F0404A0,0x000001F0
#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_RS_4       0x1F0404A0,0x0000000C
#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4       0x1F0404A0,0x00000003

#define LPM_MEM_DI1_DW_GEN_5__ADDR                   0x1F0404A4
#define LPM_MEM_DI1_DW_GEN_5__EMPTY       0x1F0404A4,0x00000000
#define LPM_MEM_DI1_DW_GEN_5__FULL       0x1F0404A4,0xffffffff
#define LPM_MEM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5       0x1F0404A4,0xFF000000
#define LPM_MEM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5       0x1F0404A4,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5       0x1F0404A4,0x0000C000
#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_6_5       0x1F0404A4,0x00003000
#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_5_5       0x1F0404A4,0x00000C00
#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_4_5       0x1F0404A4,0x00000300
#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_3_5       0x1F0404A4,0x000000C0
#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_2_5       0x1F0404A4,0x00000030
#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_1_5       0x1F0404A4,0x0000000C
#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_0_5       0x1F0404A4,0x00000003

#define LPM_MEM_DI1_DW_GEN_5__ADDR                   0x1F0404A4
#define LPM_MEM_DI1_DW_GEN_5__EMPTY       0x1F0404A4,0x00000000
#define LPM_MEM_DI1_DW_GEN_5__FULL       0x1F0404A4,0xffffffff
#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5       0x1F0404A4,0xFF000000
#define LPM_MEM_DI1_DW_GEN_5__DI1_START_PERIOD_5       0x1F0404A4,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5       0x1F0404A4,0x0000C000
#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5       0x1F0404A4,0x000001F0
#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_RS_5       0x1F0404A4,0x0000000C
#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5       0x1F0404A4,0x00000003

#define LPM_MEM_DI1_DW_GEN_6__ADDR                   0x1F0404A8
#define LPM_MEM_DI1_DW_GEN_6__EMPTY       0x1F0404A8,0x00000000
#define LPM_MEM_DI1_DW_GEN_6__FULL       0x1F0404A8,0xffffffff
#define LPM_MEM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6       0x1F0404A8,0xFF000000
#define LPM_MEM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6       0x1F0404A8,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6       0x1F0404A8,0x0000C000
#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_6_6       0x1F0404A8,0x00003000
#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_5_6       0x1F0404A8,0x00000C00
#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_4_6       0x1F0404A8,0x00000300
#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_3_6       0x1F0404A8,0x000000C0
#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_2_6       0x1F0404A8,0x00000030
#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_1_6       0x1F0404A8,0x0000000C
#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_0_6       0x1F0404A8,0x00000003

#define LPM_MEM_DI1_DW_GEN_6__ADDR                   0x1F0404A8
#define LPM_MEM_DI1_DW_GEN_6__EMPTY       0x1F0404A8,0x00000000
#define LPM_MEM_DI1_DW_GEN_6__FULL       0x1F0404A8,0xffffffff
#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6       0x1F0404A8,0xFF000000
#define LPM_MEM_DI1_DW_GEN_6__DI1_START_PERIOD_6       0x1F0404A8,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6       0x1F0404A8,0x0000C000
#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6       0x1F0404A8,0x000001F0
#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_RS_6       0x1F0404A8,0x0000000C
#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6       0x1F0404A8,0x00000003

#define LPM_MEM_DI1_DW_GEN_7__ADDR                   0x1F0404AC
#define LPM_MEM_DI1_DW_GEN_7__EMPTY       0x1F0404AC,0x00000000
#define LPM_MEM_DI1_DW_GEN_7__FULL       0x1F0404AC,0xffffffff
#define LPM_MEM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7       0x1F0404AC,0xFF000000
#define LPM_MEM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7       0x1F0404AC,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7       0x1F0404AC,0x0000C000
#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_6_7       0x1F0404AC,0x00003000
#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_5_7       0x1F0404AC,0x00000C00
#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_4_7       0x1F0404AC,0x00000300
#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_3_7       0x1F0404AC,0x000000C0
#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_2_7       0x1F0404AC,0x00000030
#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_1_7       0x1F0404AC,0x0000000C
#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_0_7       0x1F0404AC,0x00000003

#define LPM_MEM_DI1_DW_GEN_7__ADDR                   0x1F0404AC
#define LPM_MEM_DI1_DW_GEN_7__EMPTY       0x1F0404AC,0x00000000
#define LPM_MEM_DI1_DW_GEN_7__FULL       0x1F0404AC,0xffffffff
#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7       0x1F0404AC,0xFF000000
#define LPM_MEM_DI1_DW_GEN_7__DI1_START_PERIOD_7       0x1F0404AC,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7       0x1F0404AC,0x0000C000
#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7       0x1F0404AC,0x000001F0
#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_RS_7       0x1F0404AC,0x0000000C
#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7       0x1F0404AC,0x00000003

#define LPM_MEM_DI1_DW_GEN_8__ADDR                   0x1F0404B0
#define LPM_MEM_DI1_DW_GEN_8__EMPTY       0x1F0404B0,0x00000000
#define LPM_MEM_DI1_DW_GEN_8__FULL       0x1F0404B0,0xffffffff
#define LPM_MEM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8       0x1F0404B0,0xFF000000
#define LPM_MEM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8       0x1F0404B0,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8       0x1F0404B0,0x0000C000
#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_6_8       0x1F0404B0,0x00003000
#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_5_8       0x1F0404B0,0x00000C00
#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_4_8       0x1F0404B0,0x00000300
#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_3_8       0x1F0404B0,0x000000C0
#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_2_8       0x1F0404B0,0x00000030
#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_1_8       0x1F0404B0,0x0000000C
#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_0_8       0x1F0404B0,0x00000003

#define LPM_MEM_DI1_DW_GEN_8__ADDR                   0x1F0404B0
#define LPM_MEM_DI1_DW_GEN_8__EMPTY       0x1F0404B0,0x00000000
#define LPM_MEM_DI1_DW_GEN_8__FULL       0x1F0404B0,0xffffffff
#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8       0x1F0404B0,0xFF000000
#define LPM_MEM_DI1_DW_GEN_8__DI1_START_PERIOD_8       0x1F0404B0,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8       0x1F0404B0,0x0000C000
#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8       0x1F0404B0,0x000001F0
#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_RS_8       0x1F0404B0,0x0000000C
#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8       0x1F0404B0,0x00000003

#define LPM_MEM_DI1_DW_GEN_9__ADDR                   0x1F0404B4
#define LPM_MEM_DI1_DW_GEN_9__EMPTY       0x1F0404B4,0x00000000
#define LPM_MEM_DI1_DW_GEN_9__FULL       0x1F0404B4,0xffffffff
#define LPM_MEM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9       0x1F0404B4,0xFF000000
#define LPM_MEM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9       0x1F0404B4,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9       0x1F0404B4,0x0000C000
#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_6_9       0x1F0404B4,0x00003000
#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_5_9       0x1F0404B4,0x00000C00
#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_4_9       0x1F0404B4,0x00000300
#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_3_9       0x1F0404B4,0x000000C0
#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_2_9       0x1F0404B4,0x00000030
#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_1_9       0x1F0404B4,0x0000000C
#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_0_9       0x1F0404B4,0x00000003

#define LPM_MEM_DI1_DW_GEN_9__ADDR                   0x1F0404B4
#define LPM_MEM_DI1_DW_GEN_9__EMPTY       0x1F0404B4,0x00000000
#define LPM_MEM_DI1_DW_GEN_9__FULL       0x1F0404B4,0xffffffff
#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9       0x1F0404B4,0xFF000000
#define LPM_MEM_DI1_DW_GEN_9__DI1_START_PERIOD_9       0x1F0404B4,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9       0x1F0404B4,0x0000C000
#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9       0x1F0404B4,0x000001F0
#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_RS_9       0x1F0404B4,0x0000000C
#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9       0x1F0404B4,0x00000003

#define LPM_MEM_DI1_DW_GEN_10__ADDR                   0x1F0404B8
#define LPM_MEM_DI1_DW_GEN_10__EMPTY       0x1F0404B8,0x00000000
#define LPM_MEM_DI1_DW_GEN_10__FULL       0x1F0404B8,0xffffffff
#define LPM_MEM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10       0x1F0404B8,0xFF000000
#define LPM_MEM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10       0x1F0404B8,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10       0x1F0404B8,0x0000C000
#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_6_10       0x1F0404B8,0x00003000
#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_5_10       0x1F0404B8,0x00000C00
#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_4_10       0x1F0404B8,0x00000300
#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_3_10       0x1F0404B8,0x000000C0
#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_2_10       0x1F0404B8,0x00000030
#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_1_10       0x1F0404B8,0x0000000C
#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_0_10       0x1F0404B8,0x00000003

#define LPM_MEM_DI1_DW_GEN_10__ADDR                   0x1F0404B8
#define LPM_MEM_DI1_DW_GEN_10__EMPTY       0x1F0404B8,0x00000000
#define LPM_MEM_DI1_DW_GEN_10__FULL       0x1F0404B8,0xffffffff
#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10       0x1F0404B8,0xFF000000
#define LPM_MEM_DI1_DW_GEN_10__DI1_START_PERIOD_10       0x1F0404B8,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10       0x1F0404B8,0x0000C000
#define LPM_MEM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10       0x1F0404B8,0x000001F0
#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_RS_10       0x1F0404B8,0x0000000C
#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10       0x1F0404B8,0x00000003

#define LPM_MEM_DI1_DW_GEN_11__ADDR                   0x1F0404BC
#define LPM_MEM_DI1_DW_GEN_11__EMPTY       0x1F0404BC,0x00000000
#define LPM_MEM_DI1_DW_GEN_11__FULL       0x1F0404BC,0xffffffff
#define LPM_MEM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11       0x1F0404BC,0xFF000000
#define LPM_MEM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11       0x1F0404BC,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11       0x1F0404BC,0x0000C000
#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_6_11       0x1F0404BC,0x00003000
#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_5_11       0x1F0404BC,0x00000C00
#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_4_11       0x1F0404BC,0x00000300
#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_3_11       0x1F0404BC,0x000000C0
#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_2_11       0x1F0404BC,0x00000030
#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_1_11       0x1F0404BC,0x0000000C
#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_0_11       0x1F0404BC,0x00000003

#define LPM_MEM_DI1_DW_GEN_11__ADDR                   0x1F0404BC
#define LPM_MEM_DI1_DW_GEN_11__EMPTY       0x1F0404BC,0x00000000
#define LPM_MEM_DI1_DW_GEN_11__FULL       0x1F0404BC,0xffffffff
#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11       0x1F0404BC,0xFF000000
#define LPM_MEM_DI1_DW_GEN_11__DI1_START_PERIOD_11       0x1F0404BC,0x00FF0000
#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11       0x1F0404BC,0x0000C000
#define LPM_MEM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11       0x1F0404BC,0x000001F0
#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_RS_11       0x1F0404BC,0x0000000C
#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11       0x1F0404BC,0x00000003

#define LPM_MEM_DI1_DW_SET0_0__ADDR                   0x1F0404C0
#define LPM_MEM_DI1_DW_SET0_0__EMPTY       0x1F0404C0,0x00000000
#define LPM_MEM_DI1_DW_SET0_0__FULL       0x1F0404C0,0xffffffff
#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0       0x1F0404C0,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0       0x1F0404C0,0x000001FF

#define LPM_MEM_DI1_DW_SET0_1__ADDR                   0x1F0404C4
#define LPM_MEM_DI1_DW_SET0_1__EMPTY       0x1F0404C4,0x00000000
#define LPM_MEM_DI1_DW_SET0_1__FULL       0x1F0404C4,0xffffffff
#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1       0x1F0404C4,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1       0x1F0404C4,0x000001FF

#define LPM_MEM_DI1_DW_SET0_2__ADDR                   0x1F0404C8
#define LPM_MEM_DI1_DW_SET0_2__EMPTY       0x1F0404C8,0x00000000
#define LPM_MEM_DI1_DW_SET0_2__FULL       0x1F0404C8,0xffffffff
#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2       0x1F0404C8,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2       0x1F0404C8,0x000001FF

#define LPM_MEM_DI1_DW_SET0_3__ADDR                   0x1F0404CC
#define LPM_MEM_DI1_DW_SET0_3__EMPTY       0x1F0404CC,0x00000000
#define LPM_MEM_DI1_DW_SET0_3__FULL       0x1F0404CC,0xffffffff
#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3       0x1F0404CC,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3       0x1F0404CC,0x000001FF

#define LPM_MEM_DI1_DW_SET0_4__ADDR                   0x1F0404D0
#define LPM_MEM_DI1_DW_SET0_4__EMPTY       0x1F0404D0,0x00000000
#define LPM_MEM_DI1_DW_SET0_4__FULL       0x1F0404D0,0xffffffff
#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4       0x1F0404D0,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4       0x1F0404D0,0x000001FF

#define LPM_MEM_DI1_DW_SET0_5__ADDR                   0x1F0404D4
#define LPM_MEM_DI1_DW_SET0_5__EMPTY       0x1F0404D4,0x00000000
#define LPM_MEM_DI1_DW_SET0_5__FULL       0x1F0404D4,0xffffffff
#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5       0x1F0404D4,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5       0x1F0404D4,0x000001FF

#define LPM_MEM_DI1_DW_SET0_6__ADDR                   0x1F0404D8
#define LPM_MEM_DI1_DW_SET0_6__EMPTY       0x1F0404D8,0x00000000
#define LPM_MEM_DI1_DW_SET0_6__FULL       0x1F0404D8,0xffffffff
#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6       0x1F0404D8,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6       0x1F0404D8,0x000001FF

#define LPM_MEM_DI1_DW_SET0_7__ADDR                   0x1F0404DC
#define LPM_MEM_DI1_DW_SET0_7__EMPTY       0x1F0404DC,0x00000000
#define LPM_MEM_DI1_DW_SET0_7__FULL       0x1F0404DC,0xffffffff
#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7       0x1F0404DC,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7       0x1F0404DC,0x000001FF

#define LPM_MEM_DI1_DW_SET0_8__ADDR                   0x1F0404E0
#define LPM_MEM_DI1_DW_SET0_8__EMPTY       0x1F0404E0,0x00000000
#define LPM_MEM_DI1_DW_SET0_8__FULL       0x1F0404E0,0xffffffff
#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8       0x1F0404E0,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8       0x1F0404E0,0x000001FF

#define LPM_MEM_DI1_DW_SET0_9__ADDR                   0x1F0404E4
#define LPM_MEM_DI1_DW_SET0_9__EMPTY       0x1F0404E4,0x00000000
#define LPM_MEM_DI1_DW_SET0_9__FULL       0x1F0404E4,0xffffffff
#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9       0x1F0404E4,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9       0x1F0404E4,0x000001FF

#define LPM_MEM_DI1_DW_SET0_10__ADDR                   0x1F0404E8
#define LPM_MEM_DI1_DW_SET0_10__EMPTY       0x1F0404E8,0x00000000
#define LPM_MEM_DI1_DW_SET0_10__FULL       0x1F0404E8,0xffffffff
#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10       0x1F0404E8,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10       0x1F0404E8,0x000001FF

#define LPM_MEM_DI1_DW_SET0_11__ADDR                   0x1F0404EC
#define LPM_MEM_DI1_DW_SET0_11__EMPTY       0x1F0404EC,0x00000000
#define LPM_MEM_DI1_DW_SET0_11__FULL       0x1F0404EC,0xffffffff
#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11       0x1F0404EC,0x01FF0000
#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11       0x1F0404EC,0x000001FF

#define LPM_MEM_DI1_DW_SET1_0__ADDR                   0x1F0404F0
#define LPM_MEM_DI1_DW_SET1_0__EMPTY       0x1F0404F0,0x00000000
#define LPM_MEM_DI1_DW_SET1_0__FULL       0x1F0404F0,0xffffffff
#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0       0x1F0404F0,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0       0x1F0404F0,0x000001FF

#define LPM_MEM_DI1_DW_SET1_1__ADDR                   0x1F0404F4
#define LPM_MEM_DI1_DW_SET1_1__EMPTY       0x1F0404F4,0x00000000
#define LPM_MEM_DI1_DW_SET1_1__FULL       0x1F0404F4,0xffffffff
#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1       0x1F0404F4,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1       0x1F0404F4,0x000001FF

#define LPM_MEM_DI1_DW_SET1_2__ADDR                   0x1F0404F8
#define LPM_MEM_DI1_DW_SET1_2__EMPTY       0x1F0404F8,0x00000000
#define LPM_MEM_DI1_DW_SET1_2__FULL       0x1F0404F8,0xffffffff
#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2       0x1F0404F8,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2       0x1F0404F8,0x000001FF

#define LPM_MEM_DI1_DW_SET1_3__ADDR                   0x1F0404FC
#define LPM_MEM_DI1_DW_SET1_3__EMPTY       0x1F0404FC,0x00000000
#define LPM_MEM_DI1_DW_SET1_3__FULL       0x1F0404FC,0xffffffff
#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3       0x1F0404FC,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3       0x1F0404FC,0x000001FF

#define LPM_MEM_DI1_DW_SET1_4__ADDR                   0x1F040500
#define LPM_MEM_DI1_DW_SET1_4__EMPTY       0x1F040500,0x00000000
#define LPM_MEM_DI1_DW_SET1_4__FULL       0x1F040500,0xffffffff
#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4       0x1F040500,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4       0x1F040500,0x000001FF

#define LPM_MEM_DI1_DW_SET1_5__ADDR                   0x1F040504
#define LPM_MEM_DI1_DW_SET1_5__EMPTY       0x1F040504,0x00000000
#define LPM_MEM_DI1_DW_SET1_5__FULL       0x1F040504,0xffffffff
#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5       0x1F040504,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5       0x1F040504,0x000001FF

#define LPM_MEM_DI1_DW_SET1_6__ADDR                   0x1F040508
#define LPM_MEM_DI1_DW_SET1_6__EMPTY       0x1F040508,0x00000000
#define LPM_MEM_DI1_DW_SET1_6__FULL       0x1F040508,0xffffffff
#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6       0x1F040508,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6       0x1F040508,0x000001FF

#define LPM_MEM_DI1_DW_SET1_7__ADDR                   0x1F04050C
#define LPM_MEM_DI1_DW_SET1_7__EMPTY       0x1F04050C,0x00000000
#define LPM_MEM_DI1_DW_SET1_7__FULL       0x1F04050C,0xffffffff
#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7       0x1F04050C,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7       0x1F04050C,0x000001FF

#define LPM_MEM_DI1_DW_SET1_8__ADDR                   0x1F040510
#define LPM_MEM_DI1_DW_SET1_8__EMPTY       0x1F040510,0x00000000
#define LPM_MEM_DI1_DW_SET1_8__FULL       0x1F040510,0xffffffff
#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8       0x1F040510,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8       0x1F040510,0x000001FF

#define LPM_MEM_DI1_DW_SET1_9__ADDR                   0x1F040514
#define LPM_MEM_DI1_DW_SET1_9__EMPTY       0x1F040514,0x00000000
#define LPM_MEM_DI1_DW_SET1_9__FULL       0x1F040514,0xffffffff
#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9       0x1F040514,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9       0x1F040514,0x000001FF

#define LPM_MEM_DI1_DW_SET1_10__ADDR                   0x1F040518
#define LPM_MEM_DI1_DW_SET1_10__EMPTY       0x1F040518,0x00000000
#define LPM_MEM_DI1_DW_SET1_10__FULL       0x1F040518,0xffffffff
#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10       0x1F040518,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10       0x1F040518,0x000001FF

#define LPM_MEM_DI1_DW_SET1_11__ADDR                   0x1F04051C
#define LPM_MEM_DI1_DW_SET1_11__EMPTY       0x1F04051C,0x00000000
#define LPM_MEM_DI1_DW_SET1_11__FULL       0x1F04051C,0xffffffff
#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11       0x1F04051C,0x01FF0000
#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11       0x1F04051C,0x000001FF

#define LPM_MEM_DI1_DW_SET2_0__ADDR                   0x1F040520
#define LPM_MEM_DI1_DW_SET2_0__EMPTY       0x1F040520,0x00000000
#define LPM_MEM_DI1_DW_SET2_0__FULL       0x1F040520,0xffffffff
#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0       0x1F040520,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0       0x1F040520,0x000001FF

#define LPM_MEM_DI1_DW_SET2_1__ADDR                   0x1F040524
#define LPM_MEM_DI1_DW_SET2_1__EMPTY       0x1F040524,0x00000000
#define LPM_MEM_DI1_DW_SET2_1__FULL       0x1F040524,0xffffffff
#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1       0x1F040524,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1       0x1F040524,0x000001FF

#define LPM_MEM_DI1_DW_SET2_2__ADDR                   0x1F040528
#define LPM_MEM_DI1_DW_SET2_2__EMPTY       0x1F040528,0x00000000
#define LPM_MEM_DI1_DW_SET2_2__FULL       0x1F040528,0xffffffff
#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2       0x1F040528,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2       0x1F040528,0x000001FF

#define LPM_MEM_DI1_DW_SET2_3__ADDR                   0x1F04052C
#define LPM_MEM_DI1_DW_SET2_3__EMPTY       0x1F04052C,0x00000000
#define LPM_MEM_DI1_DW_SET2_3__FULL       0x1F04052C,0xffffffff
#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3       0x1F04052C,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3       0x1F04052C,0x000001FF

#define LPM_MEM_DI1_DW_SET2_4__ADDR                   0x1F040530
#define LPM_MEM_DI1_DW_SET2_4__EMPTY       0x1F040530,0x00000000
#define LPM_MEM_DI1_DW_SET2_4__FULL       0x1F040530,0xffffffff
#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4       0x1F040530,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4       0x1F040530,0x000001FF

#define LPM_MEM_DI1_DW_SET2_5__ADDR                   0x1F040534
#define LPM_MEM_DI1_DW_SET2_5__EMPTY       0x1F040534,0x00000000
#define LPM_MEM_DI1_DW_SET2_5__FULL       0x1F040534,0xffffffff
#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5       0x1F040534,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5       0x1F040534,0x000001FF

#define LPM_MEM_DI1_DW_SET2_6__ADDR                   0x1F040538
#define LPM_MEM_DI1_DW_SET2_6__EMPTY       0x1F040538,0x00000000
#define LPM_MEM_DI1_DW_SET2_6__FULL       0x1F040538,0xffffffff
#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6       0x1F040538,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6       0x1F040538,0x000001FF

#define LPM_MEM_DI1_DW_SET2_7__ADDR                   0x1F04053C
#define LPM_MEM_DI1_DW_SET2_7__EMPTY       0x1F04053C,0x00000000
#define LPM_MEM_DI1_DW_SET2_7__FULL       0x1F04053C,0xffffffff
#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7       0x1F04053C,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7       0x1F04053C,0x000001FF

#define LPM_MEM_DI1_DW_SET2_8__ADDR                   0x1F040540
#define LPM_MEM_DI1_DW_SET2_8__EMPTY       0x1F040540,0x00000000
#define LPM_MEM_DI1_DW_SET2_8__FULL       0x1F040540,0xffffffff
#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8       0x1F040540,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8       0x1F040540,0x000001FF

#define LPM_MEM_DI1_DW_SET2_9__ADDR                   0x1F040544
#define LPM_MEM_DI1_DW_SET2_9__EMPTY       0x1F040544,0x00000000
#define LPM_MEM_DI1_DW_SET2_9__FULL       0x1F040544,0xffffffff
#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9       0x1F040544,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9       0x1F040544,0x000001FF

#define LPM_MEM_DI1_DW_SET2_10__ADDR                   0x1F040548
#define LPM_MEM_DI1_DW_SET2_10__EMPTY       0x1F040548,0x00000000
#define LPM_MEM_DI1_DW_SET2_10__FULL       0x1F040548,0xffffffff
#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10       0x1F040548,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10       0x1F040548,0x000001FF

#define LPM_MEM_DI1_DW_SET2_11__ADDR                   0x1F04054C
#define LPM_MEM_DI1_DW_SET2_11__EMPTY       0x1F04054C,0x00000000
#define LPM_MEM_DI1_DW_SET2_11__FULL       0x1F04054C,0xffffffff
#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11       0x1F04054C,0x01FF0000
#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11       0x1F04054C,0x000001FF

#define LPM_MEM_DI1_DW_SET3_0__ADDR                   0x1F040550
#define LPM_MEM_DI1_DW_SET3_0__EMPTY       0x1F040550,0x00000000
#define LPM_MEM_DI1_DW_SET3_0__FULL       0x1F040550,0xffffffff
#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0       0x1F040550,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0       0x1F040550,0x000001FF

#define LPM_MEM_DI1_DW_SET3_1__ADDR                   0x1F040554
#define LPM_MEM_DI1_DW_SET3_1__EMPTY       0x1F040554,0x00000000
#define LPM_MEM_DI1_DW_SET3_1__FULL       0x1F040554,0xffffffff
#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1       0x1F040554,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1       0x1F040554,0x000001FF

#define LPM_MEM_DI1_DW_SET3_2__ADDR                   0x1F040558
#define LPM_MEM_DI1_DW_SET3_2__EMPTY       0x1F040558,0x00000000
#define LPM_MEM_DI1_DW_SET3_2__FULL       0x1F040558,0xffffffff
#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2       0x1F040558,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2       0x1F040558,0x000001FF

#define LPM_MEM_DI1_DW_SET3_3__ADDR                   0x1F04055C
#define LPM_MEM_DI1_DW_SET3_3__EMPTY       0x1F04055C,0x00000000
#define LPM_MEM_DI1_DW_SET3_3__FULL       0x1F04055C,0xffffffff
#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3       0x1F04055C,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3       0x1F04055C,0x000001FF

#define LPM_MEM_DI1_DW_SET3_4__ADDR                   0x1F040560
#define LPM_MEM_DI1_DW_SET3_4__EMPTY       0x1F040560,0x00000000
#define LPM_MEM_DI1_DW_SET3_4__FULL       0x1F040560,0xffffffff
#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4       0x1F040560,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4       0x1F040560,0x000001FF

#define LPM_MEM_DI1_DW_SET3_5__ADDR                   0x1F040564
#define LPM_MEM_DI1_DW_SET3_5__EMPTY       0x1F040564,0x00000000
#define LPM_MEM_DI1_DW_SET3_5__FULL       0x1F040564,0xffffffff
#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5       0x1F040564,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5       0x1F040564,0x000001FF

#define LPM_MEM_DI1_DW_SET3_6__ADDR                   0x1F040568
#define LPM_MEM_DI1_DW_SET3_6__EMPTY       0x1F040568,0x00000000
#define LPM_MEM_DI1_DW_SET3_6__FULL       0x1F040568,0xffffffff
#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6       0x1F040568,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6       0x1F040568,0x000001FF

#define LPM_MEM_DI1_DW_SET3_7__ADDR                   0x1F04056C
#define LPM_MEM_DI1_DW_SET3_7__EMPTY       0x1F04056C,0x00000000
#define LPM_MEM_DI1_DW_SET3_7__FULL       0x1F04056C,0xffffffff
#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7       0x1F04056C,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7       0x1F04056C,0x000001FF

#define LPM_MEM_DI1_DW_SET3_8__ADDR                   0x1F040570
#define LPM_MEM_DI1_DW_SET3_8__EMPTY       0x1F040570,0x00000000
#define LPM_MEM_DI1_DW_SET3_8__FULL       0x1F040570,0xffffffff
#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8       0x1F040570,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8       0x1F040570,0x000001FF

#define LPM_MEM_DI1_DW_SET3_9__ADDR                   0x1F040574
#define LPM_MEM_DI1_DW_SET3_9__EMPTY       0x1F040574,0x00000000
#define LPM_MEM_DI1_DW_SET3_9__FULL       0x1F040574,0xffffffff
#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9       0x1F040574,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9       0x1F040574,0x000001FF

#define LPM_MEM_DI1_DW_SET3_10__ADDR                   0x1F040578
#define LPM_MEM_DI1_DW_SET3_10__EMPTY       0x1F040578,0x00000000
#define LPM_MEM_DI1_DW_SET3_10__FULL       0x1F040578,0xffffffff
#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10       0x1F040578,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10       0x1F040578,0x000001FF

#define LPM_MEM_DI1_DW_SET3_11__ADDR                   0x1F04057C
#define LPM_MEM_DI1_DW_SET3_11__EMPTY       0x1F04057C,0x00000000
#define LPM_MEM_DI1_DW_SET3_11__FULL       0x1F04057C,0xffffffff
#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11       0x1F04057C,0x01FF0000
#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11       0x1F04057C,0x000001FF

#define LPM_MEM_DI1_STP_REP_1__ADDR                   0x1F040580
#define LPM_MEM_DI1_STP_REP_1__EMPTY       0x1F040580,0x00000000
#define LPM_MEM_DI1_STP_REP_1__FULL       0x1F040580,0xffffffff
#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_2       0x1F040580,0x0FFF0000
#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_1       0x1F040580,0x00000FFF

#define LPM_MEM_DI1_STP_REP_2__ADDR                   0x1F040584
#define LPM_MEM_DI1_STP_REP_2__EMPTY       0x1F040584,0x00000000
#define LPM_MEM_DI1_STP_REP_2__FULL       0x1F040584,0xffffffff
#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_4       0x1F040584,0x0FFF0000
#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_3       0x1F040584,0x00000FFF

#define LPM_MEM_DI1_STP_REP_3__ADDR                   0x1F040588
#define LPM_MEM_DI1_STP_REP_3__EMPTY       0x1F040588,0x00000000
#define LPM_MEM_DI1_STP_REP_3__FULL       0x1F040588,0xffffffff
#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_6       0x1F040588,0x0FFF0000
#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_5       0x1F040588,0x00000FFF

#define LPM_MEM_DI1_STP_REP_4__ADDR                   0x1F04058C
#define LPM_MEM_DI1_STP_REP_4__EMPTY       0x1F04058C,0x00000000
#define LPM_MEM_DI1_STP_REP_4__FULL       0x1F04058C,0xffffffff
#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_8       0x1F04058C,0x0FFF0000
#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_7       0x1F04058C,0x00000FFF

#define LPM_MEM_DI1_STP_REP_9__ADDR                   0x1F040590
#define LPM_MEM_DI1_STP_REP_9__EMPTY       0x1F040590,0x00000000
#define LPM_MEM_DI1_STP_REP_9__FULL       0x1F040590,0xffffffff
#define LPM_MEM_DI1_STP_REP_9__DI1_STEP_REPEAT_9       0x1F040590,0x00000FFF

#define LPM_MEM_DI1_SER_CONF__ADDR                   0x1F040594
#define LPM_MEM_DI1_SER_CONF__EMPTY       0x1F040594,0x00000000
#define LPM_MEM_DI1_SER_CONF__FULL       0x1F040594,0xffffffff
#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1       0x1F040594,0xF0000000
#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0       0x1F040594,0x0F000000
#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1       0x1F040594,0x00F00000
#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0       0x1F040594,0x000F0000
#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LATCH       0x1F040594,0x0000FF00
#define LPM_MEM_DI1_SER_CONF__DI1_LLA_SER_ACCESS       0x1F040594,0x00000020
#define LPM_MEM_DI1_SER_CONF__DI1_SER_CLK_POLARITY       0x1F040594,0x00000010
#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY       0x1F040594,0x00000008
#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY       0x1F040594,0x00000004
#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY       0x1F040594,0x00000002
#define LPM_MEM_DI1_SER_CONF__DI1_WAIT4SERIAL       0x1F040594,0x00000001

#define LPM_MEM_DI1_SSC__ADDR                   0x1F040598
#define LPM_MEM_DI1_SSC__EMPTY       0x1F040598,0x00000000
#define LPM_MEM_DI1_SSC__FULL       0x1F040598,0xffffffff
#define LPM_MEM_DI1_SSC__DI1_PIN17_ERM       0x1F040598,0x00800000
#define LPM_MEM_DI1_SSC__DI1_PIN16_ERM       0x1F040598,0x00400000
#define LPM_MEM_DI1_SSC__DI1_PIN15_ERM       0x1F040598,0x00200000
#define LPM_MEM_DI1_SSC__DI1_PIN14_ERM       0x1F040598,0x00100000
#define LPM_MEM_DI1_SSC__DI1_PIN13_ERM       0x1F040598,0x00080000
#define LPM_MEM_DI1_SSC__DI1_PIN12_ERM       0x1F040598,0x00040000
#define LPM_MEM_DI1_SSC__DI1_PIN11_ERM       0x1F040598,0x00020000
#define LPM_MEM_DI1_SSC__DI1_CS_ERM       0x1F040598,0x00010000
#define LPM_MEM_DI1_SSC__DI1_WAIT_ON       0x1F040598,0x00000020
#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_RD_IN       0x1F040598,0x00000008
#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_PNTR       0x1F040598,0x00000007

#define LPM_MEM_DI1_POL__ADDR                   0x1F04059C
#define LPM_MEM_DI1_POL__EMPTY       0x1F04059C,0x00000000
#define LPM_MEM_DI1_POL__FULL       0x1F04059C,0xffffffff
#define LPM_MEM_DI1_POL__DI1_WAIT_POLARITY       0x1F04059C,0x04000000
#define LPM_MEM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY       0x1F04059C,0x02000000
#define LPM_MEM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY       0x1F04059C,0x01000000
#define LPM_MEM_DI1_POL__DI1_CS1_DATA_POLARITY       0x1F04059C,0x00800000
#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_17       0x1F04059C,0x00400000
#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_16       0x1F04059C,0x00200000
#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_15       0x1F04059C,0x00100000
#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_14       0x1F04059C,0x00080000
#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_13       0x1F04059C,0x00040000
#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_12       0x1F04059C,0x00020000
#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_11       0x1F04059C,0x00010000
#define LPM_MEM_DI1_POL__DI1_CS0_DATA_POLARITY       0x1F04059C,0x00008000
#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_17       0x1F04059C,0x00004000
#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_16       0x1F04059C,0x00002000
#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_15       0x1F04059C,0x00001000
#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_14       0x1F04059C,0x00000800
#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_13       0x1F04059C,0x00000400
#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_12       0x1F04059C,0x00000200
#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_11       0x1F04059C,0x00000100
#define LPM_MEM_DI1_POL__DI1_DRDY_DATA_POLARITY       0x1F04059C,0x00000080
#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_17       0x1F04059C,0x00000040
#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_16       0x1F04059C,0x00000020
#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_15       0x1F04059C,0x00000010
#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_14       0x1F04059C,0x00000008
#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_13       0x1F04059C,0x00000004
#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_12       0x1F04059C,0x00000002
#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_11       0x1F04059C,0x00000001

#define LPM_MEM_DI1_AW0__ADDR                   0x1F0405A0
#define LPM_MEM_DI1_AW0__EMPTY       0x1F0405A0,0x00000000
#define LPM_MEM_DI1_AW0__FULL       0x1F0405A0,0xffffffff
#define LPM_MEM_DI1_AW0__DI1_AW_TRIG_SEL       0x1F0405A0,0xF0000000
#define LPM_MEM_DI1_AW0__DI1_AW_HEND       0x1F0405A0,0x0FFF0000
#define LPM_MEM_DI1_AW0__DI1_AW_HCOUNT_SEL       0x1F0405A0,0x0000F000
#define LPM_MEM_DI1_AW0__DI1_AW_HSTART       0x1F0405A0,0x00000FFF

#define LPM_MEM_DI1_AW1__ADDR                   0x1F0405A4
#define LPM_MEM_DI1_AW1__EMPTY       0x1F0405A4,0x00000000
#define LPM_MEM_DI1_AW1__FULL       0x1F0405A4,0xffffffff
#define LPM_MEM_DI1_AW1__DI1_AW_VEND       0x1F0405A4,0x0FFF0000
#define LPM_MEM_DI1_AW1__DI1_AW_VCOUNT_SEL       0x1F0405A4,0x0000F000
#define LPM_MEM_DI1_AW1__DI1_AW_VSTART       0x1F0405A4,0x00000FFF

#define LPM_MEM_DI1_SCR_CONF__ADDR                   0x1F0405A8
#define LPM_MEM_DI1_SCR_CONF__EMPTY       0x1F0405A8,0x00000000
#define LPM_MEM_DI1_SCR_CONF__FULL       0x1F0405A8,0xffffffff
#define LPM_MEM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT       0x1F0405A8,0x00000FFF

#define LPM_MEM_DMFC_RD_CHAN__ADDR                   0x1F0405AC
#define LPM_MEM_DMFC_RD_CHAN__EMPTY       0x1F0405AC,0x00000000
#define LPM_MEM_DMFC_RD_CHAN__FULL       0x1F0405AC,0xffffffff
#define LPM_MEM_DMFC_RD_CHAN__DMFC_PPW_C       0x1F0405AC,0x03000000
#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_CLR_0       0x1F0405AC,0x00E00000
#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_SET_0       0x1F0405AC,0x001C0000
#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_EN_0       0x1F0405AC,0x00020000
#define LPM_MEM_DMFC_RD_CHAN__DMFC_BURST_SIZE_0       0x1F0405AC,0x000000C0

#define LPM_MEM_DMFC_WR_CHAN__ADDR                   0x1F0405B0
#define LPM_MEM_DMFC_WR_CHAN__EMPTY       0x1F0405B0,0x00000000
#define LPM_MEM_DMFC_WR_CHAN__FULL       0x1F0405B0,0xffffffff
#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C       0x1F0405B0,0xC0000000
#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C       0x1F0405B0,0x38000000
#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2C       0x1F0405B0,0x07000000
#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C       0x1F0405B0,0x00C00000
#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C       0x1F0405B0,0x00380000
#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1C       0x1F0405B0,0x00070000
#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2       0x1F0405B0,0x0000C000
#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2       0x1F0405B0,0x00003800
#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2       0x1F0405B0,0x00000700
#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1       0x1F0405B0,0x000000C0
#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1       0x1F0405B0,0x00000038
#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1       0x1F0405B0,0x00000007

#define LPM_MEM_DMFC_WR_CHAN_DEF__ADDR                   0x1F0405B4
#define LPM_MEM_DMFC_WR_CHAN_DEF__EMPTY       0x1F0405B4,0x00000000
#define LPM_MEM_DMFC_WR_CHAN_DEF__FULL       0x1F0405B4,0xffffffff
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C       0x1F0405B4,0xE0000000
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C       0x1F0405B4,0x1C000000
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C       0x1F0405B4,0x02000000
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C       0x1F0405B4,0x00E00000
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C       0x1F0405B4,0x001C0000
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C       0x1F0405B4,0x00020000
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2       0x1F0405B4,0x0000E000
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2       0x1F0405B4,0x00001C00
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2       0x1F0405B4,0x00000200
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1       0x1F0405B4,0x000000E0
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1       0x1F0405B4,0x0000001C
#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1       0x1F0405B4,0x00000002

#define LPM_MEM_DMFC_DP_CHAN__ADDR                   0x1F0405B8
#define LPM_MEM_DMFC_DP_CHAN__EMPTY       0x1F0405B8,0x00000000
#define LPM_MEM_DMFC_DP_CHAN__FULL       0x1F0405B8,0xffffffff
#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F       0x1F0405B8,0xC0000000
#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F       0x1F0405B8,0x38000000
#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6F       0x1F0405B8,0x07000000
#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B       0x1F0405B8,0x00C00000
#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B       0x1F0405B8,0x00380000
#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6B       0x1F0405B8,0x00070000
#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F       0x1F0405B8,0x0000C000
#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F       0x1F0405B8,0x00003800
#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5F       0x1F0405B8,0x00000700
#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B       0x1F0405B8,0x000000C0
#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B       0x1F0405B8,0x00000038
#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5B       0x1F0405B8,0x00000007

#define LPM_MEM_DMFC_DP_CHAN_DEF__ADDR                   0x1F0405BC
#define LPM_MEM_DMFC_DP_CHAN_DEF__EMPTY       0x1F0405BC,0x00000000
#define LPM_MEM_DMFC_DP_CHAN_DEF__FULL       0x1F0405BC,0xffffffff
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F       0x1F0405BC,0xE0000000
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F       0x1F0405BC,0x1C000000
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F       0x1F0405BC,0x02000000
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B       0x1F0405BC,0x00E00000
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B       0x1F0405BC,0x001C0000
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B       0x1F0405BC,0x00020000
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F       0x1F0405BC,0x0000E000
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F       0x1F0405BC,0x00001C00
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F       0x1F0405BC,0x00000200
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B       0x1F0405BC,0x000000E0
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B       0x1F0405BC,0x0000001C
#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B       0x1F0405BC,0x00000002

#define LPM_MEM_DMFC_GENERAL1__ADDR                   0x1F0405C0
#define LPM_MEM_DMFC_GENERAL1__EMPTY       0x1F0405C0,0x00000000
#define LPM_MEM_DMFC_GENERAL1__FULL       0x1F0405C0,0xffffffff
#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_9       0x1F0405C0,0x01000000
#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6F       0x1F0405C0,0x00800000
#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6B       0x1F0405C0,0x00400000
#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5F       0x1F0405C0,0x00200000
#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5B       0x1F0405C0,0x00100000
#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_4       0x1F0405C0,0x00080000
#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_3       0x1F0405C0,0x00040000
#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_2       0x1F0405C0,0x00020000
#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_1       0x1F0405C0,0x00010000
#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_CLR_9     0x1F0401C0,0x0000E000
#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_SET_9     0x1F0401C0,0x00001C00
#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_EN_9      0x1F0401C0,0x00000200
#define LPM_MEM_DMFC_GENERAL1__DMFC_BURST_SIZE_9 0x1F0401C0,0x00000060
#define LPM_MEM_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR 0x1F0401C0,0x00000003

#define LPM_MEM_DMFC_GENERAL2__ADDR                   0x1F0405C4
#define LPM_MEM_DMFC_GENERAL2__EMPTY       0x1F0405C4,0x00000000
#define LPM_MEM_DMFC_GENERAL2__FULL       0x1F0405C4,0xffffffff
#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD       0x1F0405C4,0x1FFF0000
#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD       0x1F0405C4,0x00001FFF

#define LPM_MEM_DMFC_IC_CTRL__ADDR                   0x1F0405C8
#define LPM_MEM_DMFC_IC_CTRL__EMPTY       0x1F0405C8,0x00000000
#define LPM_MEM_DMFC_IC_CTRL__FULL       0x1F0405C8,0xffffffff
#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD       0x1F0405C8,0xFFF80000
#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD       0x1F0405C8,0x0007FFC0
#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_PPW_C       0x1F0405C8,0x00000030
#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_IN_PORT     0x1F0405C8,0x00000007

#define LPM_MEM_DC_READ_CH_CONF__ADDR                   0x1F0405CC
#define LPM_MEM_DC_READ_CH_CONF__EMPTY       0x1F0405CC,0x00000000
#define LPM_MEM_DC_READ_CH_CONF__FULL       0x1F0405CC,0xffffffff
#define LPM_MEM_DC_READ_CH_CONF__TIME_OUT_VALUE       0x1F0405CC,0xFFFF0000
#define LPM_MEM_DC_READ_CH_CONF__CS_ID_3       0x1F0405CC,0x00000800
#define LPM_MEM_DC_READ_CH_CONF__CS_ID_2       0x1F0405CC,0x00000400
#define LPM_MEM_DC_READ_CH_CONF__CS_ID_1       0x1F0405CC,0x00000200
#define LPM_MEM_DC_READ_CH_CONF__CS_ID_0       0x1F0405CC,0x00000100
#define LPM_MEM_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0       0x1F0405CC,0x00000040
#define LPM_MEM_DC_READ_CH_CONF__W_SIZE_0       0x1F0405CC,0x00000030
#define LPM_MEM_DC_READ_CH_CONF__PROG_DISP_ID_0       0x1F0405CC,0x0000000C
#define LPM_MEM_DC_READ_CH_CONF__PROG_DI_ID_0       0x1F0405CC,0x00000002
#define LPM_MEM_DC_READ_CH_CONF__RD_CHANNEL_EN       0x1F0405CC,0x00000001

#define LPM_MEM_DC_READ_CH_ADDR__ADDR                   0x1F0405D0
#define LPM_MEM_DC_READ_CH_ADDR__EMPTY       0x1F0405D0,0x00000000
#define LPM_MEM_DC_READ_CH_ADDR__FULL       0x1F0405D0,0xffffffff
#define LPM_MEM_DC_READ_CH_ADDR__ST_ADDR_0       0x1F0405D0,0x1FFFFFFF

#define LPM_MEM_DC_RL0_CH_0__ADDR                   0x1F0405D4
#define LPM_MEM_DC_RL0_CH_0__EMPTY       0x1F0405D4,0x00000000
#define LPM_MEM_DC_RL0_CH_0__FULL       0x1F0405D4,0xffffffff
#define LPM_MEM_DC_RL0_CH_0__COD_NL_START_CHAN_0       0x1F0405D4,0xFF000000
#define LPM_MEM_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0       0x1F0405D4,0x000F0000
#define LPM_MEM_DC_RL0_CH_0__COD_NF_START_CHAN_0       0x1F0405D4,0x0000FF00
#define LPM_MEM_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0       0x1F0405D4,0x0000000F

#define LPM_MEM_DC_RL1_CH_0__ADDR                   0x1F0405D8
#define LPM_MEM_DC_RL1_CH_0__EMPTY       0x1F0405D8,0x00000000
#define LPM_MEM_DC_RL1_CH_0__FULL       0x1F0405D8,0xffffffff
#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0       0x1F0405D8,0xFF000000
#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0       0x1F0405D8,0x000F0000
#define LPM_MEM_DC_RL1_CH_0__COD_EOF_START_CHAN_0       0x1F0405D8,0x0000FF00
#define LPM_MEM_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0       0x1F0405D8,0x0000000F

#define LPM_MEM_DC_RL2_CH_0__ADDR                   0x1F0405DC
#define LPM_MEM_DC_RL2_CH_0__EMPTY       0x1F0405DC,0x00000000
#define LPM_MEM_DC_RL2_CH_0__FULL       0x1F0405DC,0xffffffff
#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0       0x1F0405DC,0xFF000000
#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0       0x1F0405DC,0x000F0000
#define LPM_MEM_DC_RL2_CH_0__COD_EOL_START_CHAN_0       0x1F0405DC,0x0000FF00
#define LPM_MEM_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0       0x1F0405DC,0x0000000F

#define LPM_MEM_DC_RL3_CH_0__ADDR                   0x1F0405E0
#define LPM_MEM_DC_RL3_CH_0__EMPTY       0x1F0405E0,0x00000000
#define LPM_MEM_DC_RL3_CH_0__FULL       0x1F0405E0,0xffffffff
#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0       0x1F0405E0,0xFF000000
#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0       0x1F0405E0,0x000F0000
#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0       0x1F0405E0,0x0000FF00
#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0       0x1F0405E0,0x0000000F

#define LPM_MEM_DC_RL4_CH_0__ADDR                   0x1F0405E4
#define LPM_MEM_DC_RL4_CH_0__EMPTY       0x1F0405E4,0x00000000
#define LPM_MEM_DC_RL4_CH_0__FULL       0x1F0405E4,0xffffffff
#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0       0x1F0405E4,0x0000FF00
#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0       0x1F0405E4,0x0000000F

#define LPM_MEM_DC_WR_CH_CONF_1__ADDR                   0x1F0405E8
#define LPM_MEM_DC_WR_CH_CONF_1__EMPTY       0x1F0405E8,0x00000000
#define LPM_MEM_DC_WR_CH_CONF_1__FULL       0x1F0405E8,0xffffffff
#define LPM_MEM_DC_WR_CH_CONF_1__PROG_START_TIME_1       0x1F0405E8,0x07FF0000
#define LPM_MEM_DC_WR_CH_CONF_1__FIELD_MODE_1       0x1F0405E8,0x00000200
#define LPM_MEM_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1       0x1F0405E8,0x00000100
#define LPM_MEM_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1       0x1F0405E8,0x000000E0
#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DISP_ID_1       0x1F0405E8,0x00000018
#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DI_ID_1       0x1F0405E8,0x00000004
#define LPM_MEM_DC_WR_CH_CONF_1__W_SIZE_1       0x1F0405E8,0x00000003

#define LPM_MEM_DC_WR_CH_ADDR_1__ADDR                   0x1F0405EC
#define LPM_MEM_DC_WR_CH_ADDR_1__EMPTY       0x1F0405EC,0x00000000
#define LPM_MEM_DC_WR_CH_ADDR_1__FULL       0x1F0405EC,0xffffffff
#define LPM_MEM_DC_WR_CH_ADDR_1__ST_ADDR_1       0x1F0405EC,0x1FFFFFFF

#define LPM_MEM_DC_RL0_CH_1__ADDR                   0x1F0405F0
#define LPM_MEM_DC_RL0_CH_1__EMPTY       0x1F0405F0,0x00000000
#define LPM_MEM_DC_RL0_CH_1__FULL       0x1F0405F0,0xffffffff
#define LPM_MEM_DC_RL0_CH_1__COD_NL_START_CHAN_1       0x1F0405F0,0xFF000000
#define LPM_MEM_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1       0x1F0405F0,0x000F0000
#define LPM_MEM_DC_RL0_CH_1__COD_NF_START_CHAN_1       0x1F0405F0,0x0000FF00
#define LPM_MEM_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1       0x1F0405F0,0x0000000F

#define LPM_MEM_DC_RL1_CH_1__ADDR                   0x1F0405F4
#define LPM_MEM_DC_RL1_CH_1__EMPTY       0x1F0405F4,0x00000000
#define LPM_MEM_DC_RL1_CH_1__FULL       0x1F0405F4,0xffffffff
#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1       0x1F0405F4,0xFF000000
#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1       0x1F0405F4,0x000F0000
#define LPM_MEM_DC_RL1_CH_1__COD_EOF_START_CHAN_1       0x1F0405F4,0x0000FF00
#define LPM_MEM_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1       0x1F0405F4,0x0000000F

#define LPM_MEM_DC_RL2_CH_1__ADDR                   0x1F0405F8
#define LPM_MEM_DC_RL2_CH_1__EMPTY       0x1F0405F8,0x00000000
#define LPM_MEM_DC_RL2_CH_1__FULL       0x1F0405F8,0xffffffff
#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1       0x1F0405F8,0xFF000000
#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1       0x1F0405F8,0x000F0000
#define LPM_MEM_DC_RL2_CH_1__COD_EOL_START_CHAN_1       0x1F0405F8,0x0000FF00
#define LPM_MEM_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1       0x1F0405F8,0x0000000F

#define LPM_MEM_DC_RL3_CH_1__ADDR                   0x1F0405FC
#define LPM_MEM_DC_RL3_CH_1__EMPTY       0x1F0405FC,0x00000000
#define LPM_MEM_DC_RL3_CH_1__FULL       0x1F0405FC,0xffffffff
#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1       0x1F0405FC,0xFF000000
#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1       0x1F0405FC,0x000F0000
#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1       0x1F0405FC,0x0000FF00
#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1       0x1F0405FC,0x0000000F

#define LPM_MEM_DC_RL4_CH_1__ADDR                   0x1F040600
#define LPM_MEM_DC_RL4_CH_1__EMPTY       0x1F040600,0x00000000
#define LPM_MEM_DC_RL4_CH_1__FULL       0x1F040600,0xffffffff
#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1       0x1F040600,0x0000FF00
#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1       0x1F040600,0x0000000F

#define LPM_MEM_DC_WR_CH_CONF_2__ADDR                   0x1F040604
#define LPM_MEM_DC_WR_CH_CONF_2__EMPTY       0x1F040604,0x00000000
#define LPM_MEM_DC_WR_CH_CONF_2__FULL       0x1F040604,0xffffffff
#define LPM_MEM_DC_WR_CH_CONF_2__PROG_START_TIME_2       0x1F040604,0x07FF0000
#define LPM_MEM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2       0x1F040604,0x00000100
#define LPM_MEM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2       0x1F040604,0x000000E0
#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DISP_ID_2       0x1F040604,0x00000018
#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DI_ID_2       0x1F040604,0x00000004
#define LPM_MEM_DC_WR_CH_CONF_2__W_SIZE_2       0x1F040604,0x00000003

#define LPM_MEM_DC_WR_CH_ADDR_2__ADDR                   0x1F040608
#define LPM_MEM_DC_WR_CH_ADDR_2__EMPTY       0x1F040608,0x00000000
#define LPM_MEM_DC_WR_CH_ADDR_2__FULL       0x1F040608,0xffffffff
#define LPM_MEM_DC_WR_CH_ADDR_2__ST_ADDR_2       0x1F040608,0x1FFFFFFF

#define LPM_MEM_DC_RL0_CH_2__ADDR                   0x1F04060C
#define LPM_MEM_DC_RL0_CH_2__EMPTY       0x1F04060C,0x00000000
#define LPM_MEM_DC_RL0_CH_2__FULL       0x1F04060C,0xffffffff
#define LPM_MEM_DC_RL0_CH_2__COD_NL_START_CHAN_2       0x1F04060C,0xFF000000
#define LPM_MEM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2       0x1F04060C,0x000F0000
#define LPM_MEM_DC_RL0_CH_2__COD_NF_START_CHAN_2       0x1F04060C,0x0000FF00
#define LPM_MEM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2       0x1F04060C,0x0000000F

#define LPM_MEM_DC_RL1_CH_2__ADDR                   0x1F040610
#define LPM_MEM_DC_RL1_CH_2__EMPTY       0x1F040610,0x00000000
#define LPM_MEM_DC_RL1_CH_2__FULL       0x1F040610,0xffffffff
#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2       0x1F040610,0xFF000000
#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2       0x1F040610,0x000F0000
#define LPM_MEM_DC_RL1_CH_2__COD_EOF_START_CHAN_2       0x1F040610,0x0000FF00
#define LPM_MEM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2       0x1F040610,0x0000000F

#define LPM_MEM_DC_RL2_CH_2__ADDR                   0x1F040614
#define LPM_MEM_DC_RL2_CH_2__EMPTY       0x1F040614,0x00000000
#define LPM_MEM_DC_RL2_CH_2__FULL       0x1F040614,0xffffffff
#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2       0x1F040614,0xFF000000
#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2       0x1F040614,0x000F0000
#define LPM_MEM_DC_RL2_CH_2__COD_EOL_START_CHAN_2       0x1F040614,0x0000FF00
#define LPM_MEM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2       0x1F040614,0x0000000F

#define LPM_MEM_DC_RL3_CH_2__ADDR                   0x1F040618
#define LPM_MEM_DC_RL3_CH_2__EMPTY       0x1F040618,0x00000000
#define LPM_MEM_DC_RL3_CH_2__FULL       0x1F040618,0xffffffff
#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2       0x1F040618,0xFF000000
#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2       0x1F040618,0x000F0000
#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2       0x1F040618,0x0000FF00
#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2       0x1F040618,0x0000000F

#define LPM_MEM_DC_RL4_CH_2__ADDR                   0x1F04061C
#define LPM_MEM_DC_RL4_CH_2__EMPTY       0x1F04061C,0x00000000
#define LPM_MEM_DC_RL4_CH_2__FULL       0x1F04061C,0xffffffff
#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2       0x1F04061C,0x0000FF00
#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2       0x1F04061C,0x0000000F

#define LPM_MEM_DC_CMD_CH_CONF_3__ADDR                   0x1F040620
#define LPM_MEM_DC_CMD_CH_CONF_3__EMPTY       0x1F040620,0x00000000
#define LPM_MEM_DC_CMD_CH_CONF_3__FULL       0x1F040620,0xffffffff
#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3       0x1F040620,0xFF000000
#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3       0x1F040620,0x0000FF00
#define LPM_MEM_DC_CMD_CH_CONF_3__W_SIZE_3       0x1F040620,0x00000003

#define LPM_MEM_DC_CMD_CH_CONF_4__ADDR                   0x1F040624
#define LPM_MEM_DC_CMD_CH_CONF_4__EMPTY       0x1F040624,0x00000000
#define LPM_MEM_DC_CMD_CH_CONF_4__FULL       0x1F040624,0xffffffff
#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4       0x1F040624,0xFF000000
#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4       0x1F040624,0x0000FF00
#define LPM_MEM_DC_CMD_CH_CONF_4__W_SIZE_4       0x1F040624,0x00000003

#define LPM_MEM_DC_WR_CH_CONF_5__ADDR                   0x1F040628
#define LPM_MEM_DC_WR_CH_CONF_5__EMPTY       0x1F040628,0x00000000
#define LPM_MEM_DC_WR_CH_CONF_5__FULL       0x1F040628,0xffffffff
#define LPM_MEM_DC_WR_CH_CONF_5__PROG_START_TIME_5       0x1F040628,0x07FF0000
#define LPM_MEM_DC_WR_CH_CONF_5__FIELD_MODE_5       0x1F040628,0x00000200
#define LPM_MEM_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5       0x1F040628,0x00000100
#define LPM_MEM_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5       0x1F040628,0x000000E0
#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DISP_ID_5       0x1F040628,0x00000018
#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DI_ID_5       0x1F040628,0x00000004
#define LPM_MEM_DC_WR_CH_CONF_5__W_SIZE_5       0x1F040628,0x00000003

#define LPM_MEM_DC_WR_CH_ADDR_5__ADDR                   0x1F04062C
#define LPM_MEM_DC_WR_CH_ADDR_5__EMPTY       0x1F04062C,0x00000000
#define LPM_MEM_DC_WR_CH_ADDR_5__FULL       0x1F04062C,0xffffffff
#define LPM_MEM_DC_WR_CH_ADDR_5__ST_ADDR_5       0x1F04062C,0x1FFFFFFF

#define LPM_MEM_DC_RL0_CH_5__ADDR                   0x1F040630
#define LPM_MEM_DC_RL0_CH_5__EMPTY       0x1F040630,0x00000000
#define LPM_MEM_DC_RL0_CH_5__FULL       0x1F040630,0xffffffff
#define LPM_MEM_DC_RL0_CH_5__COD_NL_START_CHAN_5       0x1F040630,0xFF000000
#define LPM_MEM_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5       0x1F040630,0x000F0000
#define LPM_MEM_DC_RL0_CH_5__COD_NF_START_CHAN_5       0x1F040630,0x0000FF00
#define LPM_MEM_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5       0x1F040630,0x0000000F

#define LPM_MEM_DC_RL1_CH_5__ADDR                   0x1F040634
#define LPM_MEM_DC_RL1_CH_5__EMPTY       0x1F040634,0x00000000
#define LPM_MEM_DC_RL1_CH_5__FULL       0x1F040634,0xffffffff
#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5       0x1F040634,0xFF000000
#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5       0x1F040634,0x000F0000
#define LPM_MEM_DC_RL1_CH_5__COD_EOF_START_CHAN_5       0x1F040634,0x0000FF00
#define LPM_MEM_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5       0x1F040634,0x0000000F

#define LPM_MEM_DC_RL2_CH_5__ADDR                   0x1F040638
#define LPM_MEM_DC_RL2_CH_5__EMPTY       0x1F040638,0x00000000
#define LPM_MEM_DC_RL2_CH_5__FULL       0x1F040638,0xffffffff
#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5       0x1F040638,0xFF000000
#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5       0x1F040638,0x000F0000
#define LPM_MEM_DC_RL2_CH_5__COD_EOL_START_CHAN_5       0x1F040638,0x0000FF00
#define LPM_MEM_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5       0x1F040638,0x0000000F

#define LPM_MEM_DC_RL3_CH_5__ADDR                   0x1F04063C
#define LPM_MEM_DC_RL3_CH_5__EMPTY       0x1F04063C,0x00000000
#define LPM_MEM_DC_RL3_CH_5__FULL       0x1F04063C,0xffffffff
#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5       0x1F04063C,0xFF000000
#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5       0x1F04063C,0x000F0000
#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5       0x1F04063C,0x0000FF00
#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5       0x1F04063C,0x0000000F

#define LPM_MEM_DC_RL4_CH_5__ADDR                   0x1F040640
#define LPM_MEM_DC_RL4_CH_5__EMPTY       0x1F040640,0x00000000
#define LPM_MEM_DC_RL4_CH_5__FULL       0x1F040640,0xffffffff
#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5       0x1F040640,0x0000FF00
#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5       0x1F040640,0x0000000F

#define LPM_MEM_DC_WR_CH_CONF_6__ADDR                   0x1F040644
#define LPM_MEM_DC_WR_CH_CONF_6__EMPTY       0x1F040644,0x00000000
#define LPM_MEM_DC_WR_CH_CONF_6__FULL       0x1F040644,0xffffffff
#define LPM_MEM_DC_WR_CH_CONF_6__PROG_START_TIME_6       0x1F040644,0x07FF0000
#define LPM_MEM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6       0x1F040644,0x00000100
#define LPM_MEM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6       0x1F040644,0x000000E0
#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DISP_ID_6       0x1F040644,0x00000018
#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DI_ID_6       0x1F040644,0x00000004
#define LPM_MEM_DC_WR_CH_CONF_6__W_SIZE_6       0x1F040644,0x00000003

#define LPM_MEM_DC_WR_CH_ADDR_6__ADDR                   0x1F040648
#define LPM_MEM_DC_WR_CH_ADDR_6__EMPTY       0x1F040648,0x00000000
#define LPM_MEM_DC_WR_CH_ADDR_6__FULL       0x1F040648,0xffffffff
#define LPM_MEM_DC_WR_CH_ADDR_6__ST_ADDR_6       0x1F040648,0x1FFFFFFF

#define LPM_MEM_DC_RL0_CH_6__ADDR                   0x1F04064C
#define LPM_MEM_DC_RL0_CH_6__EMPTY       0x1F04064C,0x00000000
#define LPM_MEM_DC_RL0_CH_6__FULL       0x1F04064C,0xffffffff
#define LPM_MEM_DC_RL0_CH_6__COD_NL_START_CHAN_6       0x1F04064C,0xFF000000
#define LPM_MEM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6       0x1F04064C,0x000F0000
#define LPM_MEM_DC_RL0_CH_6__COD_NF_START_CHAN_6       0x1F04064C,0x0000FF00
#define LPM_MEM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6       0x1F04064C,0x0000000F

#define LPM_MEM_DC_RL1_CH_6__ADDR                   0x1F040650
#define LPM_MEM_DC_RL1_CH_6__EMPTY       0x1F040650,0x00000000
#define LPM_MEM_DC_RL1_CH_6__FULL       0x1F040650,0xffffffff
#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6       0x1F040650,0xFF000000
#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6       0x1F040650,0x000F0000
#define LPM_MEM_DC_RL1_CH_6__COD_EOF_START_CHAN_6       0x1F040650,0x0000FF00
#define LPM_MEM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6       0x1F040650,0x0000000F

#define LPM_MEM_DC_RL2_CH_6__ADDR                   0x1F040654
#define LPM_MEM_DC_RL2_CH_6__EMPTY       0x1F040654,0x00000000
#define LPM_MEM_DC_RL2_CH_6__FULL       0x1F040654,0xffffffff
#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6       0x1F040654,0xFF000000
#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6       0x1F040654,0x000F0000
#define LPM_MEM_DC_RL2_CH_6__COD_EOL_START_CHAN_6       0x1F040654,0x0000FF00
#define LPM_MEM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6       0x1F040654,0x0000000F

#define LPM_MEM_DC_RL3_CH_6__ADDR                   0x1F040658
#define LPM_MEM_DC_RL3_CH_6__EMPTY       0x1F040658,0x00000000
#define LPM_MEM_DC_RL3_CH_6__FULL       0x1F040658,0xffffffff
#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6       0x1F040658,0xFF000000
#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6       0x1F040658,0x000F0000
#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6       0x1F040658,0x0000FF00
#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6       0x1F040658,0x0000000F

#define LPM_MEM_DC_RL4_CH_6__ADDR                   0x1F04065C
#define LPM_MEM_DC_RL4_CH_6__EMPTY       0x1F04065C,0x00000000
#define LPM_MEM_DC_RL4_CH_6__FULL       0x1F04065C,0xffffffff
#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6       0x1F04065C,0x0000FF00
#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6       0x1F04065C,0x0000000F

#define LPM_MEM_DC_WR_CH_CONF1_8__ADDR                   0x1F040660
#define LPM_MEM_DC_WR_CH_CONF1_8__EMPTY       0x1F040660,0x00000000
#define LPM_MEM_DC_WR_CH_CONF1_8__FULL       0x1F040660,0xffffffff
#define LPM_MEM_DC_WR_CH_CONF1_8__MCU_DISP_ID_8       0x1F040660,0x00000018
#define LPM_MEM_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8       0x1F040660,0x00000004
#define LPM_MEM_DC_WR_CH_CONF1_8__W_SIZE_8       0x1F040660,0x00000003

#define LPM_MEM_DC_WR_CH_CONF2_8__ADDR                   0x1F040664
#define LPM_MEM_DC_WR_CH_CONF2_8__EMPTY       0x1F040664,0x00000000
#define LPM_MEM_DC_WR_CH_CONF2_8__FULL       0x1F040664,0xffffffff
#define LPM_MEM_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8       0x1F040664,0x1FFFFFFF

#define LPM_MEM_DC_RL1_CH_8__ADDR                   0x1F040668
#define LPM_MEM_DC_RL1_CH_8__EMPTY       0x1F040668,0x00000000
#define LPM_MEM_DC_RL1_CH_8__FULL       0x1F040668,0xffffffff
#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1       0x1F040668,0xFF000000
#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0       0x1F040668,0x0000FF00
#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8       0x1F040668,0x0000000F

#define LPM_MEM_DC_RL2_CH_8__ADDR                   0x1F04066C
#define LPM_MEM_DC_RL2_CH_8__EMPTY       0x1F04066C,0x00000000
#define LPM_MEM_DC_RL2_CH_8__FULL       0x1F04066C,0xffffffff
#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1       0x1F04066C,0xFF000000
#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0       0x1F04066C,0x0000FF00
#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8       0x1F04066C,0x0000000F

#define LPM_MEM_DC_RL3_CH_8__ADDR                   0x1F040670
#define LPM_MEM_DC_RL3_CH_8__EMPTY       0x1F040670,0x00000000
#define LPM_MEM_DC_RL3_CH_8__FULL       0x1F040670,0xffffffff
#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1       0x1F040670,0xFF000000
#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0       0x1F040670,0x0000FF00
#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8       0x1F040670,0x0000000F

#define LPM_MEM_DC_RL4_CH_8__ADDR                   0x1F040674
#define LPM_MEM_DC_RL4_CH_8__EMPTY       0x1F040674,0x00000000
#define LPM_MEM_DC_RL4_CH_8__FULL       0x1F040674,0xffffffff
#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1       0x1F040674,0xFF000000
#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0       0x1F040674,0x0000FF00

#define LPM_MEM_DC_RL5_CH_8__ADDR                   0x1F040678
#define LPM_MEM_DC_RL5_CH_8__EMPTY       0x1F040678,0x00000000
#define LPM_MEM_DC_RL5_CH_8__FULL       0x1F040678,0xffffffff
#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1       0x1F040678,0xFF000000
#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0       0x1F040678,0x0000FF00

#define LPM_MEM_DC_RL6_CH_8__ADDR                   0x1F04067C
#define LPM_MEM_DC_RL6_CH_8__EMPTY       0x1F04067C,0x00000000
#define LPM_MEM_DC_RL6_CH_8__FULL       0x1F04067C,0xffffffff
#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1       0x1F04067C,0xFF000000
#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0       0x1F04067C,0x0000FF00

#define LPM_MEM_DC_WR_CH_CONF1_9__ADDR                   0x1F040680
#define LPM_MEM_DC_WR_CH_CONF1_9__EMPTY       0x1F040680,0x00000000
#define LPM_MEM_DC_WR_CH_CONF1_9__FULL       0x1F040680,0xffffffff
#define LPM_MEM_DC_WR_CH_CONF1_9__MCU_DISP_ID_9       0x1F040680,0x00000018
#define LPM_MEM_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9       0x1F040680,0x00000004
#define LPM_MEM_DC_WR_CH_CONF1_9__W_SIZE_9       0x1F040680,0x00000003

#define LPM_MEM_DC_WR_CH_CONF2_9__ADDR                   0x1F040684
#define LPM_MEM_DC_WR_CH_CONF2_9__EMPTY       0x1F040684,0x00000000
#define LPM_MEM_DC_WR_CH_CONF2_9__FULL       0x1F040684,0xffffffff
#define LPM_MEM_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9       0x1F040684,0x1FFFFFFF

#define LPM_MEM_DC_RL1_CH_9__ADDR                   0x1F040688
#define LPM_MEM_DC_RL1_CH_9__EMPTY       0x1F040688,0x00000000
#define LPM_MEM_DC_RL1_CH_9__FULL       0x1F040688,0xffffffff
#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1       0x1F040688,0xFF000000
#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0       0x1F040688,0x0000FF00
#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9       0x1F040688,0x0000000F

#define LPM_MEM_DC_RL2_CH_9__ADDR                   0x1F04068C
#define LPM_MEM_DC_RL2_CH_9__EMPTY       0x1F04068C,0x00000000
#define LPM_MEM_DC_RL2_CH_9__FULL       0x1F04068C,0xffffffff
#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1       0x1F04068C,0xFF000000
#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0       0x1F04068C,0x0000FF00
#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9       0x1F04068C,0x0000000F

#define LPM_MEM_DC_RL3_CH_9__ADDR                   0x1F040690
#define LPM_MEM_DC_RL3_CH_9__EMPTY       0x1F040690,0x00000000
#define LPM_MEM_DC_RL3_CH_9__FULL       0x1F040690,0xffffffff
#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1       0x1F040690,0xFF000000
#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0       0x1F040690,0x0000FF00
#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9       0x1F040690,0x0000000F

#define LPM_MEM_DC_RL4_CH_9__ADDR                   0x1F040694
#define LPM_MEM_DC_RL4_CH_9__EMPTY       0x1F040694,0x00000000
#define LPM_MEM_DC_RL4_CH_9__FULL       0x1F040694,0xffffffff
#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1       0x1F040694,0xFF000000
#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0       0x1F040694,0x0000FF00

#define LPM_MEM_DC_RL5_CH_9__ADDR                   0x1F040698
#define LPM_MEM_DC_RL5_CH_9__EMPTY       0x1F040698,0x00000000
#define LPM_MEM_DC_RL5_CH_9__FULL       0x1F040698,0xffffffff
#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1       0x1F040698,0xFF000000
#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0       0x1F040698,0x0000FF00

#define LPM_MEM_DC_RL6_CH_9__ADDR                   0x1F04069C
#define LPM_MEM_DC_RL6_CH_9__EMPTY       0x1F04069C,0x00000000
#define LPM_MEM_DC_RL6_CH_9__FULL       0x1F04069C,0xffffffff
#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1       0x1F04069C,0xFF000000
#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0       0x1F04069C,0x0000FF00

#define LPM_MEM_DC_GEN__ADDR                   0x1F0406A0
#define LPM_MEM_DC_GEN__EMPTY       0x1F0406A0,0x00000000
#define LPM_MEM_DC_GEN__FULL       0x1F0406A0,0xffffffff
#define LPM_MEM_DC_GEN__DC_BK_EN       0x1F0406A0,0x01000000
#define LPM_MEM_DC_GEN__DC_BKDIV       0x1F0406A0,0x00FF0000
#define LPM_MEM_DC_GEN__DC_CH5_TYPE       0x1F0406A0,0x00000100
#define LPM_MEM_DC_GEN__SYNC_PRIORITY_1       0x1F0406A0,0x00000080
#define LPM_MEM_DC_GEN__SYNC_PRIORITY_5       0x1F0406A0,0x00000040
#define LPM_MEM_DC_GEN__MASK4CHAN_5       0x1F0406A0,0x00000020
#define LPM_MEM_DC_GEN__MASK_EN       0x1F0406A0,0x00000010
#define LPM_MEM_DC_GEN__SYNC_1_6       0x1F0406A0,0x00000006

#define LPM_MEM_DC_DISP_CONF1_0__ADDR                0x1F0406A4
#define LPM_MEM_DC_DISP_CONF1_0__EMPTY               0x1F0406A4,0x00000000
#define LPM_MEM_DC_DISP_CONF1_0__FULL                0x1F0406A4,0xffffffff
#define LPM_MEM_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1F0406A4,0x00000080
#define LPM_MEM_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0   0x1F0406A4,0x00000040
#define LPM_MEM_DC_DISP_CONF1_0__ADDR_BE_L_INC_0     0x1F0406A4,0x00000030
#define LPM_MEM_DC_DISP_CONF1_0__ADDR_INCREMENT_0    0x1F0406A4,0x0000000C
#define LPM_MEM_DC_DISP_CONF1_0__DISP_TYP_0          0x1F0406A4,0x00000003

#define LPM_MEM_DC_DISP_CONF1_1__ADDR                0x1F0406A8
#define LPM_MEM_DC_DISP_CONF1_1__EMPTY               0x1F0406A8,0x00000000
#define LPM_MEM_DC_DISP_CONF1_1__FULL                0x1F0406A8,0xffffffff
#define LPM_MEM_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1F0406A8,0x00000080
#define LPM_MEM_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1   0x1F0406A8,0x00000040
#define LPM_MEM_DC_DISP_CONF1_1__ADDR_BE_L_INC_1     0x1F0406A8,0x00000030
#define LPM_MEM_DC_DISP_CONF1_1__ADDR_INCREMENT_1    0x1F0406A8,0x0000000C
#define LPM_MEM_DC_DISP_CONF1_1__DISP_TYP_1          0x1F0406A8,0x00000003

#define LPM_MEM_DC_DISP_CONF1_2__ADDR                0x1F0406AC
#define LPM_MEM_DC_DISP_CONF1_2__EMPTY               0x1F0406AC,0x00000000
#define LPM_MEM_DC_DISP_CONF1_2__FULL                0x1F0406AC,0xffffffff
#define LPM_MEM_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1F0406AC,0x00000080
#define LPM_MEM_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2   0x1F0406AC,0x00000040
#define LPM_MEM_DC_DISP_CONF1_2__ADDR_BE_L_INC_2     0x1F0406AC,0x00000030
#define LPM_MEM_DC_DISP_CONF1_2__ADDR_INCREMENT_2    0x1F0406AC,0x0000000C
#define LPM_MEM_DC_DISP_CONF1_2__DISP_TYP_2          0x1F0406AC,0x00000003

#define LPM_MEM_DC_DISP_CONF1_3__ADDR                0x1F0406B0
#define LPM_MEM_DC_DISP_CONF1_3__EMPTY               0x1F0406B0,0x00000000
#define LPM_MEM_DC_DISP_CONF1_3__FULL                0x1F0406B0,0xffffffff
#define LPM_MEM_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1F0406B0,0x00000080
#define LPM_MEM_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3   0x1F0406B0,0x00000040
#define LPM_MEM_DC_DISP_CONF1_3__ADDR_BE_L_INC_3     0x1F0406B0,0x00000030
#define LPM_MEM_DC_DISP_CONF1_3__ADDR_INCREMENT_3    0x1F0406B0,0x0000000C
#define LPM_MEM_DC_DISP_CONF1_3__DISP_TYP_3          0x1F0406B0,0x00000003

#define LPM_MEM_DC_DISP_CONF2_0__ADDR                   0x1F0406B4
#define LPM_MEM_DC_DISP_CONF2_0__EMPTY       0x1F0406B4,0x00000000
#define LPM_MEM_DC_DISP_CONF2_0__FULL       0x1F0406B4,0xffffffff
#define LPM_MEM_DC_DISP_CONF2_0__SL_0       0x1F0406B4,0x1FFFFFFF

#define LPM_MEM_DC_DISP_CONF2_1__ADDR                   0x1F0406B8
#define LPM_MEM_DC_DISP_CONF2_1__EMPTY       0x1F0406B8,0x00000000
#define LPM_MEM_DC_DISP_CONF2_1__FULL       0x1F0406B8,0xffffffff
#define LPM_MEM_DC_DISP_CONF2_1__SL_1       0x1F0406B8,0x1FFFFFFF

#define LPM_MEM_DC_DISP_CONF2_2__ADDR                   0x1F0406BC
#define LPM_MEM_DC_DISP_CONF2_2__EMPTY       0x1F0406BC,0x00000000
#define LPM_MEM_DC_DISP_CONF2_2__FULL       0x1F0406BC,0xffffffff
#define LPM_MEM_DC_DISP_CONF2_2__SL_2       0x1F0406BC,0x1FFFFFFF

#define LPM_MEM_DC_DISP_CONF2_3__ADDR                   0x1F0406C0
#define LPM_MEM_DC_DISP_CONF2_3__EMPTY       0x1F0406C0,0x00000000
#define LPM_MEM_DC_DISP_CONF2_3__FULL       0x1F0406C0,0xffffffff
#define LPM_MEM_DC_DISP_CONF2_3__SL_3       0x1F0406C0,0x1FFFFFFF

#define LPM_MEM_DC_DI0_CONF_1__ADDR                   0x1F0406C4
#define LPM_MEM_DC_DI0_CONF_1__EMPTY       0x1F0406C4,0x00000000
#define LPM_MEM_DC_DI0_CONF_1__FULL       0x1F0406C4,0xffffffff
#define LPM_MEM_DC_DI0_CONF_1__DI_READ_DATA_MASK_0       0x1F0406C4,0xFFFFFFFF

#define LPM_MEM_DC_DI0_CONF_2__ADDR                   0x1F0406C8
#define LPM_MEM_DC_DI0_CONF_2__EMPTY       0x1F0406C8,0x00000000
#define LPM_MEM_DC_DI0_CONF_2__FULL       0x1F0406C8,0xffffffff
#define LPM_MEM_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0       0x1F0406C8,0xFFFFFFFF

#define LPM_MEM_DC_DI1_CONF_1__ADDR                   0x1F0406CC
#define LPM_MEM_DC_DI1_CONF_1__EMPTY       0x1F0406CC,0x00000000
#define LPM_MEM_DC_DI1_CONF_1__FULL       0x1F0406CC,0xffffffff
#define LPM_MEM_DC_DI1_CONF_1__DI_READ_DATA_MASK_1       0x1F0406CC,0xFFFFFFFF

#define LPM_MEM_DC_DI1_CONF_2__ADDR                   0x1F0406D0
#define LPM_MEM_DC_DI1_CONF_2__EMPTY       0x1F0406D0,0x00000000
#define LPM_MEM_DC_DI1_CONF_2__FULL       0x1F0406D0,0xffffffff
#define LPM_MEM_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1       0x1F0406D0,0xFFFFFFFF

#define LPM_MEM_DC_MAP_CONF_0__ADDR                   0x1F0406D4
#define LPM_MEM_DC_MAP_CONF_0__EMPTY       0x1F0406D4,0x00000000
#define LPM_MEM_DC_MAP_CONF_0__FULL       0x1F0406D4,0xffffffff
#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1       0x1F0406D4,0x7C000000
#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1       0x1F0406D4,0x03E00000
#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1       0x1F0406D4,0x001F0000
#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0       0x1F0406D4,0x00007C00
#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0       0x1F0406D4,0x000003E0
#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0       0x1F0406D4,0x0000001F

#define LPM_MEM_DC_MAP_CONF_1__ADDR                   0x1F0406D8
#define LPM_MEM_DC_MAP_CONF_1__EMPTY       0x1F0406D8,0x00000000
#define LPM_MEM_DC_MAP_CONF_1__FULL       0x1F0406D8,0xffffffff
#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3       0x1F0406D8,0x7C000000
#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3       0x1F0406D8,0x03E00000
#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3       0x1F0406D8,0x001F0000
#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2       0x1F0406D8,0x00007C00
#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2       0x1F0406D8,0x000003E0
#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2       0x1F0406D8,0x0000001F

#define LPM_MEM_DC_MAP_CONF_2__ADDR                   0x1F0406DC
#define LPM_MEM_DC_MAP_CONF_2__EMPTY       0x1F0406DC,0x00000000
#define LPM_MEM_DC_MAP_CONF_2__FULL       0x1F0406DC,0xffffffff
#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5       0x1F0406DC,0x7C000000
#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5       0x1F0406DC,0x03E00000
#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5       0x1F0406DC,0x001F0000
#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4       0x1F0406DC,0x00007C00
#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4       0x1F0406DC,0x000003E0
#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4       0x1F0406DC,0x0000001F

#define LPM_MEM_DC_MAP_CONF_3__ADDR                   0x1F0406E0
#define LPM_MEM_DC_MAP_CONF_3__EMPTY       0x1F0406E0,0x00000000
#define LPM_MEM_DC_MAP_CONF_3__FULL       0x1F0406E0,0xffffffff
#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7       0x1F0406E0,0x7C000000
#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7       0x1F0406E0,0x03E00000
#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7       0x1F0406E0,0x001F0000
#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6       0x1F0406E0,0x00007C00
#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6       0x1F0406E0,0x000003E0
#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6       0x1F0406E0,0x0000001F

#define LPM_MEM_DC_MAP_CONF_4__ADDR                   0x1F0406E4
#define LPM_MEM_DC_MAP_CONF_4__EMPTY       0x1F0406E4,0x00000000
#define LPM_MEM_DC_MAP_CONF_4__FULL       0x1F0406E4,0xffffffff
#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9       0x1F0406E4,0x7C000000
#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9       0x1F0406E4,0x03E00000
#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9       0x1F0406E4,0x001F0000
#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8       0x1F0406E4,0x00007C00
#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8       0x1F0406E4,0x000003E0
#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8       0x1F0406E4,0x0000001F

#define LPM_MEM_DC_MAP_CONF_5__ADDR                   0x1F0406E8
#define LPM_MEM_DC_MAP_CONF_5__EMPTY       0x1F0406E8,0x00000000
#define LPM_MEM_DC_MAP_CONF_5__FULL       0x1F0406E8,0xffffffff
#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11       0x1F0406E8,0x7C000000
#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11       0x1F0406E8,0x03E00000
#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11       0x1F0406E8,0x001F0000
#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10       0x1F0406E8,0x00007C00
#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10       0x1F0406E8,0x000003E0
#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10       0x1F0406E8,0x0000001F

#define LPM_MEM_DC_MAP_CONF_6__ADDR                   0x1F0406EC
#define LPM_MEM_DC_MAP_CONF_6__EMPTY       0x1F0406EC,0x00000000
#define LPM_MEM_DC_MAP_CONF_6__FULL       0x1F0406EC,0xffffffff
#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13       0x1F0406EC,0x7C000000
#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13       0x1F0406EC,0x03E00000
#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13       0x1F0406EC,0x001F0000
#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12       0x1F0406EC,0x00007C00
#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12       0x1F0406EC,0x000003E0
#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12       0x1F0406EC,0x0000001F

#define LPM_MEM_DC_MAP_CONF_7__ADDR                   0x1F0406F0
#define LPM_MEM_DC_MAP_CONF_7__EMPTY       0x1F0406F0,0x00000000
#define LPM_MEM_DC_MAP_CONF_7__FULL       0x1F0406F0,0xffffffff
#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15       0x1F0406F0,0x7C000000
#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15       0x1F0406F0,0x03E00000
#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15       0x1F0406F0,0x001F0000
#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14       0x1F0406F0,0x00007C00
#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14       0x1F0406F0,0x000003E0
#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14       0x1F0406F0,0x0000001F

#define LPM_MEM_DC_MAP_CONF_8__ADDR                   0x1F0406F4
#define LPM_MEM_DC_MAP_CONF_8__EMPTY       0x1F0406F4,0x00000000
#define LPM_MEM_DC_MAP_CONF_8__FULL       0x1F0406F4,0xffffffff
#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17       0x1F0406F4,0x7C000000
#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17       0x1F0406F4,0x03E00000
#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17       0x1F0406F4,0x001F0000
#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16       0x1F0406F4,0x00007C00
#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16       0x1F0406F4,0x000003E0
#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16       0x1F0406F4,0x0000001F

#define LPM_MEM_DC_MAP_CONF_9__ADDR                   0x1F0406F8
#define LPM_MEM_DC_MAP_CONF_9__EMPTY       0x1F0406F8,0x00000000
#define LPM_MEM_DC_MAP_CONF_9__FULL       0x1F0406F8,0xffffffff
#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19       0x1F0406F8,0x7C000000
#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19       0x1F0406F8,0x03E00000
#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19       0x1F0406F8,0x001F0000
#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18       0x1F0406F8,0x00007C00
#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18       0x1F0406F8,0x000003E0
#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18       0x1F0406F8,0x0000001F

#define LPM_MEM_DC_MAP_CONF_10__ADDR                   0x1F0406FC
#define LPM_MEM_DC_MAP_CONF_10__EMPTY       0x1F0406FC,0x00000000
#define LPM_MEM_DC_MAP_CONF_10__FULL       0x1F0406FC,0xffffffff
#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21       0x1F0406FC,0x7C000000
#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21       0x1F0406FC,0x03E00000
#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21       0x1F0406FC,0x001F0000
#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20       0x1F0406FC,0x00007C00
#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20       0x1F0406FC,0x000003E0
#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20       0x1F0406FC,0x0000001F

#define LPM_MEM_DC_MAP_CONF_11__ADDR                   0x1F040700
#define LPM_MEM_DC_MAP_CONF_11__EMPTY       0x1F040700,0x00000000
#define LPM_MEM_DC_MAP_CONF_11__FULL       0x1F040700,0xffffffff
#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23       0x1F040700,0x7C000000
#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23       0x1F040700,0x03E00000
#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23       0x1F040700,0x001F0000
#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22       0x1F040700,0x00007C00
#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22       0x1F040700,0x000003E0
#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22       0x1F040700,0x0000001F

#define LPM_MEM_DC_MAP_CONF_12__ADDR                   0x1F040704
#define LPM_MEM_DC_MAP_CONF_12__EMPTY       0x1F040704,0x00000000
#define LPM_MEM_DC_MAP_CONF_12__FULL       0x1F040704,0xffffffff
#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25       0x1F040704,0x7C000000
#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25       0x1F040704,0x03E00000
#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25       0x1F040704,0x001F0000
#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24       0x1F040704,0x00007C00
#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24       0x1F040704,0x000003E0
#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24       0x1F040704,0x0000001F

#define LPM_MEM_DC_MAP_CONF_13__ADDR                   0x1F040708
#define LPM_MEM_DC_MAP_CONF_13__EMPTY       0x1F040708,0x00000000
#define LPM_MEM_DC_MAP_CONF_13__FULL       0x1F040708,0xffffffff
#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27       0x1F040708,0x7C000000
#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27       0x1F040708,0x03E00000
#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27       0x1F040708,0x001F0000
#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26       0x1F040708,0x00007C00
#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26       0x1F040708,0x000003E0
#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26       0x1F040708,0x0000001F

#define LPM_MEM_DC_MAP_CONF_14__ADDR                   0x1F04070C
#define LPM_MEM_DC_MAP_CONF_14__EMPTY       0x1F04070C,0x00000000
#define LPM_MEM_DC_MAP_CONF_14__FULL       0x1F04070C,0xffffffff
#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29       0x1F04070C,0x7C000000
#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29       0x1F04070C,0x03E00000
#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29       0x1F04070C,0x001F0000
#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28       0x1F04070C,0x00007C00
#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28       0x1F04070C,0x000003E0
#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28       0x1F04070C,0x0000001F

#define LPM_MEM_DC_MAP_CONF_15__ADDR                   0x1F040710
#define LPM_MEM_DC_MAP_CONF_15__EMPTY       0x1F040710,0x00000000
#define LPM_MEM_DC_MAP_CONF_15__FULL       0x1F040710,0xffffffff
#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_1       0x1F040710,0x1F000000
#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_1       0x1F040710,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_0       0x1F040710,0x00001F00
#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_0       0x1F040710,0x000000FF

#define LPM_MEM_DC_MAP_CONF_16__ADDR                   0x1F040714
#define LPM_MEM_DC_MAP_CONF_16__EMPTY       0x1F040714,0x00000000
#define LPM_MEM_DC_MAP_CONF_16__FULL       0x1F040714,0xffffffff
#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_3       0x1F040714,0x1F000000
#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_3       0x1F040714,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_2       0x1F040714,0x00001F00
#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_2       0x1F040714,0x000000FF

#define LPM_MEM_DC_MAP_CONF_17__ADDR                   0x1F040718
#define LPM_MEM_DC_MAP_CONF_17__EMPTY       0x1F040718,0x00000000
#define LPM_MEM_DC_MAP_CONF_17__FULL       0x1F040718,0xffffffff
#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_5       0x1F040718,0x1F000000
#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_5       0x1F040718,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_4       0x1F040718,0x00001F00
#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_4       0x1F040718,0x000000FF

#define LPM_MEM_DC_MAP_CONF_18__ADDR                   0x1F04071C
#define LPM_MEM_DC_MAP_CONF_18__EMPTY       0x1F04071C,0x00000000
#define LPM_MEM_DC_MAP_CONF_18__FULL       0x1F04071C,0xffffffff
#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_7       0x1F04071C,0x1F000000
#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_7       0x1F04071C,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_6       0x1F04071C,0x00001F00
#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_6       0x1F04071C,0x000000FF

#define LPM_MEM_DC_MAP_CONF_19__ADDR                   0x1F040720
#define LPM_MEM_DC_MAP_CONF_19__EMPTY       0x1F040720,0x00000000
#define LPM_MEM_DC_MAP_CONF_19__FULL       0x1F040720,0xffffffff
#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_9       0x1F040720,0x1F000000
#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_9       0x1F040720,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_8       0x1F040720,0x00001F00
#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_8       0x1F040720,0x000000FF

#define LPM_MEM_DC_MAP_CONF_20__ADDR                   0x1F040724
#define LPM_MEM_DC_MAP_CONF_20__EMPTY       0x1F040724,0x00000000
#define LPM_MEM_DC_MAP_CONF_20__FULL       0x1F040724,0xffffffff
#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_11       0x1F040724,0x1F000000
#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_11       0x1F040724,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_10       0x1F040724,0x00001F00
#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_10       0x1F040724,0x000000FF

#define LPM_MEM_DC_MAP_CONF_21__ADDR                   0x1F040728
#define LPM_MEM_DC_MAP_CONF_21__EMPTY       0x1F040728,0x00000000
#define LPM_MEM_DC_MAP_CONF_21__FULL       0x1F040728,0xffffffff
#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_13       0x1F040728,0x1F000000
#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_13       0x1F040728,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_12       0x1F040728,0x00001F00
#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_12       0x1F040728,0x000000FF

#define LPM_MEM_DC_MAP_CONF_22__ADDR                   0x1F04072C
#define LPM_MEM_DC_MAP_CONF_22__EMPTY       0x1F04072C,0x00000000
#define LPM_MEM_DC_MAP_CONF_22__FULL       0x1F04072C,0xffffffff
#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_15       0x1F04072C,0x1F000000
#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_15       0x1F04072C,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_14       0x1F04072C,0x00001F00
#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_14       0x1F04072C,0x000000FF

#define LPM_MEM_DC_MAP_CONF_23__ADDR                   0x1F040730
#define LPM_MEM_DC_MAP_CONF_23__EMPTY       0x1F040730,0x00000000
#define LPM_MEM_DC_MAP_CONF_23__FULL       0x1F040730,0xffffffff
#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_17       0x1F040730,0x1F000000
#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_17       0x1F040730,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_16       0x1F040730,0x00001F00
#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_16       0x1F040730,0x000000FF

#define LPM_MEM_DC_MAP_CONF_24__ADDR                   0x1F040734
#define LPM_MEM_DC_MAP_CONF_24__EMPTY       0x1F040734,0x00000000
#define LPM_MEM_DC_MAP_CONF_24__FULL       0x1F040734,0xffffffff
#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_19       0x1F040734,0x1F000000
#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_19       0x1F040734,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_18       0x1F040734,0x00001F00
#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_18       0x1F040734,0x000000FF

#define LPM_MEM_DC_MAP_CONF_25__ADDR                   0x1F040738
#define LPM_MEM_DC_MAP_CONF_25__EMPTY       0x1F040738,0x00000000
#define LPM_MEM_DC_MAP_CONF_25__FULL       0x1F040738,0xffffffff
#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_21       0x1F040738,0x1F000000
#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_21       0x1F040738,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_20       0x1F040738,0x00001F00
#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_20       0x1F040738,0x000000FF

#define LPM_MEM_DC_MAP_CONF_26__ADDR                   0x1F04073C
#define LPM_MEM_DC_MAP_CONF_26__EMPTY       0x1F04073C,0x00000000
#define LPM_MEM_DC_MAP_CONF_26__FULL       0x1F04073C,0xffffffff
#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_23       0x1F04073C,0x1F000000
#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_23       0x1F04073C,0x00FF0000
#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_22       0x1F04073C,0x00001F00
#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_22       0x1F04073C,0x000000FF

#define LPM_MEM_DC_UGDE0_0__ADDR                   0x1F040740
#define LPM_MEM_DC_UGDE0_0__EMPTY       0x1F040740,0x00000000
#define LPM_MEM_DC_UGDE0_0__FULL       0x1F040740,0xffffffff
#define LPM_MEM_DC_UGDE0_0__NF_NL_0       0x1F040740,0x18000000
#define LPM_MEM_DC_UGDE0_0__AUTORESTART_0       0x1F040740,0x04000000
#define LPM_MEM_DC_UGDE0_0__ODD_EN_0       0x1F040740,0x02000000
#define LPM_MEM_DC_UGDE0_0__COD_ODD_START_0       0x1F040740,0x00FF0000
#define LPM_MEM_DC_UGDE0_0__COD_EV_START_0       0x1F040740,0x0000FF00
#define LPM_MEM_DC_UGDE0_0__COD_EV_PRIORITY_0       0x1F040740,0x00000078
#define LPM_MEM_DC_UGDE0_0__ID_CODED_0       0x1F040740,0x00000007

#define LPM_MEM_DC_UGDE0_1__ADDR                   0x1F040744
#define LPM_MEM_DC_UGDE0_1__EMPTY       0x1F040744,0x00000000
#define LPM_MEM_DC_UGDE0_1__FULL       0x1F040744,0xffffffff
#define LPM_MEM_DC_UGDE0_1__STEP_0       0x1F040744,0x1FFFFFFF

#define LPM_MEM_DC_UGDE0_2__ADDR                   0x1F040748
#define LPM_MEM_DC_UGDE0_2__EMPTY       0x1F040748,0x00000000
#define LPM_MEM_DC_UGDE0_2__FULL       0x1F040748,0xffffffff
#define LPM_MEM_DC_UGDE0_2__OFFSET_DT_0       0x1F040748,0x1FFFFFFF

#define LPM_MEM_DC_UGDE0_3__ADDR                   0x1F04074C
#define LPM_MEM_DC_UGDE0_3__EMPTY       0x1F04074C,0x00000000
#define LPM_MEM_DC_UGDE0_3__FULL       0x1F04074C,0xffffffff
#define LPM_MEM_DC_UGDE0_3__STEP_REPEAT_0       0x1F04074C,0x1FFFFFFF

#define LPM_MEM_DC_UGDE1_0__ADDR                   0x1F040750
#define LPM_MEM_DC_UGDE1_0__EMPTY       0x1F040750,0x00000000
#define LPM_MEM_DC_UGDE1_0__FULL       0x1F040750,0xffffffff
#define LPM_MEM_DC_UGDE1_0__NF_NL_1       0x1F040750,0x18000000
#define LPM_MEM_DC_UGDE1_0__AUTORESTART_1       0x1F040750,0x04000000
#define LPM_MEM_DC_UGDE1_0__ODD_EN_1       0x1F040750,0x02000000
#define LPM_MEM_DC_UGDE1_0__COD_ODD_START_1       0x1F040750,0x00FF0000
#define LPM_MEM_DC_UGDE1_0__COD_EV_START_1       0x1F040750,0x00007F80
#define LPM_MEM_DC_UGDE1_0__COD_EV_PRIORITY_1       0x1F040750,0x00000078
#define LPM_MEM_DC_UGDE1_0__ID_CODED_1       0x1F040750,0x00000007

#define LPM_MEM_DC_UGDE1_1__ADDR                   0x1F040754
#define LPM_MEM_DC_UGDE1_1__EMPTY       0x1F040754,0x00000000
#define LPM_MEM_DC_UGDE1_1__FULL       0x1F040754,0xffffffff
#define LPM_MEM_DC_UGDE1_1__STEP_1       0x1F040754,0x1FFFFFFF

#define LPM_MEM_DC_UGDE1_2__ADDR                   0x1F040758
#define LPM_MEM_DC_UGDE1_2__EMPTY       0x1F040758,0x00000000
#define LPM_MEM_DC_UGDE1_2__FULL       0x1F040758,0xffffffff
#define LPM_MEM_DC_UGDE1_2__OFFSET_DT_1       0x1F040758,0x1FFFFFFF

#define LPM_MEM_DC_UGDE1_3__ADDR                   0x1F04075C
#define LPM_MEM_DC_UGDE1_3__EMPTY       0x1F04075C,0x00000000
#define LPM_MEM_DC_UGDE1_3__FULL       0x1F04075C,0xffffffff
#define LPM_MEM_DC_UGDE1_3__STEP_REPEAT_1       0x1F04075C,0x1FFFFFFF

#define LPM_MEM_DC_UGDE2_0__ADDR                   0x1F040760
#define LPM_MEM_DC_UGDE2_0__EMPTY       0x1F040760,0x00000000
#define LPM_MEM_DC_UGDE2_0__FULL       0x1F040760,0xffffffff
#define LPM_MEM_DC_UGDE2_0__NF_NL_2       0x1F040760,0x18000000
#define LPM_MEM_DC_UGDE2_0__AUTORESTART_2       0x1F040760,0x04000000
#define LPM_MEM_DC_UGDE2_0__ODD_EN_2       0x1F040760,0x02000000
#define LPM_MEM_DC_UGDE2_0__COD_ODD_START_2       0x1F040760,0x00FF0000
#define LPM_MEM_DC_UGDE2_0__COD_EV_START_2       0x1F040760,0x00007F80
#define LPM_MEM_DC_UGDE2_0__COD_EV_PRIORITY_2       0x1F040760,0x00000078
#define LPM_MEM_DC_UGDE2_0__ID_CODED_2       0x1F040760,0x00000007

#define LPM_MEM_DC_UGDE2_1__ADDR                   0x1F040764
#define LPM_MEM_DC_UGDE2_1__EMPTY       0x1F040764,0x00000000
#define LPM_MEM_DC_UGDE2_1__FULL       0x1F040764,0xffffffff
#define LPM_MEM_DC_UGDE2_1__STEP_2       0x1F040764,0x1FFFFFFF

#define LPM_MEM_DC_UGDE2_2__ADDR                   0x1F040768
#define LPM_MEM_DC_UGDE2_2__EMPTY       0x1F040768,0x00000000
#define LPM_MEM_DC_UGDE2_2__FULL       0x1F040768,0xffffffff
#define LPM_MEM_DC_UGDE2_2__OFFSET_DT_2       0x1F040768,0x1FFFFFFF

#define LPM_MEM_DC_UGDE2_3__ADDR                   0x1F04076C
#define LPM_MEM_DC_UGDE2_3__EMPTY       0x1F04076C,0x00000000
#define LPM_MEM_DC_UGDE2_3__FULL       0x1F04076C,0xffffffff
#define LPM_MEM_DC_UGDE2_3__STEP_REPEAT_2       0x1F04076C,0x1FFFFFFF

#define LPM_MEM_DC_UGDE3_0__ADDR                   0x1F040770
#define LPM_MEM_DC_UGDE3_0__EMPTY       0x1F040770,0x00000000
#define LPM_MEM_DC_UGDE3_0__FULL       0x1F040770,0xffffffff
#define LPM_MEM_DC_UGDE3_0__NF_NL_3       0x1F040770,0x18000000
#define LPM_MEM_DC_UGDE3_0__AUTORESTART_3       0x1F040770,0x04000000
#define LPM_MEM_DC_UGDE3_0__ODD_EN_3       0x1F040770,0x02000000
#define LPM_MEM_DC_UGDE3_0__COD_ODD_START_3       0x1F040770,0x00FF0000
#define LPM_MEM_DC_UGDE3_0__COD_EV_START_3       0x1F040770,0x00007F80
#define LPM_MEM_DC_UGDE3_0__COD_EV_PRIORITY_3       0x1F040770,0x00000078
#define LPM_MEM_DC_UGDE3_0__ID_CODED_3       0x1F040770,0x00000007

#define LPM_MEM_DC_UGDE3_1__ADDR                   0x1F040774
#define LPM_MEM_DC_UGDE3_1__EMPTY       0x1F040774,0x00000000
#define LPM_MEM_DC_UGDE3_1__FULL       0x1F040774,0xffffffff
#define LPM_MEM_DC_UGDE3_1__STEP_3       0x1F040774,0x1FFFFFFF

#define LPM_MEM_DC_UGDE3_2__ADDR                   0x1F040778
#define LPM_MEM_DC_UGDE3_2__EMPTY       0x1F040778,0x00000000
#define LPM_MEM_DC_UGDE3_2__FULL       0x1F040778,0xffffffff
#define LPM_MEM_DC_UGDE3_2__OFFSET_DT_3       0x1F040778,0x1FFFFFFF

#define LPM_MEM_DC_UGDE3_3__ADDR                   0x1F04077C
#define LPM_MEM_DC_UGDE3_3__EMPTY       0x1F04077C,0x00000000
#define LPM_MEM_DC_UGDE3_3__FULL       0x1F04077C,0xffffffff
#define LPM_MEM_DC_UGDE3_3__STEP_REPEAT_3       0x1F04077C,0x1FFFFFFF

#define LPM_MEM_DC_LLA0__ADDR                   0x1F040780
#define LPM_MEM_DC_LLA0__EMPTY       0x1F040780,0x00000000
#define LPM_MEM_DC_LLA0__FULL       0x1F040780,0xffffffff
#define LPM_MEM_DC_LLA0__MCU_RS_3_0       0x1F040780,0xFF000000
#define LPM_MEM_DC_LLA0__MCU_RS_2_0       0x1F040780,0x00FF0000
#define LPM_MEM_DC_LLA0__MCU_RS_1_0       0x1F040780,0x0000FF00
#define LPM_MEM_DC_LLA0__MCU_RS_0_0       0x1F040780,0x000000FF

#define LPM_MEM_DC_LLA1__ADDR                   0x1F040784
#define LPM_MEM_DC_LLA1__EMPTY       0x1F040784,0x00000000
#define LPM_MEM_DC_LLA1__FULL       0x1F040784,0xffffffff
#define LPM_MEM_DC_LLA1__MCU_RS_3_1       0x1F040784,0xFF000000
#define LPM_MEM_DC_LLA1__MCU_RS_2_1       0x1F040784,0x00FF0000
#define LPM_MEM_DC_LLA1__MCU_RS_1_1       0x1F040784,0x0000FF00
#define LPM_MEM_DC_LLA1__MCU_RS_0_1       0x1F040784,0x000000FF

#define LPM_MEM_DC_R_LLA0__ADDR                   0x1F040788
#define LPM_MEM_DC_R_LLA0__EMPTY       0x1F040788,0x00000000
#define LPM_MEM_DC_R_LLA0__FULL       0x1F040788,0xffffffff
#define LPM_MEM_DC_R_LLA0__MCU_RS_R_3_0       0x1F040788,0xFF000000
#define LPM_MEM_DC_R_LLA0__MCU_RS_R_2_0       0x1F040788,0x00FF0000
#define LPM_MEM_DC_R_LLA0__MCU_RS_R_1_0       0x1F040788,0x0000FF00
#define LPM_MEM_DC_R_LLA0__MCU_RS_R_0_0       0x1F040788,0x000000FF

#define LPM_MEM_DC_R_LLA1__ADDR                   0x1F04078C
#define LPM_MEM_DC_R_LLA1__EMPTY       0x1F04078C,0x00000000
#define LPM_MEM_DC_R_LLA1__FULL       0x1F04078C,0xffffffff
#define LPM_MEM_DC_R_LLA1__MCU_RS_R_3_1       0x1F04078C,0xFF000000
#define LPM_MEM_DC_R_LLA1__MCU_RS_R_2_1       0x1F04078C,0x00FF0000
#define LPM_MEM_DC_R_LLA1__MCU_RS_R_1_1       0x1F04078C,0x0000FF00
#define LPM_MEM_DC_R_LLA1__MCU_RS_R_0_1       0x1F04078C,0x000000FF

#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ADDR                   0x1F040790
#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__EMPTY       0x1F040790,0x00000000
#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__FULL       0x1F040790,0xffffffff
#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT       0x1F040790,0x1FFFFFFF

#define LPM_MEM_IDMAC_CONF__ADDR                   0x1F040794
#define LPM_MEM_IDMAC_CONF__EMPTY       0x1F040794,0x00000000
#define LPM_MEM_IDMAC_CONF__FULL       0x1F040794,0xffffffff
#define LPM_MEM_IDMAC_CONF__P_ENDIAN       0x1F040794,0x00010000
#define LPM_MEM_IDMAC_CONF__RDI          0x1F040794,0x00000020
#define LPM_MEM_IDMAC_CONF__WIDPT       0x1F040794,0x00000018
#define LPM_MEM_IDMAC_CONF__MAX_REQ_READ       0x1F040794,0x00000007

#define LPM_MEM_IDMAC_CH_EN_1__ADDR                   0x1F040798
#define LPM_MEM_IDMAC_CH_EN_1__EMPTY       0x1F040798,0x00000000
#define LPM_MEM_IDMAC_CH_EN_1__FULL       0x1F040798,0xffffffff
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_31       0x1F040798,0x80000000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_29       0x1F040798,0x20000000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_28       0x1F040798,0x10000000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_27       0x1F040798,0x08000000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_24       0x1F040798,0x01000000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_23       0x1F040798,0x00800000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_22       0x1F040798,0x00400000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_21       0x1F040798,0x00200000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_20       0x1F040798,0x00100000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_18       0x1F040798,0x00040000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_17       0x1F040798,0x00020000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_15       0x1F040798,0x00008000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_14       0x1F040798,0x00004000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_12       0x1F040798,0x00001000
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_11       0x1F040798,0x00000800
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_7       0x1F040798,0x00000080
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_6       0x1F040798,0x00000040
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_5       0x1F040798,0x00000020
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_4       0x1F040798,0x00000010
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_3       0x1F040798,0x00000008
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_2       0x1F040798,0x00000004
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_1       0x1F040798,0x00000002
#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_0       0x1F040798,0x00000001

#define LPM_MEM_IDMAC_CH_EN_2__ADDR                   0x1F04079C
#define LPM_MEM_IDMAC_CH_EN_2__EMPTY       0x1F04079C,0x00000000
#define LPM_MEM_IDMAC_CH_EN_2__FULL       0x1F04079C,0xffffffff
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_52       0x1F04079C,0x00100000
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_51       0x1F04079C,0x00080000
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_50       0x1F04079C,0x00040000
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_49       0x1F04079C,0x00020000
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_48       0x1F04079C,0x00010000
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_47       0x1F04079C,0x00008000
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_46       0x1F04079C,0x00004000
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_45       0x1F04079C,0x00002000
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_44       0x1F04079C,0x00001000
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_43       0x1F04079C,0x00000800
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_42       0x1F04079C,0x00000400
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_41       0x1F04079C,0x00000200
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_40       0x1F04079C,0x00000100
#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_33       0x1F04079C,0x00000002

#define LPM_MEM_IDMAC_SEP_ALPHA__ADDR                   0x1F0407A0
#define LPM_MEM_IDMAC_SEP_ALPHA__EMPTY       0x1F0407A0,0x00000000
#define LPM_MEM_IDMAC_SEP_ALPHA__FULL       0x1F0407A0,0xffffffff
#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29       0x1F0407A0,0x20000000
#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27       0x1F0407A0,0x08000000
#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24       0x1F0407A0,0x01000000
#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23       0x1F0407A0,0x00800000
#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15       0x1F0407A0,0x00008000
#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14       0x1F0407A0,0x00004000

#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__ADDR                   0x1F0407A4
#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__EMPTY       0x1F0407A4,0x00000000
#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__FULL       0x1F0407A4,0xffffffff
#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29       0x1F0407A4,0x20000000
#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24       0x1F0407A4,0x01000000
#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23       0x1F0407A4,0x00800000

#define LPM_MEM_IDMAC_CH_PRI_1__ADDR                   0x1F0407A8
#define LPM_MEM_IDMAC_CH_PRI_1__EMPTY       0x1F0407A8,0x00000000
#define LPM_MEM_IDMAC_CH_PRI_1__FULL       0x1F0407A8,0xffffffff
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29       0x1F0407A8,0x20000000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28       0x1F0407A8,0x10000000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27       0x1F0407A8,0x08000000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24       0x1F0407A8,0x01000000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23       0x1F0407A8,0x00800000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22       0x1F0407A8,0x00400000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21       0x1F0407A8,0x00200000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20       0x1F0407A8,0x00100000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15       0x1F0407A8,0x00008000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14       0x1F0407A8,0x00004000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12       0x1F0407A8,0x00001000
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11       0x1F0407A8,0x00000800
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_7       0x1F0407A8,0x00000080
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_6       0x1F0407A8,0x00000040
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_5       0x1F0407A8,0x00000020
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_4       0x1F0407A8,0x00000010
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_3       0x1F0407A8,0x00000008
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_2       0x1F0407A8,0x00000004
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_1       0x1F0407A8,0x00000002
#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_0       0x1F0407A8,0x00000001

#define LPM_MEM_IDMAC_CH_PRI_2__ADDR                   0x1F0407AC
#define LPM_MEM_IDMAC_CH_PRI_2__EMPTY       0x1F0407AC,0x00000000
#define LPM_MEM_IDMAC_CH_PRI_2__FULL       0x1F0407AC,0xffffffff
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50       0x1F0407AC,0x00040000
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49       0x1F0407AC,0x00020000
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48       0x1F0407AC,0x00010000
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47       0x1F0407AC,0x00008000
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46       0x1F0407AC,0x00004000
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45       0x1F0407AC,0x00002000
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44       0x1F0407AC,0x00001000
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43       0x1F0407AC,0x00000800
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42       0x1F0407AC,0x00000400
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41       0x1F0407AC,0x00000200
#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40       0x1F0407AC,0x00000100

#define LPM_MEM_IDMAC_WM_EN_1__ADDR                   0x1F0407B0
#define LPM_MEM_IDMAC_WM_EN_1__EMPTY       0x1F0407B0,0x00000000
#define LPM_MEM_IDMAC_WM_EN_1__FULL       0x1F0407B0,0xffffffff
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_29       0x1F0407B0,0x20000000
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_28       0x1F0407B0,0x10000000
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_27       0x1F0407B0,0x08000000
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_24       0x1F0407B0,0x01000000
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_23       0x1F0407B0,0x00800000
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_14       0x1F0407B0,0x00004000
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_12       0x1F0407B0,0x00001000
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_3       0x1F0407B0,0x00000008
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_2       0x1F0407B0,0x00000004
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_1       0x1F0407B0,0x00000002
#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_0       0x1F0407B0,0x00000001

#define LPM_MEM_IDMAC_WM_EN_2__ADDR                   0x1F0407B4
#define LPM_MEM_IDMAC_WM_EN_2__EMPTY       0x1F0407B4,0x00000000
#define LPM_MEM_IDMAC_WM_EN_2__FULL       0x1F0407B4,0xffffffff
#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_44       0x1F0407B4,0x00001000
#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_43       0x1F0407B4,0x00000800
#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_42       0x1F0407B4,0x00000400
#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_41       0x1F0407B4,0x00000200
#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_40       0x1F0407B4,0x00000100

#define LPM_MEM_IDMAC_LOCK_EN_2__ADDR                   0x1F0407B8
#define LPM_MEM_IDMAC_LOCK_EN_2__EMPTY       0x1F0407B8,0x00000000
#define LPM_MEM_IDMAC_LOCK_EN_2__FULL       0x1F0407B8,0xffffffff
#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50       0x1F0407B8,0x00040000
#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49       0x1F0407B8,0x00020000
#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48       0x1F0407B8,0x00010000
#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47       0x1F0407B8,0x00008000
#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46       0x1F0407B8,0x00004000
#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45       0x1F0407B8,0x00002000

#define LPM_MEM_IDMAC_SUB_ADDR_0__ADDR                   0x1F0407BC
#define LPM_MEM_IDMAC_SUB_ADDR_0__EMPTY       0x1F0407BC,0x00000000
#define LPM_MEM_IDMAC_SUB_ADDR_0__FULL       0x1F0407BC,0xffffffff
#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_7       0x1F0407BC,0x7F000000
#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_6       0x1F0407BC,0x007F0000
#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_5       0x1F0407BC,0x00007F00
#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_4       0x1F0407BC,0x0000007F

#define LPM_MEM_IDMAC_SUB_ADDR_1__ADDR                   0x1F0407C0
#define LPM_MEM_IDMAC_SUB_ADDR_1__EMPTY       0x1F0407C0,0x00000000
#define LPM_MEM_IDMAC_SUB_ADDR_1__FULL       0x1F0407C0,0xffffffff
#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33       0x1F0407C0,0x7F000000
#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29       0x1F0407C0,0x007F0000
#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24       0x1F0407C0,0x00007F00
#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23       0x1F0407C0,0x0000007F

#define LPM_MEM_IDMAC_SUB_ADDR_2__ADDR                   0x1F0407C4
#define LPM_MEM_IDMAC_SUB_ADDR_2__EMPTY       0x1F0407C4,0x00000000
#define LPM_MEM_IDMAC_SUB_ADDR_2__FULL       0x1F0407C4,0xffffffff
#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52       0x1F0407C4,0x007F0000
#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51       0x1F0407C4,0x00007F00
#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41       0x1F0407C4,0x0000007F

#define LPM_MEM_IDMAC_BNDM_EN_1__ADDR                   0x1F0407C8
#define LPM_MEM_IDMAC_BNDM_EN_1__EMPTY       0x1F0407C8,0x00000000
#define LPM_MEM_IDMAC_BNDM_EN_1__FULL       0x1F0407C8,0xffffffff
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22       0x1F0407C8,0x00400000
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21       0x1F0407C8,0x00200000
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20       0x1F0407C8,0x00100000
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12       0x1F0407C8,0x00001000
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11       0x1F0407C8,0x00000800
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_5       0x1F0407C8,0x00000020
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_3       0x1F0407C8,0x00000008
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_2       0x1F0407C8,0x00000004
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_1       0x1F0407C8,0x00000002
#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_0       0x1F0407C8,0x00000001

#define LPM_MEM_IDMAC_BNDM_EN_2__ADDR                   0x1F0407CC
#define LPM_MEM_IDMAC_BNDM_EN_2__EMPTY       0x1F0407CC,0x00000000
#define LPM_MEM_IDMAC_BNDM_EN_2__FULL       0x1F0407CC,0xffffffff
#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50       0x1F0407CC,0x00040000
#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49       0x1F0407CC,0x00020000
#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48       0x1F0407CC,0x00010000
#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47       0x1F0407CC,0x00008000
#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46       0x1F0407CC,0x00004000
#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45       0x1F0407CC,0x00002000

#define LPM_MEM_IDMAC_SC_CORD__ADDR                   0x1F0407D0
#define LPM_MEM_IDMAC_SC_CORD__EMPTY       0x1F0407D0,0x00000000
#define LPM_MEM_IDMAC_SC_CORD__FULL       0x1F0407D0,0xffffffff
#define LPM_MEM_IDMAC_SC_CORD__SX0       0x1F0407D0,0x0FFF0000
#define LPM_MEM_IDMAC_SC_CORD__SY0       0x1F0407D0,0x000007FF

#define LPM_MEM_IPU_CONF__ADDR             0x1F0407D4
#define LPM_MEM_IPU_CONF__EMPTY            0x1F0407D4,0x00000000
#define LPM_MEM_IPU_CONF__FULL             0x1F0407D4,0xffffffff
#define LPM_MEM_IPU_CONF__CSI_SEL          0x1F0407D4,0x80000000
#define LPM_MEM_IPU_CONF__IC_INPUT         0x1F0407D4,0x40000000
#define LPM_MEM_IPU_CONF__CSI1_DATA_SOURCE 0x1F0407D4,0x20000000
#define LPM_MEM_IPU_CONF__CSI0_DATA_SOURCE 0x1F0407D4,0x10000000
#define LPM_MEM_IPU_CONF__IC_DMFC_SYNC     0x1F0407D4,0x04000000
#define LPM_MEM_IPU_CONF__IC_DMFC_SEL      0x1F0407D4,0x02000000
#define LPM_MEM_IPU_CONF__ISP_DOUBLE_FLOW  0x1F0407D4,0x01000000
#define LPM_MEM_IPU_CONF__IDMAC_DISABLE    0x1F0407D4,0x00400000
#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_ON   0x1F0407D4,0x00200000
#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_MODE 0x1F0407D4,0x001F0000
#define LPM_MEM_IPU_CONF__IPU_HSP_CLK_EN   0x1F0407D4,0x00008000
#define LPM_MEM_IPU_CONF__SISG_EN          0x1F0407D4,0x00000800
#define LPM_MEM_IPU_CONF__DMFC_EN          0x1F0407D4,0x00000400
#define LPM_MEM_IPU_CONF__DC_EN            0x1F0407D4,0x00000200
#define LPM_MEM_IPU_CONF__SMFC_EN          0x1F0407D4,0x00000100
#define LPM_MEM_IPU_CONF__DI1_EN           0x1F0407D4,0x00000080
#define LPM_MEM_IPU_CONF__DI0_EN           0x1F0407D4,0x00000040
#define LPM_MEM_IPU_CONF__DP_EN            0x1F0407D4,0x00000020
#define LPM_MEM_IPU_CONF__ISP_EN           0x1F0407D4,0x00000010
#define LPM_MEM_IPU_CONF__IRT_EN           0x1F0407D4,0x00000008
#define LPM_MEM_IPU_CONF__IC_EN            0x1F0407D4,0x00000004
#define LPM_MEM_IPU_CONF__CSI1_EN          0x1F0407D4,0x00000002
#define LPM_MEM_IPU_CONF__CSI0_EN          0x1F0407D4,0x00000001

#define LPM_MEM_SISG_CTRL0__ADDR                   0x1F0407D8
#define LPM_MEM_SISG_CTRL0__EMPTY       0x1F0407D8,0x00000000
#define LPM_MEM_SISG_CTRL0__FULL       0x1F0407D8,0xffffffff
#define LPM_MEM_SISG_CTRL0__EXT_ACTV       0x1F0407D8,0x40000000
#define LPM_MEM_SISG_CTRL0__MCU_ACTV_TRIG       0x1F0407D8,0x20000000
#define LPM_MEM_SISG_CTRL0__VAL_STOP_SISG_COUNTER       0x1F0407D8,0x1FFFFFF0
#define LPM_MEM_SISG_CTRL0__NO_OF_VSYNC       0x1F0407D8,0x0000000E
#define LPM_MEM_SISG_CTRL0__VSYNC_RESET_COUNTER       0x1F0407D8,0x00000001

#define LPM_MEM_SISG_CTRL1__ADDR                   0x1F0407DC
#define LPM_MEM_SISG_CTRL1__EMPTY       0x1F0407DC,0x00000000
#define LPM_MEM_SISG_CTRL1__FULL       0x1F0407DC,0xffffffff
#define LPM_MEM_SISG_CTRL1__SISG_OUT_POL       0x1F0407DC,0x00003F00
#define LPM_MEM_SISG_CTRL1__SISG_STROBE_CNT       0x1F0407DC,0x0000001F

#define LPM_MEM_SISG_SET_1__ADDR                   0x1F0407E0
#define LPM_MEM_SISG_SET_1__EMPTY       0x1F0407E0,0x00000000
#define LPM_MEM_SISG_SET_1__FULL       0x1F0407E0,0xffffffff
#define LPM_MEM_SISG_SET_1__SISG_SET_1       0x1F0407E0,0x01FFFFFF

#define LPM_MEM_SISG_SET_2__ADDR                   0x1F0407E4
#define LPM_MEM_SISG_SET_2__EMPTY       0x1F0407E4,0x00000000
#define LPM_MEM_SISG_SET_2__FULL       0x1F0407E4,0xffffffff
#define LPM_MEM_SISG_SET_2__SISG_SET_2       0x1F0407E4,0x01FFFFFF

#define LPM_MEM_SISG_SET_3__ADDR                   0x1F0407E8
#define LPM_MEM_SISG_SET_3__EMPTY       0x1F0407E8,0x00000000
#define LPM_MEM_SISG_SET_3__FULL       0x1F0407E8,0xffffffff
#define LPM_MEM_SISG_SET_3__SISG_SET_3       0x1F0407E8,0x01FFFFFF

#define LPM_MEM_SISG_SET_4__ADDR                   0x1F0407EC
#define LPM_MEM_SISG_SET_4__EMPTY       0x1F0407EC,0x00000000
#define LPM_MEM_SISG_SET_4__FULL       0x1F0407EC,0xffffffff
#define LPM_MEM_SISG_SET_4__SISG_SET_4       0x1F0407EC,0x01FFFFFF

#define LPM_MEM_SISG_SET_5__ADDR                   0x1F0407F0
#define LPM_MEM_SISG_SET_5__EMPTY       0x1F0407F0,0x00000000
#define LPM_MEM_SISG_SET_5__FULL       0x1F0407F0,0xffffffff
#define LPM_MEM_SISG_SET_5__SISG_SET_5       0x1F0407F0,0x01FFFFFF

#define LPM_MEM_SISG_SET_6__ADDR                   0x1F0407F4
#define LPM_MEM_SISG_SET_6__EMPTY       0x1F0407F4,0x00000000
#define LPM_MEM_SISG_SET_6__FULL       0x1F0407F4,0xffffffff
#define LPM_MEM_SISG_SET_6__SISG_SET_6       0x1F0407F4,0x01FFFFFF

#define LPM_MEM_SISG_CLR_1__ADDR                   0x1F0407F8
#define LPM_MEM_SISG_CLR_1__EMPTY       0x1F0407F8,0x00000000
#define LPM_MEM_SISG_CLR_1__FULL       0x1F0407F8,0xffffffff
#define LPM_MEM_SISG_CLR_1__SISG_CLEAR_1       0x1F0407F8,0x01FFFFFF

#define LPM_MEM_SISG_CLR_2__ADDR                   0x1F0407FC
#define LPM_MEM_SISG_CLR_2__EMPTY       0x1F0407FC,0x00000000
#define LPM_MEM_SISG_CLR_2__FULL       0x1F0407FC,0xffffffff
#define LPM_MEM_SISG_CLR_2__SISG_CLEAR_2       0x1F0407FC,0x01FFFFFF

#define LPM_MEM_SISG_CLR_3__ADDR                   0x1F040800
#define LPM_MEM_SISG_CLR_3__EMPTY       0x1F040800,0x00000000
#define LPM_MEM_SISG_CLR_3__FULL       0x1F040800,0xffffffff
#define LPM_MEM_SISG_CLR_3__SISG_CLEAR_3       0x1F040800,0x01FFFFFF

#define LPM_MEM_SISG_CLR_4__ADDR                   0x1F040804
#define LPM_MEM_SISG_CLR_4__EMPTY       0x1F040804,0x00000000
#define LPM_MEM_SISG_CLR_4__FULL       0x1F040804,0xffffffff
#define LPM_MEM_SISG_CLR_4__SISG_CLEAR_4       0x1F040804,0x01FFFFFF

#define LPM_MEM_SISG_CLR_5__ADDR                   0x1F040808
#define LPM_MEM_SISG_CLR_5__EMPTY       0x1F040808,0x00000000
#define LPM_MEM_SISG_CLR_5__FULL       0x1F040808,0xffffffff
#define LPM_MEM_SISG_CLR_5__SISG_CLEAR_5       0x1F040808,0x01FFFFFF

#define LPM_MEM_SISG_CLR_6__ADDR                   0x1F04080C
#define LPM_MEM_SISG_CLR_6__EMPTY       0x1F04080C,0x00000000
#define LPM_MEM_SISG_CLR_6__FULL       0x1F04080C,0xffffffff
#define LPM_MEM_SISG_CLR_6__SISG_CLEAR_6       0x1F04080C,0x01FFFFFF

#define LPM_MEM_IPU_INT_CTRL_1__ADDR                   0x1F040810
#define LPM_MEM_IPU_INT_CTRL_1__EMPTY       0x1F040810,0x00000000
#define LPM_MEM_IPU_INT_CTRL_1__FULL       0x1F040810,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_31       0x1F040810,0x80000000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_29       0x1F040810,0x20000000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_28       0x1F040810,0x10000000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_27       0x1F040810,0x08000000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_24       0x1F040810,0x01000000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_23       0x1F040810,0x00800000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_22       0x1F040810,0x00400000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_21       0x1F040810,0x00200000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_20       0x1F040810,0x00100000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_18       0x1F040810,0x00040000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_17       0x1F040810,0x00020000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_15       0x1F040810,0x00008000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_14       0x1F040810,0x00004000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_12       0x1F040810,0x00001000
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_11       0x1F040810,0x00000800
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_7       0x1F040810,0x00000080
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_6       0x1F040810,0x00000040
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_5       0x1F040810,0x00000020
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_4       0x1F040810,0x00000010
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_3       0x1F040810,0x00000008
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_2       0x1F040810,0x00000004
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_1       0x1F040810,0x00000002
#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_0       0x1F040810,0x00000001

#define LPM_MEM_IPU_INT_CTRL_2__ADDR                   0x1F040814
#define LPM_MEM_IPU_INT_CTRL_2__EMPTY       0x1F040814,0x00000000
#define LPM_MEM_IPU_INT_CTRL_2__FULL       0x1F040814,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_52       0x1F040814,0x00100000
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_51       0x1F040814,0x00080000
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_50       0x1F040814,0x00040000
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_49       0x1F040814,0x00020000
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_48       0x1F040814,0x00010000
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_47       0x1F040814,0x00008000
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_46       0x1F040814,0x00004000
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_45       0x1F040814,0x00002000
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_44       0x1F040814,0x00001000
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_43       0x1F040814,0x00000800
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_42       0x1F040814,0x00000400
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_41       0x1F040814,0x00000200
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_40       0x1F040814,0x00000100
#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_33       0x1F040814,0x00000002

#define LPM_MEM_IPU_INT_CTRL_3__ADDR                   0x1F040818
#define LPM_MEM_IPU_INT_CTRL_3__EMPTY       0x1F040818,0x00000000
#define LPM_MEM_IPU_INT_CTRL_3__FULL       0x1F040818,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31       0x1F040818,0x80000000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29       0x1F040818,0x20000000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28       0x1F040818,0x10000000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27       0x1F040818,0x08000000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24       0x1F040818,0x01000000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23       0x1F040818,0x00800000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22       0x1F040818,0x00400000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21       0x1F040818,0x00200000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20       0x1F040818,0x00100000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18       0x1F040818,0x00040000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17       0x1F040818,0x00020000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15       0x1F040818,0x00008000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14       0x1F040818,0x00004000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12       0x1F040818,0x00001000
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11       0x1F040818,0x00000800
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_7       0x1F040818,0x00000080
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_6       0x1F040818,0x00000040
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_5       0x1F040818,0x00000020
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_4       0x1F040818,0x00000010
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_3       0x1F040818,0x00000008
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_2       0x1F040818,0x00000004
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_1       0x1F040818,0x00000002
#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_0       0x1F040818,0x00000001

#define LPM_MEM_IPU_INT_CTRL_4__ADDR                   0x1F04081C
#define LPM_MEM_IPU_INT_CTRL_4__EMPTY       0x1F04081C,0x00000000
#define LPM_MEM_IPU_INT_CTRL_4__FULL       0x1F04081C,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52       0x1F04081C,0x00100000
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51       0x1F04081C,0x00080000
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50       0x1F04081C,0x00040000
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49       0x1F04081C,0x00020000
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48       0x1F04081C,0x00010000
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47       0x1F04081C,0x00008000
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46       0x1F04081C,0x00004000
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45       0x1F04081C,0x00002000
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44       0x1F04081C,0x00001000
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43       0x1F04081C,0x00000800
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42       0x1F04081C,0x00000400
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41       0x1F04081C,0x00000200
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40       0x1F04081C,0x00000100
#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33       0x1F04081C,0x00000002

#define LPM_MEM_IPU_INT_CTRL_5__ADDR                   0x1F040820
#define LPM_MEM_IPU_INT_CTRL_5__EMPTY       0x1F040820,0x00000000
#define LPM_MEM_IPU_INT_CTRL_5__FULL       0x1F040820,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31       0x1F040820,0x80000000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29       0x1F040820,0x20000000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28       0x1F040820,0x10000000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27       0x1F040820,0x08000000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24       0x1F040820,0x01000000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23       0x1F040820,0x00800000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22       0x1F040820,0x00400000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21       0x1F040820,0x00200000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20       0x1F040820,0x00100000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18       0x1F040820,0x00040000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17       0x1F040820,0x00020000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15       0x1F040820,0x00008000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14       0x1F040820,0x00004000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12       0x1F040820,0x00001000
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11       0x1F040820,0x00000800
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_7       0x1F040820,0x00000080
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_6       0x1F040820,0x00000040
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_5       0x1F040820,0x00000020
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_4       0x1F040820,0x00000010
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_3       0x1F040820,0x00000008
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_2       0x1F040820,0x00000004
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_1       0x1F040820,0x00000002
#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_0       0x1F040820,0x00000001

#define LPM_MEM_IPU_INT_CTRL_6__ADDR                   0x1F040824
#define LPM_MEM_IPU_INT_CTRL_6__EMPTY       0x1F040824,0x00000000
#define LPM_MEM_IPU_INT_CTRL_6__FULL       0x1F040824,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52       0x1F040824,0x00100000
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51       0x1F040824,0x00080000
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50       0x1F040824,0x00040000
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49       0x1F040824,0x00020000
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48       0x1F040824,0x00010000
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47       0x1F040824,0x00008000
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46       0x1F040824,0x00004000
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45       0x1F040824,0x00002000
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44       0x1F040824,0x00001000
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43       0x1F040824,0x00000800
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42       0x1F040824,0x00000400
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41       0x1F040824,0x00000200
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40       0x1F040824,0x00000100
#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33       0x1F040824,0x00000002

#define LPM_MEM_IPU_INT_CTRL_7__ADDR            0x1F040828
#define LPM_MEM_IPU_INT_CTRL_7__EMPTY           0x1F040828,0x00000000
#define LPM_MEM_IPU_INT_CTRL_7__FULL            0x1F040828,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_31 0x1F040828,0x80000000
#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_29 0x1F040828,0x20000000
#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_28 0x1F040828,0x10000000
#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_27 0x1F040828,0x08000000
#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_24 0x1F040828,0x01000000
#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_23 0x1F040828,0x00800000

#define LPM_MEM_IPU_INT_CTRL_8__ADDR            0x1F04082C
#define LPM_MEM_IPU_INT_CTRL_8__EMPTY           0x1F04082C,0x00000000
#define LPM_MEM_IPU_INT_CTRL_8__FULL            0x1F04082C,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_52 0x1F04082C,0x00100000
#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_51 0x1F04082C,0x00080000
#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_44 0x1F04082C,0x00001000
#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_43 0x1F04082C,0x00000800
#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_42 0x1F04082C,0x00000400
#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_41 0x1F04082C,0x00000200
#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_33 0x1F04082C,0x00000002

#define LPM_MEM_IPU_INT_CTRL_9__ADDR                   0x1F040830
#define LPM_MEM_IPU_INT_CTRL_9__EMPTY       0x1F040830,0x00000000
#define LPM_MEM_IPU_INT_CTRL_9__FULL       0x1F040830,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_9__CSI1_PUPE_EN       0x1F040830,0x80000000
#define LPM_MEM_IPU_INT_CTRL_9__CSI0_PUPE_EN       0x1F040830,0x40000000
#define LPM_MEM_IPU_INT_CTRL_9__ISP_PUPE_EN       0x1F040830,0x20000000
#define LPM_MEM_IPU_INT_CTRL_9__IC_VF_BUF_OVF_EN       0x1F040830,0x10000000
#define LPM_MEM_IPU_INT_CTRL_9__IC_ENC_BUF_OVF_EN       0x1F040830,0x08000000
#define LPM_MEM_IPU_INT_CTRL_9__IC_BAYER_BUF_OVF_EN       0x1F040830,0x04000000

#define LPM_MEM_IPU_INT_CTRL_10__ADDR                   0x1F040834
#define LPM_MEM_IPU_INT_CTRL_10__EMPTY       0x1F040834,0x00000000
#define LPM_MEM_IPU_INT_CTRL_10__FULL       0x1F040834,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_10__AXIR_ERR_EN       0x1F040834,0x40000000
#define LPM_MEM_IPU_INT_CTRL_10__AXIW_ERR_EN       0x1F040834,0x20000000
#define LPM_MEM_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN       0x1F040834,0x10000000
#define LPM_MEM_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN       0x1F040834,0x04000000
#define LPM_MEM_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN       0x1F040834,0x02000000
#define LPM_MEM_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN       0x1F040834,0x01000000
#define LPM_MEM_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN       0x1F040834,0x00400000
#define LPM_MEM_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN       0x1F040834,0x00200000
#define LPM_MEM_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN       0x1F040834,0x00100000
#define LPM_MEM_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN       0x1F040834,0x00080000
#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN       0x1F040834,0x00040000
#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN       0x1F040834,0x00020000
#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN       0x1F040834,0x00010000
#define LPM_MEM_IPU_INT_CTRL_10__ISP_RAM_HIST_OF_EN       0x1F040834,0x00000020
#define LPM_MEM_IPU_INT_CTRL_10__ISP_RAM_ST_OF_EN       0x1F040834,0x00000010
#define LPM_MEM_IPU_INT_CTRL_10__SMFC3_FRM_LOST_EN       0x1F040834,0x00000008
#define LPM_MEM_IPU_INT_CTRL_10__SMFC2_FRM_LOST_EN       0x1F040834,0x00000004
#define LPM_MEM_IPU_INT_CTRL_10__SMFC1_FRM_LOST_EN       0x1F040834,0x00000002
#define LPM_MEM_IPU_INT_CTRL_10__SMFC0_FRM_LOST_EN       0x1F040834,0x00000001

#define LPM_MEM_IPU_INT_CTRL_11__ADDR                   0x1F040838
#define LPM_MEM_IPU_INT_CTRL_11__EMPTY       0x1F040838,0x00000000
#define LPM_MEM_IPU_INT_CTRL_11__FULL       0x1F040838,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22       0x1F040838,0x00400000
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21       0x1F040838,0x00200000
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20       0x1F040838,0x00100000
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12       0x1F040838,0x00001000
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11       0x1F040838,0x00000800
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_5       0x1F040838,0x00000020
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_3       0x1F040838,0x00000008
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_2       0x1F040838,0x00000004
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_1       0x1F040838,0x00000002
#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_0       0x1F040838,0x00000001

#define LPM_MEM_IPU_INT_CTRL_12__ADDR                   0x1F04083C
#define LPM_MEM_IPU_INT_CTRL_12__EMPTY       0x1F04083C,0x00000000
#define LPM_MEM_IPU_INT_CTRL_12__FULL       0x1F04083C,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50       0x1F04083C,0x00040000
#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49       0x1F04083C,0x00020000
#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48       0x1F04083C,0x00010000
#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47       0x1F04083C,0x00008000
#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46       0x1F04083C,0x00004000
#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45       0x1F04083C,0x00002000

#define LPM_MEM_IPU_INT_CTRL_13__ADDR                   0x1F040840
#define LPM_MEM_IPU_INT_CTRL_13__EMPTY       0x1F040840,0x00000000
#define LPM_MEM_IPU_INT_CTRL_13__FULL       0x1F040840,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_31       0x1F040840,0x80000000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_29       0x1F040840,0x20000000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_28       0x1F040840,0x10000000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_27       0x1F040840,0x08000000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_24       0x1F040840,0x01000000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_23       0x1F040840,0x00800000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_22       0x1F040840,0x00400000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_21       0x1F040840,0x00200000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_20       0x1F040840,0x00100000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_18       0x1F040840,0x00040000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_17       0x1F040840,0x00020000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_15       0x1F040840,0x00008000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_14       0x1F040840,0x00004000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_12       0x1F040840,0x00001000
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_11       0x1F040840,0x00000800
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_7       0x1F040840,0x00000080
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_6       0x1F040840,0x00000040
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_5       0x1F040840,0x00000020
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_4       0x1F040840,0x00000010
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_3       0x1F040840,0x00000008
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_2       0x1F040840,0x00000004
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_1       0x1F040840,0x00000002
#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_0       0x1F040840,0x00000001

#define LPM_MEM_IPU_INT_CTRL_14__ADDR                   0x1F040844
#define LPM_MEM_IPU_INT_CTRL_14__EMPTY       0x1F040844,0x00000000
#define LPM_MEM_IPU_INT_CTRL_14__FULL       0x1F040844,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_52       0x1F040844,0x00100000
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_51       0x1F040844,0x00080000
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_50       0x1F040844,0x00040000
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_49       0x1F040844,0x00020000
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_48       0x1F040844,0x00010000
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_47       0x1F040844,0x00008000
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_46       0x1F040844,0x00004000
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_45       0x1F040844,0x00002000
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_44       0x1F040844,0x00001000
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_43       0x1F040844,0x00000800
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_42       0x1F040844,0x00000400
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_41       0x1F040844,0x00000200
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_40       0x1F040844,0x00000100
#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_33       0x1F040844,0x00000002

#define LPM_MEM_IPU_INT_CTRL_15__ADDR                   0x1F040848
#define LPM_MEM_IPU_INT_CTRL_15__EMPTY       0x1F040848,0x00000000
#define LPM_MEM_IPU_INT_CTRL_15__FULL       0x1F040848,0xffffffff
#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN       0x1F040848,0x80000000
#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN       0x1F040848,0x40000000
#define LPM_MEM_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN       0x1F040848,0x20000000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN       0x1F040848,0x10000000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN       0x1F040848,0x08000000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN       0x1F040848,0x04000000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN       0x1F040848,0x02000000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN       0x1F040848,0x01000000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN       0x1F040848,0x00800000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN       0x1F040848,0x00400000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN       0x1F040848,0x00200000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN       0x1F040848,0x00100000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN       0x1F040848,0x00080000
#define LPM_MEM_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN       0x1F040848,0x00040000
#define LPM_MEM_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN       0x1F040848,0x00020000
#define LPM_MEM_IPU_INT_CTRL_15__DC_DP_START_EN       0x1F040848,0x00010000
#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN       0x1F040848,0x00008000
#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN       0x1F040848,0x00004000
#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_6_EN       0x1F040848,0x00002000
#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_4_EN       0x1F040848,0x00001000
#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_3_EN       0x1F040848,0x00000800
#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_2_EN       0x1F040848,0x00000400
#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_1_EN       0x1F040848,0x00000200
#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_0_EN       0x1F040848,0x00000100
#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN       0x1F040848,0x00000080
#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_BRAKE_EN       0x1F040848,0x00000040
#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_END_EN       0x1F040848,0x00000020
#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_START_EN       0x1F040848,0x00000010
#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_END_EN       0x1F040848,0x00000008
#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_START_EN       0x1F040848,0x00000004
#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN       0x1F040848,0x00000002
#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN       0x1F040848,0x00000001

#define LPM_MEM_IPU_SDMA_EVENT_1__ADDR                   0x1F04084C
#define LPM_MEM_IPU_SDMA_EVENT_1__EMPTY       0x1F04084C,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_1__FULL       0x1F04084C,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31       0x1F04084C,0x80000000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29       0x1F04084C,0x20000000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28       0x1F04084C,0x10000000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27       0x1F04084C,0x08000000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24       0x1F04084C,0x01000000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23       0x1F04084C,0x00800000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22       0x1F04084C,0x00400000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21       0x1F04084C,0x00200000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20       0x1F04084C,0x00100000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18       0x1F04084C,0x00040000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17       0x1F04084C,0x00020000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15       0x1F04084C,0x00008000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14       0x1F04084C,0x00004000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12       0x1F04084C,0x00001000
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11       0x1F04084C,0x00000800
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_7       0x1F04084C,0x00000080
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_6       0x1F04084C,0x00000040
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_5       0x1F04084C,0x00000020
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_4       0x1F04084C,0x00000010
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_3       0x1F04084C,0x00000008
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_2       0x1F04084C,0x00000004
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_1       0x1F04084C,0x00000002
#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_0       0x1F04084C,0x00000001

#define LPM_MEM_IPU_SDMA_EVENT_2__ADDR                   0x1F040850
#define LPM_MEM_IPU_SDMA_EVENT_2__EMPTY       0x1F040850,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_2__FULL       0x1F040850,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52       0x1F040850,0x00100000
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51       0x1F040850,0x00080000
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50       0x1F040850,0x00040000
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49       0x1F040850,0x00020000
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48       0x1F040850,0x00010000
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47       0x1F040850,0x00008000
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46       0x1F040850,0x00004000
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45       0x1F040850,0x00002000
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44       0x1F040850,0x00001000
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43       0x1F040850,0x00000800
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42       0x1F040850,0x00000400
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41       0x1F040850,0x00000200
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40       0x1F040850,0x00000100
#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33       0x1F040850,0x00000002

#define LPM_MEM_IPU_SDMA_EVENT_3__ADDR                   0x1F040854
#define LPM_MEM_IPU_SDMA_EVENT_3__EMPTY       0x1F040854,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_3__FULL       0x1F040854,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31       0x1F040854,0x80000000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29       0x1F040854,0x20000000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28       0x1F040854,0x10000000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27       0x1F040854,0x08000000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24       0x1F040854,0x01000000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23       0x1F040854,0x00800000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22       0x1F040854,0x00400000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21       0x1F040854,0x00200000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20       0x1F040854,0x00100000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18       0x1F040854,0x00040000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17       0x1F040854,0x00020000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15       0x1F040854,0x00008000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14       0x1F040854,0x00004000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12       0x1F040854,0x00001000
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11       0x1F040854,0x00000800
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_7       0x1F040854,0x00000080
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_6       0x1F040854,0x00000040
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_5       0x1F040854,0x00000020
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_4       0x1F040854,0x00000010
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_3       0x1F040854,0x00000008
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_2       0x1F040854,0x00000004
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_1       0x1F040854,0x00000002
#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_0       0x1F040854,0x00000001

#define LPM_MEM_IPU_SDMA_EVENT_4__ADDR                   0x1F040858
#define LPM_MEM_IPU_SDMA_EVENT_4__EMPTY       0x1F040858,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_4__FULL       0x1F040858,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52       0x1F040858,0x00100000
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51       0x1F040858,0x00080000
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50       0x1F040858,0x00040000
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49       0x1F040858,0x00020000
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48       0x1F040858,0x00010000
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47       0x1F040858,0x00008000
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46       0x1F040858,0x00004000
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45       0x1F040858,0x00002000
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44       0x1F040858,0x00001000
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43       0x1F040858,0x00000800
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42       0x1F040858,0x00000400
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41       0x1F040858,0x00000200
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40       0x1F040858,0x00000100
#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33       0x1F040858,0x00000002

#define LPM_MEM_IPU_SDMA_EVENT_7__ADDR                 0x1F04085C
#define LPM_MEM_IPU_SDMA_EVENT_7__EMPTY                0x1F04085C,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_7__FULL                 0x1F04085C,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31 0x1F04085C,0x80000000
#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29 0x1F04085C,0x20000000
#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28 0x1F04085C,0x10000000
#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27 0x1F04085C,0x08000000
#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24 0x1F04085C,0x01000000
#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23 0x1F04085C,0x00800000

#define LPM_MEM_IPU_SDMA_EVENT_8__ADDR                 0x1F040860
#define LPM_MEM_IPU_SDMA_EVENT_8__EMPTY                0x1F040860,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_8__FULL                 0x1F040860,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52 0x1F040860,0x00100000
#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51 0x1F040860,0x00080000
#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44 0x1F040860,0x00001000
#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43 0x1F040860,0x00000800
#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42 0x1F040860,0x00000400
#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41 0x1F040860,0x00000200
#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32 0x1F040860,0x00000002

#define LPM_MEM_IPU_SDMA_EVENT_11__ADDR                   0x1F040864
#define LPM_MEM_IPU_SDMA_EVENT_11__EMPTY       0x1F040864,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_11__FULL       0x1F040864,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22       0x1F040864,0x00400000
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21       0x1F040864,0x00200000
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20       0x1F040864,0x00100000
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12       0x1F040864,0x00001000
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11       0x1F040864,0x00000800
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_5       0x1F040864,0x00000020
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_3       0x1F040864,0x00000008
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_2       0x1F040864,0x00000004
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_1       0x1F040864,0x00000002
#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_0       0x1F040864,0x00000001

#define LPM_MEM_IPU_SDMA_EVENT_12__ADDR                   0x1F040868
#define LPM_MEM_IPU_SDMA_EVENT_12__EMPTY       0x1F040868,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_12__FULL       0x1F040868,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50       0x1F040868,0x00040000
#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49       0x1F040868,0x00020000
#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48       0x1F040868,0x00010000
#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47       0x1F040868,0x00008000
#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46       0x1F040868,0x00004000
#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45       0x1F040868,0x00002000

#define LPM_MEM_IPU_SDMA_EVENT_13__ADDR                   0x1F04086C
#define LPM_MEM_IPU_SDMA_EVENT_13__EMPTY       0x1F04086C,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_13__FULL       0x1F04086C,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31       0x1F04086C,0x80000000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29       0x1F04086C,0x20000000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28       0x1F04086C,0x10000000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27       0x1F04086C,0x08000000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24       0x1F04086C,0x01000000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23       0x1F04086C,0x00800000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22       0x1F04086C,0x00400000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21       0x1F04086C,0x00200000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20       0x1F04086C,0x00100000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18       0x1F04086C,0x00040000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17       0x1F04086C,0x00020000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15       0x1F04086C,0x00008000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14       0x1F04086C,0x00004000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12       0x1F04086C,0x00001000
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11       0x1F04086C,0x00000800
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_7       0x1F04086C,0x00000080
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_6       0x1F04086C,0x00000040
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_5       0x1F04086C,0x00000020
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_4       0x1F04086C,0x00000010
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_3       0x1F04086C,0x00000008
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_2       0x1F04086C,0x00000004
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_1       0x1F04086C,0x00000002
#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_0       0x1F04086C,0x00000001

#define LPM_MEM_IPU_SDMA_EVENT_14__ADDR                   0x1F040870
#define LPM_MEM_IPU_SDMA_EVENT_14__EMPTY       0x1F040870,0x00000000
#define LPM_MEM_IPU_SDMA_EVENT_14__FULL       0x1F040870,0xffffffff
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52       0x1F040870,0x00100000
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51       0x1F040870,0x00080000
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50       0x1F040870,0x00040000
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49       0x1F040870,0x00020000
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48       0x1F040870,0x00010000
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47       0x1F040870,0x00008000
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46       0x1F040870,0x00004000
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45       0x1F040870,0x00002000
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44       0x1F040870,0x00001000
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43       0x1F040870,0x00000800
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42       0x1F040870,0x00000400
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41       0x1F040870,0x00000200
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40       0x1F040870,0x00000100
#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33       0x1F040870,0x00000002

#define LPM_MEM_IPU_SRM_PRI1__ADDR                   0x1F000874
#define LPM_MEM_IPU_SRM_PRI1__EMPTY       0x1F000874,0x00000000
#define LPM_MEM_IPU_SRM_PRI1__FULL       0x1F000874,0xffffffff
#define LPM_MEM_IPU_SRM_PRI1__ISP_SRM_MODE       0x1F000874,0x00180000
#define LPM_MEM_IPU_SRM_PRI1__ISP_SRM_PRI       0x1F000874,0x00070000
#define LPM_MEM_IPU_SRM_PRI1__CSI0_SRM_MODE       0x1F000874,0x00001800
#define LPM_MEM_IPU_SRM_PRI1__CSI0_SRM_PRI       0x1F000874,0x00000700
#define LPM_MEM_IPU_SRM_PRI1__CSI1_SRM_MODE       0x1F000874,0x00000018
#define LPM_MEM_IPU_SRM_PRI1__CSI1_SRM_PRI       0x1F000874,0x00000007

#define LPM_MEM_IPU_SRM_PRI2__ADDR                   0x1F000878
#define LPM_MEM_IPU_SRM_PRI2__EMPTY       0x1F000878,0x00000000
#define LPM_MEM_IPU_SRM_PRI2__FULL       0x1F000878,0xffffffff
#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_MODE       0x1F000878,0x18000000
#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_PRI       0x1F000878,0x07000000
#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_MODE       0x1F000878,0x00180000
#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_PRI       0x1F000878,0x00070000
#define LPM_MEM_IPU_SRM_PRI2__DC_6_SRM_MODE       0x1F000878,0x0000C000
#define LPM_MEM_IPU_SRM_PRI2__DC_2_SRM_MODE       0x1F000878,0x00003000
#define LPM_MEM_IPU_SRM_PRI2__DC_SRM_PRI       0x1F000878,0x00000E00
#define LPM_MEM_IPU_SRM_PRI2__DP_A1_SRM_MODE       0x1F000878,0x00000180
#define LPM_MEM_IPU_SRM_PRI2__DP_A0_SRM_MODE       0x1F000878,0x00000060
#define LPM_MEM_IPU_SRM_PRI2__DP_S_SRM_MODE       0x1F000878,0x00000018
#define LPM_MEM_IPU_SRM_PRI2__DP_SRM_PRI       0x1F000878,0x00000007

#define LPM_MEM_IPU_FS_PROC_FLOW1__ADDR                   0x1F04087C
#define LPM_MEM_IPU_FS_PROC_FLOW1__EMPTY       0x1F04087C,0x00000000
#define LPM_MEM_IPU_FS_PROC_FLOW1__FULL       0x1F04087C,0xffffffff
#define LPM_MEM_IPU_FS_PROC_FLOW1__VF_IN_VALID       0x1F04087C,0x80000000
#define LPM_MEM_IPU_FS_PROC_FLOW1__ENC_IN_VALID       0x1F04087C,0x40000000
#define LPM_MEM_IPU_FS_PROC_FLOW1__PRP_SRC_SEL       0x1F04087C,0x0F000000
#define LPM_MEM_IPU_FS_PROC_FLOW1__ISP_SRC_SEL       0x1F04087C,0x00F00000
#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL       0x1F04087C,0x000F0000
#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_SRC_SEL       0x1F04087C,0x0000F000
#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL       0x1F04087C,0x00000F00
#define LPM_MEM_IPU_FS_PROC_FLOW1__ALT_ISP_SRC_SEL       0x1F04087C,0x000000F0
#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL       0x1F04087C,0x0000000F

#define LPM_MEM_IPU_FS_PROC_FLOW2__ADDR                   0x1F040880
#define LPM_MEM_IPU_FS_PROC_FLOW2__EMPTY       0x1F040880,0x00000000
#define LPM_MEM_IPU_FS_PROC_FLOW2__FULL       0x1F040880,0xffffffff
#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_ALT_DEST_SEL       0x1F040880,0xF0000000
#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_DEST_SEL       0x1F040880,0x0F000000
#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL       0x1F040880,0x00F00000
#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL       0x1F040880,0x000F0000
#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_DEST_SEL       0x1F040880,0x0000F000
#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL       0x1F040880,0x00000F00
#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL       0x1F040880,0x000000F0
#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL       0x1F040880,0x0000000F

#define LPM_MEM_IPU_FS_PROC_FLOW3__ADDR                   0x1F040884
#define LPM_MEM_IPU_FS_PROC_FLOW3__EMPTY       0x1F040884,0x00000000
#define LPM_MEM_IPU_FS_PROC_FLOW3__FULL       0x1F040884,0xffffffff
#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC3_DEST_SEL       0x1F040884,0x00003800
#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC2_DEST_SEL       0x1F040884,0x00000780
#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC1_DEST_SEL       0x1F040884,0x00000070
#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC0_DEST_SEL       0x1F040884,0x0000000F

#define LPM_MEM_IPU_FS_DISP_FLOW1__ADDR                   0x1F040888
#define LPM_MEM_IPU_FS_DISP_FLOW1__EMPTY       0x1F040888,0x00000000
#define LPM_MEM_IPU_FS_DISP_FLOW1__FULL       0x1F040888,0xffffffff
#define LPM_MEM_IPU_FS_DISP_FLOW1__DC1_SRC_SEL       0x1F040888,0x00F00000
#define LPM_MEM_IPU_FS_DISP_FLOW1__DC2_SRC_SEL       0x1F040888,0x000F0000
#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL       0x1F040888,0x0000F000
#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL       0x1F040888,0x00000F00
#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL       0x1F040888,0x000000F0
#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL       0x1F040888,0x0000000F

#define LPM_MEM_IPU_FS_DISP_FLOW2__ADDR                   0x1F04088C
#define LPM_MEM_IPU_FS_DISP_FLOW2__EMPTY       0x1F04088C,0x00000000
#define LPM_MEM_IPU_FS_DISP_FLOW2__FULL       0x1F04088C,0xffffffff
#define LPM_MEM_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL       0x1F04088C,0x000F0000
#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL       0x1F04088C,0x000000F0
#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL       0x1F04088C,0x0000000F

#define LPM_MEM_IPU_SKIP__ADDR                   0x1F040890
#define LPM_MEM_IPU_SKIP__EMPTY       0x1F040890,0x00000000
#define LPM_MEM_IPU_SKIP__FULL       0x1F040890,0xffffffff
#define LPM_MEM_IPU_SKIP__CSI_SKIP_IC_VF       0x1F040890,0x0000F800
#define LPM_MEM_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_VF       0x1F040890,0x00000700
#define LPM_MEM_IPU_SKIP__CSI_SKIP_IC_ENC       0x1F040890,0x000000F8
#define LPM_MEM_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_ENC       0x1F040890,0x00000007

#define LPM_MEM_IPU_DISP_ALT_CONF__ADDR                   0x1F040894
#define LPM_MEM_IPU_DISP_ALT_CONF__EMPTY       0x1F040894,0x00000000
#define LPM_MEM_IPU_DISP_ALT_CONF__FULL       0x1F040894,0xffffffff

#define LPM_MEM_IPU_DISP_GEN__ADDR                   0x1F040898
#define LPM_MEM_IPU_DISP_GEN__EMPTY       0x1F040898,0x00000000
#define LPM_MEM_IPU_DISP_GEN__FULL       0x1F040898,0xffffffff
#define LPM_MEM_IPU_DISP_GEN__DI1_COUNTER_RELEASE       0x1F040898,0x02000000
#define LPM_MEM_IPU_DISP_GEN__DI0_COUNTER_RELEASE       0x1F040898,0x01000000
#define LPM_MEM_IPU_DISP_GEN__CSI_VSYNC_DEST       0x1F040898,0x00800000
#define LPM_MEM_IPU_DISP_GEN__MCU_MAX_BURST_STOP       0x1F040898,0x00400000
#define LPM_MEM_IPU_DISP_GEN__MCU_T       0x1F040898,0x003C0000
#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_9       0x1F040898,0x00020000
#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_8       0x1F040898,0x00010000
#define LPM_MEM_IPU_DISP_GEN__DP_PIPE_CLR       0x1F040898,0x00000040
#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC1       0x1F040898,0x00000020
#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC0       0x1F040898,0x00000010
#define LPM_MEM_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW       0x1F040898,0x00000008
#define LPM_MEM_IPU_DISP_GEN__DC2_DOUBLE_FLOW       0x1F040898,0x00000004
#define LPM_MEM_IPU_DISP_GEN__DI1_DUAL_MODE       0x1F040898,0x00000002
#define LPM_MEM_IPU_DISP_GEN__DI0_DUAL_MODE       0x1F040898,0x00000001

#define LPM_MEM_IPU_DISP_ALT1__ADDR                   0x1F04089C
#define LPM_MEM_IPU_DISP_ALT1__EMPTY       0x1F04089C,0x00000000
#define LPM_MEM_IPU_DISP_ALT1__FULL       0x1F04089C,0xffffffff
#define LPM_MEM_IPU_DISP_ALT1__SEL_ALT_0       0x1F04089C,0xF0000000
#define LPM_MEM_IPU_DISP_ALT1__STEP_REPEAT_ALT_0       0x1F04089C,0x0FFF0000
#define LPM_MEM_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0       0x1F04089C,0x00008000
#define LPM_MEM_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0       0x1F04089C,0x00007000
#define LPM_MEM_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0       0x1F04089C,0x00000FFF

#define LPM_MEM_IPU_DISP_ALT2__ADDR                   0x1F0408A0
#define LPM_MEM_IPU_DISP_ALT2__EMPTY       0x1F0408A0,0x00000000
#define LPM_MEM_IPU_DISP_ALT2__FULL       0x1F0408A0,0xffffffff
#define LPM_MEM_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0       0x1F0408A0,0x00070000
#define LPM_MEM_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0       0x1F0408A0,0x00007000
#define LPM_MEM_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0       0x1F0408A0,0x00000FFF

#define LPM_MEM_IPU_DISP_ALT3__ADDR                   0x1F0408A4
#define LPM_MEM_IPU_DISP_ALT3__EMPTY       0x1F0408A4,0x00000000
#define LPM_MEM_IPU_DISP_ALT3__FULL       0x1F0408A4,0xffffffff
#define LPM_MEM_IPU_DISP_ALT3__SEL_ALT_1       0x1F0408A4,0xF0000000
#define LPM_MEM_IPU_DISP_ALT3__STEP_REPEAT_ALT_1       0x1F0408A4,0x0FFF0000
#define LPM_MEM_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1       0x1F0408A4,0x00008000
#define LPM_MEM_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1       0x1F0408A4,0x00007000
#define LPM_MEM_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1       0x1F0408A4,0x00000FFF

#define LPM_MEM_IPU_DISP_ALT4__ADDR                   0x1F0408A8
#define LPM_MEM_IPU_DISP_ALT4__EMPTY       0x1F0408A8,0x00000000
#define LPM_MEM_IPU_DISP_ALT4__FULL       0x1F0408A8,0xffffffff
#define LPM_MEM_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1       0x1F0408A8,0x00070000
#define LPM_MEM_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1       0x1F0408A8,0x00007000
#define LPM_MEM_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1       0x1F0408A8,0x00000FFF

#define LPM_MEM_IPU_SNOOP__ADDR                   0x1F0408AC
#define LPM_MEM_IPU_SNOOP__EMPTY       0x1F0408AC,0x00000000
#define LPM_MEM_IPU_SNOOP__FULL       0x1F0408AC,0xffffffff
#define LPM_MEM_IPU_SNOOP__SNOOP2_SYNC_BYP       0x1F0408AC,0x00010000
#define LPM_MEM_IPU_SNOOP__AUTOREF_PER       0x1F0408AC,0x000003FF

#define LPM_MEM_IPU_MEM_RST__ADDR                   0x1F0408B0
#define LPM_MEM_IPU_MEM_RST__EMPTY       0x1F0408B0,0x00000000
#define LPM_MEM_IPU_MEM_RST__FULL       0x1F0408B0,0xffffffff
#define LPM_MEM_IPU_MEM_RST__RST_MEM_START       0x1F0408B0,0x80000000
#define LPM_MEM_IPU_MEM_RST__RST_MEM_EN       0x1F0408B0,0x007FFFFF

#define LPM_MEM_IPU_PM__ADDR                   0x1F0408B4
#define LPM_MEM_IPU_PM__EMPTY       0x1F0408B4,0x00000000
#define LPM_MEM_IPU_PM__FULL       0x1F0408B4,0xffffffff
#define LPM_MEM_IPU_PM__LPSR_MODE       0x1F0408B4,0x80000000
#define LPM_MEM_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE       0x1F0408B4,0x40000000
#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_1       0x1F0408B4,0x3F800000
#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_0       0x1F0408B4,0x007F0000
#define LPM_MEM_IPU_PM__CLOCK_MODE_STAT       0x1F0408B4,0x00008000
#define LPM_MEM_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE       0x1F0408B4,0x00004000
#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_1       0x1F0408B4,0x00003F80
#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_0       0x1F0408B4,0x0000007F

#define LPM_MEM_IPU_GPR__ADDR                     0x1F0408B8
#define LPM_MEM_IPU_GPR__EMPTY                    0x1F0408B8,0x00000000
#define LPM_MEM_IPU_GPR__FULL                     0x1F0408B8,0xffffffff
#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY1_CLR     0x1F0408B8,0x80000000
#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY0_CLR     0x1F0408B8,0x40000000
#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY1_CLR     0x1F0408B8,0x20000000
#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY0_CLR     0x1F0408B8,0x10000000
#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR 0x1F0408B8,0x08000000
#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR 0x1F0408B8,0x04000000
#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR 0x1F0408B8,0x02000000
#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR 0x1F0408B8,0x01000000
#define LPM_MEM_IPU_GPR__IPU_GP23                 0x1F0408B8,0x00800000
#define LPM_MEM_IPU_GPR__IPU_GP22                 0x1F0408B8,0x00400000
#define LPM_MEM_IPU_GPR__IPU_GP21                 0x1F0408B8,0x00200000
#define LPM_MEM_IPU_GPR__IPU_GP20                 0x1F0408B8,0x00100000
#define LPM_MEM_IPU_GPR__IPU_GP19                 0x1F0408B8,0x00080000
#define LPM_MEM_IPU_GPR__IPU_GP18                 0x1F0408B8,0x00040000
#define LPM_MEM_IPU_GPR__IPU_GP17                 0x1F0408B8,0x00020000
#define LPM_MEM_IPU_GPR__IPU_GP16                 0x1F0408B8,0x00010000
#define LPM_MEM_IPU_GPR__IPU_GP15                 0x1F0408B8,0x00008000
#define LPM_MEM_IPU_GPR__IPU_GP14                 0x1F0408B8,0x00004000
#define LPM_MEM_IPU_GPR__IPU_GP13                 0x1F0408B8,0x00002000
#define LPM_MEM_IPU_GPR__IPU_GP12                 0x1F0408B8,0x00001000
#define LPM_MEM_IPU_GPR__IPU_GP11                 0x1F0408B8,0x00000800
#define LPM_MEM_IPU_GPR__IPU_GP10                 0x1F0408B8,0x00000400
#define LPM_MEM_IPU_GPR__IPU_GP9                  0x1F0408B8,0x00000200
#define LPM_MEM_IPU_GPR__IPU_GP8                  0x1F0408B8,0x00000100
#define LPM_MEM_IPU_GPR__IPU_GP7                  0x1F0408B8,0x00000080
#define LPM_MEM_IPU_GPR__IPU_GP6                  0x1F0408B8,0x00000040
#define LPM_MEM_IPU_GPR__IPU_GP5                  0x1F0408B8,0x00000020
#define LPM_MEM_IPU_GPR__IPU_GP4                  0x1F0408B8,0x00000010
#define LPM_MEM_IPU_GPR__IPU_GP3                  0x1F0408B8,0x00000008
#define LPM_MEM_IPU_GPR__IPU_GP2                  0x1F0408B8,0x00000004
#define LPM_MEM_IPU_GPR__IPU_GP1                  0x1F0408B8,0x00000002
#define LPM_MEM_IPU_GPR__IPU_GP0                  0x1F0408B8,0x00000001

#define LPM_MEM_IC_CONF__ADDR                   0x1F0408BC
#define LPM_MEM_IC_CONF__EMPTY                  0x1F0408BC,0x00000000
#define LPM_MEM_IC_CONF__FULL                   0x1F0408BC,0xffffffff
#define LPM_MEM_IC_CONF__CSI_MEM_WR_EN          0x1F0408BC,0x80000000
#define LPM_MEM_IC_CONF__RWS_EN                 0x1F0408BC,0x40000000
#define LPM_MEM_IC_CONF__IC_KEY_COLOR_EN        0x1F0408BC,0x20000000
#define LPM_MEM_IC_CONF__IC_GLB_LOC_A           0x1F0408BC,0x10000000
#define LPM_MEM_IC_CONF__PP_ROT_EN              0x1F0408BC,0x00100000
#define LPM_MEM_IC_CONF__PP_CMB                 0x1F0408BC,0x00080000
#define LPM_MEM_IC_CONF__PP_CSC2                0x1F0408BC,0x00040000
#define LPM_MEM_IC_CONF__PP_CSC1                0x1F0408BC,0x00020000
#define LPM_MEM_IC_CONF__PP_EN                  0x1F0408BC,0x00010000
#define LPM_MEM_IC_CONF__PRPVF_ROT_EN           0x1F0408BC,0x00001000
#define LPM_MEM_IC_CONF__PRPVF_CMB              0x1F0408BC,0x00000800
#define LPM_MEM_IC_CONF__PRPVF_CSC2             0x1F0408BC,0x00000400
#define LPM_MEM_IC_CONF__PRPVF_CSC1             0x1F0408BC,0x00000200
#define LPM_MEM_IC_CONF__PRPVF_EN               0x1F0408BC,0x00000100
#define LPM_MEM_IC_CONF__PRPENC_ROT_EN          0x1F0408BC,0x00000004
#define LPM_MEM_IC_CONF__PRPENC_CSC1            0x1F0408BC,0x00000002
#define LPM_MEM_IC_CONF__PRPENC_EN              0x1F0408BC,0x00000001

#define LPM_MEM_IC_PRP_ENC_RSC__ADDR            0x1F0408C0
#define LPM_MEM_IC_PRP_ENC_RSC__EMPTY           0x1F0408C0,0x00000000
#define LPM_MEM_IC_PRP_ENC_RSC__FULL            0x1F0408C0,0xffffffff
#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_V   0x1F0408C0,0xC0000000
#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_V   0x1F0408C0,0x3FFF0000
#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_H   0x1F0408C0,0x0000C000
#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_H   0x1F0408C0,0x00003FFF

#define LPM_MEM_IC_PRP_VF_RSC__ADDR             0x1F0408C4
#define LPM_MEM_IC_PRP_VF_RSC__EMPTY            0x1F0408C4,0x00000000
#define LPM_MEM_IC_PRP_VF_RSC__FULL             0x1F0408C4,0xffffffff
#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_V     0x1F0408C4,0xC0000000
#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_V     0x1F0408C4,0x3FFF0000
#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_H     0x1F0408C4,0x0000C000
#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_H     0x1F0408C4,0x00003FFF

#define LPM_MEM_IC_PP_RSC__ADDR                 0x1F0408C8
#define LPM_MEM_IC_PP_RSC__EMPTY                0x1F0408C8,0x00000000
#define LPM_MEM_IC_PP_RSC__FULL                 0x1F0408C8,0xffffffff
#define LPM_MEM_IC_PP_RSC__PP_DS_R_V            0x1F0408C8,0xC0000000
#define LPM_MEM_IC_PP_RSC__PP_RS_R_V            0x1F0408C8,0x3FFF0000
#define LPM_MEM_IC_PP_RSC__PP_DS_R_H            0x1F0408C8,0x0000C000
#define LPM_MEM_IC_PP_RSC__PP_RS_R_H            0x1F0408C8,0x00003FFF

#define LPM_MEM_IC_CMBP_1__ADDR                 0x1F0408CC
#define LPM_MEM_IC_CMBP_1__EMPTY                0x1F0408CC,0x00000000
#define LPM_MEM_IC_CMBP_1__FULL                 0x1F0408CC,0xffffffff
#define LPM_MEM_IC_CMBP_1__IC_PP_ALPHA_V        0x1F0408CC,0x0000FF00
#define LPM_MEM_IC_CMBP_1__IC_PRPVF_ALPHA_V     0x1F0408CC,0x000000FF

#define LPM_MEM_IC_CMBP_2__ADDR                 0x1F0408D0
#define LPM_MEM_IC_CMBP_2__EMPTY                0x1F0408D0,0x00000000
#define LPM_MEM_IC_CMBP_2__FULL                 0x1F0408D0,0xffffffff
#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_R       0x1F0408D0,0x00FF0000
#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_G       0x1F0408D0,0x0000FF00
#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_B       0x1F0408D0,0x000000FF

#define LPM_MEM_IC_IDMAC_1__ADDR                0x1F0408D4
#define LPM_MEM_IC_IDMAC_1__EMPTY               0x1F0408D4,0x00000000
#define LPM_MEM_IC_IDMAC_1__FULL                0x1F0408D4,0xffffffff
#define LPM_MEM_IC_IDMAC_1__ALT_CB7_BURST_16    0x1F0408D4,0x02000000
#define LPM_MEM_IC_IDMAC_1__ALT_CB6_BURST_16    0x1F0408D4,0x01000000
#define LPM_MEM_IC_IDMAC_1__T3_FLIP_RS       0x1F0408D4,0x00400000
#define LPM_MEM_IC_IDMAC_1__T2_FLIP_RS       0x1F0408D4,0x00200000
#define LPM_MEM_IC_IDMAC_1__T1_FLIP_RS       0x1F0408D4,0x00100000
#define LPM_MEM_IC_IDMAC_1__T3_FLIP_UD          0x1F0408D4,0x00080000
#define LPM_MEM_IC_IDMAC_1__T3_FLIP_LR          0x1F0408D4,0x00040000
#define LPM_MEM_IC_IDMAC_1__T3_ROT              0x1F0408D4,0x00020000
#define LPM_MEM_IC_IDMAC_1__T2_FLIP_UD          0x1F0408D4,0x00010000
#define LPM_MEM_IC_IDMAC_1__T2_FLIP_LR          0x1F0408D4,0x00008000
#define LPM_MEM_IC_IDMAC_1__T2_ROT              0x1F0408D4,0x00004000
#define LPM_MEM_IC_IDMAC_1__T1_FLIP_UD          0x1F0408D4,0x00002000
#define LPM_MEM_IC_IDMAC_1__T1_FLIP_LR          0x1F0408D4,0x00001000
#define LPM_MEM_IC_IDMAC_1__T1_ROT              0x1F0408D4,0x00000800
#define LPM_MEM_IC_IDMAC_1__CB7_BURST_16        0x1F0408D4,0x00000080
#define LPM_MEM_IC_IDMAC_1__CB6_BURST_16        0x1F0408D4,0x00000040
#define LPM_MEM_IC_IDMAC_1__CB5_BURST_16        0x1F0408D4,0x00000020
#define LPM_MEM_IC_IDMAC_1__CB4_BURST_16        0x1F0408D4,0x00000010
#define LPM_MEM_IC_IDMAC_1__CB3_BURST_16        0x1F0408D4,0x00000008
#define LPM_MEM_IC_IDMAC_1__CB2_BURST_16        0x1F0408D4,0x00000004
#define LPM_MEM_IC_IDMAC_1__CB1_BURST_16        0x1F0408D4,0x00000002
#define LPM_MEM_IC_IDMAC_1__CB0_BURST_16        0x1F0408D4,0x00000001

#define LPM_MEM_IC_IDMAC_2__ADDR                0x1F0408D8
#define LPM_MEM_IC_IDMAC_2__EMPTY               0x1F0408D8,0x00000000
#define LPM_MEM_IC_IDMAC_2__FULL                0x1F0408D8,0xffffffff
#define LPM_MEM_IC_IDMAC_2__T3_FR_HEIGHT        0x1F0408D8,0x3FF00000
#define LPM_MEM_IC_IDMAC_2__T2_FR_HEIGHT        0x1F0408D8,0x000FFC00
#define LPM_MEM_IC_IDMAC_2__T1_FR_HEIGHT        0x1F0408D8,0x000003FF

#define LPM_MEM_IC_IDMAC_3__ADDR                0x1F0408DC
#define LPM_MEM_IC_IDMAC_3__EMPTY               0x1F0408DC,0x00000000
#define LPM_MEM_IC_IDMAC_3__FULL                0x1F0408DC,0xffffffff
#define LPM_MEM_IC_IDMAC_3__T3_FR_WIDTH         0x1F0408DC,0x3FF00000
#define LPM_MEM_IC_IDMAC_3__T2_FR_WIDTH         0x1F0408DC,0x000FFC00
#define LPM_MEM_IC_IDMAC_3__T1_FR_WIDTH         0x1F0408DC,0x000003FF

#define LPM_MEM_IC_IDMAC_4__ADDR                  0x1F0408E0
#define LPM_MEM_IC_IDMAC_4__EMPTY                 0x1F0408E0,0x00000000
#define LPM_MEM_IC_IDMAC_4__FULL                  0x1F0408E0,0xffffffff
#define LPM_MEM_IC_IDMAC_4__RM_BRDG_MAX_RQ        0x1F0408E0,0x0000F000
#define LPM_MEM_IC_IDMAC_4__IBM_BRDG_MAX_RQ       0x1F0408E0,0x00000F00
#define LPM_MEM_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ  0x1F0408E0,0x000000F0
#define LPM_MEM_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ    0x1F0408E0,0x0000000F

#endif