packages/devs/ipu/arm/imx/v1_0/src/ipu_display.c

   1 //==========================================================================
   2 //
   3 //      IPU_DI.c
   4 //
   5 //      common functions definitions for IPU modules operation
   6 //
   7 //==========================================================================
   8 //#####DESCRIPTIONBEGIN####
   9 //
  10 // Author(s):       Ray Sun <Yanfei.Sun@freescale.com>
  11 // Create Date: 2008-07-31
  12 //
  13 //####DESCRIPTIONEND####
  14 //
  15 //==========================================================================
  16
  17 #include <cyg/io/ipu_common.h>
  18 #include <cyg/hal/hal_soc.h>    // Hardware definitions
  19
  20 /*
  21 * this function is used to config the waveform generator in the DI
  22 */
  23 void ipu_di_sync_config(int di, int pointer, di_sync_wave_gen_t sync_waveform_gen)
  24 {
  25         ipu_write_field(DI_SWGEN0_RUN_VALUE_M1(di, pointer), sync_waveform_gen.runValue);
  26         ipu_write_field(DI_SWGEN0_RUN_RESOL(di, pointer), sync_waveform_gen.runResolution);
  27         ipu_write_field(DI_SWGEN0_OFFSET_VALUE(di, pointer), sync_waveform_gen.offsetValue);
  28         ipu_write_field(DI_SWGEN0_OFFSET_RESOL(di, pointer), sync_waveform_gen.offsetResolution);
  29         ipu_write_field(DI_SWGEN1_CNT_POL_GEN_EN(di, pointer), sync_waveform_gen.cntPolarityGenEn);
  30         ipu_write_field(DI_SWGEN1_CNT_AUTOLOAD(di, pointer), sync_waveform_gen.cntAutoReload);
  31         ipu_write_field(DI_SWGEN1_CNT_CLR_SEL(di, pointer), sync_waveform_gen.cntClrSel);
  32         ipu_write_field(DI_SWGEN1_CNT_DOW(di, pointer), sync_waveform_gen.cntDown);
  33         ipu_write_field(DI_SWGEN1_CNT_POL_TRIG_SEL(di, pointer), sync_waveform_gen.cntPolarityTrigSel);
  34         ipu_write_field(DI_SWGEN1_CNT_POL_CLR_SEL(di, pointer), sync_waveform_gen.cntPolarityClrSel);
  35         ipu_write_field(DI_SWGEN1_CNT_CNT_UP(di, pointer), sync_waveform_gen.cntUp);
  36         ipu_write_field(DI_STEP_RPT(di, pointer), sync_waveform_gen.stepRepeat);
  37
  38         return;
  39 }
  40
  41 void ipu_di_pointer_config(int di, int pointer, int access, int component, int cst, int pt0,
  42                                                 int pt1, int pt2, int pt3, int pt4, int pt5, int pt6)
  43 {
  44         unsigned int regVal = 0;
  45         regVal =
  46                 (access << 24) | (component << 16) | (cst << 14) | (pt6 << 12) | (pt5 << 10) | (pt4 << 8) |
  47                 (pt3 << 6) | (pt2 << 4) | (pt1 << 2) | pt0;
  48
  49         if (di == 0) {
  50                 writel(regVal, IPU_CTRL_BASE_ADDR + IPU_DI0_DW_GEN_0__ADDR + pointer * 4);
  51         } else {
  52                 writel(regVal, IPU_CTRL_BASE_ADDR + IPU_DI1_DW_GEN_0__ADDR + pointer * 4);
  53         }
  54         return;
  55 }
  56
  57 void ipu_di_waveform_config(int di, int pointer, int set, int up, int down)
  58 {
  59         ipu_write_field(DI_WAVESET_UP(di, pointer, set), up);
  60         ipu_write_field(DI_WAVESET_DOWN(di, pointer, set), down);
  61
  62         return;
  63 }
  64
  65 int ipu_di_bsclk_gen(int di, int division, int up, int down)
  66 {
  67         switch (di) {
  68         case 0:
  69                 ipu_write_field(IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET, 0);
  70                 ipu_write_field(IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD, division);
  71                 ipu_write_field(IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN, down);
  72                 ipu_write_field(IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP, up);
  73                 break;
  74
  75         case 1:
  76                 ipu_write_field(IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET, 0);
  77                 ipu_write_field(IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD, division);
  78                 ipu_write_field(IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN, down);
  79                 ipu_write_field(IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP, up);
  80                 break;
  81
  82         default:
  83                 ERRDP("Wrong di pointer!\n");
  84                 return -1;
  85         }
  86         return 0;
  87 }
  88
  89 int ipu_di_screen_set(int di, int screen_height)
  90 {
  91         switch (di) {
  92         case 0:
  93                 ipu_write_field(IPU_DI0_SCR_CONF__DI0_SCREEN_HEIGHT, screen_height);
  94                 break;
  95
  96         case 1:
  97                 ipu_write_field(IPU_DI1_SCR_CONF__DI1_SCREEN_HEIGHT, screen_height);
  98                 break;
  99
 100         default:
 101                 ERRDP("Wrong di pointer!\n");
 102                 return -1;
 103         }
 104         return 0;
 105 }
 106
 107 int ipu_di_general_set(int di, int line_prediction, int vsync_sel, int hsync_sel, int clk_sel)
 108 {
 109         switch (di) {
 110         case 0:
 111                 ipu_write_field(IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START, line_prediction);
 112                 ipu_write_field(IPU_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL, vsync_sel);
 113                 ipu_write_field(IPU_DI0_GENERAL__DI0_CLK_EXT, clk_sel);
 114
 115                 ipu_write_field(IPU_DI0_GENERAL__DI0_POLARITY_DISP_CLK, 1);
 116                 ipu_write_field(IPU_DI0_GENERAL__DI0_POLARITY_3, 0);    //HSYNC polarity, active low
 117                 ipu_write_field(IPU_DI0_GENERAL__DI0_POLARITY_2, 0);    //VSYNC polarity, active low
 118                 ipu_write_field(IPU_DI0_POL__DI0_DRDY_POLARITY_15, 1);  //VIDEO_DATA_EN polarity, active hign
 119
 120                 /* release ipu DI0 counter */
 121                 ipu_write_field(IPU_IPU_DISP_GEN__DI0_COUNTER_RELEASE, 1);
 122                 break;
 123
 124         case 1:
 125                 ipu_write_field(IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START, line_prediction);
 126                 ipu_write_field(IPU_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL, vsync_sel);
 127                 ipu_write_field(IPU_DI1_GENERAL__DI1_DISP_Y_SEL, hsync_sel);
 128                 ipu_write_field(IPU_DI1_GENERAL__DI1_CLK_EXT, clk_sel);
 129
 130                 ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_DISP_CLK, 0);
 131                 ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_8, 1);
 132                 ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_5, 1);
 133                 ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_3, 1);    //HSYNC POLARITY
 134                 ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_2, 1);    //VSYNC POLARITY
 135                 ipu_write_field(IPU_DI1_POL__DI1_DRDY_POLARITY_15, 1);
 136                 /* release ipu DI1 counter */
 137                 ipu_write_field(IPU_IPU_DISP_GEN__DI1_COUNTER_RELEASE, 1);
 138                 break;
 139
 140         default:
 141                 ERRDP("Wrong di pointer!\n");
 142                 return -1;
 143         }
 144         return 0;
 145 }